A memory and a method for operating data thereof

Abstract

The present application discloses a memory and a data operation method thereof. The memory includes at least two memory cells and at least one buffer unit. The buffer unit is connected to two of the at least two memory cells. The buffer unit receives a control signal from the memory cells and performs data operations on the two memory cells based on the control signal. By the above method, data movement, data copying, etc. can be achieved, data transmission between the memory and the processor is reduced, and there is no need to additionally configure an independent controller and a physical interface, thus saving power consumption and cost.

Description

Technical Field

[0001] This application relates to the field of computer storage technologies, and particularly to a memory and a data operation method thereof. Background Art

[0002] In the existing computer system, the processor needs to perform data interaction with the memory through the data bus. More parallel channels are added between the memory and the processor to increase the data transmission bandwidth.

[0003] Among them, each channel between the memory and the processor needs to be configured with an independent controller and a physical interface (PHY), resulting in additional cost and power consumption. Summary of the Invention

[0004] To solve the above problems, this application provides a memory and a data operation method thereof. Data operations are performed through a buffer unit, without the need to additionally configure an independent controller and a physical interface, saving power consumption and cost.

[0005] One technical solution adopted by this application is: providing a memory, including at least two storage units and at least one buffer unit. The buffer unit is connected to two of the at least two storage units. The buffer unit receives a control signal from the storage unit and performs data operations on the two storage units based on the control signal.

[0006] Among them, the at least two storage units include a first storage unit and a second storage unit. The buffer unit includes:

[0007] A control circuit, respectively connected to the first storage unit and the second storage unit, for receiving a first control signal from the first storage unit and / or receiving a second control signal from the second storage unit;

[0008] A buffer circuit, respectively connected to the first storage unit, the second storage unit, and the control circuit. The control circuit controls the buffer circuit to perform data operations on the first storage unit and the second storage unit based on the first control signal or / and the second control signal.

[0009] Among them, the control circuit generates a third control signal based on the first control signal and outputs the third control signal to the second storage unit to control the second storage unit; the control circuit generates a fourth control signal based on the second control signal and outputs the fourth control signal to the first storage unit to control the first storage unit.

[0010] Among them, the buffer circuit includes a first buffer, a second buffer, and a third buffer. The input ends of the first buffer and the second buffer are connected to the output end of the third buffer. The output end of the first buffer is connected to the physical interface of the first storage unit. The output end of the second buffer is connected to the physical interface of the second storage unit. The input end of the third buffer is respectively connected to the physical interfaces of the first storage unit, the second storage unit, and the control circuit.

[0011] Among them, the second storage unit sends a second control signal to the control circuit. The control circuit generates a fourth control signal based on the second control signal and sends the fourth control signal to the first storage unit. The first storage unit reads the first data based on the fourth control signal. The control circuit controls the first buffer to close and the second buffer to open based on the second control signal. The first storage unit sends the first data to the second storage unit through the third buffer and the second buffer, so that the second storage unit reads the first data from the first storage unit, and then obtains the second data.

[0012] Among them, the first storage unit sends a first control signal to the control circuit. The control circuit generates a third control signal based on the first control signal and sends the third control signal to the second storage unit. The control circuit controls the first buffer to close and the second buffer to open. The first storage unit writes the first data into the second storage unit through the third buffer and the second buffer to obtain the second data of the second storage unit.

[0013] Among them, the first storage unit sends a first control signal to the control circuit, and the second storage unit sends a second control signal to the control circuit. The control circuit controls the first buffer to close and the second buffer to close. The first storage unit transmits the first data to the third buffer, and the second storage unit transmits the second data to the third buffer;

[0014] The control circuit receives a fifth control signal from the first storage unit or the second storage unit, and controls the third buffer to perform an operation on the first data and the second data based on the fifth control signal to obtain a first operation result; the third buffer transmits the first operation result to the first storage unit or the second storage unit.

[0015] Among them, the first control signal includes a first read operation signal and a first write operation signal. The control circuit controls the first buffer to close and the second buffer to close based on the first read operation signal. The first storage unit reads the first data and sends the first data to the third buffer;

[0016] The control circuit receives a sixth control signal from the first storage unit, and controls the third buffer to perform an operation on the first data based on the sixth control signal to obtain a second operation result;

[0017] The control circuit controls the first buffer to open based on the first write operation signal, and transmits the second operation result to the first storage unit through the third buffer.

[0018] Wherein, the second control signal includes a second read operation signal and a second write operation signal. The control circuit controls the first buffer to close and the second buffer to close based on the second read operation signal. The second storage unit reads the second data and sends the second data to the third buffer;

[0019] The control circuit receives a sixth control signal from the second storage unit, and controls the third buffer to perform an operation on the second data based on the sixth control signal to obtain a third operation result;

[0020] The control circuit controls the second buffer to open based on the second write operation signal, and transmits the third operation result to the second storage unit through the third buffer.

[0021] Wherein, at least two storage units include a first storage unit, a second storage unit, a third storage unit and a fourth storage unit, and at least one buffer unit includes a first buffer unit and a second buffer unit. The first buffer unit is respectively connected to the first storage unit and the second storage unit, the second buffer unit is respectively connected to the third storage unit and the fourth storage unit, and the first buffer unit is connected to the second buffer unit.

[0022] Another technical solution adopted by this application is: to provide a data operation method for a memory, which is applied to the above-mentioned memory. The data operation method includes:

[0023] At least one of the two storage units sends a control signal to the buffer unit;

[0024] The buffer unit performs data operations on the two storage units based on the control signal.

[0025] The memory of this application includes at least two storage units and at least one buffer unit. The buffer unit is connected to two of the at least two storage units. The buffer unit receives a control signal from the storage unit and performs data operations on the two storage units based on the control signal. By arranging a buffer unit between two storage units in the memory of this application, and the buffer unit performs data operations on the two storage units, data movement, data copying, etc. can be realized, the data transmission between the memory and the processor can be reduced, and there is no need to configure an independent controller and physical interface additionally, saving power consumption and cost. Description of the Drawings

[0026] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings. Among them:

[0027] Figure 1 is a schematic framework diagram of the first embodiment of the memory of the present application;

[0028] Figure 2 is Figure 1 a schematic framework diagram of the buffer unit in;

[0029] Figure 3 is Figure 1 a schematic circuit diagram of the buffer unit in;

[0030] Figure 4 is a schematic structural diagram of the second embodiment of the memory of the present application;

[0031] Figure 5 is a schematic structural diagram of the third embodiment of the memory of the present application;

[0032] Figure 6 is a schematic flowchart of the first embodiment of the data operation method of the present application. Specific embodiments

[0033] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. It can be understood that the specific embodiments described herein are only used to explain the present application, rather than limiting the present application. Additionally, it should be noted that for the sake of convenience of description, only the parts related to the present application rather than all the structures are shown in the accompanying drawings. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0034] The terms "first", "second", etc. in the present application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products, or devices.

[0035] References to "embodiments" in this specification mean that the particular features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0036] Please refer to Figure 1 as shown Figure 1 is a schematic framework diagram of the first embodiment of the memory of the present application. The memory of this embodiment includes at least two storage units 11 and at least one buffer unit 12. In other embodiments, the storage unit 11 can also be referred to as a storage channel.

[0037] Among them, the buffer unit 12 is connected to two of the at least two storage units 11, that is, the buffer unit 12 is connected between the two storage units 11.

[0038] The buffer unit 12 receives a control signal from the storage unit 11 and performs data operations on the two storage units 11 based on the control signal. Specifically, the buffer unit 12 performing data operations on the two storage units 11 can be data transfer, data copy, or simple operations on the data for the two storage units 11, etc.

[0039] Among them, the buffer unit 12 can receive a control signal from at least one of the two storage units 11.

[0040] Optionally, the memory is connected to the processor 30 through a data bus 20. Each storage unit 11 is independently configured with a physical interface 111 and a controller 21, that is, each storage unit 11 is connected to the data bus 20 through the physical interface 111 and the controller 21 to be connected to the processor 30 through the data bus 20.

[0041] In this embodiment, the buffer unit 12 is connected to two of the at least two storage units 11. The buffer unit 12 receives a control signal from the storage unit 11 and performs data operations on the two storage units 11 based on the control signal; it can achieve data movement, data copy, etc., reduce data transmission between the memory and the processor 30, and there is no need to additionally configure an independent controller 21 and physical interface 111, saving power consumption and cost.

[0042] In one embodiment, the at least two storage units 11 include a first storage unit 112 and a second storage unit 113. The first storage unit 112 is provided with a physical interface 111, and the second storage unit 113 is provided with a physical interface 114.

[0043] Combined with Figure 1 and2 As shown, the buffer unit 12 includes a control circuit 121 and a buffer circuit 122. The control circuit 121 is respectively connected to the first storage unit 112, the physical interface 111 of the first storage unit 112, the second storage unit 113, and the physical interface 114 of the second storage unit 113, and is configured to receive the first control signal CTRL1 from the first storage unit 112 and / or receive the second control signal CTRL2 from the second storage unit 113. That is, the control signals received by the buffer unit 12 from the storage unit 11 include the first control signal CTRL1 and / or the second control signal CTRL2. For example, the control circuit 121 receives the first control signal CTRL1 from the physical interface 111 of the first storage unit 112, the control circuit 121 receives the second control signal CTRL2 from the physical interface 114 of the second storage unit 113, or the control circuit 121 receives the first control signal CTRL1 from the physical interface 111 of the first storage unit 112 and receives the second control signal CTRL2 from the physical interface 114 of the second storage unit 113.

[0044] The buffer circuit 122 is respectively connected to the first storage unit 112, the physical interface 111 of the first storage unit 112, the second storage unit 113, the physical interface 114 of the second storage unit 113, and the control circuit 121. The control circuit 121 controls the buffer circuit 122 to perform data operations on the first storage unit 112 and the second storage unit 113 based on the first control signal CTRL1 and / or the second control signal CTRL2.

[0045] Optionally, the control circuit 121 receives the first control signal CTRL1 from the first storage unit 112, generates a third control signal CTRL1X based on the first control signal CTRL1, and outputs the third control signal CTRL1X to the second storage unit 113 to control the second storage unit 113 to update the control signal of the second storage unit 113, and further perform data operations on the second storage unit 113. The control circuit 121 receives the second control signal CTRL2 from the second storage unit 113, generates a fourth control signal CTRL2X based on the second control signal CTRL2, and outputs the fourth control signal CTRL2X to the first storage unit 112 to update the control signal of the first storage unit 112, and further perform data operations on the first storage unit 112.

[0046] The buffer unit 12 of this embodiment includes a control circuit 121 and a buffer circuit 122. The control circuit 121 controls the buffer circuit 122 to perform data operations on the first storage unit 112 and the second storage unit 113 based on the first control signal CTRL1 and / or the second control signal CTRL2, without the need to additionally configure an independent controller 21 and a physical interface 111, saving power consumption and cost and being easy to implement.

[0047] Please further refer to Figure 3 as shown Figure 3 which is Figure 1 a schematic circuit diagram of the buffer unit in []. The buffer unit 12 includes a control circuit 121 and a buffer circuit 122. The buffer circuit 122 includes a first buffer buf1, a second buffer buf2, and a third buffer buf3. The input ends of the first buffer buf1 and the second buffer buf2 are connected to the output end of the third buffer buf3. The output end of the first buffer buf1 is connected to the physical interface 111 of the first storage unit 112. The output end of the second buffer buf2 is connected to the physical interface 114 of the second storage unit 113. The input end of the third buffer buf3 is respectively connected to the physical interface 111 of the first storage unit 112, the physical interface 114 of the second storage unit 113, and the control circuit 121. For example, the third buffer buf3 is provided with three input ends, and the three input ends of the third buffer buf3 are respectively connected to the physical interface 111 of the first storage unit 112, the physical interface 114 of the second storage unit 113, and the control circuit 121.

[0048] Optionally, the control circuit 121 controls the working states of the first buffer buf1, the second buffer buf2, and the third buffer buf3 based on the first control signal CTRL1 and / or the second control signal CTRL2, so as to perform data operations on the first storage unit 112 and the second storage unit 113.

[0049] In an embodiment of the present application, data is moved between the first storage unit 112 and the second storage unit 113. For example, the second storage unit 113 reads data from the first storage unit 112 through the buffer unit 12. The second storage unit 113 sends the second control signal CTRL2 to the control circuit 121. The second control signal CTRL2 may include a read operation instruction (also referred to as a read command) generated by the second storage unit 113. The control circuit 121 receives the second control signal CTRL2 and generates a fourth control signal CTRL2X based on the second control signal CTRL2. The control circuit 121 sends the fourth control signal CTRL2X to the first storage unit 112. The first storage unit 112 performs a read operation based on the fourth control signal CTRL2X to read the first data DATA1.

[0050] The control circuit 121 controls the first buffer buf1 to close and the second buffer buf2 to open based on the second control signal CTRL2, that is, the control circuit 121 controls the output terminal of the first buffer buf1 to close and the output terminal of the second buffer buf2 to open. The third buffer buf3 obtains the first data DATA1 from the first storage unit 112 and sends it to the second storage unit 113 through the second buffer buf2; that is, the first storage unit 112 sends the first data DATA1 to the second storage unit 113 through the third buffer buf3 and the second buffer buf2, so that the second storage unit 113 reads the first data DATA1 from the first storage unit 112, and then obtains the second data DATA2. Among them, the first data DATA1 is transmitted through the third buffer buf3 and the second buffer buf2 to become the second data DATA2 of the second storage unit 113.

[0051] After the second storage unit 113 receives the second data DATA2, the second storage unit 113 can output the second data DATA2 or save the second data DATA2 to a storage device connected to the second storage unit 113.

[0052] In this embodiment, the second storage unit 113 reads data from the first storage unit 112 through the buffer unit 12, realizes data movement, and saves power consumption and cost.

[0053] In an embodiment of the present application, the first storage unit 112 writes the first data DATA1 into the second storage unit 113 through the buffer unit 12, and the first storage unit 112 sends a first control signal CTRL1 to the control circuit 121. The first control signal CTRL1 may include a write operation instruction (also referred to as a write command) generated by the first storage unit 112; the control circuit 121 receives the first control signal CTRL1 and generates a third control signal CTRL1X based on the first control signal CTRL1. The control circuit 121 sends the third control signal CTRL1X to the second storage unit 113, and the second storage unit 113 performs a write operation based on the third control signal CTRL1X.

[0054] The control circuit 121 controls the first buffer buf1 to close and the second buffer buf2 to open based on the first control signal CTRL1, that is, the control circuit 121 controls the output terminal of the first buffer buf1 to close and the output terminal of the second buffer buf2 to open. The first storage unit 112 writes the first data DATA1 into the third buffer buf3, and the third buffer buf3 writes the first data DATA1 into the second storage unit 113 through the second buffer buf2; that is, the first storage unit 112 writes the first data DATA1 into the second storage unit 113 through the third buffer buf3 and the second buffer buf2 to obtain the second data DATA2 of the second storage unit 113. Among them, the first data DATA1 is transmitted through the third buffer buf3 and the second buffer buf2 to become the second data DATA2.

[0055] After the second storage unit 113 writes the second data DATA2, the second storage unit 113 can output the second data DATA2 or save the second data DATA2 to a storage device connected to the second storage unit 113.

[0056] In this embodiment, the first storage unit 112 writes the first data DATA1 into the second storage unit 113 through the buffer unit 12, realizing data movement and saving power consumption and cost.

[0057] In an embodiment of the present application, data operations are performed between the first storage unit 112 and the second storage unit 113. The first storage unit 112 sends a first control signal CTRL1 to the control circuit 121, and the second storage unit 113 sends a second control signal CTRL2 to the control circuit 121. The first control signal CTRL1 can be a write operation instruction or a read operation instruction, and the second control signal CTRL2 can be a write operation instruction or a read operation instruction.

[0058] This embodiment is described by taking the first control signal CTRL1 and the second control signal CTRL2 both being read operation instructions as an example. The first storage unit 112 reads the first data DATA1 based on the first control signal CTRL1, and the second storage unit 113 reads the second data DATA2 based on the second control signal CTRL2. The control circuit 121 controls the first buffer buf1 to close and the second buffer buf2 to close, that is, the control circuit 121 controls the output terminal of the first buffer buf1 to close and the output terminal of the second buffer buf2 to close; the third buffer buf3 obtains the first data DATA1 and the second data DATA2 from the first storage unit 112 and the second storage unit 113, that is, the first storage unit 112 transmits the first data DATA1 to the third buffer buf3, and the second storage unit 113 transmits the second data DATA2 to the third buffer buf3.

[0059] The control circuit 121 receives a fifth control signal from the first storage unit 112 or the second storage unit 113. The fifth control signal may be an exclusive OR instruction. The control circuit 121 controls the third buffer buf3 to perform an operation on the first data DATA1 and the second data DATA2 based on the fifth control signal, obtaining a first operation result. The third buffer buf3 transmits the first operation result to the first storage unit 112 or the second storage unit 113. For example, the control circuit 121 receives the fifth control signal from the second storage unit 113, controls the third buffer buf3 to perform an operation on the first data DATA1 and the second data DATA2 based on the fifth control signal to obtain a first operation result, and controls the output terminal of the second buffer buf2 to be opened. The second buffer buf2 transmits the first operation result to the second storage unit 113 as the second data DATA2 of the second storage unit 113.

[0060] In this embodiment, data operations are performed between the first storage unit 112 and the second storage unit 113 through the buffer unit 12, without the need for operations by the processor 30, reducing data transmission between the memory and the processor 30, alleviating the processor 30's demand for memory bandwidth, saving power consumption, and improving efficiency.

[0061] In an embodiment of the present application, the first storage unit 112 performs data operations through the buffer unit 12. The first control signal CTRL1 may include a first read operation signal and a first write operation signal. The control circuit 121 controls the first buffer buf1 to be closed and the second buffer buf2 to be closed based on the first read operation signal, that is, the output terminal of the first buffer buf1 is closed and the output terminal of the second buffer buf2 is closed. The first storage unit 112 reads the first data DATA1 and sends the first data DATA1 to the third buffer buf3. The control circuit 121 receives a sixth control signal from the first storage unit 112. The sixth control signal may be a bitwise inversion instruction. The control circuit 121 controls the third buffer buf3 to perform an operation on the first data, obtaining a second operation result.

[0062] The control circuit 121 controls the first buffer buf1 to be opened based on the first write operation signal, and transmits the second operation result to the first storage unit 112 through the third buffer buf3. That is, the control circuit 121 controls the output terminal of the first buffer buf1 to be opened, and the control circuit 121 controls the third buffer buf3 to transmit the second operation result to the first storage unit 112 through the first buffer buf1.

[0063] The first storage unit 112 of this embodiment performs data operations through the buffer unit 12 without the need for the processor 30 to perform operations, reducing data transmission between the memory and the processor 30, alleviating the processor 30's demand for storage bandwidth, saving power consumption, and improving efficiency.

[0064] In an embodiment of the present application, the second control signal CTRL2 includes a second read operation signal and a second write operation signal. The control circuit 121 controls the first buffer buf1 to close and the second buffer buf2 to close based on the second read operation signal. The second storage unit 113 reads the second data DATA2 and sends the second data DATA2 to the third buffer buf3. The control circuit 121 receives the sixth control signal from the second storage unit 113 and controls the third buffer buf3 to perform operations on the second data DATA2 based on the sixth control signal to obtain a third operation result. The control circuit 121 controls the second buffer buf2 to open based on the second write operation signal and transmits the third operation result to the second storage unit 113 through the third buffer buf3.

[0065] The second storage unit 113 of this embodiment performs data operations through the buffer unit 12 without the need for the processor 30 to perform operations, reducing data transmission between the memory and the processor 30, alleviating the processor 30's demand for storage bandwidth, saving power consumption, and improving efficiency.

[0066] Please refer to Figure 4 as shown in Figure 4 which is a schematic structural diagram of the second embodiment of the memory of the present application. At least two storage units of this embodiment include a first storage unit 712, a second storage unit 713, a third storage unit 715, and a fourth storage unit 716. At least one buffer unit includes a first buffer unit 723 and a second buffer unit 724. The first buffer unit 723 is respectively connected to the first storage unit 712 and the second storage unit 713. The second buffer unit 724 is respectively connected to the third storage unit 715 and the fourth storage unit 716. The first buffer unit 723 is connected to the second buffer unit 724.

[0067] Among them, the first buffer unit 723 is used to perform data operations on the first storage unit 712 and / or the second storage unit 713, and the second buffer unit 724 is used to perform data operations on the third storage unit 715 and / or the fourth storage unit 716, which are the same as the buffer unit 12 of the above embodiment performing data operations on two storage units 11, and will not be elaborated here.

[0068] The first buffer unit 723 of this embodiment is respectively connected to the first storage unit 712 and the second storage unit 713, and the second buffer unit 724 is respectively connected to the third storage unit 715 and the fourth storage unit 716. The first buffer unit 723 is connected to the second buffer unit 724, which can realize data transmission between the first buffer unit 723 and the second buffer unit 724, relieve the processor 30's demand for storage bandwidth, save power consumption, and improve efficiency.

[0069] Please refer to Figure 5 as shown in Figure 5 FIG. is a schematic structural diagram of the third embodiment of the memory of the present application. The memory of this embodiment includes a memory chip 81 and a buffer chip 82 stacked. The memory chip 81 and the buffer chip 82 are bonded together, that is, the memory of this embodiment is a 3D memory; for example, the memory chip 81 and the buffer chip 82 are connected by hybrid bonding technology to achieve 3D heterogeneous integration.

[0070] Among them, the memory chip 81 includes at least two storage units 811, and the storage unit 811 is the storage unit disclosed in the above embodiment. The buffer chip 82 includes at least one buffer unit 821, and the buffer unit 821 is the buffer unit disclosed in the above embodiment, which will not be elaborated here.

[0071] The buffer unit 821 is connected to the corresponding storage unit 811 through a hybrid bond. The buffer unit 821 has the data operation and arithmetic functions of the buffer unit in the above embodiment, and can realize data transmission between different storage units 811; and different two buffer units 821 are connected to realize data transmission; which will not be elaborated here.

[0072] Optionally, the memory and the processor 90 are bonded together, that is, the memory and the processor 90 are stacked. The buffer chip 82 is respectively connected to the memory chip 81 and the processor 90, so that the memory chip 81 and the processor 90 perform data transmission through the buffer chip 82. The memory of this embodiment is stacked with the processor 90, so that the distance between the memory and the processor 90 is closer to achieve higher data bandwidth.

[0073] Please refer to Figure 6 as shown in Figure 6 FIG. is a schematic flowchart of the first embodiment of the data operation method of the present application. The data operation method of this embodiment is applied to the above memory, and the data operation method includes the following steps:

[0074] S901: At least one of the two storage units 11 sends a control signal to the buffer unit 12.

[0075] S902: The buffer unit 12 performs data operations on the two storage units 11 based on the control signal.

[0076] Among them, the buffer unit 12 is connected to two of the at least two storage units 11. The buffer unit 12 receives a control signal from at least one of the two storage units 11 and performs data operations on the two storage units 11 based on the control signal, capable of realizing data movement, data copying, etc., saving power consumption and cost.

[0077] In several embodiments provided in the present application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0078] The units described as separate components may or may not be physically separated. The components shown as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0079] In addition, the functional units in each embodiment of the present application can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated units can be implemented in the form of hardware or in the form of software functional units.

[0080] The above are only the embodiments of the present application, and do not limit the patent scope of the present application. All equivalent structural or equivalent process transformations made according to the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, are equally included in the patent protection scope of the present application.

Claims

1. A memory, characterized in that, the memory includes at least two storage units and at least one buffer unit, the buffer unit is connected to two of the at least two storage units, the buffer unit receives a control signal from the storage units, and performs a data operation on the two storage units based on the control signal; the at least two storage units include a first storage unit and a second storage unit, and the buffer unit includes: a control circuit respectively connected to the first storage unit and the second storage unit; a buffer circuit respectively connected to the first storage unit, the second storage unit and the control circuit; the buffer circuit includes a first buffer, a second buffer and a third buffer, an input end of the first buffer and an input end of the second buffer are connected to an output end of the third buffer, an output end of the first buffer is connected to a physical interface of the first storage unit, an output end of the second buffer is connected to a physical interface of the second storage unit, and input ends of the third buffer are respectively connected to the physical interface of the first storage unit, the physical interface of the second storage unit and the control circuit; the first storage unit sends a first control signal to the control circuit, the control circuit generates a third control signal based on the first control signal, and sends the third control signal to the second storage unit, the control circuit controls the first buffer to be closed and the second buffer to be opened, and the first storage unit writes first data into the second storage unit through the third buffer and the second buffer to obtain second data of the second storage unit.

2. The memory according to claim 1, characterized in that, the control circuit is configured to receive a first control signal from the first storage unit, and / or receive a second control signal from the second storage unit; the control circuit controls the buffer circuit to perform a data operation on the first storage unit and the second storage unit based on the first control signal or / and the second control signal.

3. The memory according to claim 2, characterized in that, the control circuit generates a third control signal based on the first control signal, and outputs the third control signal to the second storage unit for controlling the second storage unit; the control circuit generates a fourth control signal based on the second control signal, and outputs the fourth control signal to the first storage unit for controlling the first storage unit.

4. The memory according to claim 1, characterized in that, The second storage unit sends a second control signal to the control circuit. The control circuit generates a fourth control signal based on the second control signal and sends the fourth control signal to the first storage unit. The first storage unit reads first data based on the fourth control signal. The control circuit controls the first buffer to close and the second buffer to open based on the second control signal. The first storage unit sends the first data to the second storage unit through the third buffer and the second buffer, so that the second storage unit reads the first data from the first storage unit, and then obtains the second data.

5. The memory according to claim 1, wherein, the first storage unit sends the first control signal to the control circuit, the second storage unit sends a second control signal to the control circuit, the control circuit controls the first buffer to close and the second buffer to close, the first storage unit transmits first data to the third buffer, and the second storage unit transmits second data to the third buffer; the control circuit receives a fifth control signal from the first storage unit or the second storage unit, and controls the third buffer to perform an operation on the first data and the second data based on the fifth control signal to obtain a first operation result; the third buffer transmits the first operation result to the first storage unit or the second storage unit.

6. The memory according to claim 1, wherein, the first control signal includes a first read operation signal and a first write operation signal. The control circuit controls the first buffer to close and the second buffer to close based on the first read operation signal. The first storage unit reads first data and sends the first data to the third buffer; the control circuit receives a sixth control signal from the first storage unit and controls the third buffer to perform an operation on the first data based on the sixth control signal to obtain a second operation result; the control circuit controls the first buffer to open based on the first write operation signal and transmits the second operation result to the first storage unit through the third buffer.

7. The memory according to claim 1, wherein, the second control signal includes a second read operation signal and a second write operation signal. The control circuit controls the first buffer to close and the second buffer to close based on the second read operation signal. The second storage unit reads second data and sends the second data to the third buffer; the control circuit receives a sixth control signal from the second storage unit and controls the third buffer to perform an operation on the second data based on the sixth control signal to obtain a third operation result; the control circuit controls the second buffer to open based on the second write operation signal and transmits the third operation result to the second storage unit through the third buffer.

8. The memory according to claim 1, wherein, The at least two storage units include a first storage unit, a second storage unit, a third storage unit, and a fourth storage unit. The at least one buffer unit includes a first buffer unit and a second buffer unit. The first buffer unit is respectively connected to the first storage unit and the second storage unit. The second buffer unit is respectively connected to the third storage unit and the fourth storage unit. The first buffer unit is connected to the second buffer unit.

9. The memory according to any one of claims 1-8, wherein, the memory includes a memory chip and a buffer chip stacked and arranged, the memory chip and the buffer chip are bonded and connected, the memory chip includes the at least two storage units, and the buffer chip includes at least one of the buffer units.

10. The memory according to claim 9, wherein, the memory and the processor are bonded and connected, and the buffer chip is respectively connected to the memory chip and the processor, so that the memory chip and the processor perform data transmission through the buffer chip.

11. A data operation method for a memory, wherein, applied to the memory according to any one of claims 1-10, the data operation method includes: at least one of the two storage units sends a control signal to the buffer unit; the buffer unit performs data operation on the two storage units based on the control signal.

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