Optimization method, verification method, and storage medium for a circuit containing uncertain signals
By mapping the circuit to a simple structure and optimizing uncertain signals into deterministic signals, the uncertainty problem in tieX and tieZ signal processing is solved, thereby achieving accurate circuit verification and efficient resource utilization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN STATE MICRO TECH CO LTD
- Filing Date
- 2022-04-29
- Publication Date
- 2026-07-07
AI Technical Summary
The existing technology does not clearly show how to set the tieX and tieZ signals, resulting in inaccurate circuit optimization and verification results.
The circuit is mapped into a simple structure containing only AND and NOT gates. The AND and NOT gates with uncertain input signals are traversed and optimized to transform them into deterministic signals. The equivalence of the circuit is then verified using an equivalence verification tool.
To avoid uncertainties during verification, normalized tieX and tieZ processing methods were explored to ensure the accuracy of verification results and the effective use of resources.
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Figure CN114970420B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the technical field of formal verification, and in particular to an optimization method and an equivalence verification method for circuits containing uncertain signals. Background Technology
[0002] In circuit design, some RTL (Register Transfer Level) designs may have bugs or be incomplete during implementation, such as uninitialized elements or black box outputs, or the designer may intentionally set uncertain signals, such as setting tieX and / or tieZ values, which can lead to uncertain signals in the RTL design.
[0003] The tieX signal indicates "don't care," meaning that in this case, the synthesizer will synthesize the circuit so that it conforms to the specification regardless of whether tieX is 0 or 1. Introducing the uncertain signal tieX changes the circuit from two-valued logic to three-valued logic. The uncertain value of X, acting as a constant, will also propagate through the circuit along with the definite signals, namely the constant 1 and the constant 0.
[0004] The specific methods of transmission are shown in the table below.
[0005]
[0006] As shown in the diagram, when one input of the AND gate is X, the output of the AND gate is 0 only if the other input is 0; otherwise, it outputs X. When one input of the OR gate is X, the other input must be 1 for the OR gate to output 1; otherwise, it outputs X. When the input of the NOT gate is X, it outputs X. Although constant propagation will eliminate some X in the circuit, some X will still not be optimized away, thus allowing uncertain signals to continue to exist in the circuit (e.g., X is one input of the AND gate, and the other input is the output of combinational logic).
[0007] tieZ, also known as high-impedance state, refers to an output state of a circuit that is neither high nor low. If this high-impedance state drives the next stage of a circuit, it has no effect on that stage. In extreme cases, it can be considered floating. Because using tieZ signals in circuit design can effectively save bus resources, it is commonly used in circuit design.
[0008] Different logic synthesis tools or verification tools have their own unique default handling methods for the tieX and tieZ signals. For example, they may assign tieX and tieZ a default value of 0, or treat them directly as additional PI (input ports). Therefore, when performing equivalence verification on the design before and after synthesis, the formal verification tool needs to be configured in the same way as the different logic synthesis tools to make the equivalence verification results more authoritative.
[0009] However, in many cases, due to reasons such as technical confidentiality, when using logic synthesis tools, it is impossible to clearly know how the logic synthesis tool handles tieX and tieZ. Therefore, how to set tieX and tieZ can only be done by guessing and observation, which leads to inaccurate verification results.
[0010] Therefore, how to provide a circuit optimization method that is highly adaptable to tieX and / or tieZ is a technical problem that the industry urgently needs to solve. Summary of the Invention
[0011] To address the technical problem in existing technologies where the method for setting uncertain signals is not clearly known, this invention proposes an optimization method, a verification method, and a storage medium for circuits containing uncertain signals.
[0012] The present invention proposes an optimization method for circuits containing uncertain signals, wherein the uncertain signals contained in the circuit include at least one of tieX and tieZ, and the optimization method includes:
[0013] The circuit to be verified for equivalence is mapped into a simple circuit structure containing only AND and NOT gates;
[0014] The simple circuit structure is traversed, and AND and / or NOT gates with uncertain input signals are optimized to transform the uncertain input signals into certain signals.
[0015] Furthermore, the simple circuit structure is traversed, and AND and / or NOT gates with uncertain input signals are optimized to transform the input signals from uncertain signals to certain signals. Specifically, this includes:
[0016] If one of the input ports of any AND gate in the circuit is driven by an uncertain signal, the currently traversed AND gate is deleted, and the other input port of the AND gate is directly connected to the output port of the AND gate.
[0017] If the input port of any NOT gate in the circuit is driven by an uncertain signal, the currently traversed NOT gate is deleted, and the input port of the NOT gate is directly connected to the output port of the NOT gate.
[0018] Furthermore, mapping the circuit to be verified for equivalence into a simple circuit structure containing only AND and NOT gates specifically includes:
[0019] The circuit to be verified is divided into multiple sub-circuits;
[0020] Map all sub-circuits into multiple simple circuit structures.
[0021] Furthermore, during the traversal process, a search space is first created for each gate of the circuit whose output is not an uncertain signal, and then the circuit is optimized.
[0022] The search space is connected to the input ports of the corresponding optimized circuit through AND gates or NOT gates to form a combinational logic circuit of the optimized circuit and its search space.
[0023] Furthermore, the process of creating a search space for each gate in the optimized circuit whose output is not an uncertain signal during the traversal specifically includes:
[0024] Add the expression whose output of the currently traversed gate is not an indeterminate signal to the search space;
[0025] Based on whether the currently traversed gate is an AND gate or a NOT gate, the combined expression of the input ports of the currently traversed gate whose output is not an uncertain signal is derived, and the expressions of the currently traversed gates whose output is not an uncertain signal in the search space are updated with the derived combined expression.
[0026] Furthermore, when the currently traversed gate is an AND gate, the combinatorial expression for the corresponding search space PC is PC =
[0027] {(a!=X&b!=X)|(a=X&b=0)|(a=1&b!=X)}, or the corresponding combinatorial expression of the search space PC is PC={(a!=Z&b!=Z)|(a=Z&b=0)|(a=1&b!=X)}.
[0028] Z)}.
[0029] Furthermore, when the currently traversed gate is a NOT gate, the combinatorial expression of the corresponding search space PC is PC = {a ! = X}, or the combinatorial expression of the corresponding search space PC is PC = {a ! = Z}.
[0030] The present invention proposes an equivalent verification method for circuits containing uncertain signals, comprising:
[0031] The original RTL circuit is optimized using the optimization method for circuits containing uncertain signals described in the above technical solution;
[0032] The netlist design circuit is optimized using the optimization method for circuits containing uncertain signals described in the above technical solution;
[0033] The optimized original RTL circuit or its sub-circuit is matched with the optimized netlist design circuit or its sub-circuit in pairs. The two matched circuits are set to share a common input port, and the output ports of the two circuits are connected through an XOR gate. Then, the output port of the XOR gate is connected to the search space of the original RTL circuit through an AND gate to form the connected circuit.
[0034] The equivalence verification tool is used to verify the connected circuit. If a combination of input signals that makes the output of the connected circuit 1 can be found, then the original RTL circuit or its sub-circuit is equivalent to the corresponding netlist design circuit or its sub-circuit.
[0035] Furthermore, when the output of the connected circuit is always 0, if the input signal of the XOR gate is 0, then the optimized original RTL circuit or its sub-circuit is equivalent to the corresponding optimized netlist design circuit or its sub-circuit.
[0036] The present invention proposes a computer-readable storage medium for storing a computer program, which, when executed, performs the optimization method for circuits containing uncertain signals as described in the above technical solution.
[0037] This invention optimizes uncertain signals into deterministic signals, avoiding the uncertainties inherent in traditional methods, and explores a normalized tieX and tieZ processing method. This avoids the need for real-time adjustments to the verification scheme based on the comprehensive solution during validation, and also prevents resource waste due to design flaws in the verification scheme. After using this invention, all examples in the original test set still passed validation, and the validation results were indistinguishable from the original scheme. This invention, while ensuring the correctness of the validation results, solves the various trivial problems caused by different tieX and tieZ processing methods in traditional schemes. Attached Figure Description
[0038] The present invention will now be described in detail with reference to the embodiments and accompanying drawings, wherein:
[0039] Figure 1 This is a flowchart of the present invention.
[0040] Figure 2 This is an optimized schematic diagram of the tieX signal in the case of AND gate and NAND gate of the present invention.
[0041] Figure 3 This is an example circuit of the present invention.
[0042] Figure 4 This is the golden circuit under PC constraint of the present invention.
[0043] Figure 5 This is the SAT verification circuit under PC constraints of the present invention. Detailed Implementation
[0044] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.
[0045] Therefore, a feature pointed out in this specification is used to describe one feature of one embodiment of the invention, and does not imply that every embodiment of the invention must have the described feature. Furthermore, it should be noted that this specification describes many features. Although certain features may be combined to illustrate possible system designs, these features may also be used in other combinations not explicitly stated. Therefore, unless otherwise stated, the described combinations are not intended to be limiting.
[0046] In the optimization method for circuits containing uncertain signals proposed in this invention, the uncertain signals in the circuit include at least one of tieX or tieZ. The circuit can contain tieX, tieZ, or both, which facilitates subsequent operations. Then, the simple circuit structure is traversed, and AND and / or NOT gates with uncertain input signals are optimized to transform their input signals from uncertain to certain, i.e., tieX and tieZ are converted to 0 and 1, respectively. The optimized circuit no longer contains uncertain signals in its input and output signals, thus eliminating uncertainty when using logic synthesis tools.
[0047] First, the circuit to be verified for equivalence is mapped into a simple circuit structure containing only AND and NOT gates. Then, the simple circuit structure is traversed, and the AND and / or NOT gates with uncertain input signals are optimized to transform the uncertain input signals into certain signals.
[0048] When the uncertain signal is tieX, the simple structure circuit is traversed, and the AND gates and / or NOT gates with uncertain input signals are optimized to transform the input signals from uncertain signals to certain signals. The specific steps are as follows.
[0049] If an input port of any AND gate in the circuit is driven by an indeterminate signal tieX, the currently traversed AND gate is deleted, and the other input port of that AND gate is directly connected to its output port.
[0050] If the input port of any NOT gate in the circuit is driven by the uncertain signal tieX, the currently traversed NOT gate is deleted, and the input port of the NOT gate is directly connected to the output port of the NOT gate.
[0051] When the uncertain signal is tieZ, the simple structure circuit is traversed, and the AND gates and / or NOT gates whose output signals are uncertain signals are optimized so that their input signals are transformed from uncertain signals to certain signals. The specific steps are as follows.
[0052] If the output port of any NOT gate in the circuit is an uncertain signal tieZ, delete the NOT gate being traversed and connect the input port of the NOT gate directly to its output port.
[0053] The above technical solution targets simple, original circuits, meaning the circuit to be verified as an equivalence test is a simple, original RTL circuit, also known as an original Golden circuit, or a simple netlist design circuit, also known as a Revised circuit. If the original RTL circuit and netlist design circuit have relatively complex structures, then the following processing can be performed.
[0054] In one embodiment, the circuit is divided into multiple sub-circuits, and each sub-circuit is mapped to multiple simple circuit structures.
[0055] Taking the processing of the original RTL circuit as an example, when processing the original RTL circuit, it is also necessary to first create a search space for each gate in the original RTL circuit whose output is not an uncertain signal during the traversal process, then optimize the original RTL circuit, and then connect the search space to the input port of the corresponding optimized original RTL circuit through AND gates or NOT gates to form the combinational logic circuit corresponding to the optimized original RTL circuit.
[0056] Taking a netlist-based circuit design as an example, it is only necessary to optimize the netlist-based circuit design to convert the uncertain tieX and / or tieZ signals into deterministic signals. There is no need to generate the corresponding search space.
[0057] In specific implementation, creating a search space for each gate in the optimized circuit whose output is not an uncertain signal during the traversal process includes: adding the expression for the currently traversed gate whose output is not an uncertain signal to the search space; deriving the combined expression of the input ports of the currently traversed gate whose output is not an uncertain signal based on whether the currently traversed gate is an AND gate or a NOT gate; and updating the expression for the currently traversed gate whose output is not an uncertain signal in the search space to the derived combined expression. If the currently traversed gate is an AND gate, the combined expression of the corresponding search space PC is PC = {(a!=X&b!=X)|(a=X&b=0)|(a=1&b!=X)}, or the combined expression of the corresponding search space PC is PC = {(a!=Z&b!=Z)|(a=Z&b=0)|(a=1&b!=Z)}. If the currently traversed gate is a NOT gate, the combined expression of the corresponding search space PC is PC = {a!=Z&b!=Z}. =X}, or the combined expression of the corresponding search space PC is PC = {a! = Z}.
[0058] The present invention also proposes an equivalence verification method for circuits containing uncertain signals. This method first optimizes the original RTL circuit to be verified using the optimization method for circuits containing uncertain signals described above, to obtain the optimized original RTL circuit or sub-circuits of multiple optimized original RTL circuits, and their corresponding search spaces.
[0059] Next, the netlist design circuit to be verified for equivalence is optimized using the optimization method for circuits containing uncertain signals described in the above technical solution, resulting in an optimized netlist design circuit or a sub-circuit of multiple optimized netlist design circuits.
[0060] The optimized original RTL circuit or its sub-circuit is matched with the optimized netlist design circuit or its sub-circuit in pairs. The two matched circuits are set to share a common input port. The output ports of the two matched circuits are connected through an XOR gate. The output port of the XOR gate is then connected to the corresponding search space through an AND gate to form the connected circuit.
[0061] The equivalence verification tool is used to verify the connected circuit. If a combination of input signals that makes the output of the connected circuit 1 can be found, then the original RTL circuit or its sub-circuit to be verified is equivalent to the corresponding netlist design circuit or its sub-circuit to be verified.
[0062] If the output of the connected circuit is always 0, and the input signal of the XOR gate is 0, then the optimized original RTL circuit or its sub-circuit is equivalent to the corresponding optimized netlist design circuit or its sub-circuit. All other cases are not equivalent.
[0063] The following uses the original golden circuit (original RTL circuit) and a revised circuit (netlist design circuit) that require equivalence verification as examples to illustrate the specific implementation of the present invention.
[0064] The original golden circuit (original RTL circuit) and the revised circuit are divided into register units. The output of the register in the divided sub-circuit is used as PO (Put Out). If this register drives other registers, the PO of this register is used as the PI of the driven register. The split sub-circuits are smaller in size, which is beneficial for subsequent operation and verification.
[0065] Match the sub-circuits of the original golden circuit to the corresponding sub-circuits of the revised circuit.
[0066] Next, the sub-circuit can be mapped to the AIG format. Since the AIG format only contains AND gates and NOT gates, after the original Golden circuit is mapped to AIG, all primitives are converted into combinations of AND and NOT gates. This simple circuit structure facilitates subsequent operations. Besides mapping the sub-circuit to the AIG format for conversion, other conversion methods can also be used, all of which fall within the scope of this invention.
[0067] Next, a depth-first traversal is performed on the sub-circuit from PO to PI (Put In). In other embodiments, the sub-circuit can also be traversed from PI to PO, but the processing method during the traversal needs to be adjusted accordingly.
[0068] When a tieX signal is detected, we optimize the sub-circuit of the original golden circuit to remove the tieX signal present in the sub-circuit. The specific optimization method is as follows: Figure 2 As shown.
[0069] When one input port of an AND gate is driven by X, the AND gate is removed, and the other input is directly connected to the output port. When a NOT gate is driven by X, the NOT gate is removed, and its input port is directly connected to the output port, continuing to propagate X. When the tieX signal directly drives the AND gate, this X is completely removed.
[0070] Next, construct the non-X search space PC(!X).
[0071] While traversing the circuit, we also need to create a search space PC(!X) for each gate we traverse, where the output is not X, and connect the created search space circuit to the corresponding port in the original golden circuit through AND, OR, and NOT gates. We use Figure 3 The circuit shown illustrates the basic derivation of the search space for non-X.
[0072] like Figure 3 As shown, signals a and b are the original inputs PI of this example circuit, and signal o is the original output PO. If we want the output of PO to be non-X, then the input c of the NOT gate cannot be X. The constraint c! = X is added to the search space, i.e., PC = {c! = X}. Further derivation shows that when the output c! = X of the AND gate, the input signals a and b of the AND gate must satisfy one of the following three assignment conditions: (a! = X & b! = X), (a = X & b = 0), or (a = 1 & b! = X) to make c! = X. This leads to a new non-X search space PC = {(a! = X & b! = X) | (a = X & b = 0) | (a = 0 & b! = X)}.
[0073] After the circuit traversal is complete, we obtain the following: Figure 4 The original Golden circuit shown is a combinational logic circuit with its search space.
[0074] The constructed search space circuit serves as a constraint, equivalent to a branch of the original Golden circuit, sharing PI with the original Golden circuit. The final output port PC of the PC circuit represents the search space PC(!X) where the original Golden circuit's final output is not X.
[0075] Next, equivalence verification is performed.
[0076] In this embodiment, the equivalence verification between the original golden circuit and the revised circuit is performed using the SAT tool. The SAT tool reads a circuit and determines whether a solution for PI can be found such that the final output of the circuit is 1. If a solution can be found, the output is "satisfied," meaning the two are equivalent; otherwise, the output is "unsatisfied," meaning the two are not equivalent.
[0077] We establish a miter (connection) between the sub-circuits of the optimized original golden circuit and the sub-circuits of the revised circuit. That is, the corresponding sub-circuits of the original golden circuit and the matching sub-circuits of the revised circuit share the input PI, and the output PO is connected using an XOR gate. Then, an AND gate is used to connect the miter output miter_po to port PC. The final circuit to be verified is as follows. Figure 5 As shown.
[0078] If the SAT tool is used to solve this circuit, and no set of values for PI can be found that makes Final = 1, SAT returns unsatisfied. The two circuits to be verified as equivalent are then considered equivalent.
[0079] When no set of values for the input PI can be found that makes the final output FINAL_PO = 1, that is, the final output FINAL_PO is always 0 regardless of the value of PI. Therefore, MITER_PO, as the input of the AND gate, and PC have three input cases:
[0080] 1. When the MITER_PO port input value is 0 and the PC port input value is 1:
[0081] The output MITER_PO serves as the output of the XOR gate. Based on the characteristic that an XOR gate outputs 0 when the two inputs are equal and 1 when they are unequal, MITER_PO = 0 indicates that the simplified golden sub-circuit is equivalent to the revised sub-circuit. PC = 1 indicates that the search space exists. Therefore, given the existence of the search space, the sub-circuit design of the revised circuit conforms to the sub-circuit design of the simplified original golden circuit, and the two sub-circuits are equivalent.
[0082] 2. When the output MITER_PO port input value is 1 and the PC port input value is 0:
[0083] When the output MITER_PO = 1, the simplified golden sub-circuit and the revised sub-circuit are not equivalent. PC = 0 indicates that the non-X search space does not exist, meaning the output of golden is always X. Based on the characteristic that X can be 0 or 1, we can determine that the two sub-circuits are not equivalent.
[0084] 3. When the MITER_PO port input value is 0 and the PC port input value is 0:
[0085] The non-X search space does not exist, and the simplified golden subcircuit is equivalent to the revised subcircuit.
[0086] In summary, under all cases where the final output FINAL_PO = 0, it can be determined that the sub-circuit of the revised circuit conforms to the sub-circuit design of the corresponding original golden circuit, that is, the two circuits are equivalent under the constraint PC.
[0087] Repeat the above operation for the sub-circuits of each matched original golden circuit and revised circuit. When all matched sub-circuits can be proven to be equivalent, we can determine that the original golden circuit and the revised circuit are equivalent.
[0088] The present invention also protects a corresponding computer-readable storage medium used to store a computer program that, when executed, performs the optimization method for circuits containing uncertain signals according to the above-described technical solution of the present invention.
[0089] The focus of this invention is the aforementioned search space-based tieX and tieZ optimization strategy to address the flexible handling of tieX and tieZ signals in synthesizers and verification tools. Specifically, during equivalence verification, the golden and revised circuits are first segmented and matched one-to-one based on registers. Then, the tieX and tieZ signals present in the golden sub-design are processed to optimize the circuit and extract the search space PC(!X) that prevents the original output PO of the circuit from being X. This search space is used as a constraint on the golden and revised sub-circuits. It is proven that the two sub-circuits are equivalent under this constraint, and by utilizing the characteristics of X, it is further proven that the two sub-circuits are always equivalent under all assignments. Finally, it is proven that the revised design satisfies the golden design, and the two designs are equivalent. In addition, the focus of this invention also includes the relevant flowcharts illustrating this scheme, the relevant code for implementing this scheme, and the relevant SAT calculation tools using this scheme.
[0090] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A method for optimizing a circuit containing uncertain signals, wherein the uncertain signals in the circuit include at least one of tieX and tieZ, characterized in that, The optimization method includes: The circuit is mapped into a simple circuit structure containing only AND and NOT gates; The simple circuit structure is traversed, and AND and / or NOT gates with uncertain input signals are optimized to transform the uncertain input signals into certain signals, including: If one of the input ports of any AND gate in the circuit is driven by an uncertain signal, the currently traversed AND gate is deleted, and the other input port of the AND gate is directly connected to the output port of the AND gate. If the input port of any NOT gate in the circuit is driven by an uncertain signal, delete the NOT gate being traversed and connect the input port of the NOT gate directly to the output port of the NOT gate. In the traversal process, a search space is first created for each gate of the circuit whose output is not the uncertain signal. Then, each gate of the optimized circuit is connected to the corresponding search space to form a combinational logic circuit of the optimized circuit and its search space.
2. The optimization method for circuits containing uncertain signals as described in claim 1, characterized in that, Mapping the circuit into a simple circuit structure containing only AND and NOT gates specifically includes: The circuit to be verified is divided into multiple sub-circuits; Map all sub-circuits into multiple simple circuit structures.
3. The optimization method for circuits containing uncertain signals as described in claim 1, characterized in that, The process of creating a search space for each gate in the optimized circuit whose output is not an uncertain signal during the traversal includes: Add the expression whose output of the currently traversed gate is not an indeterminate signal to the search space; Based on whether the currently traversed gate is an AND gate or a NOT gate, the combined expression of the input ports that makes the output of the currently traversed gate not an uncertain signal is derived, and the expression in the search space that makes the output of the currently traversed gate not an uncertain signal is updated to the derived combined expression.
4. The optimization method for circuits containing uncertain signals as described in claim 3, characterized in that, When the currently traversed gate is an AND gate, the combinatorial expression of the corresponding search space PC is PC = {(a != X & b != X) | (a = X & b = 0) | (a = 1 & b != X)}, or the combinatorial expression of the corresponding search space PC is PC = {(a != Z & b != Z) | (a = Z & b = 0) | (a = 1 & b != Z)}.
5. The optimization method for a circuit containing uncertain signals as described in claim 3, characterized in that, When the currently traversed gate is a NOT gate, the combinatorial expression of the corresponding search space PC is PC = {a != X}, or the combinatorial expression of the corresponding search space PC is PC = {a != Z}.
6. An equivalence verification method for a circuit containing uncertain signals, characterized in that, include: The original RTL circuit is optimized using the optimization method for circuits containing uncertain signals as described in any one of claims 1 to 5; The netlist design circuit is optimized using the optimization method for circuits containing uncertain signals as described in claim 1 or 2. The optimized original RTL circuit or its sub-circuit is matched with the optimized netlist design circuit or its sub-circuit in pairs. The two matched circuits are set to share a common input port. The output ports of the two matched circuits are connected through an XOR gate. The output port of the XOR gate is then connected to the search space of the original RTL circuit through an AND gate to form the connected circuit. The equivalence verification tool is used to verify the connected circuit. If a combination of input signals that makes the output of the connected circuit 1 can be found, then the original RTL circuit or its sub-circuit is equivalent to the corresponding netlist design circuit or its sub-circuit.
7. The equivalent verification method for circuits containing uncertain signals as described in claim 6, characterized in that, When the output of the connected circuit is always 0, if the input signal of the XOR gate is 0, then the optimized original RTL circuit or its sub-circuit is equivalent to the corresponding optimized netlist design circuit or its sub-circuit.
8. A computer-readable storage medium for storing a computer program, characterized in that, When the computer program is executed, it performs the optimization method for circuits containing uncertain signals as described in any one of claims 1 to 5.