Switching device with fin structure, logic nor gate circuit, and method of manufacturing the same

Abstract

The application provides a preparation method of a switch device with a fin structure, comprising the following steps: S1, preparing a substrate; S2, performing ion implantation to prepare spaced source ohmic contact regions and drain ohmic contact regions; S3, removing part of the barrier layer under the gate; S4, forming a gate material layer covering the barrier layer; S5, etching the gate material layer to form a gate with an initial morphology; S6, forming a fin structure with the gate on the fin structure; S7, forming a passivation layer covering the fin structure; and S8, forming a lead electrode electrically connected with the source ohmic contact region, the drain ohmic contact region and the gate respectively. The application can keep the device always off without an external voltage, realizes better gate control ability by using the fin structure, effectively utilizes the substrate area and reduces the device size. In addition, the ion implantation process is used to form a lower ohmic contact resistance, which can reduce the device working energy consumption, improve the device performance and production yield.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, specifically to a power switching device, and particularly to a switching device with a fin structure, a logic NOR gate circuit, and a method for fabricating the same. Background Technology

[0002] Third-generation semiconductor materials such as GaN (gallium nitride) possess wide bandgap characteristics, allowing devices fabricated from them to operate at higher temperatures and exhibiting good radiation resistance. In high-temperature, high-radiation environments, temperature and cosmic ray irradiation can affect the bandgap of semiconductors, narrowing the bandgap of silicon materials and generating more intrinsic charge carriers. This causes a shift in the threshold voltage of traditional silicon-based devices, affecting the operating voltage of switches. GaN, with its wider bandgap, offers greater resistance to temperature and radiation. Furthermore, because GaN devices conduct electricity through a two-dimensional electron gas generated by polarization, and electrons have high mobility, GaN devices exhibit higher switching speeds, enabling them to respond to voltage signals more quickly than traditional silicon-based devices. These advantages have led to the increasing attention and application of GaN-based devices.

[0003] Due to the polarization effect, a two-dimensional electron gas layer is distributed on the surface of the GaN channel layer. Controlling the pinch-off of these two-dimensional electrons is crucial for achieving device turn-off. For GaN switching devices, a large current generated by the two-dimensional electron gas is not required; on the contrary, the lower the concentration of the generated two-dimensional electron gas, the easier it is to pinch off the device. Existing switching devices, due to their structural characteristics, are in a normally-on state, which increases device power consumption and operating costs. Furthermore, existing technologies use metal sputtering followed by alloy annealing to form ohmic contacts, which results in a relatively rough metal surface, making it difficult to form low-value ohmic contact resistances.

[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a switching device with a fin structure, a logic NOR gate circuit, and a method for fabricating the same, to solve the problem that existing switching devices are in a normally open state due to their structural characteristics, which increases device power consumption and operating costs. Furthermore, the prior art uses metal sputtering followed by alloy annealing to form ohmic contacts, which results in a relatively rough metal surface, making it difficult to form low-value ohmic contact resistances.

[0006] To achieve the above and other related objectives, the present invention provides a method for fabricating a switching device with a fin structure, comprising the following steps:

[0007] S1: Prepare a substrate, which includes a substrate layer, a buffer layer, a channel layer and a barrier layer stacked on top of each other;

[0008] S2: Ion implantation is performed on the substrate to prepare spaced source ohmic contact regions and drain ohmic contact regions on the substrate, the source ohmic contact regions and drain ohmic contact regions extending downward to contact the channel layer;

[0009] S3: Remove part of the barrier layer located below the gate;

[0010] S4: Gate material layer forming the covering barrier layer;

[0011] S5: Etch the gate material layer to form a gate with an initial morphology;

[0012] S6: Etch the barrier layer, channel layer and part of the buffer layer except for the area below the gate to form a fin structure, with the gate located on the fin structure;

[0013] S7: Forms a passivation layer covering the fin structure;

[0014] S8: Forms lead-out electrodes that are electrically connected to the source ohmic contact region, the drain ohmic contact region, and the gate, respectively.

[0015] Optionally, the substrate further includes an insertion layer and a cap layer, the insertion layer being located between the channel layer and the barrier layer, the cap layer being located above the barrier layer, and the bandgap of the insertion layer being greater than the bandgap of the barrier layer.

[0016] Optionally, the material of the cap layer is the same as the material of the channel layer.

[0017] Optionally, the substrate layer includes several of silicon substrates, silicon carbide substrates, sapphire substrates, and silicon nitride substrates; the buffer layer includes a GaN layer; the channel layer and barrier layer include several of GaN layers, AlN layers, AlGaN layers, InGaN layers, and InAlN layers; and the insertion layer includes an AlN layer.

[0018] Optionally, step S2 includes:

[0019] A passivation layer is formed on the substrate surface using LPCVD technology, the passivation layer comprising a SiN layer;

[0020] Photolithography is performed to form windows in the passivation layer that expose the source ohmic contact region and the drain ohmic contact region;

[0021] Ion implantation is performed on the substrate exposed in the window to form heavily doped source and drain ohmic contact regions, and the implanted ions include silicon ions.

[0022] Remove the residual passivation layer by etching with BOE etchant.

[0023] Optionally, the method for removing part of the barrier layer in step S3 includes etching using an inductively coupled plasma etching process after the desired pattern is defined by photolithography, wherein the etching gas includes Cl2 and BCl3, and then NMP and IPA are used to remove the residual photoresist layer.

[0024] Optionally, step S4 includes first using oxygen plasma to remove residual photoresist from the surface, then using BOE solution to treat and etch the oxide on the substrate surface, and then using MOCVD to epitaxially grow a 30nm magnesium-doped GaN layer as the gate material layer.

[0025] Optionally, the method for etching the gate material layer includes: using photolithography to shield the Schottky electrode area, and then using inductively coupled plasma etching to etch the unshielded magnesium-doped GaN layer to obtain the initial morphology of the P-type Schottky gate.

[0026] Optionally, forming the lead-out electrode includes:

[0027] The passivation layer was etched using inductively coupled plasma etching to expose the source ohmic contact region and the drain ohmic contact region.

[0028] Metal layers are formed that are in contact with the source ohmic contact region and the drain ohmic contact region respectively, and then subjected to high-temperature annealing, thereby forming the source ohmic electrode and the drain ohmic electrode.

[0029] A window exposing the gate is formed in the passivation layer using photolithography etching. After removing the residual photoresist layer, BOE solution is used to remove oxides from the etched window and reduce surface roughness. Then, the substrate is surface treated in hot ammonia water and the gate window is redefined.

[0030] A metal layer that is in electrical contact with the gate is formed and then subjected to high-temperature annealing, thereby forming the gate electrode.

[0031] Optionally, in step S7, a SiN layer is deposited as a passivation layer using a PECVD process. The gas used to etch the passivation layer includes CF4, the temperature of the hot ammonia water is 50℃-60℃, the ammonia water treatment time is 3min-10min, the source ohmic electrode and the drain ohmic electrode are made of a titanium layer and a gold layer and / or a platinum layer located on the titanium layer, and the gate electrode includes a titanium layer and several of the nickel layer, gold layer and platinum layer located on the titanium layer.

[0032] Optionally, the lead-out electrode electrically connected to the gate extends from the upper surface of the gate to the side of the gate to form a semi-enclosed structure of the gate.

[0033] The present invention also provides a logic NOR gate circuit, which includes two switching devices with fin structures prepared by the preparation method described in any of the above schemes. The gates of the two switching devices serve as inputs, the sources are connected to each other and grounded through pull-down resistors, and the drains are connected to each other and connected to a power supply through pull-up resistors.

[0034] The present invention also provides a method for fabricating a logic NOR gate circuit, the method comprising:

[0035] A substrate is provided, and two symmetrically fabricated switching devices with fin structures are completed in two mutually isolated active regions of the substrate using the fabrication method described in any of the above schemes.

[0036] Connect the gate, source, and drain of the two switching devices and electrically bring them out.

[0037] Optionally, after providing the substrate, a passivation layer is first deposited on the substrate surface using LPCVD, then an exposure and development process is used to define spaced active regions on the substrate, followed by nitrogen ion implantation to isolate two adjacent active regions from each other.

[0038] As described above, the fin-structured switching device, logic NOR gate circuit, and fabrication method of the present invention have the following beneficial effects: The improved structure and process design of the present invention fabricates a fin-gate switching device, which can achieve normally-off operation without an external voltage, reducing device power consumption, circuit design complexity, and design and usage costs. The fin structure achieves better gate control capability, effectively utilizing the substrate area and reducing device size. Furthermore, the present invention uses ion implantation to form ohmic contacts, thus allowing the ohmic contact electrodes to be drawn at a lower temperature (500°C), helping to ensure good device morphology and achieving lower ohmic contact resistance, thereby improving device performance. The fabrication process is simple, contributing to improved production efficiency and yield, and reducing production costs. Attached Figure Description

[0039] Figure 1 The flowchart shown is a method for fabricating a finned switching device provided by the present invention.

[0040] Figure 2 The diagram shows an exemplary cross-sectional view of the structure obtained after the fabrication of the source-drain ohmic contact region is completed.

[0041] Figure 3 The diagram shows an exemplary cross-sectional view of the structure obtained after etching the gate to form the gate.

[0042] Figure 4 The diagram shown is an exemplary cross-sectional view of the structure obtained after depositing a gate material layer.

[0043] Figure 5 The diagram shown is an exemplary cross-sectional view of the structure obtained after fabricating a gate with an initial morphology.

[0044] Figure 6 The diagram shown is an exemplary cross-sectional view of the structure obtained after the gate fabrication is completed.

[0045] Figure 7 The diagram shows an exemplary cross-section of the structure obtained after the deposition of the passivation layer.

[0046] Figure 8 The diagram shows an exemplary cross-sectional view of the structure obtained after forming the source-drain ohmic contact region in the passivation layer.

[0047] Figure 9 The diagram shows an exemplary cross-sectional view of the structure obtained after forming the source and drain electrodes.

[0048] Figure 10 The diagram shows an exemplary cross-sectional view of the structure obtained after etching the gate electrode.

[0049] Figure 11 The diagram shown is an exemplary cross-sectional view of the structure obtained after fabricating the gate electrode.

[0050] Figure 12 The diagram shows an exemplary cross-section where the formed gate electrode is located only above the gate.

[0051] Figure 13 The diagram shown is an exemplary structural schematic illustrating the process of fabricating a semi-enclosed gate electrode.

[0052] Figure 14 Displayed as Figure 13 A schematic diagram of the cross-sectional structure.

[0053] Figures 15 to 17 The diagram shows an exemplary structure of a device with a semi-enclosed gate electrode, viewed from different sides.

[0054] Figure 18 The diagram shows a symmetrical arrangement of two switching devices with fin structures.

[0055] Figure 19 Displayed as Figure 18 The corresponding equivalent circuit diagram.

[0056] Figure 20 The diagram shown is a schematic diagram of the logic OR gate circuit provided by the present invention.

[0057] Figure 21 Displayed as Figure 20 The equivalent circuit diagram. Detailed Implementation

[0058] The following specific examples illustrate the embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. For ease of explanation, when detailing the embodiments of the present invention, the cross-sectional views showing the device structure are partially enlarged, not according to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0059] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0060] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0061] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components related to the present invention and are not drawn according to the actual number, shape, and size of the components in the actual implementation. In the actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex. To keep the illustrations as concise as possible, not all structures are shown in the figures.

[0062] like Figure 1 As shown, the present invention provides a method for fabricating a switching device with a fin structure, the method comprising the following steps:

[0063] S1: Prepare a substrate, which includes a substrate layer, a buffer layer, a channel layer and a barrier layer stacked on top of each other;

[0064] S2: Ion implantation is performed on the substrate to prepare spaced source ohmic contact regions and drain ohmic contact regions on the substrate, the source ohmic contact regions and drain ohmic contact regions extending downward to contact the channel layer, the source ohmic contact regions and drain ohmic contact regions being located at opposite ends of the device to be formed.

[0065] S3: Remove part of the barrier layer located below the gate;

[0066] S4: Gate material layer forming the covering barrier layer;

[0067] S5: Etch the gate material layer to form a gate with an initial morphology;

[0068] S6: Etch the barrier layer, channel layer and part of the buffer layer except for the area below the gate to form a fin structure. The gate is located on the fin structure, that is, the gate is a fin structure.

[0069] S7: Forms a passivation layer covering the fin structure;

[0070] S8: Forms lead-out electrodes that are electrically connected to the source ohmic contact region, the drain ohmic contact region, and the gate, respectively.

[0071] This invention utilizes an improved structural and process design to fabricate a switching device with a finned gate, enabling normally-off operation without an external voltage, reducing power consumption, circuit design complexity, and design and usage costs. The finned structure achieves superior gate control capability, effectively utilizing substrate area and minimizing device size. Furthermore, this invention employs ion implantation to form ohmic contacts, allowing for electrode formation at a lower temperature (500°C), ensuring good device morphology and achieving lower ohmic contact resistance, thus improving device performance. The fabrication process is simple, contributing to increased production efficiency and yield, and reducing production costs.

[0072] To further highlight the technical solution and advantages of the present invention, the following will be discussed in conjunction with the appendix. Figures 2 to 21 The present invention will be described in detail below.

[0073] First, step S1 is performed to prepare the substrate, which includes a substrate layer 11, a buffer layer 12, a channel layer 13, and a barrier layer 14 stacked on top of each other. This embodiment provides an enhancement device, with these structural layers stacked sequentially from bottom to top. The substrate layer 11 can be selected from, but is not limited to, several semiconductor substrates such as silicon substrates, silicon carbide substrates, sapphire substrates, and silicon nitride substrates. In this embodiment, a silicon carbide substrate or a silicon substrate is preferred. An epitaxial material layer, such as a GaN layer, is formed on the substrate.

[0074] In one example, the buffer layer 12 and the channel layer 13 are made of the same material. For example, if the substrate includes a GaN epitaxial layer, both the buffer layer 12 and the channel layer 13 include GaN layers, more specifically N-type GaN layers, but are not limited thereto. The buffer layer 12 can have a gradually changing doping concentration from the substrate layer 11 towards the channel layer 13, thereby mitigating problems such as lattice mismatch and thermal expansion coefficient mismatch between the substrate layer 11 and the channel layer 13. The channel layer 13 and the barrier layer 14 are typically made of different materials, thereby forming a heterojunction at their interface. Furthermore, due to polarization effects, a two-dimensional electron gas 22 is distributed on the surface of the channel layer 13. The channel layer 13 and the barrier layer 14 can be selected from, for example, but not limited to, GaN layers, AlN layers, AlGaN layers, InGaN layers, and InAlN layers. When these two structural layers contain the same elements, different doping concentrations can be used to give them different bandgap widths. The barrier layer 14 can be a single-layer structure or a stack of two or more material layers with different bandgap widths. For example, the barrier layer 14 may include AlN and AlGaN layers stacked on top of each other. This helps to improve the self-polarization capability of the barrier layer 14 and further increase the concentration of the two-dimensional electron gas 22, thereby helping to improve the electrical performance of the device. The buffer layer 12, the channel layer 13, and the barrier layer 14 are preferably formed using MOCVD technology. These structural layers are continuously fabricated on the substrate on the same device by adjusting parameters such as doping concentration and deposition time, which helps to simplify the fabrication process. However, the fabrication of these structural layers is not limited to this, and there are no strict restrictions. The thickness of the buffer layer 12 is, for example, 2μm-4μm, the thickness of the channel layer 13 can be 10nm-100nm, for example, 10, 20, 30, 40...100 or any value in this range, and the thickness of the barrier layer 14 can be 10nm-30nm, for example, 10, 15, 20, 25, 30 or any value in this range. In other examples, the buffer layer 12 and the substrate layer 11 can be a single structure, distinguished only by different concentrations of doping.

[0075] In one example, reference Figure 2As shown, the substrate further includes an insertion layer 15 and / or a cap layer 16, preferably having both structural layers simultaneously. For example, the cap layer 16 is a GaN layer, and the insertion layer 15 is an AlN layer. The insertion layer 15 is located between the channel layer 13 and the barrier layer 14, and the cap layer 16 is located above the barrier layer 14. The bandgap of the insertion layer 15 is larger than the bandgap of the barrier layer 14, and the material of the cap layer 16 is preferably the same as that of the channel layer 14. For example, in this embodiment, both the cap layer and the channel layer are made of GaN. The growth of the GaN cap layer 16 can reduce the relaxation in the AlGaN barrier layer 14 to increase the concentration of the two-dimensional electron gas 22, thereby increasing the transconductance and saturation current and improving the breakdown performance of the device. The AlN insertion layer 15 can better confine the two-dimensional electron gas 22 to the surface of the GaN channel layer 13, reduce the leakage current of the gate 21, and improve the DC performance. The thickness of the insertion layer 15 is preferably less than 10 nm, for example, 3 nm-5 nm.

[0076] It should be noted that in the actual device fabrication process, the substrate can be purchased externally, such as by contracting an epitaxial growth company, or the required structural layers can be fabricated on the purchased bare wafers at the chip manufacturing plant. There are no restrictions on this.

[0077] After providing the substrate, it can be cleaned and then dried to improve the cleanliness of the substrate surface.

[0078] After preparing the substrate, step S2 is performed: ion implantation is performed on the substrate to fabricate spaced source ohmic contact regions 17 and drain ohmic contact regions 18. For example, the source ohmic contact regions 17 and drain ohmic contact regions 18 are located at opposite ends of the device to be formed, and the source ohmic contact regions 17 and drain ohmic contact regions 18 extend downward to contact the channel layer 13. To ensure contact between these two ohmic contact regions and the channel layer 13, the ion implantation energy can be appropriately increased so that the implanted ions can enter the surface layer of the channel layer 13.

[0079] In one example, step S2 includes: forming a SiN passivation layer 19 on the substrate surface using an LPCVD process as a barrier layer to prevent silicon precipitation during ion implantation and activation. The passivation layer 19 includes, but is not limited to, a SiN layer, preferably with a thickness of less than 30 nm, for example, 20 nm, to minimize lattice mismatch with the substrate and prevent film cracking. Simultaneously, forming a thin SiN layer using the LPCVD process helps reduce transport losses and improve subsequent etching accuracy.

[0080] The next step is to coat a photoresist layer on the surface of the passivation layer 19 and perform photolithography etching to form a window in the passivation layer 19 that exposes the source ohmic contact region 17 and the drain ohmic contact region 18.

[0081] Next, ion implantation is performed on the exposed substrate in the window to form heavily doped source ohmic contact region 17 and drain ohmic contact region 18. In this embodiment, the implanted ions are preferably silicon ions, but not limited to them, and the doping concentration is, for example, greater than or equal to 10¹⁹ cm³. After ion implantation, high-temperature annealing can be performed to activate the ions, preferably at a temperature not lower than 1300°C, for example, 1400°C.

[0082] The remaining passivation layer 19 was then completely removed to ensure perfect contact between the P-GaN layer and the GaN cap layer. The removal method included etching with BOE etchant to remove the SiN layer; the resulting structure can be referenced further. Figure 2 As shown. It should be noted that, although Figure 2 The injection region on the left is marked as the source ohmic contact region 17, while the injection region on the right is marked as the drain ohmic contact region 18. However, this is only for illustration and not a limitation, and the positions of the two can be interchanged.

[0083] In traditional power device fabrication, ohmic contacts are typically achieved using metal alloys. This invention achieves ohmic contacts through ion implantation, which helps reduce the resistance of the ohmic contacts. Ion implantation requires defining the implantation window using photoresist, followed by high-temperature activation. Without prior ohmic contact fabrication, the device surface will be uneven, affecting the accuracy of the photolithography window. Furthermore, high-temperature activation can also affect other device performance characteristics. Therefore, in this embodiment, ion implantation and activation of the ohmic region are performed first, avoiding these problems and contributing to improved device quality.

[0084] Next, step S3 is performed to remove part of the barrier layer 14 located below the gate 21.

[0085] In one example, the method for removing part of the barrier layer 14 in step S3 includes:

[0086] First, the desired pattern is defined using photolithography, that is, the window 21a of the Schottky electrode (here referring to gate 21) is first opened. Then, inductively coupled plasma etching (ICP) is used to etch part of the barrier layer 14. If a cap layer 16 is formed, the cap layer 16 is also etched. Next, NMP (N-methylpyrrolidone) and IPA (isopropanol) solvents are used to remove the photoresist layer on the surface. When the barrier layer 14 is an AlGaN layer, the main gas components in ICP etching are Cl2 and BCl3, and O2 can be added to increase etching selectivity.

[0087] Subsequently, oxygen plasma was used to remove residual photoresist from the surface, and BOE (Buffered Oxide Etch, mainly composed of hydrofluoric acid) solution was used to treat the substrate surface, etching the oxide on the substrate surface, thereby obtaining the desired result. Figure 3 The structure shown.

[0088] Then, step S4 is performed to form a gate material layer 211 covering the barrier layer 14.

[0089] Specifically, in this step, a magnesium-doped GaN layer is grown using MOCVD epitaxy as the gate material layer 211, with a thickness preferably not exceeding 100 nm, and more preferably 30 nm. This gate material layer 211 will cover the surface of the structure obtained after step S3, as detailed in [reference needed]. Figure 4 As shown in the diagram, in this embodiment, a P-type doped material layer is deposited as the gate material layer 211, and a P-type gate is fabricated accordingly. This allows the two-dimensional electron gas 22 to be pinched off, enabling the device to remain in a normally off state even without power, thus helping to reduce device power consumption. Of course, in other examples, other suitable materials and / or methods can be used to fabricate the P-type gate material layer, such as a magnesium-doped zinc oxide layer, and the fabrication method can be, for example, sputtering deposition, etc., without strict limitations. However, using MOCVD to grow the gate material layer allows the fabrication of the gate material layer and other structural layers to be performed on the same equipment. It also allows for easier adjustment of parameters such as the doping type, doping concentration, and thickness of the gate material layer based on the material and bandgap properties of other structural layers, to better match the performance of the fabricated device and contribute to further improvement of device performance.

[0090] Continue with step S5 to etch the gate material layer 211, thereby forming a gate 21 with an initial morphology.

[0091] Specifically, in this step, photolithography is used to continue masking the Schottky electrode area (here referring to the region corresponding to gate 21), and an ICP etching process including Cl2, BCl3, and O2 (optional) gases is used to etch the unmasked magnesium-doped GaN layer, thereby obtaining the initial morphology of the P-type Schottky gate. This initial morphology shows the prototype of the fin structure, which can be found in the following reference. Figure 5 As shown.

[0092] Next, step S6 is performed to etch the barrier layer 14, channel layer 13, and part of the buffer layer 12, excluding the area below the gate 21, thereby forming a fin structure. The gate 21 is located on the fin structure, meaning that the formed gate structure is a fin gate. In this example, the P-type gate structure allows the device to remain normally off without an external voltage, effectively reducing device power consumption, circuit design complexity, and usage costs.

[0093] In this example, the cap layer 16 is made of GaN, the barrier layer 14 is made of AlGaN, the insertion layer 15 is made of AlN, and the channel layer 13 and buffer layer 12 are made of GaN. Therefore, in a preferred example, this step first uses photolithography to mask the pattern of the fin structure, and then uses an ICP etching process including Cl2, BCl3, and O2 (optional) gases to etch the cap layer 16, barrier layer 14, insertion layer 15, channel layer 13, and part of the buffer layer 12 to form the fin structure. The gate 21 is formed on the fin structure. That is to say, in this example, the etching of each structural layer is completed simultaneously in the same etching process, which can greatly simplify the fabrication process. If the structural layers are made of other materials, other corresponding etching methods can be used, and there is no limitation on this.

[0094] After etching, residual photoresist on the surface is treated with oxygen plasma, and the etched substrate surface is treated with BOE solution to etch oxides, resulting in the desired product. Figure 6 The structure shown.

[0095] Then, step S7 is performed to form a passivation layer 19 covering the fin structure. For example, a SiN layer is deposited using PECVD for surface passivation, resulting in... Figure 7 The structure shown is illustrated. This step uses PECVD instead of LPCVD to deposit the SiN layer, which helps to improve the deposition rate and allows for a thicker SiN layer, for example, greater than or equal to 200 nm. This allows the SiN layer to withstand multiple high-temperature annealing processes, providing better protection for the device.

[0096] Next, step S8 is executed to form lead-out electrodes that are electrically connected to the source ohmic contact region 17, the drain ohmic contact region 18 and the gate 21 respectively, thus forming the source electrode, the drain electrode and the gate electrode.

[0097] The lead-out electrodes in these three regions can be formed simultaneously in the same process, but in the preferred example provided in this application, the source / drain lead-out electrodes and the gate electrode 25 are formed separately. This step specifically includes:

[0098] First, photolithography is used to create windows in the ohmic contact regions of the source and drain. Then, an ICP etching process containing CF4 gas is used to etch the SiN passivation layer 19 located above the source and drain ohmic contact regions, thereby exposing the heavily doped source ohmic contact region 17 and drain ohmic contact region 18, resulting in the following... Figure 8 The structure shown;

[0099] An ohmic electrode metal layer is deposited by vapor deposition. For example, a titanium layer is first deposited as an adhesion layer, and then a noble metal layer, including but not limited to a platinum layer and / or a gold layer, is deposited on the adhesion layer. Following this, high-temperature annealing is performed, for example, tempering at a temperature above 500°C, to form ohmic contact electrodes, namely the source electrode 23 and the drain electrode 24, resulting in... Figure 9 The structure shown;

[0100] Next, photolithography is used to create an etch window 212 in the region corresponding to the gate 21. An ICP dry etching process, including CF4 gas, is then used to etch the SiN passivation layer 19 on the surface, exposing the Schottky contact surface, thus revealing the gate 21. After removing the photoresist, a BOE solution is used to remove the oxide from the etch window and reduce surface roughness. Finally, the surface is rinsed with deionized water and dried. The resulting structure is shown below. Figure 10 As shown;

[0101] Then, the substrate surface is treated with hot ammonia solution, for example, boiling ammonia solution at 50-60°C, for 3-8 minutes, preferably 5 minutes. Afterwards, the window of the Schottky contact (i.e., gate electrode 25) is redefined by photolithography, and metal layers for the gate electrode 25, which are electrically in contact with the gate 21, are deposited. For example, a titanium layer and several of the following layers are deposited: a nickel layer, a gold layer, and a platinum layer on top of the titanium layer. The mixture is then annealed at a high temperature above 500°C to complete the lead-out of the gate electrode 25, resulting in the desired appearance. Figure 11 The structure shown.

[0102] In this example, the source / drain ohmic contact electrode is formed first, followed by the gate electrode 25. Therefore, the source / drain ohmic contact electrode and the gate electrode can use different metal materials to meet their respective work function requirements. In this case, after the gate electrode is fabricated, the source / drain ohmic electrode and the gate electrode can be annealed simultaneously at the same temperature (above 500°C) (i.e., annealing is not performed immediately after the source / drain ohmic contact electrode is fabricated). The gate electrode 25 can be located only on the upper surface of the gate 21, specifically as follows... Figure 12 As shown. It can also be done during the preparation process, such as... Figure 13 and 14 As shown, by increasing the thickness of the photoresist layer 20, a support point is added to the bottom of the gate 21 metal. Then, the etching window is enlarged to achieve good adhesion of the gate electrode 25. A cross-sectional view of the enlarged etching window is shown in the reference diagram. Figure 15 As shown, the photoresist layer 20 is finally removed. Figure 16 and Figure 17 As can be seen, the lead-out electrode (i.e., gate electrode 25) of gate 21 extends from the upper surface of gate 21 to the side of gate 21 to form a semi-enclosed structure of gate 21, which helps to increase the gate control capability of the device and better surface adhesion.

[0103] The present invention also provides a method for fabricating a logic NOR gate circuit, the method comprising:

[0104] A substrate is provided, and two symmetrically fabricated switching devices 100 with fin structures are completed in two mutually isolated active regions of the substrate using the fabrication method described in any of the above schemes, resulting in... Figure 18 The structure shown has the following equivalent circuit diagram: Figure 19 As shown. The fabrication process of the device can be referred to the above content, and will not be repeated for the sake of brevity.

[0105] After the switching devices are fabricated, the gates 21, sources, and drains of the two switching devices are connected and electrically led out, resulting in the structure shown below. Figure 20 As shown, its corresponding equivalent circuit diagram is as follows: Figure 21 As shown.

[0106] It should be noted that the substrate in this embodiment and the substrate used to fabricate the finned switching device 100 can essentially be the same substrate. For example, after providing a semiconductor substrate, surface cleaning is performed first, and then an insulating passivation layer is formed on the substrate surface. For example, a 20nm SiN passivation layer is deposited on the substrate surface using LPCVD. Then, spaced source regions are defined on the substrate using an exposure and development process. Next, two adjacent active regions are isolated from each other, for example, by nitrogen or oxygen ion implantation, or by forming a shallow trench isolation structure between two adjacent active regions to electrically isolate them (ion implantation is recommended). Finally, the finned switching device 100 is fabricated. In wafer-level manufacturing, hundreds or even thousands of devices will be formed on the substrate, as long as the fabricated switching devices are ensured to be symmetrical pairwise.

[0107] After completing the symmetrical fabrication of the devices, the pattern of the interconnect metal layer 26 is defined using photolithography, a metal seed layer, such as a gold layer, is deposited, and then electroplating is performed to connect the source and drain regions of the two devices. The gates 21 of the two devices (labeled as device A and device B in the figure) are led out as inputs through gold wire bonding. The drain electrodes of the two devices are connected to the power supply through pull-up resistors, and the source electrodes are grounded through pull-down resistors, forming a configuration as shown in the figure. Figure 20 The logic OR gate circuit structure is shown.

[0108] If multiple logic NOR gates are fabricated on the substrate at the same time, a slitting step may be included afterwards.

[0109] Using this invention, multiple circuits can be fabricated using only the front-end chip manufacturing process, and the circuit impedance can be adjusted more easily, which helps to improve production efficiency and reduce production costs.

[0110] The present invention also provides a logic NOR gate circuit, the structure of which is referenced. Figure 20 and 21 As shown, it includes two finned switching devices 100 fabricated using the methods described in any of the above schemes. Therefore, the foregoing content can be quoted in its entirety here, and will not be repeated for the sake of brevity. The gates 21 of the two switching devices serve as inputs, their sources are interconnected and grounded via pull-down resistors, and their drains are interconnected and connected to the power supply via pull-up resistors. The truth table of the logic NOR gate circuit in this example is shown in the table below.

[0111] Table 1 Truth Table

[0112] A B Y1 1 1 0 1 0 0 0 1 0 0 0 1

[0113] In summary, this invention, through improved structural and process design, fabricates a switching device with a finned gate, enabling normally-off operation without an external voltage, reducing power consumption, circuit design complexity, and design and usage costs. The finned structure achieves better gate control capability, effectively utilizing substrate area and reducing device size. Furthermore, this invention employs ion implantation to form ohmic contacts, allowing for the extraction of ohmic contact electrodes at a lower temperature (500°C), helping to ensure good device morphology and achieving lower ohmic contact resistance, thus improving device performance. The fabrication process is simple, contributing to improved production efficiency and yield, and reducing production costs.

[0114] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0115] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a switching device having a fin structure, characterized by, Including the following steps: S1: Prepare a substrate, which includes a substrate layer, a buffer layer, a channel layer and a barrier layer stacked on top of each other; S2: Ion implantation is performed on the substrate to prepare spaced source ohmic contact regions and drain ohmic contact regions on the substrate, the source ohmic contact regions and drain ohmic contact regions extending downward to contact the channel layer; S3: Remove part of the barrier layer located below the gate; S4: Gate material layer forming the covering barrier layer; S5: Etch the gate material layer to form a gate with an initial morphology; S6: Etch the barrier layer, channel layer and part of the buffer layer except for the area below the gate to form a fin structure, with the gate located on the fin structure; S7: Forms a passivation layer covering the fin structure; S8: Forming lead-out electrodes that are electrically connected to the source ohmic contact region, the drain ohmic contact region, and the gate respectively; wherein the lead-out electrodes electrically connected to the gate extend from the upper surface of the gate to the side of the gate to form a semi-enclosed structure of the gate.

2. The production method according to claim 1, characterized by, The substrate further includes an insertion layer and a cap layer. The insertion layer is located between the channel layer and the barrier layer, and the cap layer is located above the barrier layer. The bandgap of the insertion layer is greater than the bandgap of the barrier layer, and the material of the cap layer is the same as that of the channel layer.

3. The method of claim 2, wherein, The substrate layer includes several types of silicon substrate, silicon carbide substrate, sapphire substrate and silicon nitride substrate, the buffer layer includes a GaN layer, the channel layer and barrier layer include several types of GaN layer, AlN layer, AlGaN layer, InGaN layer and InAlN layer, and the insertion layer includes an AlN layer.

4. The method of claim 1, wherein, Step S2 includes: A passivation layer is formed on the substrate surface using LPCVD technology, the passivation layer comprising a SiN layer; Photolithography is performed to form windows in the passivation layer that expose the source ohmic contact region and the drain ohmic contact region; Ion implantation is performed on the substrate exposed in the window to form heavily doped source and drain ohmic contact regions, and the implanted ions include silicon ions. Remove the residual passivation layer by etching with BOE etchant.

5. The preparation method according to claim 3, characterized in that, The method for removing part of the barrier layer in step S3 includes etching using an inductively coupled plasma etching process after the desired pattern is defined by photolithography and development, wherein the etching gases include Cl2 and BCl3, and then NMP and IPA are used to remove the residual photoresist layer.

6. The preparation method according to claim 1, characterized in that, Step S4 includes first using oxygen plasma to remove residual photoresist from the surface, then using BOE solution to treat and etch the oxide on the substrate surface, and then using MOCVD to epitaxially grow a 30nm magnesium-doped GaN layer as the gate material layer.

7. The production method according to claim 6, wherein The method for etching the gate material layer includes: using photolithography to shield the Schottky electrode area, and then using inductively coupled plasma etching to etch the unshielded magnesium-doped GaN layer to obtain the initial morphology of the P-type Schottky gate.

8. The method of claim 1, wherein, Forming the lead-out electrode includes: The passivation layer was etched using inductively coupled plasma etching to expose the source ohmic contact region and the drain ohmic contact region. Metal layers are formed that are in contact with the source ohmic contact region and the drain ohmic contact region respectively, and then subjected to high-temperature annealing, thereby forming the source ohmic electrode and the drain ohmic electrode. A window exposing the gate is formed in the passivation layer using photolithography etching. After removing the residual photoresist layer, BOE solution is used to remove oxides from the etched window and reduce surface roughness. Then, the substrate is surface treated in hot ammonia water and the gate window is redefined. A metal layer that is in electrical contact with the gate is formed and then subjected to high-temperature annealing, thereby forming the gate electrode.

9. The production method according to claim 8, characterized by, In step S7, a SiN layer is deposited using PECVD process as a passivation layer. The gas used to etch the passivation layer includes CF4. The temperature of the hot ammonia water is 50℃-60℃, and the ammonia water treatment time is 3min-10min. The source ohmic electrode and the drain ohmic electrode are made of titanium layer and gold layer and / or platinum layer on titanium layer. The gate electrode is made of titanium layer and several of nickel layer, gold layer and platinum layer on titanium layer.

10. A logic NOR gate circuit, comprising: The logic NOR gate circuit includes two switching devices with fin structures prepared by the preparation method described in any one of claims 1 to 9. The gates of the two switching devices serve as inputs, their sources are connected to each other and grounded through pull-down resistors, and their drains are connected to each other and connected to a power supply through pull-up resistors.

11. A method of fabricating a logical NOR gate circuit, characterized by: The preparation method includes: A substrate is provided, and two symmetrically fabricated switching devices with fin structures are completed in two mutually isolated active regions of the substrate using the fabrication method described in any one of claims 1 to 9. Connect the gate, source, and drain of the two switching devices and electrically bring them out.

12. The method of claim 11, wherein, After providing the substrate, a passivation layer is first deposited on the substrate surface using LPCVD process. Then, an exposure and development process is used to define spaced active regions on the substrate. Nitrogen ion implantation is then performed to isolate two adjacent active regions from each other. Next, the switching device with the fin structure is fabricated.

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