Smart lock control circuit and method thereof

Abstract

This invention discloses a smart lock control circuit and method, including a processing unit. In the processing unit, the first input terminal of AND gate U1 is connected to the cathodes of diodes D1 and D2, the second input terminal is connected to the emitter of transistor Q1, and the output terminal is connected to the input terminal of inverter U2, one end of resistor R3, the third pin of flip-flop U5, and the Start terminal. The output terminal of inverter U2 is connected to the anode of diode D1 and the collector of transistor Q1. The first input terminal of NAND gate U3 is connected to the fifth pin of flip-flop U4 and the Out terminal, the second input terminal is connected to the first input terminal of NAND gate U6 and the Port_2 terminal, and the output terminal is connected to the fourth pin of flip-flop U4. The first pin of flip-flop U4 is connected to the collector of transistor Q3 and one end of resistor R11, the second pin is connected to the sixth pin and the second input terminal of NAND gate U6, and the third pin is connected to the anodes of diodes D2 and D3, the fifth pin of flip-flop U5, and one end of resistor R5.

Description

Technical Field

[0001] This invention relates to the field of power supply technology, and in particular to a smart lock control circuit and method. Background Technology

[0002] In existing power supply systems, to ensure power supply reliability and power supply in case of faults, a mechanical interlocking control mechanism of "three locks and two keys" is used between power supply cabinets and interconnection cabinets. This mechanism enforces the operation sequence of power line switching through physical interlocking of three locks and two keys to prevent short circuits or power outages caused by misoperation. Due to the characteristics of the mechanism, the circuit breaker closing operation requires the insertion of a key, and the key will be locked by the lock after closing, ensuring that at most two circuit breakers in the same power supply circuit can be in the closed state. Although this mechanical interlocking method ensures operational safety to a certain extent, in practical applications, since the entire operation process relies entirely on manual execution, maintenance personnel need to frequently travel between the incoming line cabinet and the interconnection cabinet to perform mutual power supply and switching operations during faults. This is time-consuming and labor-intensive, and the excessive operation time can delay fault recovery. Furthermore, mechanical keys are easy to copy or lose. In order to save operation time, some maintenance personnel often violate regulations by using a "padlock without locking" workaround, and even remote operation is sometimes carried out in different locations, rendering the interlocking mechanism ineffective and creating hidden dangers in power supply. Summary of the Invention

[0003] See Figure 3The three-lock, two-key system primarily prevents accidents in the feeder circuit and power distribution cabinet caused by the simultaneous conduction of 1QF, 2QF, and 3QF. To address this technical problem, this invention provides an intelligent lock control circuit and method, including a processing unit. The processing unit comprises several AND gates, several flip-flops, several transistors, several diodes, several resistors, and an inverter. The first input terminal of AND gate U1 is connected to the cathodes of diodes D1 and D2, and the second input terminal is connected to the emitter of transistor Q1. The output terminal is connected to the input terminal of inverter U2, one end of resistor R3, the third pin of flip-flop U5, and the Start terminal. The output terminal of inverter U2 is connected to the anode of diode D1 and the collector of transistor Q1. The first input terminal of NAND gate U3 is connected to the fifth pin of flip-flop U4 and the Out terminal, and the second input terminal is connected to the first input terminal of NAND gate U6 and the Port_2 terminal. The output terminal is connected to the flip-flop U4. 4. Pin 4: The first pin of flip-flop U4 is connected to the collector of transistor Q3 and one end of resistor R11. The second pin is connected to the sixth pin and the second input of NAND gate U6. The third pin is connected to the anode of diode D2, the anode of diode D3, the fifth pin of flip-flop U5, and one end of resistor R5. The second pin of flip-flop U5 is connected to the sixth pin, the base of transistor Q2, one end of resistor R7, and Port_3. The output of NAND gate U6 is connected to the other end of resistor R11. The base of transistor Q1 is connected to the collector of transistor Q2 and one end of resistor R6. The base of transistor Q3 is connected to Port_4. The cathode of diode D3 is connected to Port_1. The emitter of transistor Q2 and the fourth pin of flip-flop U5 are connected to the power supply. The emitter of transistor Q3, the first pin of flip-flop U5, the output of AND gate U7, the other end of resistor R3, the other end of resistor R5, the other end of resistor R6, and the other end of resistor R7 are grounded.

[0004] Furthermore, the Port1 counting signal, Port_2 disable signal, Port3 self-feedback signal, Port4 restart signal, Start unlock signal, and Out lock start signal in the processing unit are input and output through the host control chip.

[0005] Furthermore, it also includes a detection unit, which includes a counter and several resistors. In the detection unit, the fourth pin of the counter U8 is connected to the thirteenth pin, one end of the resistor R9, and the Port_2 terminal; the fourteenth pin is connected to one end of the resistor R8 and the Port_1 terminal; the fifteenth pin is connected to one end of the resistor R10 and the Port_4 terminal; and the sixteenth pin is connected to the power supply. The eighth pin of the counter U8, the other end of the resistor R8, the other end of the resistor R9, and the other end of the resistor R10 are grounded.

[0006] Furthermore, it also includes a Wi-Fi unit, through which the processing unit and the detection unit transmit signals.

[0007] Furthermore, the processing unit also includes several resistors. One end of resistor R1 in the processing unit is connected to the emitter of transistor Q1; one end of resistor R2 is connected to the collector of transistor Q1; one end of resistor R4 is connected to the cathode of diode D1; and the other ends of resistors R1, R2, and R4 are grounded.

[0008] Furthermore, the processing unit also includes a connector, namely connector P1, whose second pin is connected to the first input terminal of AND gate U7 and its fourth pin is connected to the second input terminal of AND gate U7.

[0009] Furthermore, the smart lock control method includes the following steps;

[0010] S1: The processing unit detects the Start unlock signal and feeds back the Out lock start signal during startup, as well as outputs the Port_3 self-feedback signal during startup to cross-shield the signals input to the detection unit from other processing units.

[0011] S2: The processing unit generates an interrupt signal during the duration of the Start unlock signal and removes the shield to close the loop after the Start unlock signal input is completed.

[0012] S3: During the duration of the Start unlock signal, the processing unit sends a Port_1 counting signal back to the detection unit for counting.

[0013] S4: The detection unit sets a quantity threshold and outputs a Port_2 disable signal to the processing unit based on the number of Port_1 signals of the corresponding processing unit;

[0014] S5: When there is an input in Port_2, the processing unit generates the corresponding disable or disable signal based on the status of the Out lock start signal.

[0015] The advantages of this invention compared to the prior art are:

[0016] This invention forms an operational closed loop through cross-shielding and automatic interruption, ensuring that only a single cabinet (incoming line or communication cabinet) is controlled at any given time, and automatically generates a prohibition signal based on the cabinet status to prevent misoperation. This method can support safe interlocking control for remote collaborative operations. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is the circuit structure diagram of the processing unit.

[0019] Figure 2 This is the circuit structure diagram of the detection unit.

[0020] Figure 3 This is a schematic diagram of the power distribution cabinet connection. Detailed Implementation

[0021] To make the objectives and advantages of the present invention clearer, the present invention will be specifically described below in conjunction with embodiments. It should be understood that the following text is only used to describe one or more specific embodiments of the present invention and does not strictly limit the scope of protection specifically claimed by the present invention.

[0022] This invention discloses a smart lock control circuit and method, including a processing unit. In the processing unit, the first input terminal of AND gate U1 is connected to the cathodes of diodes D1 and D2, the second input terminal is connected to the emitter of transistor Q1, and the output terminal is connected to the input terminal of inverter U2, one end of resistor R3, the third pin of flip-flop U5, and the Start terminal. The output terminal of inverter U2 is connected to the anode of diode D1 and the collector of transistor Q1. The first input terminal of NAND gate U3 is connected to the fifth pin of flip-flop U4 and the Out terminal, the second input terminal is connected to the first input terminal of NAND gate U6 and the Port_2 terminal, and the output terminal is connected to the fourth pin of flip-flop U4. The first pin of flip-flop U4 is connected to the collector of transistor Q3 and one end of resistor R11, the second pin is connected to the sixth pin of the NAND gate... The second input terminal and the third pin of U6 are connected to the anode of diode D2, the anode of diode D3, the fifth pin of flip-flop U5, and one end of resistor R5; the second pin of flip-flop U5 is connected to the sixth pin, the base of transistor Q2, one end of resistor R7, and the Port_3 terminal; the output terminal of NAND gate U6 is connected to the other end of resistor R11; the base of transistor Q1 is connected to the collector of transistor Q2 and one end of resistor R6; the base of transistor Q3 is connected to the Port_4 terminal; the cathode of diode D3 is connected to the Port_1 terminal; the emitter of transistor Q2 and the fourth pin of flip-flop U5 are connected to the power supply; the emitter of transistor Q3, the first pin of flip-flop U5, the output terminal of AND gate U7, the other end of resistor R3, the other end of resistor R5, the other end of resistor R6, and the other end of resistor R7 are grounded.

[0023] Specifically, the Port1 counting signal, Port_2 disable signal, Port3 self-feedback signal, Port4 restart signal, Start unlock signal, and Out lock start signal in the processing unit are input and output through the host control chip.

[0024] Specifically, in the detection unit, the fourth pin of counter U8 is connected to the thirteenth pin, one end of resistor R9, and Port_2; the fourteenth pin is connected to one end of resistor R8 and Port_1; the fifteenth pin is connected to one end of resistor R10 and Port_4; and the sixteenth pin is connected to the power supply. The eighth pin of counter U8, the other end of resistor R8, the other end of resistor R9, and the other end of resistor R10 are grounded.

[0025] Specifically, it also includes a Wi-Fi unit, through which the processing unit and the detection unit transmit signals.

[0026] Specifically, in the processing unit, one end of resistor R1 is connected to the emitter of transistor Q1; one end of resistor R2 is connected to the collector of transistor Q1; one end of resistor R4 is connected to the cathode of diode D1; and the other ends of resistors R1, R2, and R4 are grounded.

[0027] Specifically, in the processing unit, the second pin of connector P1 is connected to the first input terminal of AND gate U7, and the fourth pin is connected to the second input terminal of AND gate U7.

[0028] Specifically, the smart lock control method includes the following steps;

[0029] S1: The processing unit detects the Start unlock signal and feeds back the Out lock start signal during startup, as well as outputs the Port_3 self-feedback signal during startup to cross-shield the signals input to the detection unit from other processing units.

[0030] S2: The processing unit generates an interrupt signal during the duration of the Start unlock signal and removes the shield to close the loop after the Start unlock signal input is completed.

[0031] S3: During the duration of the Start unlock signal, the processing unit sends a Port_1 counting signal back to the detection unit for counting.

[0032] S4: The detection unit sets a quantity threshold and outputs a Port_2 disable signal to the processing unit based on the number of Port_1 signals of the corresponding processing unit;

[0033] S5: When there is an input in Port_2, the processing unit generates the corresponding disable or disable signal based on the status of the Out lock start signal.

[0034] See Figure 1In one embodiment, there are three processing units, each corresponding to two incoming line cabinets and one communication cabinet. Each processing unit includes a Port1 counting signal, a Port_2 disable signal, a Port3 self-feedback signal, a Port4 restart signal, a Start unlock signal, and an Out lock start signal. The Port_1 counting signal is input to the detection unit, the Port_2 disable signal is fed back to the processing unit by the detection unit, and the Port_3 self-feedback signal is input to the connector P1 of other processing units. The connector P1 of the processing unit itself receives the Port_3 self-feedback signals corresponding to the other two processing units. During use, when the first Start unlock signal is input to the processing unit, the processing unit feeds back the Out lock start signal and the Port_1 counting signal to the detection unit. At the same time, the Port_3 self-feedback signal is used to cross-shield the output of other processing units, and during this period, the process is prepared to generate... An interrupt signal is used to shield the signal so that only one processing unit can output one Out lock start signal and one Port_1 count signal at a time. This is to prevent short circuits caused by misoperation of the cabinet or digital circuit breaker when multiple people are working together. The interrupt signal is prepared to release the interrupt signal and remove the shield after the Start unlock signal is input, thus forming a closed loop. The detection unit will feed back the Port_1 count signal to the processing unit after receiving the Port_1 count signal from any two processing units. At this time, the processing unit will generate a corresponding enable or disable signal based on the output state of the different Out lock start signals to complete the self-locking between the Out lock start signals. When the power supply connection is switched, the input signal at the Port_4 terminal is reset and restarted. After restarting, the Out lock start signal is reset, and the above operation is repeated. When the power supply and distribution are centrally controlled, the processing unit can directly feed back to the upper chip of the current system for signal input and output control.

[0035] See Figure 1In one embodiment, when the processing unit is in operation during the Start signal period, it feeds back to pin 3 of flip-flop U5 and the input of inverter U2. Pin 5 of flip-flop U5 outputs a high-level signal, which is fed back to Port_1 via diode D3, input to AND gate U1 via diode D2, and input to pin 3 of flip-flop U4. Pin 5 of flip-flop U4 outputs a high-level signal to Out and NAND gate U3. Simultaneously, pin 6 of flip-flop U5 is low-level, which is input to connector P1 of other processing units via Port_3. The AND gate U7 of the corresponding processing unit receives the signal from Port_3 and outputs a low-level signal to flip-flop U4. Pin 1 of U5 forces pin 6 of the corresponding flip-flop U5 to be set to 1, shielding the Port_1 and Out signals from other processing units to the detection unit. Simultaneously, the power supply to the emitter of transistor Q2 in the current processing unit is looped through the base of transistor Q2, resistor R7, and ground, turning on transistor Q2. The power signal is then fed back to the base of transistor Q1 for interrupt preparation after looping through the emitter, collector, and ground of transistor Q2 via resistor R6. Inverter U2 outputs a low level to the collector of transistor Q1. After the Start input is complete, inverter U2 inverts the high-level signal again, passing it through the collector, emitter, and resistor R1 of transistor Q1. After the grounding loop is pulled up, the input is sent to AND gate U1. With input on both input pins of AND gate U1, AND gate U1 outputs a high-level signal to pin 3 of flip-flop U5 to release the interrupt signal. At this time, pin 5 of flip-flop U5 outputs a low-level signal to release the occupancy of Port_1 on the detection unit. Pin 6 of flip-flop U5 outputs a high-level signal to Port_3 to release the shielding of the remaining processing units, completing the closed loop. When any two processing units have finished inputting to Port_1, the detection unit feeds back the Port_2 signal. When NAND gates U3 and U6 of the processing unit receive the Port_2 signal, NAND gate U3 samples the input state of pin 5 of flip-flop U4. The NAND gate U6 samples the input state of pin 6 of flip-flop U4. When there is an output, NAND gate U3 outputs a low-level signal to pin 4 of flip-flop U4 to lock the output state of Out. NAND gate U6 outputs a high-level signal, which is fed back to pin 1 of flip-flop U4 through resistor R11, preventing pin 6 of flip-flop U4 from outputting again, thus completing the disable function. Conversely, the output states of NAND gates U3 and U6 switch to complete the disable function. Resistors R4, R2, and R1 are used to prevent the low noise tolerance characteristic from causing output failure when interference occurs when using TTL device circuits. When using CMOS devices, they can be removed as appropriate depending on the interference situation.

[0036] See Figure 2In one embodiment, the signal from Port_1 is fed back to pin 14 of counter U8. Counter U8 switches the output from pin 3 to pin 2 until pin 4 of counter U8 outputs, at which point the signal is fed back to Port_2 and pin 13 of counter U8, and counter U8 enters sleep mode. During reset, a signal is input to Port_4. One path of the signal passes through pin 15 of counter U8 to reset counter U8, and the other path feeds back to the base of transistor Q3 in the processing unit. Transistor Q3 is turned on, and the processing unit with the output of NAND gate U6 will pull down the potential of pin 1 of trigger U4 through resistor R11, collector, emitter, and ground of transistor Q3. At the same time, the signal input to the processing unit from Port_2 reset by counter U8 will cause NAND gate U3 in the processing unit with the output of NAND gate U6 to output a high level again to complete the reset.

[0037] In one embodiment, in addition to electrical connection, the processing unit and the detection unit can also be controlled via Wi-Fi network. The Out signal is turned on and off by controlling the electromagnetic lock coil of the control switch cabinet, or by performing closing or opening operation when the digital circuit breaker receives the Out signal. When the number of processing units changes, the output pin of counter U8 in the detection unit is changed to the corresponding connection position. The Wi-Fi unit is not shown in the attached figure.

[0038] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No markings in the claims should be construed as limiting the scope of the claims.

Claims

1. A smart lock control circuit, characterized in that, The system includes three processing units. Each processing unit includes a Port_1 counting signal, a Port_2 disable signal, a Port_3 self-feedback signal, a Port_4 restart signal, a Start unlock signal, and an Out lock start signal. The Port_3 signal of this processing unit is input to the connector P1 of other processing units. The connector P1 of this processing unit receives the signal output of the Port_3 of other processing units. When the Start unlock signal of any processing unit is input, the processing unit feeds back the Out lock start signal and the Port_1 counting signal to the detection unit. At the same time, it inputs the Port_3 self-feedback signal to other processing units to cross-shield the output of other processing units and prepares to generate an interrupt signal. When the Start unlock signal is input, the interrupt signal is released to remove the shielding and form a closed loop. After receiving any two Port_1 counting signals, the detection unit inputs signals to the Port_2 terminals of all processing units. The processing unit then generates a corresponding disable or disable signal according to the output state of the current Out lock start signal to complete the self-locking. In the processing unit, the first input terminal of AND gate U1 is connected to the cathodes of diodes D1 and D2, the second input terminal is connected to the emitter of transistor Q1, and the output terminal is connected to the input terminal of inverter U2, one end of resistor R3, the third pin of flip-flop U5, and the Start terminal; the output terminal of inverter U2 is connected to the anode of diode D1 and the collector of transistor Q1; the first input terminal of NAND gate U3 is connected to the fifth pin of flip-flop U4 and the Out terminal, the second input terminal is connected to the first input terminal of NAND gate U6 and the Port_2 terminal, and the output terminal is connected to flip-flop U4. The fourth pin; the first pin of flip-flop U4 is connected to the collector of transistor Q3 and one end of resistor R11; the second pin is connected to the sixth pin and the second input of NAND gate U6; the third pin is connected to the anode of diode D2, the anode of diode D3, the fifth pin of flip-flop U5, and one end of resistor R5; the second pin of flip-flop U5 is connected to the sixth pin, the base of transistor Q2, one end of resistor R7, and Port_3; the output of NAND gate U6 is connected to the other end of resistor R11; the base of transistor Q1 is connected to the collector of transistor Q2 and one end of resistor R6; the transistor... The base of transistor Q3 is connected to Port_4; the cathode of diode D3 is connected to Port_1; the emitter of transistor Q2 and the fourth pin of flip-flop U5 are connected to the power supply; the emitter of transistor Q3, the first pin of flip-flop U5, the output of AND gate U7, the other end of resistor R3, the other end of resistor R5, the other end of resistor R6, and the other end of resistor R7 are grounded; one end of resistor R1 is connected to the emitter of transistor Q1; one end of resistor R2 is connected to the collector of transistor Q1; one end of resistor R4 is connected to the cathode of diode D1; the other ends of resistor R1, the other ends of resistor R2, and the other ends of resistor R4 are grounded; the second pin of connector P1 is connected to the first input of AND gate U7, and the fourth pin is connected to the second input of AND gate U7; in flip-flops U4 and U5, the second pin is the input pin, the third pin is the clock signal input pin, the fifth pin is the positive output pin, the sixth pin is the negative output pin, the fourth pin is the asynchronous preset input pin, and the first pin is the asynchronous clear input pin; in connector P1, the second and fourth pins are output pins, and the first and third pins are input pins.

2. The smart lock control circuit according to claim 1, characterized in that, The Port_1 counting signal, Port_2 disable signal, Port_3 self-feedback signal, Port_4 restart signal, Start unlock signal, and Out lock start signal in the processing unit are input and output through the host control chip.

3. The smart lock control circuit according to claim 1, characterized in that, It also includes a detection unit, in which the fourth pin of counter U8 is connected to the thirteenth pin, one end of resistor R9, and Port_2; the fourteenth pin is connected to one end of resistor R8 and Port_1; the fifteenth pin is connected to one end of resistor R10 and Port_4; and the sixteenth pin is connected to the power supply. The eighth pin of counter U8, the other end of resistor R8, the other end of resistor R9, and the other end of resistor R10 are grounded. In counter U8, the fourth pin is the output pin, the fourteenth pin is the clock input pin, the thirteenth pin is the enable pin, the fifteenth pin is the reset pin, the sixteenth pin is the power supply pin, and the eighth pin is the ground pin.

4. The intelligent lock control circuit according to claim 3, characterized in that, It also includes a Wi-Fi unit, through which the processing unit and the detection unit transmit signals.

5. A smart lock control method, comprising the smart lock control circuit according to any one of claims 1-4, characterized in that, Includes the following steps; S1: The processing unit detects the Start unlock signal and feeds back the Out lock start signal during startup, as well as outputs the Port_3 self-feedback signal during startup to cross-shield the signals input to the detection unit from other processing units. S2: The processing unit generates an interrupt signal during the duration of the Start unlock signal and removes the shield to close the loop after the Start unlock signal input is completed. S3: During the duration of the Start unlock signal, the processing unit sends a Port_1 counting signal back to the detection unit for counting. S4: The detection unit sets a quantity threshold and outputs a Port_2 disable signal to the processing unit based on the number of Port_1 signals of the corresponding processing unit; S5: When there is an input in Port_2, the processing unit generates the corresponding disable or disable signal based on the status of the Out lock start signal.

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