Driving circuit and driving method thereof, and display panel

Abstract

The present invention discloses a driving circuit and a driving method thereof, and a display panel, and relates to the field of display technology. In the driving circuit, a first output control module is used to respond to the conduction level of a first node, and transmit the voltage of a first voltage terminal to an output terminal; a second output control module is used to respond to the conduction level of a second node, and transmit the voltage of a second voltage terminal to an output terminal; a first node potential maintaining module and a first node control module are electrically connected to a fourth node, and are used to respond to a signal of the fourth node and a signal of a second clock signal terminal, or respond to a signal of the input terminal, the fourth node, and a signal of the second clock signal terminal, and transmit a first level signal to the first node, wherein the voltage of the first level signal is lower than the voltage of the first voltage terminal. In this way, when the voltage of the first voltage terminal is transmitted to the output terminal, the potential of the first node is pulled down to suppress the output tailing phenomenon.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and more specifically, to a driving circuit and a driving method thereof, and a display panel. Background Art

[0002] At present, display panels on the market usually include a display area and a non-display area. Sub-pixel units are arranged in an array in the display area, and a driving circuit, such as a gate driving circuit, is arranged in the non-display area. The gate driving circuit is used to output a gate driving signal to control the sub-pixel units in the display area to emit light in an orderly manner. The output of the gate driving circuit directly affects the display effect of the sub-pixel units. Therefore, the gate driving circuit has always been a major research hotspot in the display field, and providing a driving circuit with stable output has become an inevitable trend. Summary of the invention

[0003] In view of this, the present invention provides a driving circuit and a driving method thereof, and a display panel, aiming to improve the output stability of the driving circuit and enhance the display effect.

[0004] In a first aspect, the present application provides a driving circuit, comprising at least two cascaded shift registers, wherein the shift register comprises: an input terminal, an output terminal, a first voltage terminal, a second voltage terminal, a first clock signal terminal, a second clock signal terminal, and,

[0005] a first output control module, configured to transmit the voltage of the first voltage terminal to the output terminal in response to the conduction level of the first node;

[0006] a second output control module, configured to transmit the voltage of the second voltage terminal to the output terminal in response to the conduction level of the second node;

[0007] a first node control module, configured to transmit the voltage of the input terminal to the first node in response to the conduction level of the first clock signal terminal, and transmit the voltage of the second voltage terminal to the first node in response to the conduction levels of the second clock signal terminal and the third node, or in response to the conduction level of the second node;

[0008] a second node control module, configured to transmit the voltage of the second voltage terminal to the second node in response to the conduction level of the first node, and to transmit the voltage of the second clock signal terminal to the second node in response to the conduction level of the third node and the second clock signal terminal;

[0009] a third node control module, configured to transmit the voltage of the first voltage terminal to the third node in response to the conduction level of the first clock signal terminal, and transmit the voltage of the first clock signal terminal to the third node in response to the conduction level of the first node;

[0010] A first node potential maintaining module is electrically connected to the first node control module at a fourth node, and is used to respond to a signal at the fourth node and a signal at the second clock signal terminal, or to respond to a signal at the input terminal, the fourth node and the second clock signal terminal, to transmit a first level signal to the first node, wherein a voltage of the first level signal is lower than a voltage at the first voltage terminal.

[0011] In a second aspect, the present invention provides a display panel, comprising the driving circuit provided in the first aspect.

[0012] In a third aspect, the present invention provides a driving method of a driving circuit, wherein the driving circuit comprises at least two cascaded shift registers, wherein the shift register comprises: an input terminal, an output terminal, a first voltage terminal, a second voltage terminal, a first clock signal terminal, a second clock signal terminal, and,

[0013] a first output control module, configured to transmit the voltage of the first voltage terminal to the output terminal in response to the conduction level of the first node;

[0014] a second output control module, configured to transmit the voltage of the second voltage terminal to the output terminal in response to the conduction level of the second node;

[0015] a first node control module, configured to transmit the voltage of the input terminal to the first node in response to the conduction level of the first clock signal terminal, and transmit the voltage of the second voltage terminal to the first node in response to the conduction levels of the second clock signal terminal and the third node, or in response to the conduction level of the second node;

[0016] a second node control module, configured to transmit the voltage of the second voltage terminal to the second node in response to the conduction level of the first node, and to transmit the voltage of the second clock signal terminal to the second node in response to the conduction level of the third node and the second clock signal terminal;

[0017] a third node control module, configured to transmit the voltage of the first voltage terminal to the third node in response to the conduction level of the first clock signal terminal, and transmit the voltage of the first clock signal terminal to the third node in response to the conduction level of the fourth node;

[0018] a first node potential maintaining module, electrically connected to the first node control module at a fourth node, and connected in series between the fourth node and the first node;

[0019] The driving method comprises:

[0020] In the first output stage, the first node control module transmits the voltage of the input terminal to the first node in response to the conduction level of the first clock signal terminal, so that the first output control module is turned on, and the signal of the first voltage terminal is output through the output terminal;

[0021] In the first node potential maintaining stage, the first node potential maintaining module responds to the conduction level of the first clock signal terminal, transmits the signal of the input terminal to the fourth node, and responds to the signal of the fourth node and the signal of the second clock signal terminal, or responds to the signals of the input terminal, the fourth node and the second clock signal terminal, and transmits the first level signal to the first node, wherein the voltage of the first level signal is lower than the voltage of the first voltage terminal.

[0022] Compared with the prior art, the driving circuit and driving method thereof, and the display panel provided by the present invention achieve at least the following beneficial effects:

[0023] The driving circuit provided by the embodiment of the present invention is provided with a plurality of cascaded shift registers, and the shift register includes a first output control module, a second output control module, a first node control module, a second node control module and a third node control module, so that the first output control module and the second output control module are alternately turned on, and the signal of the first voltage terminal and the signal of the second voltage terminal are alternately output from the output terminal. In particular, in the gate driving circuit provided by the embodiment of the present invention, a first node potential maintaining module is introduced into the shift register, and the first node potential maintaining module is used to respond to the signal of the fourth node and the signal of the second clock signal terminal, and transmit the first level signal to the first node, and the voltage of the first level signal is lower than the voltage of the first voltage terminal. When the first output control module is turned on and the signal of the first voltage terminal is output through the output control module, the first node potential maintaining module can be controlled to transmit a first level signal with a smaller voltage value to the first node to lower the potential of the first node. When the potential of the first node is pulled down, the threshold loss of the first node can be compensated. After the threshold of the first node is compensated, it is beneficial to maintain the conduction state of the first output control module in a constant state, so that the first output control module is fully turned on, so that the first output control module can constantly output the signal of the first voltage end from the first output control module to avoid the tailing phenomenon, which is beneficial to improve the display effect of the display panel when the driving circuit is applied to the display panel.

[0024] Of course, any product implementing the present invention does not necessarily need to achieve all of the technical effects described above at the same time.

[0025] Further features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0027] Figure 1 FIG. 1 is a schematic diagram of a structure of a driving circuit provided by an embodiment of the present invention;

[0028] Figure 2 FIG. 1 is a schematic diagram of a structure of a shift register in a driving circuit provided in an embodiment of the present invention;

[0029] Figure 3 FIG. 2 is another schematic diagram of the structure of a shift register in a driving circuit provided in an embodiment of the present invention;

[0030] Figure 4 FIG. 2 is another schematic diagram of the structure of a shift register in a driving circuit provided by an embodiment of the invention;

[0031] Figure 5 FIG. 2 is another schematic diagram of the structure of a shift register in a driving circuit provided in an embodiment of the present invention;

[0032] Figure 6 FIG. 2 is another schematic diagram of the structure of a shift register in a driving circuit provided in an embodiment of the present invention;

[0033] Figure 7 FIG. 2 is another schematic diagram of the structure of a shift register in a driving circuit provided in an embodiment of the present invention;

[0034] Figure 8 FIG. 1 is another schematic diagram of the structure of a shift register in a driving circuit provided in an embodiment of the present invention;

[0035] Fig. 9 FIG. 1 is another schematic diagram of the structure of a shift register in a driving circuit provided in an embodiment of the present invention;

[0036] Fig.10 FIG. 1 is another schematic diagram of the structure of a shift register in a driving circuit provided in an embodiment of the present invention;

[0037] Fig.11 FIG. 1 is a circuit diagram of a shift register in a driving circuit provided by an embodiment of the present invention;

[0038] Fig.12 FIG. 2 is another circuit diagram of a shift register in a driving circuit provided by an embodiment of the present invention;

[0039] Fig.13 FIG. 1 is a schematic diagram of a structure of a display panel provided by an embodiment of the present invention;

[0040] Fig.14 FIG. 1 is a flow chart of a driving method of a driving circuit provided by an embodiment of the present invention;

[0041] Fig.15 FIG. 1 is a timing diagram of a driving circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0042] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless otherwise specifically stated.

[0043] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0044] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0045] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0046] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0047] Figure 1 FIG. 1 is a schematic diagram of a structure of a driving circuit provided by an embodiment of the present invention. Figure 2 FIG. 1 is a schematic diagram of a structure of a shift register in a driving circuit provided in an embodiment of the present invention. Figure 3 FIG. 1 is another schematic diagram of the structure of the shift register in the driving circuit provided in the embodiment of the present invention. Please refer to FIG. Figure 1 , Figure 2 and Figure 3 The embodiment of the present invention provides a driving circuit 200, comprising at least two cascaded shift registers 100, wherein the shift register 100 comprises: an input terminal IN, an output terminal OUT, a first voltage terminal VGL, a second voltage terminal VGH, a first clock signal terminal CK, a second clock signal terminal XCK, and,

[0048] A first output control module 11, configured to transmit the voltage of the first voltage terminal VGL to the output terminal OUT in response to the conduction level of the first node N1;

[0049] A second output control module 12, configured to transmit the voltage of the second voltage terminal VGH to the output terminal OUT in response to the conduction level of the second node N2;

[0050] The first node control module 21 is used to transmit the voltage of the input terminal IN to the first node N1 in response to the conduction level of the first clock signal terminal CK, and transmit the voltage of the second voltage terminal VGH to the first node N1 in response to the conduction level of the second clock signal terminal XCK and the third node N3, or in response to the conduction level of the second node;

[0051] The second node control module 22 is used to transmit the voltage of the second voltage terminal VGH to the second node N2 in response to the conduction level of the first node N1, and to transmit the voltage of the second clock signal terminal XCK to the second node N2 in response to the conduction level of the third node N3 and the second clock signal terminal XCK;

[0052] The third node control module 23 is used to transmit the voltage of the first voltage terminal VGL to the third node N3 in response to the conduction level of the first clock signal terminal CK, and transmit the voltage of the first clock signal terminal CK to the third node N3 in response to the conduction level of the fourth node N4;

[0053] The first node potential maintaining module 30 is electrically connected to the fourth node N4 with the first node control module 21, and is used for responding to the conduction level of the fourth node N4 and the signal of the second clock signal terminal XCK, or responding to the signal of the input terminal IN, the fourth node N4 and the second clock signal terminal XCK, to transmit the first level signal to the first node N1, wherein the voltage of the first level signal is lower than the voltage of the first voltage terminal VGL.

[0054] Optionally, the shift register 100 includes a transistor, and the on-level and the off-level in the embodiment of the present invention are distinguished according to the type of transistor. The on-level refers to the level that can control the conduction of the transistor, and the off-level refers to the level that can control the cut-off of the transistor. For example, when the transistor is a P-type transistor, the on-level is a low level and the off-level is a high level; when the transistor is an N-type transistor, the on-level is a high level and the off-level is a low level. It should also be noted that one of the first voltage terminal VGL and the second voltage terminal VGH outputs a high level and the other a low level. For the convenience of illustration, the following description will be based on the example that the transistor is a P-type transistor, the first voltage terminal VGL outputs a low level, and the second voltage terminal VGH outputs a high level. At this time, the on-levels are all low levels and the off-levels are all high levels.

[0055] It should be noted that Figure 1The connection relationship of some shift registers 100 in the driving circuit is only illustrated, and does not represent the number and size of the shift registers 100 actually included in the driving circuit. Figure 1 The driving circuit is arranged in the non-display area on one side of the display area. Of course, the driving circuit can also be arranged in the non-display areas on both sides of the display area. Figure 1 The present invention does not specifically limit the driving circuit shown.

[0056] For more information, see Figure 1 When the driving circuit provided by the present invention is applied to a display panel, the first voltage terminal VGL of each level of the shift register 100 is electrically connected to the first voltage signal line vgl of the display panel, the second voltage terminal VGH is electrically connected to the second voltage signal line vgh of the display panel, the first clock signal terminal CK is electrically connected to the first clock signal line ck of the display panel, and the second clock signal terminal XCK is electrically connected to the second clock signal line xck of the display panel. The input terminal IN of the first-level shift register 100 is electrically connected to the start trigger signal line stv of the display panel, and the input terminals IN of the remaining shift registers 100, except the first-level shift register 100, are electrically connected to the output terminal OUT of the previous-level shift register 100.

[0057] Please refer to Figure 2 and Figure 3 In order to clearly illustrate the electrical connection relationship of each module in the shift register 100, the first node N1, the second node N2, the third node N3 and the fourth node N4 are introduced in the circuit diagram of the shift register 100, wherein the potential of the first node N1 is controlled by the first node control module 21, the potential of the second node N2 is controlled by the second node control module 22, and the potential of the third node N3 is controlled by the third node control module 23. When the potential of the first node N1 is controlled by the first node control module 21, the first node control module 21 can select to transmit the voltage of the input terminal IN or the voltage of the second voltage terminal VGH to the first node N1, so that the potential of the first node N1 is low potential or high potential, thereby controlling the first output control module 11 to be turned on or off. When the potential of the second node N2 is controlled by the second node control module 22, the second node control module 22 can select to transmit the voltage of the second voltage terminal VGH or the voltage of the second clock signal terminal XCK to the second node N2, so that the potential of the second node N2 is a high potential or a low potential, thereby controlling the second output control module 12 to be turned off or turned on. When the potential of the third node N3 is controlled by the third node control module 23, the voltage of the first voltage terminal VGL or the voltage of the first clock signal terminal CK can be selected to be transmitted to the third node N3, so that the potential of the third node N3 is a low potential or a high potential, thereby realizing the control of the second node control module 22.

[0058] In actual application, the first output control module 11 responds to the conduction level of the first node N1, and outputs the voltage of the first voltage terminal VGL through the output terminal OUT; the second output control module 12 responds to the conduction level of the second node N2, and outputs the voltage of the second voltage terminal VGH through the output terminal OUT. Optionally, the first output control module 11 and the second output control module 12 are alternately turned on, and the signal of the first voltage terminal VGL and the signal of the second voltage terminal VGH are alternately output from the output terminal OUT.

[0059] In the related art, since the voltage of the internal control node of the shift register inevitably has a threshold loss when the shift register is working, the corresponding switch module cannot be fully turned on (fully open state), resulting in the voltage level transmitted to the output end of the shift register failing to reach the target voltage, resulting in a tailing phenomenon and affecting the display effect.

[0060] To solve the above problem, in the gate driving circuit provided by the embodiment of the present invention, a first node potential maintaining module 30 is introduced into the shift register 100. Figure 2 In the illustrated embodiment, the first node potential maintaining module 30 is used to respond to the signal of the fourth node N4 and the signal of the second clock signal terminal XCK, and transmit a first level signal to the first node N1, wherein the voltage of the first level signal is lower than the voltage of the first voltage terminal VGL. Figure 3 In the illustrated embodiment, the first node potential maintaining module 30 is used to respond to the signals of the input terminal IN, the fourth node N4 and the second clock signal terminal XCK, and transmit the first level signal to the first node N1, wherein the voltage of the first level signal is lower than the voltage of the first voltage terminal VGL. When the first output control module 11 is turned on and the signal of the first voltage terminal VGL is output through the output control module, the first node potential maintaining module 30 can be controlled to transmit the first level signal with a smaller voltage value to the first node N1 to lower the potential of the first node N1. When the potential of the first node N1 is lowered, the threshold loss of the first node N1 can be compensated. After the threshold of the first node N1 is compensated, it is beneficial to maintain the conduction state of the first output control module 11 in a constant state, so that the first output control module 11 is fully turned on, and then the first output control module 11 can output the signal of the first voltage terminal VGL from the first output control module 11 constantly, avoiding the tailing phenomenon, and thus it is beneficial to improve the display effect of the display panel when the driving circuit is applied to the display panel.

[0061] Continue to refer Figure 2 and Figure 3In an optional embodiment of the present invention, the first node potential maintaining module 30 is connected in series between the fourth node N4 and the first node N1; the first node control module 21 is connected to the first node N1 through the fourth node N4; the second node control module 22 is electrically connected to the second node N2 and the third node N3 respectively; the third node control module 23 is connected to the third node N3; the first output control module 11 and the second output control module 12 are connected in series between the first voltage terminal VGL and the second voltage terminal VGH, the control end of the first output control module 11 is connected to the first node N1, and the control end of the second output control module 12 is connected to the second node N2.

[0062] Specifically, in the shift register 100 of the gate drive circuit provided in the embodiment of the present application, please refer to Figure 2 The first node control module 21 is electrically connected to the input terminal IN, the first clock signal terminal CK, the second clock signal terminal XCK, the second voltage terminal VGH, the first node N1 and the third node N3 respectively. When the conduction level of the first clock signal is transmitted to the first node control module 21, the first node control module 21 can transmit the voltage of the input terminal IN to the first node N1; when the conduction levels of the second clock signal terminal XCK and the third node N3 are transmitted to the first node control module 21, the first node control module 21 can transmit the voltage of the second voltage terminal VGH to the first node N1.

[0063] Or please refer to Figure 3 The first node control module 21 is electrically connected to the input terminal IN, the first clock signal terminal CK, the second voltage terminal VGH, the first node N1, the second node N2 and the third node N3 respectively. When the conduction level of the first clock signal is transmitted to the first node control module 21, the first node control module 21 can transmit the voltage of the input terminal IN to the first node N1; when the conduction level of the second node N2 is transmitted to the first node control module 21, the first node control module can transmit the voltage of the second voltage terminal VGH to the first node N1.

[0064] Continue to refer Figure 2 and Figure 3The second node control module 22 is respectively connected to the first node N1, the second node N2, the third node N3, the second voltage terminal VGH and the second clock signal terminal XCK, and is used to transmit the voltage of the second voltage terminal VGH to the second node N2 when receiving the conduction level of the first node N1; and is used to transmit the voltage of the second clock signal terminal to the second node N2 when receiving the conduction level of the third node N3 and the second clock signal terminal XCK. The third node control module 23 is respectively electrically connected to the third node N3, the fourth node N4, the first clock signal terminal CK and the first voltage terminal VGL, and is used to transmit the voltage of the first voltage terminal VGL to the third node N3 when receiving the conduction level of the first clock signal terminal CK; and is used to transmit the voltage of the first clock signal terminal CK to the third node N3 when receiving the conduction level of the fourth node N4. Figure 2 In the illustrated embodiment, the first node potential maintaining module 30 is connected to the first node N1, the fourth node N4 and the second clock signal terminal XCK respectively, according to the conduction level of the fourth node N4 and the signal of the second clock signal terminal XCK; Figure 3 In the illustrated embodiment, the first node potential location module 30 is electrically connected to the input terminal IN in addition to being connected to the first node N1 , the fourth node N4 and the second clock signal terminal XCK. Figure 2 and Figure 3 The first node potential maintaining module 30 in the embodiment is capable of transmitting the first level signal to the first node N1. The voltage of the first level signal is lower than the voltage value of the first voltage terminal VGL, thereby lowering the potential of the first node N1 and compensating for the threshold loss of the first node N1, so that the first output control module 11 is fully turned on and the occurrence of the tailing phenomenon is suppressed.

[0065] Figure 4 FIG. 1 is another schematic diagram of the structure of the shift register 100 in the driving circuit provided in an embodiment of the invention. This embodiment illustrates a specific structure of the first node potential maintaining module 30 in the shift register 100 .

[0066] Please refer to Figure 4 In an optional embodiment of the present invention, the first node potential maintaining module 30 includes a first transistor T1, a second transistor T2 and a first capacitor C1, wherein the gate of the first transistor T1 is electrically connected to the first electrode of the first transistor T1 and coupled to the fifth node N5, the second electrode of the first transistor T1 is connected to the first node N1, wherein the fifth node N5 is electrically connected to the fourth node N4;

[0067] The gate of the second transistor T2 is connected to the fifth node N5, the first electrode is connected to the second clock signal terminal XCK, and the second electrode is connected to the sixth node N6; the two ends of the first capacitor C1 are respectively connected to the sixth node N6 and the first electrode of the first transistor T1.

[0068] Specifically, Figure 4 A circuit structure of a first node potential maintaining module 30 is illustrated. In this embodiment, the first node potential module includes a first transistor T1, a second transistor T2 and a first capacitor C1. Optionally, this embodiment is described by taking the first transistor T1 and the second transistor T2 as P-type transistors. Of course, in some other embodiments of the present invention, the first transistor T1 and the second transistor T2 may also be embodied as N-type transistors, and the present invention does not specifically limit this.

[0069] The gate and the first electrode of the first transistor T1 are connected together and connected to the fifth node N5, and the second electrode of the first transistor T1 is connected to the first node N1; the gate of the second transistor T2 is connected to the fifth node N5, the first electrode is connected to the second clock signal terminal XCK, and the second electrode is connected to the sixth node N6; one end of the first capacitor C1 is connected to the sixth node N6, and the other end is connected to the gate and the first electrode of the first transistor T1. When the first node N1 provides the conduction level to the first output control module 11, optionally, the fourth node N4 provides the conduction level to the fifth node N5, so that the second transistor T2 is turned on, and the signal of the second clock signal terminal XCK is transmitted to the sixth node N6 through the second transistor T2. Due to the coupling effect of the first capacitor C1, the potential of the end of the first capacitor C1 connected to the sixth node N6 is higher than the potential of the end connected to the gate and the first electrode of the first transistor T1.

[0070] When the low level signal of the first voltage terminal VGL is output through the first output control module 11, since the output signal is a low level signal, the low level signal will be coupled to the potential of the first node N1 through the first output control module 11, so that the potential of the first node N1 is lower than the low level signal output by the first voltage terminal VGL. When the potential of the first node N1 is lower than the low level signal of the first voltage terminal VGL and the potential of the fifth node N5 is a low level signal, the first transistor T1 will remain in the cut-off state. When the second transistor T2 is turned on and the signal of the second clock signal terminal XCK is a low level signal, due to the coupling effect of the first capacitor C1, the potential of one end of the first capacitor C1 connected to the gate of the first transistor T1 will be reduced and become a first level signal far lower than the low level signal of the first voltage terminal VGL, so that the first transistor T1 is turned on. When the first transistor T1 is turned on, the first level signal will be transmitted to the first node N1, thereby further lowering the potential of the first node N1, so that the first output control module 11 can still be fully turned on and output the signal of the first voltage terminal VGL through the output terminal OUT to avoid tailing of the output signal.

[0071] Figure 5FIG. 1 is another structural schematic diagram of the shift register 100 in the driving circuit provided in an embodiment of the present invention. This embodiment illustrates another specific structure of the first node potential maintaining module 30 in the shift register 100 .

[0072] Please refer to Figure 5 In an optional embodiment of the present invention, the first node potential maintaining module 30 further includes a third transistor T3, the gate of the third transistor T3 is connected to the first voltage terminal VGL, the first electrode is connected to the fourth node N4, and the second electrode is connected to the fifth node N5. Optionally, the first electrode is the source of the third transistor T3, and the second electrode is the drain of the third transistor T3.

[0073] Specifically, the embodiment of the present invention introduces the third transistor T3 between the fourth node N4 and the fifth node N5, which can limit the direction of the signal, for example, the control electric signal can only be transmitted from the fourth node N4 to the fifth node N5, but cannot be transmitted from the fifth node N5 to the fourth node N4. Considering that in the first node potential maintaining module 30, the potential of the sixth node N6 will change with the change of the potential of the second clock signal terminal XCK, due to the coupling effect of the first capacitor C1, the potential of the fifth node N5 will change with the change of the potential of the sixth node N6, therefore, when the third transistor T3 is introduced, it can be avoided that the potential of the fifth node N5 changes to affect the potential of the fourth node N4, and affect the state of other transistors connected to the fourth node N4, so the introduction of the third transistor T3 is conducive to maintaining the stability of the circuit.

[0074] Figure 6 FIG. 1 is another structural schematic diagram of the shift register 100 in the driving circuit provided in an embodiment of the present invention. This embodiment illustrates another specific structure of the first node potential maintaining module 30 in the shift register 100 .

[0075] Please refer to Figure 6 In an optional embodiment of the present invention, the first node potential maintaining module 30 further includes a fourth transistor T4, a gate of the fourth transistor T4 is connected to the first clock signal terminal CK, a first electrode is connected to the second clock signal terminal XCK, and a second electrode of the fourth transistor T4 is connected to the sixth node N6.

[0076] Specifically, the present embodiment introduces a fourth transistor T4 between the second clock signal terminal XCK and the sixth node N6, the gate of the fourth transistor T4 is connected to the first clock signal terminal CK, and is used to be turned on in response to the conduction level of the first clock signal terminal CK, and optionally, the fourth transistor T4 is a P-type transistor, and when the signal of the first voltage terminal VGL connected to the gate of the fourth transistor T4 is a low-level signal, the fourth transistor T4 remains in a conducting state. In some other embodiments of the present invention, the fourth transistor T4 may also be an N-type transistor, and accordingly, the signal connected to its gate is a high-level signal, so that the fourth transistor T4 remains in a conducting state.

[0077] When the fourth transistor T4 is turned on, the signal of the second clock signal terminal XCK can be transmitted to the sixth node N6. Since the potential of the fifth node N5 affects the conduction state of the second transistor T2, and thus affects the signal of the second clock signal terminal XCK transmitted to the sixth node N6 through the second transistor T2, when the potential of the fifth node N5 changes, the potential transmitted to the sixth node N6 through the second transistor T2 will be unstable. After the fourth transistor T4 is introduced in this embodiment, the fourth transistor T4 is turned on in response to the conduction level of the first clock signal terminal CK, and after being turned on, the signal of the second clock signal terminal XCK can be transmitted to the sixth node N6, thereby ensuring that when the potential of the fifth node N5 is unstable, the target potential can still be written into the sixth node N6.

[0078] Figure 7 FIG. 2 is another structural schematic diagram of the shift register 100 in the driving circuit provided in an embodiment of the present invention. This embodiment illustrates another specific structure of the first node potential maintaining module 30 in the shift register 100 .

[0079] Please refer to Figure 7 In an optional embodiment of the present invention, the first node potential maintaining module 30 further includes a fifth transistor T5, the gate of the fifth transistor T5 is connected to the first voltage terminal VGL, and the first electrode and the second electrode are connected in series between the fourth node N4 and the first node N1.

[0080] Specifically, the present embodiment introduces a fifth transistor T5 in the first node potential maintaining module 30, and the fifth transistor T5 is used to be turned on in response to the signal of the first voltage terminal VGL. Among them, the first electrode of the fifth transistor T5 is connected to the fourth node N4, and the second electrode is connected to the first node N1. Optionally, the first electrode of the fifth transistor T5 is a source electrode, and the second electrode is a drain electrode. Optionally, the fifth transistor T5 is a P-type transistor, and when the signal of the first voltage terminal VGL connected to the gate of the fifth transistor T5 is a low-level signal, the fifth transistor T5 remains in a conducting state. In some other embodiments of the present invention, the fifth transistor T5 can also be an N-type transistor, and accordingly, the signal connected to its gate is a high-level signal, so that the fifth transistor T5 remains in a conducting state.

[0081] The fifth transistor T5 introduced in this embodiment has the function of limiting the direction of the electric signal. When the fifth transistor T5 is turned on, the electric signal can be transmitted from the fourth node N4 to the first node N1, but cannot be transmitted from the first node N1 to the fourth node N4. When the first output control module 11 is turned on, the signal of the first voltage terminal VGL is output through the first output control module 11. Due to the coupling effect of the first output control module 11, the potential of the first node N1 will change. If the changed potential of the first node N1 is transmitted to the fourth node N4, it will affect the state of the transistor connected to the fourth node N4 and affect the stability of the circuit. Therefore, by introducing the fifth transistor T5, this embodiment can inhibit the electric signal of the first node N1 from being transmitted to the fourth node N4, thereby ensuring the stability of the potential of the fourth node N4, which is conducive to improving the stability of the circuit.

[0082] Figure 8 FIG. 1 is another structural schematic diagram of the shift register 100 in the driving circuit provided in an embodiment of the present invention. This embodiment illustrates another specific structure of the first node potential maintaining module 30 in the shift register 100 .

[0083] In this embodiment, the first node N1 potential maintaining module includes a first transistor T1, a second transistor T2 and a first capacitor C1, wherein the gate of the first transistor T1 is connected to the input terminal IN, the first electrode is connected to the fifth node N5, the second electrode is connected to the first node N1, and the fifth node N5 is electrically connected to the fourth node N4; the gate of the second transistor T2 is connected to the fifth node N5, the first electrode is connected to the second clock signal terminal XCK, and the second electrode is connected to the sixth node N6; the two ends of the first capacitor C1 are respectively connected to the sixth node N6 and the fifth node N5; wherein the first transistor T1 is an oxide transistor.

[0084] Specifically, Figure 8Another circuit structure of the first node potential maintaining module is illustrated. In this embodiment, the first node potential module includes a first transistor T1, a second transistor T2 and a first capacitor C1. Optionally, this embodiment is illustrated by taking the second transistor T2 as a P-type transistor as an example. Of course, in some other embodiments of the present invention, the second transistor T2 can also be embodied as an N-type transistor, and the present invention does not specifically limit this.

[0085] In this embodiment, the first transistor T1 is an oxide transistor, the gate of the first transistor T1 is connected to the input terminal, and when the input terminal IN is at a low level, the first transistor T1 is turned off. When the first node N1 provides the conduction level to the first output control module 11, optionally, the fourth node N4 provides the conduction level to the fifth node N5, so that the second transistor T2 is turned on, and the signal of the second clock signal terminal XCK is transmitted to the sixth node N6 through the second transistor T2. Due to the coupling effect of the first capacitor C1, the potential of the end of the first capacitor C1 connected to the sixth node N6 is higher than the potential of the end connected to the gate of the first transistor T1 and the first electrode.

[0086] When the low-level signal of the first voltage terminal VGL is output through the first output control module 11, since the output signal is a low-level signal, the low-level signal will be coupled to the potential of the first node N1 through the first output control module 11, so that the potential of the first node N1 is lower than the low-level signal output by the first voltage terminal VGL, and the low-level signal output by the first output module will have no tail. When the signal at the second clock signal terminal XCK becomes a low-level signal, due to the coupling effect of the first capacitor C1, the potential of one end of the first capacitor C1 connected to the fifth node N5 will be reduced and become a first-level signal which is much lower than the low-level signal of the first voltage terminal VGL. The first transistor T1 is an oxide transistor, and the threshold voltage of the oxide transistor is positive and the leakage current is very small. When the potential of the fifth node N5 connected to its first pole is lower than the potential of the first node N1 connected to its second pole and the input terminal IN connected to its gate is a low-level signal, the first transistor T1 is turned on, and the first-level signal will be transmitted to the first node N1 through the first transistor T1, thereby further lowering the potential of the first node N1, so that the first output control module 11 can still be fully turned on, and the signal of the first voltage terminal VGL is output through the output terminal OUT, thereby avoiding the phenomenon of tailing of the output signal.

[0087] Fig. 9 FIG. 1 is another structural schematic diagram of the shift register 100 in the driving circuit provided in an embodiment of the present invention. This embodiment illustrates another specific structure of the first node potential maintaining module 30 in the shift register 100 .

[0088] Please refer to Fig. 9In an optional embodiment of the present invention, the first node potential maintaining module 30 further includes a third transistor T3, a gate of the third transistor T3 is connected to the first voltage terminal VGL, a first electrode is connected to the fourth node N4, and a second electrode is connected to the fifth node N5.

[0089] Specifically, when the first transistor T5 in the first node potential maintaining module 30 is an oxide transistor, the third transistor T3 is introduced between the fourth node N4 and the fifth node N5 in the first node potential maintaining module 30, which can limit the direction of the signal, for example, the control signal can only be transmitted from the fourth node N4 to the fifth node N5, but cannot be transmitted from the fifth node N5 to the fourth node N4. Considering that in the first node potential maintaining module 30, the potential of the sixth node N6 will change with the change of the potential of the second clock signal terminal XCK, due to the coupling effect of the first capacitor C1, the potential of the fifth node N5 will change with the change of the potential of the sixth node N6, therefore, when the third transistor T3 is introduced, it can be avoided that the potential of the fifth node N5 changes to affect the potential of the fourth node N4, and affect the state of other transistors connected to the fourth node N4, so the introduction of the third transistor T3 is conducive to maintaining the stability of the circuit.

[0090] Fig.10 FIG. 1 is another structural schematic diagram of the shift register 100 in the driving circuit provided in an embodiment of the present invention. This embodiment illustrates another specific structure of the first node potential maintaining module 30 in the shift register 100 .

[0091] Please refer to Fig.10 In an optional embodiment of the present invention, the first node potential maintaining module 30 further includes a fourth transistor T4, a gate of the fourth transistor T4 is connected to the first clock signal terminal CK, a first electrode is connected to the second clock signal terminal XCK, and a second electrode of the fourth transistor T4 is connected to the sixth node N6.

[0092] Specifically, when the first transistor T5 in the first node potential maintaining module 30 is an oxide transistor, the fourth transistor T4 is introduced between the second clock signal terminal XCK and the sixth node N6 in this embodiment, and the gate of the fourth transistor T4 is connected to the first clock signal terminal CK, and is used to be turned on in response to the conduction level of the first clock signal terminal CK. Optionally, the fourth transistor T4 is a P-type transistor, and when the signal of the first voltage terminal VGL connected to the gate of the fourth transistor T4 is a low-level signal, the fourth transistor T4 remains in a conducting state. In some other embodiments of the present invention, the fourth transistor T4 can also be an N-type transistor, and accordingly, the signal connected to its gate is a high-level signal, so that the fourth transistor T4 remains in a conducting state.

[0093] When the fourth transistor T4 is turned on, the signal of the second clock signal terminal XCK can be transmitted to the sixth node N6. Since the potential of the fifth node N5 affects the conduction state of the second transistor T2, and thus affects the signal of the second clock signal terminal XCK transmitted to the sixth node N6 through the second transistor T2, when the potential of the fifth node N5 changes, the potential transmitted to the sixth node N6 through the second transistor T2 will be unstable. After the fourth transistor T4 is introduced in this embodiment, the fourth transistor T4 is turned on in response to the conduction level of the first clock signal terminal CK, and after being turned on, the signal of the second clock signal terminal XCK can be transmitted to the sixth node N6, thereby ensuring that when the potential of the fifth node N5 is unstable, the target potential can still be written into the sixth node N6.

[0094] Fig.11 FIG. 1 is a circuit diagram of a shift register 100 in a driving circuit provided in an embodiment of the present invention. This embodiment illustrates a detailed circuit structure of each module in the shift register 100. It should be noted that: Fig.11 Only one circuit structure of the first node potential maintaining module 30 is shown. In some other embodiments of the present invention, Fig.11 The circuit structure of the first node potential maintaining module 30 can also be replaced by Figure 4 , Figure 5 or Figure 6 The structure in the present invention is not specifically limited to this.

[0095] Please refer to Fig.11 In an optional embodiment of the present invention, the first node control module 21 includes a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8, wherein the gate of the sixth transistor T6 is connected to the first clock signal terminal CK, the first electrode is connected to the input terminal IN, and the second electrode is connected to the fourth node N4; the gate of the seventh transistor T7 is connected to the second clock signal terminal XCK, the first electrode is connected to the second electrode of the eighth transistor T8, and the second electrode is connected to the fourth node N4; the gate of the eighth transistor T8 is connected to the third node N3, and the first electrode is connected to the second voltage terminal VGH.

[0096] Optionally, this embodiment is described by taking the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 included in the first node control module 21 as P-type transistors. In some other embodiments of the present invention, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 may also be embodied as N-type transistors, and the present invention does not specifically limit this.

[0097] Specifically, in the first node control module 21, the gates of the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are connected to different signal terminals, and the second electrodes of the sixth transistor T6 and the seventh transistor T7 are coupled to the first node N1. When the first clock signal terminal CK provides a conduction level to the sixth transistor T6, the signal of the input terminal IN can be transmitted to the first node N1 through the sixth node N6; when the seventh transistor T7 is turned on in response to the conduction level of the second clock signal terminal XCK, and the eighth transistor T8 is turned on in response to the conduction level of the third node N3, the signal of the second voltage terminal VGH can be transmitted to the first node N1 through the eighth transistor T8 and the seventh transistor T7. Optionally, the signal transmitted to the first node N1 through the eighth transistor T8 and the seventh transistor T7 is a high-level signal, and the first output control module 11 will be in a cut-off state. Optionally, when the signal transmitted to the first node N1 through the sixth transistor T6 is a low-level signal, the first output control module 11 will be turned on, and the signal of the first voltage terminal VGL can be output through the first output control module 11. In this way, the potential of the first node can be controlled through the cooperation of the three transistors.

[0098] Understandably, Fig.11 Only one structure of the first node control module 21 capable of controlling the potential of the first node is shown. In some other embodiments of the present invention, the first node control module 21 may also adopt other feasible structures to control the potential of the first node N1, and the present invention does not specifically limit this. For example, please refer to Fig.12 , Fig.12 FIG. 1 is another circuit diagram of the shift register 100 in the driving circuit provided in an embodiment of the present invention. This embodiment illustrates a detailed circuit structure of each module in the shift register 100. It should be noted that: Fig.12 Only one circuit structure of the first node potential maintaining module 30 is shown when the first transistor is an oxide transistor. In some other embodiments of the present invention, Fig.12 The circuit structure of the first node potential maintaining module 30 can also be replaced by Figure 8 , Fig. 9 or Fig.10 The present invention does not specifically limit the structure in this regard. Of course, Fig.12 The first node potential maintaining module in can also be embodied as Figure 4 , Fig.11 , Figure 5 or Figure 6 The structures in the present invention are no longer shown one by one.

[0099] Continue to refer Fig.12In an optional embodiment of the present invention, the first node control module 21 includes a sixth transistor T6 and a seventh transistor T7, wherein the gate of the sixth transistor T6 is connected to the first clock signal terminal CK, the first electrode is connected to the input terminal IN, and the second electrode is connected to the fourth node N4; the gate of the seventh transistor T7 is connected to the second node N2, the first electrode is connected to the second voltage terminal VGH, and the second electrode is connected to the first node N1.

[0100] Optionally, this embodiment is described by taking the sixth transistor T6 and the seventh transistor T7 included in the first node control module 21 as P-type transistors. In some other embodiments of the present invention, the sixth transistor T6 and the seventh transistor T7 may also be N-type transistors, and the present invention does not specifically limit this.

[0101] Specifically, in the first node control module 21, the gates of the sixth transistor T6 and the seventh transistor T7 are connected to different signal terminals, and the second electrodes of the sixth transistor T6 and the seventh transistor T7 are coupled to the first node N1. When the first clock signal terminal CK provides a conduction level to the sixth transistor T6, the signal of the input terminal IN can be transmitted to the first node N1 through the sixth node N6. Optionally, when the signal transmitted to the first node N1 via the sixth transistor T6 is a low-level signal, the first output control module 11 will be turned on, and the signal of the first voltage terminal VGL will be able to be output through the first output control module 11. When the conduction level of the second node N2 is transmitted to the seventh transistor T7, the seventh transistor T7 is turned on, and the high-level signal of the second voltage terminal VGH will be transmitted to the first node N1, so that the first output control module 11 is in a cut-off state. In this way, the control of the potential of the first node can be achieved through the cooperation of the two transistors.

[0102] Continue to refer Fig.11 or Fig.12 In an optional embodiment of the present invention, the second node control module 22 includes a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a second capacitor C2 and a third capacitor C3, wherein the gate of the ninth transistor T9 is connected to the third node N3, and the first electrode is connected to the second clock signal terminal XCK; the second capacitor C2 is coupled between the second electrode and the gate of the ninth transistor T9; the gate of the tenth transistor T10 is connected to the second clock signal terminal XCK, the first electrode is connected to the first electrode of the ninth transistor T9, and the second electrode of the tenth transistor T10 is connected to the second node N2; the gate of the eleventh transistor T11 is connected to the fourth node N4, the first electrode is connected to the second voltage terminal VGH, and the second electrode is connected to the second node N2; the third capacitor C3 is coupled between the second voltage terminal VGH and the second node N2.

[0103] Optionally, this embodiment is described by taking the ninth transistor T9, the tenth transistor T10 and the eleventh transistor T11 included in the second node control module 22 as P-type transistors. In some other embodiments of the present invention, the ninth transistor T9, the tenth transistor T10 and the eleventh transistor T11 may also be embodied as N-type transistors, and the present invention does not specifically limit this.

[0104] Specifically, the second node control module 22 in this embodiment includes three transistors and two capacitors, specifically a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a second capacitor C2 and a third capacitor C3, wherein the gates of the three transistors are connected to different signal terminals respectively, wherein the eleventh transistor T11 is used to respond to the conduction level of the first node N1 and turn on, so that the signal of the second voltage terminal VGH is transmitted to the second node N2; the ninth transistor T9 is turned on in response to the conduction level of the third node N3, and the tenth transistor T10 is turned on in response to the conduction level of the second clock signal terminal XCK, so that the signal of the second clock signal terminal XCK is transmitted to the second node N2 through the ninth transistor T9 and the tenth transistor T10. Among the signal transmitted to the second node N2 through the eleventh transistor T11 and the signal transmitted to the second node N2 through the ninth transistor T9 and the tenth transistor T10, one of them can control the second output control module 12 to be turned on, and the other can control the second output control module 12 to be turned off.

[0105] In this embodiment, a second capacitor C2 and a third capacitor C3 are introduced into the second node control module 22. The second capacitor C2 can be used to maintain the potential of the third node N3, and the third capacitor C3 can be used to maintain the potential of the second node N2, thereby making the on or off state of the second output control module 12 more stable.

[0106] It should be noted that Fig.11 and Fig.12 The second node control module 22 is illustrated by taking the structure of three transistors and two capacitors as an example. In some other embodiments of the present invention, the second node control module 22 may also adopt other feasible structures, which is not specifically limited in the present invention.

[0107] Continue to refer Fig.11 and Fig.12 In an optional embodiment of the present invention, the third node control module 23 includes a twelfth transistor T12 and a thirteenth transistor T13, wherein the gate of the twelfth transistor T12 is connected to the fourth node N4, the first electrode is connected to the third node N3, the second electrode of the twelfth transistor T12 and the gate of the thirteenth transistor T13 are both connected to the first clock signal terminal CK, the first electrode of the thirteenth transistor T13 is connected to the first voltage terminal VGL, and the second electrode is connected to the third node N3.

[0108] Optionally, in this embodiment, the twelfth transistor T12 and the thirteenth transistor T13 included in the third node control module 23, in some other embodiments of the present invention, the twelfth transistor T12 and the thirteenth transistor T13 can also be embodied as N-type transistors, and the present invention does not specifically limit this.

[0109] Specifically, the third node control module 23 includes a twelfth transistor T12 and a thirteenth transistor T13, wherein the gate of the twelfth transistor T12 is used to respond to the conduction level of the fourth node N4 and turn on. When the twelfth transistor T12 is turned on, the signal of the first clock signal terminal CK is transmitted to the third node N3 through the second transistor T2; the thirteenth transistor T13 is used to respond to the conduction level of the first clock signal terminal CK and turn on. When the thirteenth transistor T13 is turned on, the signal of the first voltage terminal VGL is transmitted to the third node N3 through the thirteenth transistor T13. At this time, the signal transmitted to the third node N3 is a low-level signal.

[0110] It should be noted that Fig.11 and Fig.12 The third node control module 23 is illustrated by taking two transistors as an example. In some other embodiments of the present invention, the third node control module 23 may also adopt other feasible structures, which is not specifically limited in the present invention.

[0111] Continue to refer Fig.11 and Fig.12 In an optional embodiment of the present invention, the first output control module 11 includes a fourteenth transistor T14, a gate of the fourteenth transistor T14 is connected to the first node N1, a first electrode is connected to the first voltage terminal VGL, and a second electrode is connected to the output terminal OUT.

[0112] Optionally, Fig.11 and Fig.12 The fourteenth transistor T14 is a P-type transistor for example. In some other embodiments of the present invention, the fourteenth transistor T14 may also be an N-type transistor, which is not limited in the present invention.

[0113] Specifically, in the shift register 100 provided in the embodiment of the present invention, the fourteenth transistor T14 is turned on in response to the conduction level of the first node N1. In this embodiment, when the first node N1 is a low level signal, the fourteenth transistor T14 will be turned on, and the signal of the first voltage terminal VGL will be transmitted to the output terminal OUT through the fourteenth transistor T14. The present invention uses one transistor to form the first output control module 11, which is conducive to simplifying the circuit structure of the drive circuit.

[0114] Continue to refer Fig.11 and Fig.12In an optional embodiment of the present invention, the second output control module 12 includes a fifteenth transistor T15, a gate of the fifteenth transistor T15 is connected to the second node N2, a first electrode is connected to the second voltage terminal VGH, and a second electrode is connected to the output terminal OUT.

[0115] Optionally, Fig.11 and Fig.12 The fifteenth transistor T15 is a P-type transistor for example. In some other embodiments of the present invention, the fifteenth transistor T15 may also be an N-type transistor, which is not limited in the present invention.

[0116] Specifically, in this embodiment, the fifteenth transistor T15 is turned on in response to the conduction level of the second node N2. When the second node N2 is a low level signal, the fifteenth transistor T15 will be turned on, and the signal of the second voltage terminal VGH will be transmitted to the output terminal OUT through the fifteenth transistor T15. The present invention uses one transistor to form the second output control module 12, which is conducive to simplifying the circuit structure of the drive circuit.

[0117] Optionally, at the same time, only one of the fourteenth transistor T14 and the fifteenth transistor T15 is turned on, that is, only one outputs a signal.

[0118] In an optional embodiment of the present invention, the driving circuit provided in the embodiment of the present invention is a gate driving circuit.

[0119] Specifically, when the driving circuit of the present application is a gate driving circuit in a display panel, the output terminal OUT of the gate driving circuit is used to connect the scan line in the display panel. In practical applications, the gate driving circuit can control the sub-pixels on the display panel to be turned on row by row. Since the present invention introduces a first node potential maintaining module 30 in the shift register 100 of the gate driving circuit, the first node potential can be pulled down when the first output control module 11 outputs a signal of the first voltage terminal VGL, so as to ensure that the first output control module 11 is fully turned on, suppress the output tailing phenomenon, and thus help improve the display effect.

[0120] Based on the same inventive concept, the present invention also provides a display panel. Fig.13 FIG. 1 is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. The display panel includes the driving circuit in any one of the above embodiments.

[0121] Optionally, Fig.13The display panel shown includes a display area and a non-display area. This embodiment is described by taking the example of providing a driving circuit on both sides of the display area. For example, a bilateral driving method can be used to drive the sub-pixels in the display panel. In some other embodiments of the present invention, a driving circuit can be provided on only one side of the display area, and a unilateral driving method can be used to drive the sub-pixels in the display panel. The present invention does not specifically limit this.

[0122] Please combine Figures 1 to 13 Since the first node potential maintaining module 30 is introduced into the shift register 100 of the driving circuit in the display panel provided by the embodiment of the present invention, when the first output control module 11 is turned on and the signal of the first voltage terminal VGL is output through the first output control module 11, the first node potential maintaining module 30 can be controlled to transmit a first level signal with a smaller voltage value to the first node N1 to pull down the potential of the first node N1. When the potential of the first node N1 is pulled down, the threshold loss of the first node N1 can be compensated. After the threshold of the first node N1 is compensated, it is beneficial to maintain the conduction state of the first output control module 11 in a constant state, so that the first output control module 11 is fully turned on, so that the first output control module 11 can output the signal of the first voltage terminal VGL from the first output control module 11 constantly, avoiding the tailing phenomenon, and thus helping to improve the display effect of the display panel.

[0123] Based on the same inventive concept, the present invention also provides a driving method for a driving circuit. Figures 1 to 11 The driving circuit includes at least two cascaded shift registers 100, the shift register 100 includes: an input terminal IN, an output terminal OUT, a first voltage terminal VGL, a second voltage terminal VGH, a first clock signal terminal CK, a second clock signal terminal XCK, and,

[0124] A first output control module 11, configured to transmit the voltage of the first voltage terminal VGL to the output terminal OUT in response to the conduction level of the first node N1;

[0125] A second output control module 12, configured to transmit the voltage of the second voltage terminal VGH to the output terminal OUT in response to the conduction level of the second node N2;

[0126] The first node control module 21 is used to transmit the voltage of the input terminal IN to the first node N1 in response to the conduction level of the first clock signal terminal CK, and transmit the voltage of the second voltage terminal VGH to the first node N1 in response to the conduction level of the second clock signal terminal XCK and the third node N3, or in response to the conduction level of the second node N2;

[0127] The second node control module 22 is used to transmit the voltage of the second voltage terminal VGH to the second node N2 in response to the conduction level of the first node N1, and to transmit the voltage of the second clock signal terminal XCK to the second node N2 in response to the conduction level of the third node N3 and the second clock signal terminal XCK;

[0128] The third node control module 23 is used to transmit the voltage of the first voltage terminal VGL to the third node N3 in response to the conduction level of the first clock signal terminal CK, and transmit the voltage of the first clock signal terminal CK to the third node N3 in response to the conduction level of the first node N1;

[0129] The first node potential maintaining module 30 is electrically connected to the fourth node N4 with the first node control module 21, and is connected in series between the fourth node N4 and the first node N1;

[0130] Please refer to Fig.14 , Fig.14 FIG. 1 is a flow chart of a driving method of a driving circuit provided by an embodiment of the present invention. The driving method includes:

[0131] Please combine Figures 1 to 11 In the first output stage, the first node control module 21 responds to the conduction level of the first clock signal terminal CK, transmits the voltage of the input terminal IN to the first node N1, turns on the first output control module 11, and outputs the signal of the first voltage terminal VGL through the output terminal OUT;

[0132] In the first node potential maintaining stage, the first node potential maintaining module 30 responds to the conduction level of the first clock signal terminal CK, transmits the signal of the input terminal IN to the fourth node N4, and responds to the signal of the fourth node N4 and the signal of the second clock signal terminal XCK, or responds to the signal of the input terminal IN, the fourth node N4 and the second clock signal terminal XCK, and transmits the first level signal to the first node N1, wherein the voltage of the first level signal is lower than the voltage of the first voltage terminal VGL.

[0133] Specifically, please combine Figure 1-Figure 11 Fig.12 ,as well as Fig.14 The driving method of the driving circuit provided by the embodiment of the present invention includes a first output stage and a first node potential maintaining module 30 executed after the first output stage. In the first output stage, the first output control module 11 is turned on, and the signal of the first voltage terminal VGL is transmitted to the output terminal OUT via the first output control module 11. Fig.11 and Fig.12Taking the embodiment shown as an example, when the first clock signal terminal CK outputs a low level, the sixth transistor T6 in the first node control module 21 is turned on, and the low level signal of the input terminal IN is transmitted to the first node N1, so that the fourteenth transistor T14 in the first output control module 11 is turned on, and the low level signal of the first voltage terminal VGL is output to the output terminal OUT through the fourteenth transistor T14. At the same time, the signal of the input terminal IN is transmitted to the fourth node N4, and the signal of the fourth node N4 is transmitted to the fifth node N5, and the second transistor T2 is controlled to be turned on, so that the signal of the second clock signal terminal XCK is transmitted to the sixth node N6. In the first node potential maintenance stage, when the signal of the second clock signal terminal XCK changes from a high level signal to a low level signal, the potential of the sixth node N6 decreases. Due to the coupling effect of the first capacitor C1, the potential of the fifth node N5 will also become lower and become a first level signal lower than the voltage of the first voltage terminal VGL. Fig.11 In the embodiment, since the gate of the first transistor T1 is connected to the fifth node T5, Fig.12 As the first transistor T1 is an oxide transistor, when the potential of the fifth node N5 becomes a first level signal, Fig.11 and Fig.12 The first transistors T1 in the fifth node N5 will all be turned on, and the first level signal corresponding to the fifth node N5 will be transmitted to the first node N1 through the first transistor T1, pulling down the potential of the first node N1. When the potential of the first node N1 is pulled down, the threshold loss of the first node N1 can be compensated. After the threshold of the first node N1 is compensated, it is beneficial to maintain the conduction state of the first output control module 11 in a constant state, so that the first output control module 11 is fully turned on, so that the first output control module 11 can output the signal of the first voltage terminal VGL from the first output control module 11 constantly, avoiding the tailing phenomenon, and thus helping to improve the display effect of the display panel.

[0134] Continue to refer Figure 2 and Fig.11 ,as well as Figure 3 and Fig.12In an optional embodiment of the present invention, the first node potential maintaining module 30 includes a first transistor T1, a second transistor T2 and a first capacitor C1, wherein the gate of the first transistor T1 is electrically connected to the first electrode of the first transistor T1 and coupled to the fifth node N5, or the first transistor T1 is an oxide transistor, the gate of the first transistor T1 is connected to the input terminal IN, and the first electrode is connected to the fifth node N5; the second electrode of the first transistor T1 is connected to the first node N1, wherein the fifth node N5 is electrically connected to the fourth node N4; the gate of the second transistor T2 is connected to the fifth node N5, the first electrode is connected to the second clock signal terminal XCK, and the second electrode is connected to the sixth node N6; the two ends of the first capacitor C1 are respectively connected to the sixth node N6 and the first electrode of the first transistor T1;

[0135] In the first output stage, the first transistor T1 is turned off, the signal at the input terminal IN is transmitted to the fifth node N5 via the fourth node N4, the second transistor T2 is controlled to be turned on, the signal at the second clock signal terminal XCK is transmitted to the sixth node N6, and the potential of the end of the first capacitor C1 connected to the sixth node N6 is higher than the potential of the end connected to the gate and the first electrode of the first transistor T1.

[0136] Fig.11 and Fig.12 In the illustrated embodiment, the transistors in the first node control module 21 and the first node potential maintaining module 30 are both P-type transistors. In some other embodiments of the present invention, the transistors in the first node control module 21 and the first node potential maintaining module 30 may also be both N-type transistors, which is not specifically limited in the present invention.

[0137] Specifically, in the first output stage, the first node N1 is at a low level, the fourteenth transistor T14 in the first output control module 11 is turned on, and the low level signal of the first voltage terminal VGL is transmitted to the output terminal OUT. Due to the coupling effect of the fourteenth transistor T14, the potential of the first node N1 is reduced, so that the potential of the first node N1 is much lower than the potential of the first voltage terminal VGL, the fourteenth transistor T14 is fully turned on, and the signal outputted by the fourteenth transistor T14 has no tail.

[0138] At the same time, in the first output stage, the first clock signal terminal CK is at a low level, and the input terminal IN is also at a low level. At this time, the sixth transistor T6 is turned on, and the low level signal of the input terminal IN is transmitted to the fourth node N4, and then transmitted to the fifth node N5, so that the second transistor T2 is turned on, and the high level signal of the second clock signal terminal XCK is transmitted to the sixth node N6. Due to the coupling effect of the first capacitor C1, the potential of the sixth node N6 is higher than the potential of the gate and the first electrode of the first transistor T1. When the fifth node N5 is at a low level, due to the low level signal of the first voltage terminal VGL of the potential of the first node N1, it will also be lower than the low level potential of the fifth node N5, so the first transistor T1 is in a cut-off state at this time.

[0139] Continue to refer Fig.11 and Fig.12 In an optional embodiment of the present invention, during the first node potential maintaining stage, the second clock signal terminal XCK changes from a high level signal to a low level signal, and transmits the low level signal to the sixth node N6, and the potential of the fifth node N5 is coupled to a first level signal through the first capacitor C1, so that the first transistor T1 is turned on, and the first transistor T1 transmits the first level signal to the first node N1.

[0140] Specifically, if the first node potential maintaining module 30 is not introduced, when the potential of the first node N1 gradually increases, it may affect the conduction state of the fourteenth transistor T14, and the output tailing phenomenon occurs. When the present invention introduces the first node potential maintaining module 30, and in the first node potential maintaining stage, the signal of the second clock signal terminal XCK changes from a high level to a low level, and the low level signal is transmitted to the sixth node N6. Due to the coupling effect of the first capacitor C1, the potential of the gate and the first electrode of the first transistor T1 is reduced accordingly, and is reduced to a first level signal lower than the low level signal of the first voltage terminal VGL, so that the first transistor T1 is turned on. At this time, the first level signal is transmitted to the first node N1, and the potential of the first node N1 is further lowered to ensure that the fourteenth transistor T14 can still be fully turned on, and the signal of the first voltage terminal VGL is smoothly output, which effectively suppresses the output tailing phenomenon, thereby being conducive to improving the display effect.

[0141] Continue to refer Fig.11 and Fig.12 In an optional embodiment of the present invention, the first node potential maintaining module 30 further includes a fourth transistor T4, a gate of the fourth transistor T4 is connected to the first clock signal terminal CK, a first electrode is connected to the second clock signal terminal XCK, and a second electrode of the fourth transistor T4 is connected to the sixth node N6; in the first node potential maintaining stage, the fourth transistor T4 is turned on in response to the signal of the first clock signal terminal CK, and the signal of the second clock signal terminal XCK is transmitted from the fourth transistor T4 to the sixth node N6.

[0142] Specifically, the present invention introduces a fourth transistor T4 in the first node potential maintaining module 30, and the gate of the fourth transistor T4 is connected to the first clock signal terminal CK, and is used to be turned on in response to the conduction level of the first clock signal terminal CK. Optionally, this embodiment only takes the fourth transistor T4 as a P-type transistor as an example for illustration. In some other embodiments of the present invention, the fourth transistor T4 can also be embodied as an N-type transistor.

[0143] When the fourth transistor T4 is turned on, the signal of the second clock signal terminal XCK can be transmitted to the sixth node N6. In the first node potential maintaining module 30, since the potential of the fifth node N5 affects the conduction state of the second transistor T2, thereby affecting the signal of the second clock signal terminal XCK transmitted to the sixth node N6 through the second transistor T2, when the potential of the fifth node N5 changes, the potential transmitted to the sixth node N6 through the second transistor T2 will be unstable. After the fourth transistor T4 is introduced in this embodiment, the fourth transistor T4 is turned on in response to the conduction level of the first clock signal terminal CK, and after being turned on, the signal of the second clock signal terminal XCK can be stably transmitted to the sixth node N6, thereby ensuring that when the potential of the fifth node N5 is unstable, the target potential can still be written to the sixth node N6.

[0144] Continue to refer Fig.11 and Fig.12 In an optional embodiment of the present invention, the first node potential maintaining module 30 also includes a fifth transistor T5, the gate of the fifth transistor T5 is connected to the first voltage terminal VGL, and the first electrode and the second electrode are connected in series between the fourth node N4 and the first node N1; in the first output stage, the fifth transistor T5 is turned on, and the voltage of the input terminal IN is transmitted to the first node N1 through the fifth transistor T5.

[0145] Specifically, the fifth transistor T5 introduced in this embodiment has the function of limiting the direction of the electric signal. When the fifth transistor T5 is turned on, the electric signal can be transmitted from the fourth node N4 to the first node N1, but cannot be transmitted from the first node N1 to the fourth node N4. When the first output control module 11 is turned on, the signal of the first voltage terminal VGL is output through the first output control module 11. Due to the coupling effect of the first output control module 11, the potential of the first node N1 will change. If the changed potential of the first node N1 is transmitted to the fourth node N4, it will affect the state of the transistor connected to the fourth node N4 and affect the stability of the circuit. Therefore, by introducing the fifth transistor T5, this embodiment can inhibit the electric signal of the first node N1 from being transmitted to the fourth node N4, thereby ensuring the stability of the potential of the fourth node N4, which is conducive to improving the stability of the circuit.

[0146] Continue to refer Fig.11 and Fig.12In an optional embodiment of the present invention, the first node potential maintaining module 30 also includes a third transistor T3, the gate of the third transistor T3 is connected to the first voltage terminal VGL, the first electrode is connected to the fourth node N4, and the second electrode is connected to the fifth node N5; in the first node potential maintaining stage, the third transistor T3 is turned on, and the signal of the fourth node N4 is transmitted to the fifth node N5 through the third transistor T3.

[0147] Specifically, the embodiment of the present invention introduces the third transistor T3 between the fourth node N4 and the fifth node N5, which can limit the direction of the signal, for example, the control electric signal can only be transmitted from the fourth node N4 to the fifth node N5, but cannot be transmitted from the fifth node N5 to the fourth node N4. Considering that in the first node potential maintaining module 30, the potential of the sixth node N6 will change with the change of the potential of the second clock signal terminal XCK, due to the coupling effect of the first capacitor C1, the potential of the fifth node N5 will change with the change of the potential of the sixth node N6, therefore, when the third transistor T3 is introduced, it can be avoided that the potential of the fifth node N5 changes to affect the potential of the fourth node N4, and affect the state of other transistors connected to the fourth node N4, so the introduction of the third transistor T3 is conducive to maintaining the stability of the circuit.

[0148] In order to more clearly reflect the design concept of the present invention, the following Fig.11 , Fig.12 and Fig.15 The working process of the shift register 100 in the driving circuit of the present invention is further described, wherein: Fig.15 The following is a timing diagram of a driving circuit provided by an embodiment of the present invention. Fig.11 , Fig.12 and Fig.15 , the driving method of the driving circuit provided by the embodiment of the present invention includes:

[0149] In the t0 stage, the input terminal IN is at a low level, the first clock signal terminal CK is at a low level, the second clock signal terminal XCK is at a high level, the sixth transistor T6 is turned on, and the low level signal of the input terminal IN is transmitted to the fourth node N4, the first node N1 and the fifth node N5, the fourteenth transistor T14 is turned on, and the low level signal of the first voltage terminal VGL is output via the output terminal OUT; the second transistor T2 is turned on; the high level signal of the second clock signal terminal XCK is transmitted to the sixth node N6.

[0150] In the stage t1, the signal of the second clock signal terminal XCK changes from high level to low level, so that the signal of the sixth node N6 changes to low level. Due to the coupling effect of the first capacitor C1, the signal of the fifth node N5 changes to a first level signal lower than the above low level signal. Fig.11 and Fig.12The first transistors T1 in the circuit can all be turned on, and the first level signal is transmitted to the first node N1, which lowers the potential of the first node N1, so that the fourteenth transistor T14 is fully turned on, suppressing the output tailing phenomenon, and the output terminal OUT outputs a low level signal.

[0151] In the t2 stage, the input terminal IN is at a high level, the first clock signal terminal CK is at a low level, the second clock signal terminal XCK is at a high level, the high level signal of the input terminal IN is transmitted to the first node N1, and the fourteenth transistor T14 is turned off; the thirteenth transistor T13 is turned on, and the low level signal of the first voltage terminal VGL is transmitted to the third node N3 through the thirteenth transistor T13, and the ninth transistor T9 is turned on.

[0152] In the t3 phase, the input terminal IN is at a high level, the first clock signal terminal CK is at a high level, the second clock signal terminal XCK is at a low level, the tenth transistor T10 is turned on, the low level signal of the second clock signal terminal XCK is transmitted to the second node N2 through the tenth transistor T10, and the potential of the second node N2 is pulled down, the fifteenth transistor T15 is turned on, and the high level signal of the second voltage terminal VGH is output through the output terminal OUT. At this time, Fig.11 The seventh transistor T7 and the eighth transistor T8 are turned on, and the high level signal of the second voltage terminal VGH is transmitted to the first node N1 through the eighth transistor T8, the seventh transistor T7, the fourth node N4 and the fifth transistor T5, ensuring that the fourteenth transistor T14 is in the cut-off state, thereby ensuring the output stability of the fifteenth transistor T15. Fig.12 The seventh transistor T7 is turned on, and the high level signal of the second voltage terminal VGH is transmitted to the first node N1 through the seventh transistor T7, which can also ensure that the fourteenth transistor T14 is in a cut-off state, thereby ensuring the output stability of the fifteenth transistor T15.

[0153] In the t4 stage, the input terminal IN is at a high level, the first clock signal terminal CK is at a low level, the second clock signal terminal XCK is at a high level, the high level signal of the input terminal IN is transmitted to the first node N1, and the fourteenth transistor T14 is turned off; the thirteenth transistor T13 is turned on, and the low level signal of the first voltage terminal VGL is transmitted to the third node N3 through the thirteenth transistor T13, the ninth transistor T9 is turned on, and the tenth transistor T10 is turned off.

[0154] In the stage t5, the input terminal IN is at a low level, the first clock signal terminal CK is at a high level, the second clock signal terminal XCK is at a low level, and the fifteenth transistor T15 outputs a high level through the output terminal OUT.

[0155] In the t6 phase, the input terminal IN is at a low level, the first clock signal terminal CK is at a low level, the second clock signal terminal XCK is at a high level, the sixth transistor T6 is turned on, the low level of the input terminal IN is transmitted to the first node N1 through the sixth transistor T6, the fourth node N4 and the fifth transistor T5, the fourteenth transistor T14 is turned on, and the low level signal of the first voltage terminal VGL is output through the fourteenth transistor T14. Due to the coupling effect of the fourteenth transistor T14, when the potential of the output terminal OUT decreases, the potential of the first node N1 becomes lower and is lower than the low level of the first output terminal OUT. At this time, the fourteenth transistor T14 is fully turned on, and the output terminal OUT outputs the low level signal of the first voltage terminal VGL without tailing. At the same time, the low level signal of the input terminal IN is written into the fifth node N5 through the fourth node N4, the second transistor T2 is turned on, and the high level signal of the second clock signal terminal XCK is written into the sixth node N6 through the second transistor T2, so that the signal at both ends of the first capacitor C1 is high at one end and low at the other end.

[0156] At stage t7, the signal at the second clock signal terminal XCK changes from a high level to a low level, and the potential transmitted to the sixth node N6 decreases to become a low level signal at the second clock signal terminal XCK. Due to the coupling effect of the first capacitor C1, the potential of the fifth node N5 is pulled down to be much lower than the above low level signal. Assuming that the signal at the fifth node N5 is a first level signal, Fig.11 The gate of the first transistor T1 is connected to the fifth node N5, and the first level signal of the fifth node N5 turns on the first transistor T1; Fig.12 The first transistor T1 in the circuit is an oxide transistor, the threshold voltage of the oxide transistor is positive, and the leakage current is very small. When the potential of the fifth node N5 connected to the first electrode is lower than the potential of the first node N1 connected to the second electrode, and the input terminal IN connected to the gate is a low-level signal at the t7 stage, the oxide transistor will be turned on; when the first transistor T1 is turned on, the first-level signal is transmitted to the first node N1 through the first transistor T1, lowering the potential of the first node N1, so that the fourteenth transistor T14 can still be fully turned on, thereby suppressing the output tailing phenomenon.

[0157] In the stage t8, the input terminal IN is at a low level, the first clock signal terminal CK is at a low level, the second clock signal terminal XCK is at a high level, the low level signal of the input terminal IN is written into the fifth node N5 through the fourth node N4, the second transistor T2 is turned on, and the high level signal of the second clock signal terminal XCK is written into the sixth node N6.

[0158] In the t9 stage, the signal of the second clock signal terminal XCK changes from a high level to a low level, and the potential transmitted to the sixth node N6 is reduced and becomes a low-level signal of the second clock signal terminal XCK. Due to the coupling effect of the first capacitor C1, the potential of the fifth node N5 is pulled down to be much lower than the above-mentioned low-level signal. Assuming that the signal of the fifth node N5 is a first-level signal, the first-level signal turns on the first transistor T1 and is transmitted to the first node N1, pulling down the potential of the first node N1, so that the fourteenth transistor T14 can still be fully turned on, thereby suppressing the output tailing phenomenon.

[0159] In summary, the driving circuit and driving method thereof, and the display panel provided by the present invention achieve at least the following beneficial effects:

[0160] The driving circuit provided by the embodiment of the present invention is provided with a plurality of cascaded shift registers, and the shift register includes a first output control module, a second output control module, a first node control module, a second node control module and a third node control module, so that the first output control module and the second output control module are alternately turned on, and the signal of the first voltage terminal and the signal of the second voltage terminal are alternately output from the output terminal. In particular, in the gate driving circuit provided by the embodiment of the present invention, a first node potential maintaining module is introduced into the shift register, and the first node potential maintaining module is used to respond to the conduction level of the fourth node and the signal of the second clock signal terminal, and transmit the first level signal to the first node, and the voltage of the first level signal is lower than the voltage of the first voltage terminal. When the first output control module is turned on and the signal of the first voltage terminal is output through the output control module, the first node potential maintaining module can be controlled to transmit a first level signal with a smaller voltage value to the first node to lower the potential of the first node. When the potential of the first node is pulled down, the threshold loss of the first node can be compensated. After the threshold of the first node is compensated, it is beneficial to maintain the conduction state of the first output control module in a constant state, so that the first output control module is fully turned on, so that the first output control module can constantly output the signal of the first voltage end from the first output control module to avoid the tailing phenomenon, which is beneficial to improve the display effect of the display panel when the driving circuit is applied to the display panel.

[0161] Although some specific embodiments of the present invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that the above embodiments may be modified without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A driving circuit, characterized in that: The invention comprises at least two cascaded shift registers, wherein the shift register comprises: an input terminal, an output terminal, a first voltage terminal, a second voltage terminal, a first clock signal terminal, a second clock signal terminal, and, a first output control module, configured to transmit the voltage of the first voltage terminal to the output terminal in response to the conduction level of the first node; a second output control module, configured to transmit the voltage of the second voltage terminal to the output terminal in response to the conduction level of the second node; a first node control module, configured to transmit the voltage of the input terminal to the first node in response to the conduction level of the first clock signal terminal, and transmit the voltage of the second voltage terminal to the first node in response to the conduction levels of the second clock signal terminal and the third node, or in response to the conduction level of the second node; a second node control module, configured to transmit the voltage of the second voltage terminal to the second node in response to the conduction level of the first node, and to transmit the voltage of the second clock signal terminal to the second node in response to the conduction level of the third node and the second clock signal terminal; a third node control module, configured to transmit the voltage of the first voltage terminal to the third node in response to the conduction level of the first clock signal terminal, and transmit the voltage of the first clock signal terminal to the third node in response to the conduction level of the fourth node; a first node potential maintaining module, electrically connected to the fourth node with the first node control module, and configured to transmit a first level signal to the first node in response to a conduction level of the fourth node and a signal at the second clock signal terminal, or in response to a signal at the input terminal, the fourth node and the second clock signal terminal, wherein a voltage of the first level signal is lower than a voltage at the first voltage terminal; The first node potential maintaining module includes a first transistor, a second transistor, a fourth transistor and a first capacitor, wherein the gate of the first transistor is electrically connected to the first electrode of the first transistor and coupled to the fifth node, the second electrode of the first transistor is connected to the first node, wherein the fifth node is electrically connected to the fourth node; the gate of the second transistor is connected to the fifth node, the first electrode is connected to the second clock signal end, and the second electrode is connected to the sixth node; the two ends of the first capacitor are respectively connected to the sixth node and the first electrode of the first transistor; the gate of the fourth transistor is connected to the first clock signal end, the first electrode is connected to the second clock signal end, and the second electrode of the fourth transistor is connected to the sixth node; or, The first node potential maintaining module includes a first transistor, a second transistor and a first capacitor, wherein the gate of the first transistor is connected to the input end, the first electrode is connected to the fifth node, the second electrode is connected to the first node, and the fifth node is electrically connected to the fourth node; the gate of the second transistor is connected to the fifth node, the first electrode is connected to the second clock signal end, and the second electrode is connected to the sixth node; the two ends of the first capacitor are respectively connected to the sixth node and the fifth node; wherein the first transistor is an oxide transistor.

2. The driving circuit according to claim 1, characterized in that: The first node potential maintaining module is connected in series between the fourth node and the first node; the first node control module is connected to the first node through the fourth node; the second node control module is electrically connected to the second node and the third node respectively; the third node control module is connected to the third node; the first output control module and the second output control module are connected in series between the first voltage terminal and the second voltage terminal, the control end of the first output control module is connected to the first node, and the control end of the second output control module is connected to the second node.

3. The driving circuit according to claim 1, characterized in that: When the first node potential maintaining module includes a first transistor, a second transistor, a fourth transistor and a first capacitor, wherein the gate of the first transistor is electrically connected to the first electrode of the first transistor and coupled to the fifth node, the second electrode of the first transistor is connected to the first node, wherein the fifth node is electrically connected to the fourth node; the gate of the second transistor is connected to the fifth node, the first electrode is connected to the second clock signal end, and the second electrode is connected to the sixth node; and the two ends of the first capacitor are respectively connected to the sixth node and the first electrode of the first transistor, The first node potential maintaining module further includes a third transistor, wherein a gate of the third transistor is connected to the first voltage terminal, a first electrode is connected to the fourth node, and a second electrode is connected to the fifth node.

4. The driving circuit according to claim 1, characterized in that: The first node potential maintaining module further includes a fifth transistor, the gate of the fifth transistor is connected to the first voltage terminal, and the first electrode and the second electrode are connected in series between the fourth node and the first node.

5. The driving circuit according to claim 1, characterized in that: When the first node potential maintaining module includes a first transistor, a second transistor and a first capacitor, wherein the gate of the first transistor is connected to the input terminal, the first electrode is connected to the fifth node, the second electrode is connected to the first node, and the fifth node is electrically connected to the fourth node; the gate of the second transistor is connected to the fifth node, the first electrode is connected to the second clock signal terminal, and the second electrode is connected to the sixth node; the two ends of the first capacitor are connected to the sixth node and the fifth node respectively; wherein the first transistor is an oxide transistor, The first node potential maintaining module further includes a third transistor, a gate of the third transistor is connected to the first voltage terminal, a first electrode is connected to the fourth node, and a second electrode is connected to the fifth node.

6. The driving circuit according to claim 1, characterized in that: When the first node potential maintaining module includes a first transistor, a second transistor and a first capacitor, wherein the gate of the first transistor is connected to the input terminal, the first electrode is connected to the fifth node, the second electrode is connected to the first node, and the fifth node is electrically connected to the fourth node; the gate of the second transistor is connected to the fifth node, the first electrode is connected to the second clock signal terminal, and the second electrode is connected to the sixth node; the two ends of the first capacitor are connected to the sixth node and the fifth node respectively; wherein the first transistor is an oxide transistor, The first node potential maintaining module further includes a fourth transistor, a gate of the fourth transistor is connected to the first clock signal terminal, a first electrode is connected to the second clock signal terminal, and a second electrode of the fourth transistor is connected to the sixth node.

7. The driving circuit according to claim 1, characterized in that: The first node control module includes a sixth transistor, a seventh transistor and an eighth transistor, wherein the gate of the sixth transistor is connected to the first clock signal terminal, the first electrode is connected to the input terminal, and the second electrode is connected to the fourth node; the gate of the seventh transistor is connected to the second clock signal terminal, the first electrode is connected to the second electrode of the eighth transistor, and the second electrode is connected to the fourth node; the gate of the eighth transistor is connected to the third node, and the first electrode is connected to the second voltage terminal.

8. The driving circuit according to claim 1, characterized in that: The first node control module includes a sixth transistor and a seventh transistor, wherein the gate of the sixth transistor is connected to the first clock signal terminal, the first electrode is connected to the input terminal, and the second electrode is connected to the fourth node; the gate of the seventh transistor is connected to the second node, the first electrode is connected to the second voltage terminal, and the second electrode is connected to the first node.

9. The driving circuit according to claim 1, characterized in that: The second node control module includes a ninth transistor, a tenth transistor, an eleventh transistor, a second capacitor and a third capacitor, wherein the gate of the ninth transistor is connected to the third node, and the first electrode is connected to the second clock signal terminal; the second capacitor is coupled between the second electrode and the gate of the ninth transistor; The gate of the tenth transistor is connected to the second clock signal terminal, the first electrode is connected to the first electrode of the ninth transistor, and the second electrode of the tenth transistor is connected to the second node; The gate of the eleventh transistor is connected to the fourth node, the first electrode is connected to the second voltage terminal, and the second electrode is connected to the second node; the third capacitor is coupled between the second voltage terminal and the second node.

10. The driving circuit according to claim 1, characterized in that: The third node control module includes a twelfth transistor and a thirteenth transistor, wherein the gate of the twelfth transistor is connected to the fourth node, the first electrode is connected to the third node, the second electrode of the twelfth transistor and the gate of the thirteenth transistor are both connected to the first clock signal terminal, the first electrode of the thirteenth transistor is connected to the first voltage terminal, and the second electrode is connected to the third node.

11. The driving circuit according to claim 1, characterized in that: The first output control module includes a fourteenth transistor, a gate of the fourteenth transistor is connected to the first node, a first electrode is connected to the first voltage terminal, and a second electrode is connected to the output terminal.

12. The driving circuit according to claim 1, characterized in that: The second output control module includes a fifteenth transistor, a gate of the fifteenth transistor is connected to the second node, a first electrode is connected to the second voltage terminal, and a second electrode is connected to the output terminal.

13. The driving circuit according to claim 1, characterized in that: The driving circuit is a gate driving circuit.

14. A display panel, characterized in that: The invention comprises the driving circuit described in any one of claims 1 to 13.

15. A driving method for a driving circuit, characterized in that: The driving circuit includes at least two cascaded shift registers, the shift register including: an input terminal, an output terminal, a first voltage terminal, a second voltage terminal, a first clock signal terminal, a second clock signal terminal, and, a first output control module, configured to transmit the voltage of the first voltage terminal to the output terminal in response to the conduction level of the first node; a second output control module, configured to transmit the voltage of the second voltage terminal to the output terminal in response to the conduction level of the second node; a first node control module, configured to transmit the voltage of the input terminal to the first node in response to the conduction level of the first clock signal terminal, and transmit the voltage of the second voltage terminal to the first node in response to the conduction levels of the second clock signal terminal and the third node, or in response to the conduction level of the second node; a second node control module, configured to transmit the voltage of the second voltage terminal to the second node in response to the conduction level of the first node, and to transmit the voltage of the second clock signal terminal to the second node in response to the conduction level of the third node and the second clock signal terminal; a third node control module, configured to transmit the voltage of the first voltage terminal to the third node in response to the conduction level of the first clock signal terminal, and transmit the voltage of the first clock signal terminal to the third node in response to the conduction level of the first node; a first node potential maintaining module, electrically connected to the first node control module at a fourth node, and connected in series between the fourth node and the first node; The first node potential maintaining module includes a first transistor, a second transistor, a fourth transistor and a first capacitor, wherein the gate of the first transistor is electrically connected to the first electrode of the first transistor and coupled to the fifth node, the second electrode of the first transistor is connected to the first node, wherein the fifth node is electrically connected to the fourth node; the gate of the second transistor is connected to the fifth node, the first electrode is connected to the second clock signal end, and the second electrode is connected to the sixth node; the two ends of the first capacitor are respectively connected to the sixth node and the first electrode of the first transistor; the gate of the fourth transistor is connected to the first clock signal end, the first electrode is connected to the second clock signal end, and the second electrode of the fourth transistor is connected to the sixth node; or, The first node potential maintaining module comprises a first transistor, a second transistor and a first capacitor, wherein the gate of the first transistor is connected to the input terminal, the first electrode is connected to the fifth node, the second electrode is connected to the first node, and the fifth node is electrically connected to the fourth node; the gate of the second transistor is connected to the fifth node, the first electrode is connected to the second clock signal terminal, and the second electrode is connected to the sixth node; the two ends of the first capacitor are connected to the sixth node and the fifth node respectively; wherein the first transistor is an oxide transistor; The driving method comprises: In the first output stage, the first node control module transmits the voltage of the input terminal to the first node in response to the conduction level of the first clock signal terminal, so that the first output control module is turned on, and the signal of the first voltage terminal is output through the output terminal; In the first node potential maintaining stage, the first node potential maintaining module transmits the signal of the input terminal to the fourth node in response to the conduction level of the first clock signal terminal, and transmits the first level signal to the first node in response to the conduction level of the fourth node and the signal of the second clock signal terminal, or in response to the signals of the input terminal, the fourth node and the second clock signal terminal, wherein the voltage of the first level signal is lower than the voltage of the first voltage terminal.

16. The driving method according to claim 15, characterized in that: In the first output stage, the first transistor is turned off, the signal at the input end is transmitted to the fifth node via the fourth node to control the second transistor to be turned on, the signal at the second clock signal end is transmitted to the sixth node, and the potential of the end of the first capacitor connected to the sixth node is higher than the potential of the end connected to the gate and the first electrode of the first transistor.

17. The driving method according to claim 16, characterized in that: In the first node potential maintaining stage, the second clock signal end changes from a high level signal to a low level signal, and transmits the low level signal to the sixth node, the potential of the fifth node is lowered to a first level signal through the first capacitor coupling, so that the first transistor is turned on, and the first transistor transmits the first level signal to the first node.

18. The driving method according to claim 16, characterized in that: In the first node potential maintaining stage, the fourth transistor is turned on in response to the signal at the first clock signal terminal, and the signal at the second clock signal terminal is transmitted from the fourth transistor to the sixth node.

19. The driving method according to claim 16, characterized in that: When the first node potential maintaining module includes a first transistor, a second transistor, a fourth transistor and a first capacitor, wherein the gate of the first transistor is electrically connected to the first electrode of the first transistor and coupled to the fifth node, the second electrode of the first transistor is connected to the first node, wherein the fifth node is electrically connected to the fourth node; the gate of the second transistor is connected to the fifth node, the first electrode is connected to the second clock signal end, and the second electrode is connected to the sixth node; the two ends of the first capacitor are respectively connected to the sixth node and the first electrode of the first transistor; the gate of the fourth transistor is connected to the first clock signal end, the first electrode is connected to the second clock signal end, and the second electrode of the fourth transistor is connected to the sixth node, The first node potential maintaining module further includes a fifth transistor, the gate of the fifth transistor is connected to the first voltage terminal, and the first electrode and the second electrode are connected in series between the fourth node and the first node; In the first output stage, the fifth transistor is turned on, and the voltage at the input terminal is transmitted to the first node through the fifth transistor.

20. The driving method according to claim 16, characterized in that: The first node potential maintaining module further includes a third transistor, wherein the gate of the third transistor is connected to the first voltage terminal, the first electrode is connected to the fourth node, and the second electrode is connected to the fifth node; In the first node potential maintaining stage, the third transistor is turned on, and the signal of the fourth node is transmitted to the fifth node through the third transistor.

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