Array substrate, display panel and display device

Abstract

The present disclosure provides an array substrate, a display panel and a display device, and belongs to the technical field of display, which can solve the problem that static discharge is prone to occur between redundant fan-out wires in the existing fan-out area. The array substrate of the present disclosure has a display area and a fan-out area arranged on one side of the display area, and comprises a substrate, fan-out wires arranged in the middle area of the fan-out area on the substrate, and redundant fan-out wires arranged in the edge area of the fan-out area on the substrate; the redundant fan-out wires comprise a plurality of sub-redundant fan-out wires; the plurality of sub-redundant fan-out wires are arranged in a disconnected manner.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to an array substrate, a display panel, and a display device. Background Technology

[0002] With the continuous development of display technology, various types of display devices have gradually emerged, such as Liquid Crystal Display (LCD) devices and Organic Light-Emitting Display (OLED) devices. Currently, in display devices, data lines or gate lines in the display area are generally bonded to integrated circuits (ICs) through fan-out traces located in the non-display area. Before being bonded to the IC, the fan-out traces are centrally arranged in the fan-out area of ​​the non-display area, making the wiring density of the fan-out traces in the fan-out area much greater than the wiring density in other areas.

[0003] During the manufacturing process of display panels, the etching solution concentration differs between the edge and center regions of the fan-out traces. This difference in etching solution concentration leads to variations in the linewidth of the fan-out traces at the edges, potentially causing instability or even open circuits and affecting signal transmission. Redundant fan-out traces are often placed at the edges of the fan-out area. However, because these redundant traces do not receive signals and are relatively long, they are susceptible to electrostatic discharge, which can damage them, causing open circuits and disrupting signal transmission. Summary of the Invention

[0004] This disclosure aims to at least solve one of the technical problems existing in the prior art, and to provide an array substrate, a display panel, and a display device.

[0005] In a first aspect, embodiments of this disclosure provide an array substrate having a display area and a fan-out area disposed on one side of the display area. The array substrate includes: a substrate, fan-out traces disposed on the substrate in the middle region of the fan-out area, and redundant fan-out traces disposed on the substrate in the edge region of the fan-out area.

[0006] The redundant fan-out routing includes: multiple sub-redundant fan-out routings; the multiple sub-redundant fan-out routings are disconnected from each other.

[0007] Optionally, the disconnection points of adjacent redundant fan-out routes are staggered.

[0008] Optionally, the array substrate further includes: a plurality of connecting portions;

[0009] Both ends of each of the connecting parts are respectively connected to the sub-redundant fan-out routing lines spaced apart in the middle of the same redundant fan-out routing line;

[0010] The connection part includes: multiple sub-connection parts; the multiple sub-connection parts are disconnected from each other; the disconnection positions of the connection parts are staggered with the disconnection positions of the redundant fan-out routing lines.

[0011] Optionally, the line widths of the fan-out trace, the redundant fan-out trace, and the connector are equal.

[0012] Optionally, the array substrate further includes: a plurality of data lines disposed on the substrate in the display area;

[0013] The data lines are connected one-to-one with the fan-out cables.

[0014] Optionally, the fan-out trace, the redundant fan-out trace, and the data line are arranged on the same layer.

[0015] Optionally, the array substrate further includes: a plurality of gate lines disposed on the substrate in the display area;

[0016] The grid lines are connected one-to-one with the fan-out routing lines.

[0017] Optionally, the fan-out routing, the redundant fan-out routing, and the gate line are arranged on the same layer.

[0018] Secondly, embodiments of this disclosure provide a display panel including the array substrate as described above.

[0019] Thirdly, embodiments of this disclosure provide a display device, including the display panel as described above. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of an exemplary array substrate structure;

[0021] Figure 2 This is a schematic diagram of the structure of an array substrate provided in an embodiment of the present disclosure;

[0022] Figure 3 This is a schematic diagram of another array substrate provided in an embodiment of the present disclosure;

[0023] Figure 4 This is a schematic diagram of another array substrate provided in an embodiment of the present disclosure;

[0024] Figure 5 This is a schematic diagram of another array substrate provided in an embodiment of the present disclosure. Detailed Implementation

[0025] To enable those skilled in the art to better understand the technical solutions of this disclosure, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0026] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0027] Figure 1 This is a schematic diagram of an exemplary array substrate structure, such as... Figure 1The array substrate has a display area and a fan-out area disposed on one side of the display area. The array substrate includes: a substrate 101, multiple gate lines 102 and multiple data lines 103 disposed on the substrate 101 in the display area; pixel units 104 are disposed in the intersection area of ​​the gate lines 102 and the data lines 103. A gate driver chip (not shown) can provide scan signals to each pixel unit 104 through the gate lines 102, and a source driver chip (not shown) can provide data signals to each pixel unit 104 through the data lines 103. Generally, since the width of the gate driver chip and the source driver chip is generally smaller than the width of the wiring area in the display area of ​​the array substrate, a fan-out trace 105 needs to be provided in the fan-out area of ​​the array substrate to connect the gate driver chip to the gate line 102 and the source driver chip to the data line 103. As user demands for resolution continue to increase, the number of wirings in the display area is also increasing. When the same number of fan-out traces 105 are arranged in the fan-out area, the spacing between adjacent fan-out traces 105 is smaller than the spacing between adjacent signal lines in the display area, resulting in a much higher wiring density for the fan-out traces 105 in the fan-out area compared to other areas. During the manufacturing process of the display panel, the etching solution concentration at the edge of the fan-out area differs from that in the middle, causing a difference in linewidth between the edge and middle fan-out traces. This can easily lead to unstable linewidths of the fan-out traces in the array substrate, and even open circuits, affecting signal transmission. Redundant fan-out traces 106 are often placed at the edge of the fan-out area. However, since the redundant fan-out traces 106 do not receive signals and are relatively long, they are prone to electrostatic discharge, which can break down the fan-out traces 105, causing open circuits and affecting signal transmission.

[0028] In order to at least solve one of the above-mentioned technical problems, the present disclosure provides an array substrate, a display panel, and a display device. The array substrate, display panel, and display device provided in the present disclosure will be described in further detail below with reference to the accompanying drawings and specific embodiments.

[0029] In a first aspect, embodiments of this disclosure provide an array substrate, Figure 2 This is a schematic diagram of the structure of an array substrate provided in an embodiment of the present disclosure. Figure 3 This is a schematic diagram of another array substrate provided in an embodiment of the present disclosure, as shown below. Figure 2 and Figure 3As shown, the array substrate has a display area and a fan-out area disposed on one side of the display area. The array substrate includes: a substrate 101, a fan-out trace 105 disposed on the substrate 101 in the middle region of the fan-out area, and a redundant fan-out trace 106 disposed on the substrate 101 in the edge region of the fan-out area. The redundant fan-out trace 106 includes: a plurality of sub-redundant fan-out traces 1061. The plurality of sub-redundant fan-out traces 1061 are disconnected from each other.

[0030] In some embodiments, the substrate 101 can be a flexible substrate, and its specific material may include polyimide, polyethylene terephthalate, or polyethylene. It is understood that the substrate 101 can also be a rigid substrate, and its specific material may be glass, etc. The material of the substrate 101 can be selected according to actual needs, and is not limited here. The fan-out trace 105 and the redundant fan-out trace 106 can be one or more of metals such as aluminum, copper, or molybdenum. Both can be made of the same material and using the same process to save manufacturing costs.

[0031] In the array substrate provided in this embodiment, there are multiple fan-out traces 105, and the number of redundant fan-out traces 106 can be only one (e.g., ...). Figure 2 As shown), it can also be multiple (such as...). Figure 3 As shown in the illustration (two examples are used in this embodiment), at least a portion of the redundant fan-out traces 106 include: multiple sub-redundant fan-out traces 1061, which are disconnected from each other. This allows a long redundant fan-out trace 106 to be divided into multiple shorter sub-redundant fan-out traces 1061, reducing the facing area between adjacent redundant fan-out traces 106 and preventing electrostatic discharge from breaking down the fan-out trace 105, thus ensuring stable signal transmission in the fan-out trace 105. Furthermore, the presence of redundant fan-out traces 106 in the edge region of the display area prevents excessive etching solution from flowing to the middle region of the fan-out area during fabrication, avoiding over-etching of the fan-out traces 105 in the middle region by a higher concentration of etching solution. This stabilizes the linewidth of the fan-out traces 105 in the display substrate, preventing open circuits and ensuring stable signal transmission in the fan-out traces 105.

[0032] Figure 4 This is a schematic diagram of another array substrate provided in an embodiment of the present disclosure, as shown below. Figure 4 As shown, the disconnection positions of adjacent redundant fan-out traces 106 in the array substrate are staggered.

[0033] It should be noted here that... Figure 4 The array substrate shown contains multiple redundant fan-out traces 106 (two are used as an example in this embodiment), which are related to... Figure 3 The array substrate shown is different in that, Figure 3 In the fabrication process of the array substrate shown, to ensure a neat structure and facilitate fabrication, the disconnection positions of adjacent redundant fan-out traces 106 are arranged relative to each other. However... Figure 4 The disconnection points of adjacent redundant fan-out traces 106 in the array substrate shown are staggered. This has two advantages: First, the staggered disconnection points of adjacent redundant fan-out traces 106 further reduce the facing area between them, preventing electrostatic discharge from breaking down the fan-out traces 105 and causing an open circuit, thus ensuring stable signal transmission in the fan-out traces 105. Second, the staggered disconnection points of adjacent redundant fan-out traces 106 are not conducive to the flow of etching solution, further preventing excessive etching solution from flowing to the middle region of the fan-out area. This avoids over-etching of the fan-out traces 105 in the middle region by a higher concentration of etching solution, thereby stabilizing the linewidth of the fan-out traces 105 in the display substrate, preventing open circuits, and thus ensuring stable signal transmission in the fan-out traces 105.

[0034] Figure 5 This is a schematic diagram of another array substrate provided in an embodiment of the present disclosure, as shown below. Figure 5 As shown, the array substrate further includes: a plurality of connection portions 107; each connection portion 107 has its two ends connected to sub-redundant fan-out traces 1061 spaced apart in the same redundant fan-out trace 106; the connection portion 107 includes: a plurality of sub-connection portions 1071; the plurality of sub-connection portions 1071 are disconnected from each other; the disconnection positions of the connection portions 107 and the disconnection positions of the redundant fan-out traces 106 are staggered.

[0035] It should be noted that the two ends of the connection portion 107 are respectively connected to the spacer sub-redundant fan-out traces 1061. This allows the connection portion 107 to block the break points of the redundant fan-out traces 106, preventing excessive etching solution from flowing into the middle region of the fan-out area during the fabrication process. This avoids the fan-out traces 105 in the middle region of the fan-out area being over-etched by a high concentration of etching solution, thereby stabilizing the linewidth of the fan-out traces 105 in the display substrate, preventing open circuits, and ensuring stable signal transmission in the fan-out traces 105. Furthermore, the connection portion 107 includes: multiple sub-connection portions 1071 (such as... Figure 5As shown in the illustration (two examples are used in this embodiment), the multiple sub-connection portions 1071 are also disconnected, with their disconnection positions staggered with the disconnection positions of the redundant fan-out traces 106. This avoids continuity between the spaced-apart sub-redundant fan-out traces 1061 and reduces the facing area between adjacent connection portions 107 and sub-redundant fan-out traces 1061, preventing electrostatic discharge from breaking down the fan-out traces 105 and causing an open circuit, thereby ensuring stable signal transmission in the fan-out traces 105. In practical applications, the connection portion 107 can be made of the same material as the redundant fan-out traces 106 to reduce manufacturing difficulty and save on production costs. It is understood that the shape of the connection portion 107 can be as follows: Figure 5 The right-angle bend shown can also be a bend at other angles, or even an arc shape. The shape of the connecting part can be set according to actual needs, and will not be listed here.

[0036] In some embodiments, the line widths of the fan-out trace 105, the redundant fan-out trace 106, and the connector 107 are equal.

[0037] It should be noted that the fan-out trace 105, redundant fan-out trace 106, and connecting portion 107 have equal line widths and can be made of the same material. This ensures uniform wiring in the fan-out area of ​​the array substrate, prevents overlapping between different traces during dense wiring, and avoids defects such as short circuits. It also reduces manufacturing complexity and saves on production costs.

[0038] In some real-time scenarios, such as Figure 2-5 As shown, the array substrate also includes: multiple data lines 103 disposed on the substrate 101 in the display area; the data lines 103 are connected one-to-one with the fan-out traces 105.

[0039] It should be noted that the fan-out area can be set in the region extending along the data line 103. The data line 103 can be connected to the source driver chip (not shown in the figure) through the fan-out trace 105, so that the data signal provided by the source driver chip can be transmitted to the corresponding pixel unit 104 through the fan-out trace 105 and the data line 103 to control the display brightness of the pixel unit 104 and realize the display function. At this time, the redundant fan-out trace 106 is suspended and does not receive any signal. Correspondingly, the fan-out area of ​​the array substrate can also be provided with the same redundant pads for the redundant fan-out trace 106 to overlap.

[0040] In some embodiments, fan-out traces 105 and redundant fan-out traces 106 are arranged on the same layer as data lines 103.

[0041] During the fabrication process, the fan-out trace 105, redundant fan-out trace 106, and data line 103 can be fabricated using the same material and process to reduce process steps and save fabrication costs. It is understood that the three can also be arranged on different layers and connected via vias.

[0042] In some real-time configurations, the array substrate also includes: multiple grid lines 102 disposed on the substrate 101 in the display area; the grid lines 102 are connected one-to-one with the fan-out traces 105 (not shown in the figure).

[0043] It should be noted that the fan-out area can also be set in the region extending along the gate line 102. The gate line 102 can be connected to the gate driver chip (not shown in the figure) through the fan-out trace 105, so that the scan signal provided by the gate driver chip can be transmitted to the corresponding pixel unit 104 through the fan-out trace 105 and the gate line 102 to control the on state of the pixel unit 104 and realize the display function. At this time, the redundant fan-out trace 106 is suspended and does not receive any signal. Correspondingly, the fan-out area of ​​the array substrate can also be provided with the same redundant pads for the redundant fan-out trace 106 to overlap.

[0044] In some embodiments, fan-out traces 105 and redundant fan-out traces 106 are disposed on the same layer as gate lines 102.

[0045] During fabrication, fan-out traces 105, redundant fan-out traces 106, and gate lines 102 can be fabricated using the same material and process to reduce process steps and save fabrication costs. It is understood that these three elements can also be arranged on different layers and connected via vias.

[0046] Secondly, embodiments of this disclosure provide a display panel, which includes the array substrate as described above. The implementation principle and technical effects of this display panel can be found in the above discussion of the implementation principle and technical effects of the array substrate, and will not be repeated here.

[0047] Thirdly, this disclosure also provides an electronic device, which can be an electronic device with a display panel, such as a mobile phone, tablet computer, electronic watch, fitness tracker, or laptop computer. The implementation principle and technical effects of this electronic device can be found in the above discussion of the implementation principle and technical effects of the array substrate, and will not be repeated here.

[0048] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. An array substrate having a display area and a fan-out area disposed on one side of the display area, characterized in that, The array substrate includes: a substrate, fan-out traces disposed on the substrate in the middle region of the fan-out area, and redundant fan-out traces disposed on the substrate in the edge region of the fan-out area; The redundant fan-out routing includes: multiple sub-redundant fan-out routings; the multiple sub-redundant fan-out routings are disconnected from each other; The array substrate further includes: multiple connecting portions; Both ends of each of the connecting parts are respectively connected to the sub-redundant fan-out routing lines spaced apart in the middle of the same redundant fan-out routing line; The connection part includes: multiple sub-connection parts; the multiple sub-connection parts are disconnected from each other; the disconnection positions of the connection parts are staggered with the disconnection positions of the redundant fan-out routing lines.

2. The array substrate according to claim 1, characterized in that, The disconnection points of adjacent redundant fan-out traces are staggered.

3. The array substrate according to claim 1, characterized in that, The line widths of the fan-out trace, the redundant fan-out trace, and the connector are equal.

4. The array substrate according to claim 1, characterized in that, The array substrate further includes: multiple data lines located on the substrate and disposed in the display area; The data lines are connected one-to-one with the fan-out cables.

5. The array substrate according to claim 4, characterized in that, The fan-out traces and the redundant fan-out traces are arranged on the same layer as the data lines.

6. The array substrate according to claim 1, characterized in that, The array substrate further includes: multiple gate lines disposed on the substrate in the display area; The grid lines are connected one-to-one with the fan-out routing lines.

7. The array substrate according to claim 6, characterized in that, The fan-out routing lines and the redundant fan-out routing lines are arranged on the same layer as the gate lines.

8. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-7.

9. A display device, characterized in that, Includes the display panel as described in claim 8.

Images