A gate trench forming method and a DRAM manufacturing method
By using spin-coated hard mask layers and photolithographic mask layer patterns made of the same material, combined with dry etching and etch-back processes, the problem of unevenness in word line trenches in DRAM was solved, and the uniformity of gate trenches and process stability were improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2021-02-24
- Publication Date
- 2026-05-22
AI Technical Summary
In the prior art, different hard mask materials (SOH and polysilicon) cause inhomogeneity in the critical dimensions and contours of word line trenches in DRAM.
Using the same material, a first spin-coated hard mask layer and a second spin-coated hard mask layer are combined with a photolithography mask layer pattern. A combined hard mask pattern is formed through dry etching and etch-back processes. An oxide layer is used to define the width of the gate trench. Etching is performed using a multi-frequency capacitively coupled plasma etching device, which simplifies the process steps and improves stability.
It achieves uniformity in key dimensions and contours of the gate trench, simplifies fabrication steps, improves process stability, and allows adjustment of the gate trench width, reducing non-uniformity.
Smart Images
Figure CN114975442B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for forming a gate trench and a method for manufacturing DRAM. Background Technology
[0002] Memory is a device or component in a digital system used to store large amounts of information, and it is an important part of computers and digital devices. Memory can be divided into two main categories: Random Access Memory (RAM) and Read-Only Memory (ROM). RAM includes DRAM, PRAM, MRAM, etc., and transistors are the key components in the manufacture of these RAMs.
[0003] There are various methods for forming BCAT (Buried Channel Array Transistor) in DRAM. The existing SADP (Self-Aligned Double Patterning) method includes the following steps: BCAT mask photolithography; dry etching of the BCAT mask; a first SOH (Spin On Hard-mask) formation followed by core etching; formation of oxide spacers using ALD (Atomic Layer Deposition); a second polysilicon deposition; etching back the polysilicon and removing the oxide spacers to form trench spaces, which are then transferred to the active region via an underlying mask to form gate trenches. However, the first SOH formation and the second polysilicon deposition differ, and the characteristics of these different materials result in non-uniformity in the critical dimensions and contours of the final word line trenches. Summary of the Invention
[0004] Based on the above analysis, the embodiments of the present invention aim to provide a gate trench formation method and a DRAM manufacturing method to solve the problems of critical size dispersion and uneven contour of the final word line trench caused by different hard mask materials (SOH and polysilicon).
[0005] On one hand, embodiments of the present invention provide a gate trench formation method, comprising: sequentially forming a gate mask layer, a first spin-coated hard mask layer, and a photolithographic mask layer over a semiconductor substrate, wherein the photolithographic mask layer has a photolithographic mask layer pattern; etching the first spin-coated hard mask layer using the photolithographic mask layer pattern as a mask to form a patterned first spin-coated hard mask layer; depositing an oxide layer over the patterned first spin-coated hard mask layer, and forming a second spin-coated hard mask layer over the oxide layer; etching the second spin-coated hard mask layer to form a patterned second spin-coated hard mask layer; removing portions of the oxide layer not covered by the patterned second spin-coated hard mask layer to form a combined hard mask pattern including the patterned first spin-coated hard mask layer and the patterned second spin-coated hard mask layer; and transferring the combined hard mask pattern via the gate mask layer to the semiconductor substrate to form a gate trench, wherein the material of the first spin-coated hard mask layer is the same as the material of the second spin-coated hard mask layer.
[0006] The beneficial effects of the above technical solution are as follows: According to the gate trench formation method provided by the embodiment of the present invention, the material of the first spin-coated hard mask layer is the same as that of the second spin-coated hard mask layer, which can simplify the manufacturing steps, improve the process stability, and minimize the critical size distribution and contour non-uniformity of the first spin-coated hard mask layer pattern and the second spin-coated hard mask layer pattern in the combined hard mask pattern during the gate trench formation process, thereby minimizing the critical size distribution and contour non-uniformity of the final gate trench.
[0007] A further improvement to the above method, using a photolithographic mask layer pattern as a mask to etch the first spin-coated hard mask layer to form a patterned first spin-coated hard mask layer, further includes: using a photolithographic mask layer pattern as a mask, etching the first spin-coated hard mask layer through a dry etching process to form the patterned first spin-coated hard mask layer with a first pattern, wherein the first pattern is the inverse pattern of the photolithographic mask layer pattern.
[0008] Based on a further improvement of the above method, after forming the gate mask layer and before forming the first spin-coated hard mask layer, the method further includes: forming a silicon oxynitride mask layer over the gate mask layer.
[0009] A further improvement to the above method involves depositing an oxide layer over a patterned first spin-coated hard mask layer and forming a second spin-coated hard mask layer over the oxide layer, which further includes: depositing an oxide layer on the sidewalls and top surface of the patterned first spin-coated hard mask layer and over an exposed silicon oxynitride mask layer using an atomic layer deposition process, wherein the thickness of the oxide layer is used to define the width of the gate trench; and forming the second spin-coated hard mask layer over the oxide layer by a spin-coating process, wherein the second spin-coated hard mask layer has a flat top surface.
[0010] The beneficial effects of the above technical solution are as follows: the thickness of the oxide layer is used to define the width of the gate trench, so the width of the gate trench can be adjusted by changing the thickness of the oxide layer. Furthermore, replacing the polysilicon layer formed by the deposition process with a second spin-coated hard mask layer formed by a spin-coating process improves process stability.
[0011] Further improvements to the above method include etching the second spin-coated hard mask layer to form a patterned second spin-coated hard mask layer, which further includes etching the second spin-coated hard mask layer through an etch-back process to form a patterned second spin-coated hard mask layer, while exposing portions of the oxide layer located on the top surface and sidewalls of the patterned first spin-coated hard mask layer, wherein the top surface of the patterned first spin-coated hard mask layer is flush with the top surface of the patterned second spin-coated hard mask layer.
[0012] The beneficial effects of the above technical solution are as follows: by making the top surface of the patterned first spin-coated hard mask layer flush with the top surface of the patterned second spin-coated hard mask layer, the contour non-uniformity is minimized.
[0013] Based on a further improvement of the above method, the etching process utilizes an inductively coupled plasma etching device; and in the etching process, the etching gas includes a mixture of O2 / N2 / CH4 or a mixture of O2 / HBr.
[0014] A further improvement to the above method, removing the portion of the oxide layer not covered by the patterned second spin-coated hard mask layer to form a combined hard mask pattern including a patterned first spin-coated hard mask layer and a patterned second spin-coated hard mask layer, further includes: removing portions of the oxide layer located on the top surface and sidewalls of the patterned first spin-coated hard mask layer by an etching process to expose a portion of the top surface of the silicon oxynitride mask, and forming a combined hard mask pattern including a patterned first spin-coated hard mask layer and a patterned second spin-coated hard mask layer, wherein the width of the patterned first spin-coated hard mask layer is the same as the width of the patterned second spin-coated hard mask layer.
[0015] Based on a further improvement of the above method, the etching process of the oxide layer utilizes a multi-frequency capacitively coupled plasma etching (FCP) device; in the etching process of the oxide layer, the LF is 3000W to 8000W, wherein the frequency of the LF is 100KHz to 12.36KHz; and the HF is 100W to 3000W, wherein the frequency of the HF is 13.56KHz to 100MHz; and in the etching process of the oxide layer, the etching gas includes a mixture of Ar, C4F8, O2 and C4F6.
[0016] The beneficial effects of the above technical solution are as follows: the multi-frequency capacitively coupled plasma etching equipment can ensure the selectivity between oxide and the first and second spin-coated hard mask layers in the oxide layer etching process.
[0017] Based on a further improvement of the above method, the gate trench formation method further includes: using a multi-frequency capacitively coupled plasma etching apparatus to further remove the exposed portion of the silicon oxynitride mask that is not covered by the first spin-coated hard mask layer and the patterned second spin-coated hard mask layer, so as to expose the top surface of the gate mask layer and form a silicon oxynitride mask layer pattern, wherein the silicon oxynitride mask layer pattern is the same as the combined hard mask pattern.
[0018] A further improvement to the above method includes, before forming the gate mask layer, forming an etch stop layer over the semiconductor substrate, wherein transferring the combined hard mask pattern to the semiconductor substrate via the gate mask layer to form a gate trench further includes: transferring the combined hard mask pattern to the gate mask layer and the etch stop layer using an over-etching process to form a gate mask layer pattern and an etch stop layer pattern; and etching a plurality of active regions of the semiconductor substrate using the gate mask layer pattern and the etch stop layer pattern as masks to form the gate trench in the plurality of active regions, wherein adjacent active regions among the plurality of active regions are isolated by a shallow trench isolation (STI) region.
[0019] Based on a further improvement of the above method, after forming the first spin-coated hard mask layer and before forming the photolithography mask layer, the method further includes: forming an anti-reflection layer above the first spin-coated hard mask layer; after forming the photolithography mask layer above the anti-reflection layer, performing photolithography on the photolithography mask layer to form a photolithography mask layer pattern; and after etching the first spin-coated hard mask layer, removing the anti-reflection layer.
[0020] On the other hand, embodiments of the present invention provide a DRAM manufacturing method, comprising: forming a gate trench using the gate trench forming method described in the above embodiments; and forming a gate dielectric layer and a gate material layer in the gate trench to form word lines.
[0021] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:
[0022] 1. The material of the first spin-coated hard mask layer is the same as that of the second spin-coated hard mask layer, which can simplify the manufacturing steps, improve process stability, and minimize the critical size distribution and contour non-uniformity of the first spin-coated hard mask layer pattern and the second spin-coated hard mask layer pattern in the gate trench formation process. This can minimize the critical size distribution and contour non-uniformity of the final gate trench.
[0023] 2. The thickness of the oxide layer is used to define the width of the gate trench; therefore, the width of the gate trench can be adjusted by changing the thickness of the oxide layer. Furthermore, a second spin-coated hard mask layer formed by a spin-coating process replaces the polysilicon layer formed by the deposition process, improving process stability.
[0024] 3. By making the top surface of the patterned first spin-coated hard mask layer flush with the top surface of the patterned second spin-coated hard mask layer, the contour non-uniformity is minimized.
[0025] 4. The multi-frequency capacitively coupled plasma etching equipment can ensure the selectivity between oxide and the first and second spin-coated hard mask layers in the oxide layer etching process.
[0026] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description
[0027] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.
[0028] Figure 1 This is a cross-sectional view of an intermediate stage of a gate trench formation method according to an embodiment of the present invention.
[0029] Figure 2 This is a cross-sectional view of an intermediate stage of a gate trench formation method according to an embodiment of the present invention.
[0030] Figure 3 This is a cross-sectional view of an intermediate stage of a gate trench formation method according to an embodiment of the present invention.
[0031] Figure 4 This is a cross-sectional view of an intermediate stage of a gate trench formation method according to an embodiment of the present invention.
[0032] Figure 5 This is a cross-sectional view of an intermediate stage of a gate trench formation method according to an embodiment of the present invention.
[0033] Figure 6 This is a cross-sectional view of an intermediate stage of a gate trench formation method according to an embodiment of the present invention.
[0034] Figure 7 This is a cross-sectional view of an intermediate stage of a gate trench formation method according to an embodiment of the present invention.
[0035] Figure label:
[0036] 100 - Semiconductor substrate; 102 - Active region; 104 - STI region; 106 - Etch stop layer; 108 - Gate mask layer; 110 - Silicon oxynitride mask layer; 112 - First spin-coated hard mask layer; 114 - Anti-reflective layer; 116 - Photolithography mask layer pattern; 118 - First pattern; 120 - Oxide layer; 122 - Second spin-coated hard mask layer; 124 - Second spin-coated hard mask layer pattern; 126 - Silicon oxynitride mask layer pattern; 128 - Oxide layer pattern; 130 - Trench; 132 - Gate mask layer pattern; 134 - Etch stop layer pattern; 136 - Trench Detailed Implementation
[0037] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.
[0038] A specific embodiment of the present invention discloses a method for forming a gate trench. Hereinafter, reference will be made to... Figures 1 to 7 The method for forming gate trenches is described in detail.
[0039] First, refer to Figure 1 A semiconductor substrate 100 is provided. The semiconductor substrate 100 includes a plurality of active regions 102 and an STI (shallow trench isolation) region 104, wherein adjacent active regions among the plurality of active regions 102 are isolated by the shallow trench isolation STI region 104.
[0040] refer to Figure 1A gate mask layer 108, a first spin-coated hard mask layer 112, and a photolithography mask layer are sequentially formed on a semiconductor substrate, wherein the photolithography mask layer has a photolithography mask layer pattern 116. Specifically, an etch stop layer 106, a gate mask layer 108, a silicon oxynitride mask layer 110, a first spin-coated hard mask layer 112, an anti-reflection layer 114, and a photolithography mask layer are sequentially formed on the semiconductor substrate. In an embodiment, after forming the photolithography mask layer on the anti-reflection layer 114, the photolithography mask layer is photolithographically ...
[0041] refer to Figure 2 The first spin-coated hard mask layer 112 is etched using the photolithographic mask layer pattern 116 as a mask to form a patterned first spin-coated hard mask layer. Specifically, the etching of the first spin-coated hard mask layer 112 using the photolithographic mask layer pattern 116 as a mask to form a patterned first spin-coated hard mask layer 112 further includes: using the photolithographic mask layer pattern 116 as a mask, the first spin-coated hard mask layer 112 is etched using a dry etching process to form the patterned first spin-coated hard mask layer 112 with a first pattern 118 (also referred to as the first spin-coated hard mask layer pattern 118), wherein the first pattern is the inverse pattern of the photolithographic mask layer pattern 116. The width of the first pattern 118 is the same as the spacing width between adjacent photolithographic mask layer patterns 116, that is, the width of the first pattern 118 is the minimum critical dimension. In addition, while etching the first spin-coated hard mask layer 112, the anti-reflective layer 114 is also etched, and then the anti-reflective layer pattern located above the patterned first spin-coated hard mask layer is removed.
[0042] refer to Figure 3 and Figure 4 An oxide layer 120 is deposited over a patterned first spin-coated hard mask layer 112, and a second spin-coated hard mask layer 122 is formed over the oxide layer 120. Specifically, refer to... Figure 3 The deposition of an oxide layer over the patterned first spin-coated hard mask layer 112 further includes: depositing an oxide layer 120 on the sidewalls and top surface of the patterned first spin-coated hard mask layer 112 and over the exposed silicon oxynitride mask layer 110 using an atomic layer deposition process, wherein the thickness of the oxide layer 120 is used to define the width of the gate trench. Reference Figure 4The formation of a second spin-coated hard mask layer 122 over the oxide layer 120 further includes: forming the second spin-coated hard mask layer 122 over the oxide layer 120 by a spin-coating process, wherein the second spin-coated hard mask layer 122 has a flat top surface. The second spin-coated hard mask layer 122 is formed using the same equipment and process parameters as the first spin-coated hard mask layer 112, without requiring a polysilicon deposition process, thereby simplifying the fabrication steps and improving process stability.
[0043] refer to Figure 5 The second spin-coating hard mask layer 122 is etched to form a patterned second spin-coating hard mask layer. Specifically, the second spin-coating hard mask layer 122 is etched using an etch-back process to form a patterned second spin-coating hard mask layer, i.e., Figure 5 The second spin-coated hard mask layer pattern 124 shown exposes portions of the oxide layer located on the top surface and sidewalls of the patterned first spin-coated hard mask layer. (Reference) Figure 5 The oxide layer comprises three parts: a first part located beneath a patterned second spin-coated hard mask layer, a second part located above the top surface of a patterned first spin-coated hard mask layer, and a third part located between the patterned first and second spin-coated hard masks layer, specifically between the sidewalls of the patterned first and second spin-coated hard masks layer. Therefore, after the etch-back process, the tops of the entire second and third parts of the oxide layer are exposed. The top surface of the patterned first spin-coated hard mask layer is flush with the top surface of the patterned second spin-coated hard mask layer. This etch-back process utilizes an inductively coupled plasma etching apparatus. In the etch-back process, the etching gas includes a mixture of O2 / N2 / CH4 or a mixture of O2 / HBr. In one embodiment, during the etch-back process, the atmospheric pressure is 5 mT, the power is 550 Ws, the voltage is 380 Vb, the CH4 gas flow rate is 17 sccm, the Ar gas flow rate is 150 sccm, the N2 gas flow rate is 90 sccm, and the O2 gas flow rate is 30 sccm. In an optional embodiment, the atmospheric pressure is 10 mT, the power is 300 Ws-50 Wb, the O2 gas flow rate is 100 sccm, the Ar gas flow rate is 100 sccm, and the HBr gas flow rate is 50 sccm.
[0044] refer to Figure 6The process involves removing portions of the oxide layer not covered by the patterned second spin-coating hard mask layer to form a combined hard mask pattern including a patterned first spin-coating hard mask layer 112 and a patterned second spin-coating hard mask layer 122. This process further includes: removing portions of the oxide layer located on the top surface and sidewalls of the patterned first spin-coating hard mask layer 112 by an etching process to expose a portion of the top surface of the silicon oxynitride mask, thus forming the combined hard mask pattern including the patterned first spin-coating hard mask layer and the patterned second spin-coating hard mask layer, wherein the width of the patterned first spin-coating hard mask layer is the same as the width of the patterned second spin-coating hard mask layer. (Reference) Figure 6 The combined hard mask pattern includes a second spin-coated hard mask layer pattern 124 and an oxide layer pattern 128 located below the second spin-coated hard mask layer pattern 124, and also includes a first spin-coated hard mask layer pattern 118. The oxide layer etching process utilizes a multi-frequency capacitively coupled plasma etching (CCP) apparatus to ensure the selectivity between the first and second spin-coated hard mask layers (SOH) and the oxide. In this oxide layer etching process, the LF is 3000W to 8000W, wherein the frequency of the LF is 100kHz to 12.36kHz; and the HF is 100W to 3000W, wherein the frequency of the HF is 13.56kHz to 100MHz. In the oxide layer etching process, the etching gas includes a mixture of Ar, C4F8, O2, and C4F6. In one embodiment, during the etching process of the oxide layer, the atmospheric pressure is 30 mT, the power is 2000 W for HF, 4500 W for LF, RF is synchronous radio frequency at 5 kHz, the duty cycle is 40, the DC power supply is -150 V, the Ar gas flow rate is 1000 sccm, the C4H8 gas flow rate is 10 sccm, the O2 gas flow rate is 35 sccm, the C4H6 gas flow rate is 30 sccm, the RDC is 50 (33 / 33 / 34)%. The over-etching (OE) is 30%, B.He is 30 Tr, ATCC is 45 °C, temperature T is 150 °C, temperature W is 150 °C, and the chiller temperature is -10 °C.
[0045] Next, refer to Figure 6The exposed portions of the silicon oxynitride mask covered by the unpatterned first spin-coated hard mask layer 112 and the patterned second spin-coated hard mask layer 122 are further removed using a multi-frequency capacitively coupled plasma etching apparatus to expose the top surface of the gate mask layer 108 and form a silicon oxynitride mask layer pattern 126 and a trench 130. The silicon oxynitride mask layer pattern 126 is identical to the combined hard mask pattern; specifically, the silicon oxynitride mask layer pattern 126 is located below and perpendicularly aligned with the combined hard mask pattern. For example, the first sidewall of the trench 130 includes the sidewall of the first spin-coated hard mask layer pattern 118 and the sidewall of the silicon oxynitride mask layer pattern 126. The first sidewall of the trench 130 includes the sidewall of the second spin-coated hard mask layer pattern 124, the sidewall of the oxide layer pattern 128, and the sidewall of the silicon oxynitride mask layer pattern 126.
[0046] refer to Figure 7 The combined hard mask pattern is transferred to the semiconductor substrate via the gate mask layer 108 to form a gate trench, wherein the material of the first spin-coated hard mask layer 112 is the same as the material of the second spin-coated hard mask layer 122. Specifically, the transfer of the combined hard mask pattern to the semiconductor substrate via the gate mask layer 108 to form a gate trench further includes: using an over-etching process to transfer the combined hard mask pattern to the gate mask layer 108 and the etch stop layer 106 to form a gate mask layer pattern 132 and an etch stop layer pattern 134, while simultaneously forming a trench 136. Then, using the gate mask layer pattern 132 and the etch stop layer pattern 134 as masks, a plurality of active regions of the semiconductor substrate are etched to form gate trenches in the plurality of active regions, wherein adjacent active regions among the plurality of active regions are isolated by shallow trench isolation (STI) regions.
[0047] One specific embodiment of the present invention discloses a DRAM manufacturing method. The DRAM manufacturing method includes: forming a gate trench using the gate trench forming method described in the above embodiments; and forming a gate dielectric layer and a gate material layer in the gate trench to form a gate or word line of BCAT.
[0048] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:
[0049] 1. The material of the first spin-coated hard mask layer is the same as that of the second spin-coated hard mask layer, which can simplify the manufacturing steps, improve process stability, and minimize the critical size distribution and contour non-uniformity of the first spin-coated hard mask layer pattern and the second spin-coated hard mask layer pattern in the gate trench formation process. This can minimize the critical size distribution and contour non-uniformity of the final gate trench.
[0050] 2. The thickness of the oxide layer is used to define the width of the gate trench; therefore, the width of the gate trench can be adjusted by changing the thickness of the oxide layer. Furthermore, a second spin-coated hard mask layer formed by a spin-coating process replaces the polysilicon layer formed by the deposition process, improving process stability.
[0051] 3. By making the top surface of the patterned first spin-coated hard mask layer flush with the top surface of the patterned second spin-coated hard mask layer, the contour non-uniformity is minimized.
[0052] 4. The multi-frequency capacitively coupled plasma etching equipment can ensure the selectivity between oxide and the first and second spin-coated hard mask layers in the oxide layer etching process.
[0053] Those skilled in the art will understand that all or part of the processes of the methods described in the above embodiments can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium. The computer-readable storage medium may be a disk, optical disk, read-only memory, or random access memory, etc.
[0054] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.
Claims
1. A method for forming a gate trench, characterized in that, include: A gate mask layer, a first spin-coated hard mask layer, and a photolithography mask layer are sequentially formed on a semiconductor substrate, wherein the photolithography mask layer has a photolithography mask layer pattern; The first spin-coated hard mask layer is etched using a photolithographic mask layer pattern as a mask to form a patterned first spin-coated hard mask layer; An oxide layer is deposited over a patterned first spin-coated hard mask layer, and a second spin-coated hard mask layer is formed over the oxide layer, wherein the bottom surface of the patterned second spin-coated hard mask layer is higher than the bottom surface of the patterned first spin-coated hard mask layer; The second spin-coated hard mask layer is etched to form a patterned second spin-coated hard mask layer; Remove the portion of the oxide layer not covered by the patterned second spin-coated hard mask layer to form a combined hard mask pattern including a patterned first spin-coated hard mask layer and a patterned second spin-coated hard mask layer; and The combined hard mask pattern is transferred to the semiconductor substrate via the gate mask layer to form a gate trench, wherein the material of the first spin-coated hard mask layer is the same as the material of the second spin-coated hard mask layer, and the width of the gate trench is adjusted by changing the thickness of the oxide layer; The method further includes, before forming the gate mask layer, forming an etch stop layer over the semiconductor substrate; The process of transferring the combined hard mask pattern to the semiconductor substrate via the gate mask layer to form a gate trench further includes: transferring the combined hard mask pattern to the gate mask layer and the etch stop layer using an over-etching process to form a gate mask layer pattern and an etch stop layer pattern; and etching a plurality of active regions of the semiconductor substrate using the gate mask layer pattern and the etch stop layer pattern as masks to form the gate trench in the plurality of active regions, wherein adjacent active regions among the plurality of active regions are isolated by a shallow trench isolation (STI) region. The deposition of an oxide layer over a patterned first spin-coated hard mask layer and the formation of a second spin-coated hard mask layer over the oxide layer further include: depositing an oxide layer on the sidewalls and top surface of the patterned first spin-coated hard mask layer and over an exposed silicon oxynitride mask layer using an atomic layer deposition process, wherein the thickness of the oxide layer is used to define the width of the gate trench; and forming the second spin-coated hard mask layer over the oxide layer by a spin-coating process, wherein the second spin-coated hard mask layer has a flat top surface.
2. The gate trench formation method according to claim 1, characterized in that, The process of etching the first spin-coating hard mask layer using a photolithographic mask layer pattern as a mask to form a patterned first spin-coating hard mask layer further includes: Using a photolithographic mask layer pattern as a mask, the first spin-coated hard mask layer is etched through a dry etching process to form a patterned first spin-coated hard mask layer with a first pattern, wherein the first pattern is the inverse pattern of the photolithographic mask layer pattern.
3. The gate trench formation method according to claim 1, characterized in that, The process further includes forming a silicon oxynitride mask layer over the gate mask layer after the gate mask layer is formed and before the first spin-coated hard mask layer is formed.
4. The gate trench formation method according to claim 3, characterized in that, Etching the second spin-coated hard mask layer to form a patterned second spin-coated hard mask layer further includes: The second spin-coated hard mask layer is etched using an etch-back process to form a patterned second spin-coated hard mask layer, while exposing portions of the oxide layer located on the top surface and sidewalls of the patterned first spin-coated hard mask layer, wherein the top surface of the patterned first spin-coated hard mask layer is flush with the top surface of the patterned second spin-coated hard mask layer.
5. The gate trench formation method according to claim 4, characterized in that, The etching process utilizes an inductively coupled plasma etching device. as well as In the etching process, the etching gas includes a mixture of O2 / N2 / CH4 or a mixture of O2 / HBr.
6. The gate trench formation method according to claim 3, characterized in that, Removing the portion of the oxide layer not covered by the patterned second spin-coated hard mask layer to form a combined hard mask pattern including a patterned first spin-coated hard mask layer and a patterned second spin-coated hard mask layer further includes: The oxide layer is removed by etching to expose a portion of the top surface of the silicon oxynitride mask by removing portions of the top surface of the patterned first spin-coated hard mask layer and the patterned first spin-coated hard mask layer and the patterned second spin-coated hard mask layer, wherein the width of the patterned first spin-coated hard mask layer is the same as the width of the patterned second spin-coated hard mask layer.
7. The gate trench formation method according to claim 6, characterized in that, The etching process of the oxide layer utilizes a multi-frequency capacitively coupled plasma etching device; In the etching process of the oxide layer, the LF is 3000W to 8000W, wherein the frequency of the LF is 100KHz to 12.36KHz; and the HF is 100W to 3000W, wherein the frequency of the HF is 13.56KHz to 100MHz; and In the etching process of the oxide layer, the etching gas includes a mixture of Ar, C4F8, O2 and C4F6.
8. The gate trench formation method according to claim 6, characterized in that, Further includes: The exposed portions of the silicon oxynitride mask covered by the unpatterned first spin-coated hard mask layer and the patterned second spin-coated hard mask layer are further removed using a multi-frequency capacitively coupled plasma etching apparatus to expose the top surface of the gate mask layer and form a silicon oxynitride mask layer pattern, wherein the silicon oxynitride mask layer pattern is the same as the combined hard mask pattern.
9. The gate trench formation method according to any one of claims 1 to 8, characterized in that, After forming the first spin-coated hard mask layer, and before forming the photolithographic mask layer, the method further includes: An anti-reflection layer is formed above the first spin-coated hard mask layer; After forming the photomask layer over the anti-reflection layer, photolithography is performed on the photomask layer to form a photomask layer pattern; and After etching the first spin-coated hard mask layer, the anti-reflective layer is removed.
10. A method for manufacturing DRAM, characterized in that, include: The gate trench is formed by the gate trench forming method according to any one of claims 1 to 9; as well as A gate dielectric layer and a gate material layer are formed in the gate trench to form a word line.