Memory structure and method of forming the same

Abstract

A memory structure and a forming method thereof, comprising: providing a substrate, the substrate comprising a contact region and a cell region, the contact region and the cell region having an initial floating gate layer, an initial control gate layer and an initial first dielectric layer thereon; forming a first patterning layer on the initial first dielectric layer; performing a patterning process based on the first patterning layer to form a plurality of word line openings arranged along a second direction in the initial floating gate layer, the initial control gate layer and the initial first dielectric layer on the cell region, so as to form an intermediate floating gate layer, an intermediate control gate layer and an intermediate first dielectric layer; forming a plurality of word line structures in the plurality of word line openings; forming a second patterning layer on the plurality of word line structures and the intermediate first dielectric layer; performing a patterning process based on the second patterning layer to form a plurality of first openings and a plurality of second openings. Thus, the performance and reliability of the memory structure are improved, and the process difficulty is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and particularly relates to a memory structure and a forming method thereof. BACKGROUND

[0002] NOR flash memory is developed on the basis of ETOX structure proposed by Intel Corporation, and is a kind of non-volatile memory, i.e. the data stored in the chip can be kept without loss after power-off. Meanwhile, NOR flash memory is a kind of voltage-controlled device, adopts hot electron injection to write data, and erases data based on tunnel effect. A remarkable feature of NOR flash memory is fast random read speed. As a kind of non-volatile memory, NOR flash memory has the characteristics of non-volatility, high device density, low power consumption and electric re-writability, and is widely applied to portable electronic products such as mobile phones, digital cameras, smart cards and the like.

[0003] The structure of a flash memory cell is similar to that of a MOS device, and the storage of electric charges is realized by adding a floating gate and a dielectric layer. The access of electrons in the floating gate will cause the change of threshold voltage of the device, thereby indicating the state of the flash memory cell. The Nor flash array is connected together through lateral gates, which are called word lines. The drain is connected with longitudinal metal through a contact hole, which is called bit line. The source of two adjacent devices is connected together, forming a lateral source line.

[0004] However, there are still many problems in the forming process of the existing Nor flash device. SUMMARY

[0005] The technical problem solved by the present application is to provide a memory structure and a forming method thereof, so as to improve the performance and reliability of the Nor flash device, and reduce the process difficulty.

[0006] To solve the above technical problems, the technical scheme of the present application provides a forming method of a memory structure, comprising: providing a substrate, the substrate comprising a contact region and a cell region arranged along a first direction and abutting each other, the contact region and the cell region having an initial floating gate layer, an initial control gate layer located on the initial floating gate layer, and an initial first dielectric layer located on the initial control gate layer; forming a first patterning layer on the initial first dielectric layer; performing a patterning process based on the first patterning layer to form a plurality of word line openings arranged along a second direction in the initial floating gate layer, the initial control gate layer and the initial first dielectric layer on the cell region, so as to form an intermediate floating gate layer, an intermediate control gate layer and an intermediate first dielectric layer, the second direction being perpendicular to the first direction; forming a plurality of word line structures in the plurality of word line openings; forming a second patterning layer on the plurality of word line structures and the intermediate first dielectric layer; performing a patterning process based on the second patterning layer to form a plurality of first openings in the intermediate floating gate layer, the intermediate control gate layer and the intermediate first dielectric layer on the cell region and the contact region, and to form a plurality of second openings in the intermediate floating gate layer, the intermediate control gate layer and the intermediate first dielectric layer on the contact region, so as to form a plurality of composite structures independent of each other and arranged along the second direction on the cell region and the contact region, the composite structures having the first openings between adjacent composite structures, the composite structures having the word line structures and the second openings connected to each other, and the composite structures comprising the floating gate layer, the control gate layer and the first dielectric layer located on both sides of the word line structures and the second openings in the second direction.

[0007] Optionally, the first openings have first projections on the surface of the substrate, and in the second direction, the first projection of the cell region has a first width, the first projection of the contact region has a second width, and the first width is greater than the second width.

[0008] Optionally, the first openings have first projections on the surface of the substrate, and the first projection of the contact region comprises a plurality of first offset boundaries offset towards the first projection along the second direction.

[0009] Optionally, the first projection of the contact region further comprises a plurality of second offset boundaries offset away from the first projection along the second direction, each second offset boundary being opposite to one first offset boundary, and the opposite first offset boundary and second offset boundary have the same offset distance.

[0010] Optionally, after forming the plurality of composite structures, further comprising: forming a second dielectric layer in the first opening and the second opening; forming a third patterned layer on the first dielectric layer and the second dielectric layer, the third patterned layer exposing the first dielectric layer and the second dielectric layer surface on the contact region; etching the exposed first dielectric layer and the second dielectric layer as a mask until exposing the control gate layer surface of the plurality of composite structures on the contact region, forming a contact opening in the first dielectric layer and the second dielectric layer on the contact region, the contact opening having a contact projection on the substrate surface, and the plurality of first offset boundaries being within the range of the contact projection.

[0011] Optionally, after forming the contact opening, further comprising: forming a contact layer on the control gate layer surface of the plurality of composite structures exposed by the contact opening using a metal silicide process.

[0012] Optionally, after forming the contact layer, further comprising: forming a third dielectric layer in the contact opening; forming a plurality of conductive structures in the third dielectric layer, the conductive structures having a bottom surface in contact with the contact layer surface, the conductive structures having a third projection on the substrate surface, and a part of the third projection being adjacent to or coinciding with the first offset boundary.

[0013] Optionally, the intermediate control gate layer comprises: an initial fourth dielectric film, an initial fifth dielectric film on the surface of the initial fourth dielectric film, an initial sixth dielectric film on the surface of the initial fifth dielectric film, and an initial control gate on the surface of the initial sixth dielectric film.

[0014] Optionally, the first patterned layer has a plurality of first patterned openings, the plurality of first patterned openings are arranged along a second direction, and the bottom of the first patterned opening exposes the initial first dielectric layer surface on the unit region.

[0015] Optionally, the method for patterning based on the first patterning layer comprises: etching the initial first dielectric layer and the initial control gate layer on the unit area with the first patterning layer as a mask until the initial fifth dielectric film is exposed to form an intermediate sixth dielectric film, an intermediate control gate on the surface of the intermediate sixth dielectric film, and an intermediate first dielectric layer on the surface of the intermediate control gate, the intermediate sixth dielectric film, the intermediate control gate, and the intermediate first dielectric layer having a plurality of word line upper openings; forming an initial first sidewall gate dielectric layer on the sidewall surface of the word line upper opening and the first patterning opening; etching the exposed initial fifth dielectric film, the initial fourth dielectric film, and the initial floating gate layer until the surface of the substrate is exposed with the initial first sidewall gate dielectric layer and the first patterning layer as a mask to form an intermediate fifth dielectric film, an intermediate fourth dielectric film, and an intermediate floating gate layer, the intermediate fifth dielectric film, the intermediate fourth dielectric film, and the intermediate floating gate layer having a plurality of word line lower openings, the intermediate fourth dielectric film, the intermediate fifth dielectric film, the intermediate sixth dielectric film, and the intermediate control gate constituting the intermediate control gate layer, and the word line upper opening and the word line lower opening constituting the word line opening.

[0016] Optionally, after the word line lower opening is formed, the method further comprises: removing the first patterning layer and the initial first sidewall gate dielectric layer on the sidewall of the first patterning layer to form a first sidewall gate dielectric layer on the sidewall surface of the word line upper opening.

[0017] Optionally, after the word line lower opening is formed and before the word line structure is formed, the method further comprises: forming a second sidewall gate dielectric layer on the sidewall surface of the first sidewall gate dielectric layer and the sidewall surface of the word line lower opening.

[0018] Optionally, the substrate comprises: a base and a seventh dielectric film on the surface of the base.

[0019] Optionally, the method for patterning based on the second patterning layer comprises: etching the exposed intermediate first dielectric layer, the intermediate control gate layer, and the intermediate floating gate layer until the seventh dielectric film on the surface of the base is exposed with the second patterning layer as a mask.

[0020] Correspondingly, the technical scheme of the present application also provides a memory structure, comprising: a substrate, the substrate comprising a contact region and a cell region arranged along a first direction and adjacent to each other; a plurality of composite structures arranged along a second direction and independent of each other on the contact region and the cell region, the second direction being perpendicular to the first direction, and a first opening being provided between adjacent composite structures, each of the composite structures having a word line opening and a second opening in communication, the word line opening being provided on the cell region, the second opening being provided on the contact region, and the word line opening having a word line structure therein; the composite structure comprising a floating gate layer, a control gate layer and a first dielectric layer provided on both sides of the word line structure and the second opening in the second direction, and the control gate layer being provided on the floating gate layer, and the first dielectric layer being provided on the control gate layer.

[0021] Optionally, the first opening has a first projection on the substrate surface, and in the second direction, the first projection of the cell region has a first width, the first projection of the contact region has a second width, and the first width is greater than the second width.

[0022] Optionally, the first opening has a first projection on the substrate surface, and the first projection of the contact region comprises a plurality of first offset boundaries offset towards the first projection in the second direction.

[0023] Optionally, the first projection of the contact region further comprises a plurality of second offset boundaries offset away from the first projection in the second direction, each of the second offset boundaries being opposite to one of the first offset boundaries, and the opposite first offset boundary and second offset boundary have the same offset distance.

[0024] Optionally, further comprising: a second dielectric layer provided in the first opening and the second opening; a contact opening provided in the first dielectric layer and the second dielectric layer on the contact region, the bottom of the contact opening exposing the control gate layer surface of the plurality of composite structures on the contact region, and the contact opening having a contact projection on the substrate surface, and the plurality of first offset boundaries being within the range of the contact projection.

[0025] Optionally, further comprising: a contact layer provided on the control gate layer surface of the plurality of composite structures exposed by the contact opening.

[0026] Optionally, further comprising: a third dielectric layer provided in the contact opening; a plurality of conductive structures provided in the third dielectric layer, the bottom surface of the conductive structure being in contact with the surface of the contact layer, the conductive structure having a third projection on the substrate surface, and part of the boundary of the third projection being adjacent to or coinciding with the first offset boundary.

[0027] Optionally, the control gate layer comprises: a fourth dielectric film, a fifth dielectric film on the surface of the fourth dielectric film, a sixth dielectric film on the surface of the fifth dielectric film, and a control gate on the surface of the sixth dielectric film; and the word line opening comprises: a word line upper opening in the sixth dielectric film, the control gate and the first dielectric layer; a word line lower opening in the fifth dielectric film, the fourth dielectric film and the floating gate layer, the word line upper opening and the word line lower opening being communicated, and the bottom of the word line lower opening exposing the surface of the substrate.

[0028] Optionally, the method further comprises: a first sidewall gate dielectric layer on the sidewall surface of the word line upper opening; and a second sidewall gate dielectric layer on the sidewall surface of the first sidewall gate dielectric layer and the word line lower opening.

[0029] Compared with the prior art, the technical scheme of the embodiment of the application has the following beneficial effects:

[0030] In the method for forming a memory structure provided by the technical scheme, the first patterning layer is used for patterning to form a plurality of word line openings arranged along a second direction in the initial floating gate layer, the initial control gate layer and the initial first dielectric layer on the unit area, so as to form an intermediate floating gate layer, an intermediate control gate layer and an intermediate first dielectric layer, and the second direction is perpendicular to the first direction; a plurality of word line structures are formed in the plurality of word line openings; a second patterning layer is formed on the plurality of word line structures and the intermediate first dielectric layer; the second patterning layer is used for patterning to form a plurality of first openings in the intermediate floating gate layer, the intermediate control gate layer and the intermediate first dielectric layer on the unit area and a plurality of second openings in the intermediate floating gate layer, the intermediate control gate layer and the intermediate first dielectric layer on the contact area, so as to form a plurality of composite structures arranged along the second direction and independent of each other on the unit area and the contact area, the first openings are between adjacent composite structures, the word line structure and the second opening are connected in the composite structure, and the composite structure comprises the floating gate layer, the control gate layer and the first dielectric layer located on both sides of the word line structure and the second opening in the second direction. Since the first patterning layer is used for patterning to form the word line openings and the second patterning layer is used for patterning to form the first openings and the second openings, the mutual dependence between the processes for forming the word line structures and the composite structures is reduced, the performance and reliability of the formed memory structure are improved, and the process difficulty is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figures 1 to 3 FIG. 1 is a structural schematic diagram of each step in a method for forming a memory structure;

[0032] Figures 4 to 24 FIG. 1 is a structural schematic diagram of each step in a method for forming a memory structure; DETAILED DESCRIPTION

[0033] As described in the background section, there are still many problems in the forming process of the existing Nor Flash device. The following will be described in detail with reference to the accompanying drawings.

[0034] Figures 1 to 3 is a schematic view of each step of a forming method of a memory structure.

[0035] Please refer to Figure 1 and Figure 2 , Figure 1 is Figure 2 a schematic view of the top structure, Figure 2 is Figure 1 a schematic view of the cross-section structure along the direction M1-M2 in , a substrate 100 is provided, which includes a contact region I and a cell region II.

[0036] The contact region I and the cell region II have a floating gate material layer 110 and a control gate material layer 120 on the surface of the floating gate material layer 110.

[0037] The control gate material layer 120 has a patterned layer 130 on it, and the patterned layer 130 has a plurality of independent patterned openings 131.

[0038] Please continue to refer to Figure 1 and Figure 2 , a sidewall 140 is formed on the sidewall of the patterned opening 131.

[0039] It should be noted that Figure 1 the sidewall 140 is not shown in .

[0040] Please refer to Figure 3 , Figure 3 and Figure 2 , the view direction is consistent with that of , the patterned layer 130 and the sidewall 140 are used as masks to etch the exposed control gate material layer 120 and the floating gate material layer 110 until the surface of the substrate 100 is exposed, forming an initial control gate layer (not shown) and an initial floating gate layer (not shown), which have word line openings (not shown) connected to the patterned openings 131; a word line structure 160 is formed in the word line openings and the patterned openings 131; after the formation of the word line structure 160, a plurality of patterned layers 130 are removed to expose the surface of the initial control gate layer below the patterned layer 130; after the removal of the patterned structure 130, the word line structure 160 and the sidewall 140 are used as masks to etch the exposed initial control gate layer and the initial floating gate layer until the surface of the substrate 100 is exposed, forming openings 150 in the initial control gate layer and the initial floating gate layer to form a control gate layer 121 and a floating gate layer 111.

[0041] In the above method, the patterned layer 130 formed by one photoetching mask, and the sidewall 140 of the sidewall surface of the patterned opening 131, realize the self-alignment process to define the pattern of the word line structure 160, and the pattern of the control gate layer 121 and the floating gate layer 111.

[0042] However, since the pattern of the word line structure 160, and the pattern of the control gate layer 121 and the floating gate layer 111 are defined in a self-alignment process (i.e. the pattern of the word line opening and the opening 150 are defined in a self-alignment process), the process of forming the word line structure 160 and the process of forming the control gate layer 121 and the floating gate layer 111 are highly dependent on each other, resulting in not only poor performance and reliability of the formed memory structure, but also high process difficulty.

[0043] Specifically, since the word line opening and the opening 150 need to be separated by the sidewall 140, it is usually necessary to form a relatively thick sidewall 140 by a deposition process and an anisotropic etching process, so that the sidewall surface of the sidewall 140 has poor verticality, resulting in poor morphology of the word line structure 160, and in the direction perpendicular to the sidewall surface of the sidewall 140, the sidewall of the control gate layer 121 in the word line opening is larger in size than the sidewall of the floating gate layer 111, which further causes poor performance of the memory structure.

[0044] Furthermore, on the one hand, since the word line structure 160 and the sidewall 140 need to be used as a mask to etch the exposed initial control gate layer 121 and the initial floating gate layer 111 to form the control gate layer 121 and the floating gate layer 111, the word line structure 160 needs to be located on both the contact region I and the cell region II; on the other hand, since the sidewall 140 has poor verticality, the word line structure 160 severely blocks the control gate layer 121. Thus, the word line structure 160 with severe blocking of the control gate layer 121 is on the contact region I. Since the word line structure 160 with severe blocking of the control gate layer 121 is on the contact region I, on the one hand, a conductive structure subsequently formed in contact with the surface of the control gate layer 121 on the contact region I is prone to be disconnected between the conductive structure and the control gate layer 121, resulting in poor reliability of the memory structure; on the other hand, a complex pattern of the patterned layer 130 (such as the "S" shape shown in the region M3 of Figure 1 ) needs to be formed on the contact region I to form the word line structure 160 with a corresponding pattern, which provides space for forming the conductive structure, thereby not only resulting in a small process window and high process difficulty, but also resulting in a large spacing between adjacent word line structures 160, which leads to low integration of the memory structure and poor performance of the memory structure.

[0045] In summary, the above method not only has high process difficulty, but also has poor performance and low reliability of the formed memory structure.

[0046] To solve the above technical problems, the technical scheme of the present application provides a memory structure and a forming method thereof. The memory structure is formed by performing a patterning process based on a first patterning layer to form a plurality of word line openings arranged along a second direction in an initial floating gate layer, an initial control gate layer and an initial first dielectric layer on the cell region, so as to form an intermediate floating gate layer, an intermediate control gate layer and an intermediate first dielectric layer, wherein the second direction is perpendicular to the first direction; a plurality of word line structures are formed in the plurality of word line openings; a second patterning layer is formed on the plurality of word line structures and the intermediate first dielectric layer; a patterning process is performed based on the second patterning layer to form a plurality of first openings in the intermediate floating gate layer, the intermediate control gate layer and the intermediate first dielectric layer on the cell region and a contact region, and a plurality of second openings in the intermediate floating gate layer, the intermediate control gate layer and the intermediate first dielectric layer on the contact region, so as to form a plurality of composite structures which are independent of each other and arranged along the second direction on the cell region and the contact region, wherein the composite structures have the first openings between adjacent composite structures, the composite structures have the word line structures and the second openings connected to each other, and the composite structures include the floating gate layer, the control gate layer and the first dielectric layer located on both sides of the word line structure and the second opening in the second direction. Thus, the performance and reliability of the formed memory structure are improved, and the process difficulty is reduced.

[0047] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0048] Figures 4 to 24 FIG. 1 is a structural schematic diagram of each step in a forming method of a memory structure according to an embodiment of the present application.

[0049] Please refer to Figure 4 and Figure 5 , Figure 4 is a top view structural schematic diagram of Figure 5 , Figure 5 is a cross-sectional structural schematic diagram of Figure 4 along the direction A1-A2, a substrate 200 is provided, wherein the substrate 200 includes a contact region T and a cell region C arranged along a first direction X and adjacent to each other.

[0050] In the embodiment, the substrate 200 includes a base 201 and a seventh dielectric film 202 located on the surface of the base 201.

[0051] In the embodiment, the material of the base 201 is silicon. In other embodiments, the material of the base can also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0052] In the embodiment, the base 201 of the cell region C has a plurality of active regions (not shown) arranged along the first direction X and independent of each other.

[0053] In this embodiment, the material of the seventh dielectric film 202 includes oxides.

[0054] Specifically, the material of the seventh dielectric film 202 includes silicon oxide.

[0055] Please refer to Figure 6 , Figure 6 and Figure 5 With the view orientation consistent, an initial floating gate layer 210 is formed on the contact area T and the unit area C; an initial control gate layer 220 is formed on the initial floating gate layer 210; and an initial first dielectric layer 230 is formed on the initial control gate layer 220.

[0056] Thus, the contact area T and the cell area C have: an initial floating gate layer 210, an initial control gate layer 220 located on the initial floating gate layer 210, and an initial first dielectric layer 230 located on the initial control gate layer 220.

[0057] The initial floating gate layer 210 provides material for forming the floating gate layer.

[0058] In this embodiment, the process for forming the initial floating gate layer 210 includes one or more of chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

[0059] In this embodiment, the material of the initial floating gate layer 210 includes polycrystalline silicon.

[0060] The initial control gate layer 220 provides material for forming the control gate layer.

[0061] In this embodiment, the process for forming the initial control gate layer 220 includes one or more of chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

[0062] In this embodiment, the initial control gate layer 220 includes: an initial fourth dielectric film 221, an initial fifth dielectric film 222 located on the surface of the initial fourth dielectric film 221, an initial sixth dielectric film 223 located on the surface of the initial fifth dielectric film 222, and an initial control gate 224 located on the surface of the initial sixth dielectric film 223.

[0063] The initial fourth dielectric film 221 provides material for forming the fourth dielectric film, the initial fifth dielectric film 222 provides material for forming the fifth dielectric film, and the initial sixth dielectric film 223 provides material for forming the sixth dielectric film.

[0064] In this embodiment, the initial fourth dielectric film 221 is made of oxide, the initial fifth dielectric film 222 is made of nitride, and the initial sixth dielectric film 223 is made of silicon oxide. Thus, the subsequently formed fourth, fifth, and sixth dielectric films can constitute an oxide-nitride-oxide (ONO) dielectric structure.

[0065] The initial control gate 224 provides material for forming the control gate.

[0066] In this embodiment, the material of the initial control gate 224 includes polysilicon.

[0067] The initial first dielectric layer 230 provides materials for forming the first dielectric layer.

[0068] In this embodiment, the process for forming the initial first dielectric layer 230 includes one or more of the following: spin coating, chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

[0069] In this embodiment, the material of the initial first dielectric layer 230 includes oxides.

[0070] Specifically, the material of the initial first dielectric layer 230 includes silicon oxide.

[0071] Please refer to Figure 7 and Figure 8 , Figure 7 yes Figure 8 A top-view structural diagram. Figure 8 yes Figure 7 A cross-sectional structural diagram along the direction A1-A2 shows a first patterned layer 240 formed on the initial first dielectric layer 230.

[0072] Specifically, the first patterned layer 240 has a plurality of first patterned openings 241, the plurality of first patterned openings 241 are arranged along the second direction Y, and the bottom of the first patterned openings 241 exposes the surface of the initial first dielectric layer 230 on the cell region C.

[0073] Wherein, the second direction Y is perpendicular to the first direction X.

[0074] In this embodiment, the first patterned layer 240 is formed using a photolithography process. Specifically, the material of the first patterned layer 240 includes a first photoresist layer (not shown).

[0075] Preferably, the first patterning layer 240 further includes a first mask layer (not shown) located between the first photoresist layer and the initial first dielectric layer 230 to improve the stability of the photolithographic pattern transfer.

[0076] Next, based on the first patterning layer 240, patterning processing is performed to form a plurality of word line openings arranged along the second direction Y within the initial floating gate layer 210, initial control gate layer 220, and initial first dielectric layer 230 on the cell region C, thereby forming an intermediate floating gate layer, an intermediate control gate layer, and an intermediate first dielectric layer. For details on the steps of patterning based on the first patterning layer 240 to form the plurality of word line openings, please refer to [reference needed]. Figures 9 to 11 .

[0077] Please refer to Figure 9 , Figure 9 and Figure 8 With the view orientation consistent, and using the first patterning layer 240 as a mask, the initial first dielectric layer 230 and the initial control gate layer 220 on the cell region C are etched (e.g., ...). Figure 8 As shown in the figure, until the initial fifth dielectric film 222 is exposed, an intermediate sixth dielectric film 323, an intermediate control gate 324 located on the surface of the intermediate sixth dielectric film 323, and an intermediate first dielectric layer 330 located on the surface of the intermediate control gate 324 are formed. The intermediate sixth dielectric film 323, the intermediate control gate 324 and the intermediate first dielectric layer 330 have a plurality of word line openings 301.

[0078] The intermediate first dielectric layer 330 provides materials for the subsequent formation of the first dielectric layer.

[0079] In this embodiment, the process of etching the initial first dielectric layer 230 and the initial control gate layer 220 on the cell region C includes at least one of dry etching and wet etching processes.

[0080] Please refer to Figure 10 , Figure 10 and Figure 9 With the view orientation aligned, an initial first sidewall gate dielectric layer 250 is formed on the sidewall surface of the opening 301 on the word line and the sidewall surface of the first patterned opening 241.

[0081] The initial first sidewall gate dielectric layer 250 serves two purposes: firstly, it provides material for the subsequent formation of the first sidewall gate dielectric layer; secondly, it works together with the first patterning layer 240 as a mask in the subsequent etching process for forming the opening under the word line.

[0082] In this embodiment, the initial first sidewall gate dielectric layer 250 includes an initial first inner sidewall gate dielectric layer 251, which is connected to the intermediate sixth dielectric film 323 to subsequently form a connected first inner sidewall gate dielectric layer and sixth dielectric film.

[0083] In this embodiment, the material of the initial first inner sidewall gate dielectric layer 251 includes oxides.

[0084] Specifically, the material of the initial first inner sidewall gate dielectric layer 251 is the same as the material of the intermediate sixth dielectric film 323, and the material of the initial first inner sidewall gate dielectric layer 251 includes silicon oxide.

[0085] In this embodiment, the initial first sidewall gate dielectric layer 250 further includes an initial first outer sidewall gate dielectric layer 252 located on the surface of the initial first inner sidewall gate dielectric layer 251.

[0086] In this embodiment, the material of the initial first outer sidewall gate dielectric layer 252 includes nitrides.

[0087] Specifically, the material of the initial first outer sidewall gate dielectric layer 252 is the same as the material of the initial fifth dielectric film 222, and the material of the initial first outer sidewall gate dielectric layer 252 includes silicon nitride.

[0088] In this embodiment, the method for forming the initial first sidewall gate dielectric layer 250 includes: depositing an initial first inner sidewall gate dielectric material layer (not shown) on the surface of the first patterned layer 240 and the inner wall surface of the word line opening 301; depositing an initial first outer sidewall gate dielectric material layer (not shown) on the surface of the initial first inner sidewall gate dielectric material layer; and using an anisotropic etching process to etch the initial first outer sidewall gate dielectric material layer and the initial first inner sidewall gate dielectric material layer until the top surface of the first patterned layer 240 and the bottom surface of the word line opening 301 are exposed.

[0089] Please refer to Figure 11 , Figure 11 and Figure 10 With the view direction consistent, using the initial first sidewall gate dielectric layer 250 and the first patterning layer 240 as masks, the exposed initial fifth dielectric film 222, initial fourth dielectric film 221 and initial floating gate layer 210 are etched until the surface of the substrate 200 is exposed, forming an intermediate fifth dielectric film 322, intermediate fourth dielectric film 321 and intermediate floating gate layer 310. The intermediate fifth dielectric film 322, intermediate fourth dielectric film 321 and intermediate floating gate layer 310 have a plurality of under-word openings 302.

[0090] The intermediate floating gate layer 310 provides materials for the subsequent formation of the floating gate layer.

[0091] The lower opening 302 of the character line is connected to the upper opening 301 of the character line, and the lower opening 302 of the character line and the upper opening 301 of the character line constitute the character line opening.

[0092] The intermediate fourth dielectric film 321, intermediate fifth dielectric film 322, intermediate sixth dielectric film 323 and intermediate control gate 324 constitute the intermediate control gate layer 320.

[0093] The intermediate control gate layer 320 provides material for the subsequent formation of control gate layers.

[0094] Therefore, based on the first patterning layer 240, a number of word line openings arranged along the second direction Y are formed in the initial floating gate layer 210, the initial control gate layer 220 and the initial first dielectric layer 230 on the cell region C, so as to form the intermediate floating gate layer 310, the intermediate control gate layer 320 and the intermediate first dielectric layer 330.

[0095] Specifically, the intermediate floating gate layer 310, the intermediate control gate layer 320, and the intermediate first dielectric layer 330 have several word line openings arranged along the second direction Y.

[0096] Specifically, the bottom of the word line opening exposes the surface of the seventh dielectric film 202.

[0097] In this embodiment, the etching process for exposing the initial fifth dielectric film 222, the initial fourth dielectric film 221, and the initial floating gate layer 210 includes at least one of dry etching and wet etching processes.

[0098] Please refer to Figure 12 , Figure 12 and Figure 11 With the view direction consistent, in the direction perpendicular to the sidewall of the opening 301 on the word line, the initial first outer sidewall gate dielectric layer 252 and the intermediate fifth dielectric film 322 are etched to reduce the thickness of the initial first outer sidewall gate dielectric layer 252 and increase the width of the opening 302 under the word line in the intermediate fifth dielectric film 322 to form the opening 302a under the word line.

[0099] By thinning the initial first outer wall gate dielectric layer 252 and increasing the width of the word line under-aperture 302 within the intermediate fifth dielectric film 322, the sidewall of the floating gate layer 310 exposed in the word line under-aperture protrudes relative to the sidewall of the initial first outer wall gate dielectric layer 252. This allows the subsequently formed word line structure to form erase points (e.g., ...) with the floating gate layer when covering the sidewall of the floating gate layer exposed in the word line under-aperture. Figure 14 (as shown in region B) to provide erase performance of the memory structure, thereby further improving the performance of the memory structure.

[0100] In this embodiment, the process of etching the initial first outer sidewall gate dielectric layer 252 and the intermediate fifth dielectric film 322 includes a dry etching process.

[0101] In another embodiment, the initial first outer sidewall gate dielectric layer 252 and the intermediate fifth dielectric film 322 are not etched in a direction perpendicular to the sidewall surface of the opening 301 on the word line, that is, the thickness of the initial first outer sidewall gate dielectric layer 252 is not thinned, and the opening 302 on the word line is not enlarged.

[0102] Please refer to Figure 13 , Figure 13 and Figure 12 With the view direction consistent, after thinning the thickness of the initial first outer sidewall gate dielectric layer 252, the first patterned layer 240 and the initial first sidewall gate dielectric layer 250 on the sidewall of the first patterned layer 240 are removed, and the first sidewall gate dielectric layer 350 is formed on the sidewall surface of the opening 301 on the word line.

[0103] In this embodiment, the first sidewall gate dielectric layer 350 includes: a first inner sidewall gate dielectric layer 351 and a first outer sidewall gate dielectric layer 352 located on the sidewall surface of the first inner sidewall gate dielectric layer 351.

[0104] In this embodiment, the process of removing the first patterned layer 240 and the initial first sidewall gate dielectric layer 250 on the sidewall of the first patterned layer 240 includes at least one of the following: ashing process, etching process and planarization process.

[0105] The etching process includes at least one of dry etching and wet etching.

[0106] The planarization process includes chemical mechanical polishing (CMP).

[0107] Please continue to refer to this. Figure 13 After the first sidewall gate dielectric layer 350 is formed, a second sidewall gate dielectric layer 360 is formed on the sidewall surface of the first sidewall gate dielectric layer 350 and the sidewall surface of the opening 302a under the word line.

[0108] In this embodiment, the sidewall of the second sidewall gate dielectric layer 360 of the sidewall surface of the opening 302a below the word line protrudes from the sidewall of the second sidewall gate dielectric layer 360 relative to the sidewall surface of the first sidewall gate dielectric layer 350.

[0109] In another embodiment, since the thickness of the initial first outer sidewall gate dielectric layer 252 is not thinned, the sidewall surfaces of the second sidewall gate dielectric layer are flush.

[0110] In this embodiment, the material of the second sidewall gate dielectric layer 360 includes oxides.

[0111] Specifically, the material of the second sidewall gate dielectric layer 360 is the same as the material of the intermediate fourth dielectric film 321, and the material of the second sidewall gate dielectric layer 360 includes silicon oxide.

[0112] In this embodiment, the method for forming the second sidewall gate dielectric layer 360 includes: depositing a second sidewall gate dielectric material layer (not shown) on the surface of the intermediate first dielectric layer 330, the surface of the first sidewall gate dielectric layer 350, and the inner wall surface of the word line opening 302a; and etching the second sidewall gate dielectric material layer using an anisotropic etching process until the top surface of the intermediate first dielectric layer 330, the top surface of the first sidewall gate dielectric layer 350, and the bottom surface of the word line opening 302a are exposed.

[0113] Please refer to Figure 14 After forming the second sidewall gate dielectric layer 360, a plurality of word line structures 370 are formed within the plurality of word line openings.

[0114] In this embodiment, the material of the word line structure 370 includes polycrystalline silicon.

[0115] In this embodiment, the method of forming a plurality of word line structures 370 within a plurality of word line openings includes: forming a word line structure material layer (not shown) within the plurality of word line openings and on the surface of the intermediate first dielectric layer 330, wherein the surface of the word line structure material layer is higher than the surface of the intermediate first dielectric layer 330; planarizing the word line structure material layer until the top surface of the intermediate first dielectric layer 330 is exposed.

[0116] The process for planarizing the word line structure material layer includes chemical mechanical polishing.

[0117] Please refer to Figure 15 and Figure 16 , Figure 15 yes Figure 16 A top-view structural diagram. Figure 16 yes Figure 15 A cross-sectional structural diagram along the central direction A1-A2 shows that a second patterning layer 260 is formed on several of the word line structures 370 and the intermediate first dielectric layer 330, and the second patterning layer 260 exposes part of the surface of the intermediate first dielectric layer 330.

[0118] It should be noted that, Figure 16 The first sidewall gate dielectric layer 350 and the second sidewall gate dielectric layer 360 are not shown in the diagram.

[0119] In this embodiment, the second patterned layer 260 is formed using a photolithography process. Specifically, the material of the second patterned layer 260 includes a second photoresist layer (not shown).

[0120] Preferably, the second patterning layer 260 further includes a second mask layer (not shown) located between the second photoresist layer and the intermediate first dielectric layer 330 to improve the stability of the photolithographic pattern transfer.

[0121] refer to Figure 17 and Figure 18 , Figure 17 yes Figure 18 A top-view structural diagram. Figure 18 yes Figure 17 A schematic diagram of the cross-sectional structure along the direction A1-A2, based on the second patterning layer 260 (e.g., Figure 15 and Figure 16 The diagram shows that a plurality of first openings 303 are formed in the intermediate floating gate layer 310, intermediate control gate layer 320 and intermediate first dielectric layer 330 on the cell region C and the contact region T, and a plurality of second openings 304 are formed in the intermediate floating gate layer 310, intermediate control gate layer 320 and intermediate first dielectric layer 330 on the contact region T, so as to form a plurality of composite structures 400 that are independent of each other and arranged along the second direction Y on the cell region C and the contact region T.

[0122] It should be noted that, Figure 17 The first sidewall gate dielectric layer 350 and the second sidewall gate dielectric layer 360 are not shown in the diagram.

[0123] Specifically, adjacent composite structures 400 have a first opening 303 between them, and the composite structure 400 has a connected word line structure 370 and a second opening 304.

[0124] The composite structure 400 includes a floating gate layer 410, a control gate layer 420, and a first dielectric layer 430 located on both sides of the word line structure 370 and the second opening 304 in the second direction Y.

[0125] The control gate layer 420 is located on the floating gate layer 410, and the first dielectric layer 430 is located on the control gate layer 420.

[0126] Since the word line openings are formed by patterning based on the first patterning layer 240 and the first opening 303 and the second opening 304 are formed by patterning based on the second patterning layer 260, the interdependence between the processes of forming the word line structure 370 and the composite structure 400 is reduced, thereby improving the performance and reliability of the formed memory structure and reducing the process difficulty.

[0127] Specifically, patterning is performed based on the first patterning layer 240 to form the word line opening, and patterning is performed based on the second patterning layer 260 to form the first opening 303 and the second opening 304. Therefore, the word line opening and the first opening 303 and the second opening 304 are highly independent of each other. Thus, on the one hand, word line openings with high sidewall verticality can be formed, thereby not only forming a word line structure 370 with good sidewall morphology, but also having a smaller settling dimension of the sidewall of the formed control gate layer 420 (especially the control gate 424) relative to the sidewall of the floating gate layer 410 in the direction perpendicular to the sidewall of the word line opening, thereby improving the performance of the memory structure. On the other hand, word line openings can be formed only on cell region C, so that the word line structure 370 is formed only on cell region C, so that the word line structure 370 does not block the surface of the control gate layer 420 of the contact area T. Thus, not only the subsequently formed conductive structure 460 (such as Figure 24 The risk of false connections and open circuits between the control gate layer 420 and the contact area T is small, thus improving the reliability of the memory structure. Furthermore, it simplifies the pattern of the composite structure 400 formed on the contact area T (i.e., simplifies the patterns of the first opening 303 and the second opening 304). Simultaneously, a larger contact opening 305 can be formed subsequently (e.g., as shown). Figure 22 (as shown) to expose the surface of the control gate layer 220 of the contact area T, so that the contact opening 305 and the contact layer 421 (as shown) can be subsequently formed. Figure 23 The process windows (as shown in the figure) have all been enlarged to reduce the difficulty of the process.

[0128] Furthermore, since the pattern of the composite structure 400 formed on the contact area T can be simplified (i.e., the pattern of the first opening 303 and the second opening 304 can be simplified), the spacing between adjacent composite structures 400 can be reduced, thereby improving the performance of the memory structure.

[0129] In summary, this improves the performance and reliability of the resulting memory structure while reducing the manufacturing complexity.

[0130] Furthermore, compared to the formation method of forming memory structures through self-alignment, the word line openings and the first and second openings are formed based on the first patterning layer 240 and the second patterning layer 260 respectively (i.e., pattern transfer is based on two photolithography patterns). Since there is no need to form and remove sidewalls to define the word line openings and the first and second openings, the number of processing steps is greatly reduced and the complexity of the processing is reduced. Therefore, it is not only beneficial to reduce the difficulty of the process, but also to shorten the production cycle and increase the production capacity.

[0131] In this embodiment, the material of the floating gate layer 410 includes polycrystalline silicon.

[0132] In this embodiment, the control gate layer 420 includes: a fourth dielectric film 421, a fifth dielectric film 422 located on the surface of the fourth dielectric film 421, a sixth dielectric film 423 located on the surface of the fifth dielectric film 422, and a control gate 424 located on the surface of the sixth dielectric film 423.

[0133] In this embodiment, the material of the fourth dielectric film 421 includes oxides. Specifically, the material of the fourth dielectric film 421 includes silicon oxide.

[0134] In this embodiment, the material of the fifth dielectric film 422 includes nitrides. Specifically, the material of the fifth dielectric film 422 includes silicon nitride.

[0135] In this embodiment, the material of the sixth dielectric film 423 includes oxides. Specifically, the material of the sixth dielectric film 423 includes silicon oxide.

[0136] In this embodiment, the material of the control gate 424 includes polycrystalline silicon.

[0137] In this embodiment, the material of the first dielectric layer 430 includes silicon oxide.

[0138] In this embodiment, the method for performing patterning processing based on the second patterning layer 260 includes: using the second patterning layer 260 as a mask, etching the exposed intermediate first dielectric layer 330, intermediate control gate layer 320 and intermediate floating gate layer 310 until the seventh dielectric film 202 on the surface of the substrate 201 is exposed.

[0139] In this embodiment, the first opening 303 has a first projection on the substrate 200.

[0140] Preferably, in the second direction Y, the first projection of the unit region C has a first width W1 (e.g., ...). Figure 17 As shown in the diagram, the first projection of the contact area T has a second width W2 (as shown in the diagram). Figure 17 As shown in the diagram, the first width W1 is greater than the second width W2. By forming a wider first opening 303 on the cell region C (compared to the contact region T), adjacent composite structures 400 can be better separated, thereby reducing the risk of leakage and short circuit between adjacent composite structures 400, and thus further improving the performance and reliability of the memory structure.

[0141] Preferably, the first projection of the contact area T includes: a plurality of first offset boundaries 303a offset along the second direction Y toward the first projection (e.g., Figure 17(As shown in the diagram). Therefore, the width of the composite structure 400 on the contact area T can be locally increased in the second direction Y, providing a larger contactable area for the subsequently formed conductive structure. This further reduces the risk of incomplete connection or open circuit between the conductive structure and the control gate layer 320 on the contact area T, thereby improving the performance and reliability of the semiconductor structure.

[0142] Preferably, the first projection of the contact area T further includes: a plurality of second offset boundaries 303b offset from the first projection along the second direction Y (e.g., ...). Figure 17 As shown in the diagram, each second offset boundary 303b is opposite to one first offset boundary 303a, and the opposite first offset boundaries 303a and second offset boundaries 303b have the same offset distance. Therefore, the risk of leakage and short circuit between adjacent composite structures 400 on the contact area T is better reduced, thereby further improving the performance and reliability of the memory structure.

[0143] Preferably, the length of the second offset boundary 303b is greater than the length of the first offset boundary 303a.

[0144] In this embodiment, after performing graphical processing based on the second graphical layer 260, the second graphical layer 260 is removed.

[0145] In this embodiment, the process of removing the second patterned layer 260 includes an ashing process.

[0146] Next, please refer to Figure 19 and Figure 20 , Figure 19 yes Figure 20 A top-view structural diagram. Figure 20 yes Figure 19 A cross-sectional structural diagram along the direction A1-A2 shows that a second dielectric layer 440 is formed within the first opening 303 and the second opening 304.

[0147] In this embodiment, the surface of the second dielectric layer 440 is flush with the surface of the first dielectric layer 430.

[0148] In other embodiments, the surface of the second dielectric layer is higher than the surface of the first dielectric layer.

[0149] In this embodiment, the process for forming the second dielectric layer 440 includes at least one of spin coating, chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

[0150] Please refer to Figure 21 , Figure 21 and Figure 19With the view direction consistent, a third patterned layer 270 is formed on the first dielectric layer 430 and the second dielectric layer 440, and the third patterned layer 270 exposes the surfaces of the first dielectric layer 430 and the second dielectric layer 440 on the contact area T.

[0151] In other embodiments, a third patterned layer is formed on the surface of a second dielectric layer above the surface of the first dielectric layer, the third patterned layer exposing the surface of the second dielectric layer on the contact area.

[0152] In this embodiment, the material of the third patterning layer 270 includes a third photoresist layer (not shown).

[0153] Preferably, the third patterning layer 270 further includes a third mask layer (not shown) located between the third photoresist layer and the first dielectric layer 430 and the second dielectric layer 440 to improve the stability of the photolithographic pattern transfer.

[0154] Please refer to Figure 22 , Figure 22 and Figure 21 With the view direction consistent, using the third patterning layer 270 as a mask, the exposed first dielectric layer 430 and second dielectric layer 440 are etched until the surface of the control gate layer 420 of several composite structures 400 on the contact area T is exposed, and a contact opening 305 is formed in the first dielectric layer 430 and second dielectric layer 440 on the contact area T.

[0155] The contact opening 305 has a contact projection on the surface of the substrate 200.

[0156] Preferably, a plurality of the first offset boundaries 303a are within the range of the contact projection.

[0157] In this embodiment, after forming the contact opening 305, the third patterned layer 270 is removed. The process for removing the second patterned layer 260 includes an ashing process.

[0158] Please refer to Figure 23 , Figure 23 and Figure 24 With the view orientation consistent, after the contact opening 305 is formed, a contact layer 421 is formed on the surface of the control gate layer 420 of the plurality of composite structures 400 exposed by the contact opening 305 using a metal siliconization process.

[0159] By forming the contact layer 421, the contact resistance between the subsequently formed conductive structure and the control gate layer 420 can be reduced, thereby further improving the conductivity of the memory structure.

[0160] In this embodiment, the method of forming a contact layer 421 on the surface of the control gate layer 420 of the plurality of composite structures 400 exposed by the contact opening 305 using a metal silicide process includes: forming a metal layer (not shown) on the inner wall surface of the contact opening 305, the surface of the first dielectric layer 430 and the second dielectric layer 440; after forming the metal layer, performing a heat treatment to react the metal layer with the surface of the contact control gate layer 420; and after the heat treatment, removing the unreacted metal layer.

[0161] Next, please refer to Figure 24 , Figure 24 and Figure 23 With the view orientation consistent, a third dielectric layer 450 is formed within the contact opening 305, on the surface of the composite structure 400, and on the surface of the word line structure 370.

[0162] In this embodiment, the process for forming the third dielectric layer 450 includes at least one of spin coating, chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

[0163] Please continue to refer to this. Figure 24 A plurality of conductive structures 460 are formed within the third dielectric layer 450, and the bottom surface of the conductive structure 460 is in contact with the surface of the contact layer 421.

[0164] Thus, the conductive structure 460 is electrically connected to the control gate layer 420.

[0165] It should be noted that, for ease of understanding and explanation, Figure 24 The first projection 303c of the first opening 303 is represented by a dashed line.

[0166] Preferably, the conductive structure 460 has a third projection on the surface of the substrate 200, and a portion of the boundary of the third projection is adjacent to or coincides with the first offset boundary 303a.

[0167] In this embodiment, the method for forming a plurality of conductive structures 460 includes: forming a fourth patterned layer (not shown) on the surface of a third dielectric layer 450, the fourth patterned layer having a plurality of fourth patterned openings (not shown), the bottom of the fourth patterned openings exposing the surface of the third dielectric layer 450 on the control gate layer 420; using the fourth patterned layer as a mask, etching the third dielectric layer 450 until the surface of the contact layer 421 is exposed, forming a plurality of conductive openings (not shown) in the third dielectric layer 450, the bottom of the conductive openings exposing the surface of the contact layer 421; and forming a plurality of conductive structures 460 in the plurality of conductive openings.

[0168] Accordingly, one embodiment of the present invention also provides a memory structure formed by the above-described forming method. Please refer to [the original text]. Figure 24 Including: substrate 200 (e.g. Figure 4 and Figure 5 As shown in the diagram, the substrate 200 includes contact regions T and unit regions C arranged and adjacent to each other along a first direction X; and a plurality of independent composite structures 400 (e.g., [examples of composite structures]) located on the contact regions T and unit regions C and arranged along a second direction Y. Figure 17 As shown), the second direction Y is perpendicular to the first direction X, and adjacent composite structures 400 have a first opening 303 (as shown). Figure 17 and Figure 18 As shown in the diagram), each of the composite structures 400 has a connected word line opening and a second opening 304 (as shown in the diagram). Figure 17 As shown), the word line opening is located on the unit area C, the second opening 304 is located on the contact area T, and the word line opening has a word line structure 370 (as shown). Figure 18 (as shown in the image).

[0169] In this embodiment, the substrate 200 includes a substrate 201 and a seventh dielectric film 202 located on the surface of the substrate 201.

[0170] In this embodiment, the substrate 201 is made of silicon. In other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0171] In this embodiment, the substrate 201 of the unit region C has a plurality of active regions (not shown) arranged along the first direction X and independent of each other.

[0172] In this embodiment, the material of the seventh dielectric film 202 includes oxides.

[0173] Specifically, the material of the seventh dielectric film 202 includes silicon oxide.

[0174] In this embodiment, the material of the word line structure 370 includes polycrystalline silicon.

[0175] The composite structure 400 includes a floating gate layer 410, a control gate layer 420, and a first dielectric layer 430 located on both sides of the word line structure 370 and the second opening 304 in the second direction Y. The control gate layer 420 is located on the floating gate layer 410, and the first dielectric layer 430 is located on the control gate layer 420.

[0176] In this embodiment, the material of the floating gate layer 410 includes polycrystalline silicon.

[0177] In this embodiment, the control gate layer 420 includes: a fourth dielectric film 421, a fifth dielectric film 422 located on the surface of the fourth dielectric film 421, a sixth dielectric film 423 located on the surface of the fifth dielectric film 422, and a control gate 424 located on the surface of the sixth dielectric film 423.

[0178] In this embodiment, the material of the fourth dielectric film 421 includes oxides. Specifically, the material of the fourth dielectric film 421 includes silicon oxide.

[0179] In this embodiment, the material of the fifth dielectric film 422 includes nitrides. Specifically, the material of the fifth dielectric film 422 includes silicon nitride.

[0180] In this embodiment, the material of the sixth dielectric film 423 includes oxides. Specifically, the material of the sixth dielectric film 423 includes silicon oxide.

[0181] In this embodiment, the material of the control gate 424 includes polycrystalline silicon.

[0182] In this embodiment, the material of the first dielectric layer 430 includes silicon oxide.

[0183] In this embodiment, the word line opening includes: a word line opening 301 located within the sixth dielectric film 423, the control gate 424, and the first dielectric layer 430 (e.g., Figure 9 (as shown in the diagram); the under-word opening 302a located within the fifth dielectric film 422, the fourth dielectric film 421, and the floating gate layer 410 (as shown in the diagram); Figure 12 As shown in the figure, the opening 301 on the upper part of the word line and the opening 302a below the word line are connected, and the bottom of the opening 302a below the word line exposes the surface of the substrate 200.

[0184] Specifically, the bottom of the opening 302a below the word line exposes the surface of the seventh dielectric film 202.

[0185] Specifically, the width of the opening 301 above the character line is greater than the width of the opening 302a below the character line.

[0186] In this embodiment, the memory structure further includes: a first sidewall gate dielectric layer 350 located on the sidewall surface of the word line opening 301 (e.g., Figure 14 (as shown in the image).

[0187] In this embodiment, the sidewall surface of the first sidewall gate dielectric layer 350 is recessed relative to the sidewall surface of the floating gate layer 410 in the word line opening. This improves the erase performance of the memory structure.

[0188] In another embodiment, in the word line opening, the sidewall surface of the first sidewall gate dielectric layer is flush with the sidewall surface of the floating gate layer.

[0189] In this embodiment, the first sidewall gate dielectric layer 350 includes: a first inner sidewall gate dielectric layer 351 and a first outer sidewall gate dielectric layer 352 located on the sidewall surface of the first inner sidewall gate dielectric layer 351.

[0190] In this embodiment, the material of the first inner sidewall gate dielectric layer 351 includes oxide. Specifically, the material of the first inner sidewall gate dielectric layer 351 includes silicon oxide.

[0191] In this embodiment, the material of the first outer sidewall gate dielectric layer 352 includes nitride. Specifically, the material of the first outer sidewall gate dielectric layer 352 includes silicon nitride.

[0192] In this embodiment, the memory structure further includes a second sidewall gate dielectric layer 360 located on the sidewall surface of the first sidewall gate dielectric layer 350 and the word line opening 302a.

[0193] In this embodiment, the material of the second sidewall gate dielectric layer 360 includes oxide. Specifically, the material of the second sidewall gate dielectric layer 360 includes silicon oxide.

[0194] In this embodiment, the sidewall of the second sidewall gate dielectric layer 360 of the sidewall surface of the opening 302a below the word line protrudes from the sidewall of the second sidewall gate dielectric layer 360 relative to the sidewall surface of the first sidewall gate dielectric layer 350.

[0195] In another embodiment, the sidewall surfaces of the second sidewall gate dielectric layer are flush.

[0196] In this embodiment, the first opening 303 has a first projection on the substrate 200.

[0197] Preferably, in the second direction Y, the first projection of the unit region C has a first width W1 (e.g., ...). Figure 17 As shown in the diagram, the first projection of the contact area T has a second width W2 (as shown in the diagram). Figure 17 As shown in the figure, the first width W1 is greater than the second width W2.

[0198] Preferably, the first projection of the contact area T includes: a plurality of first offset boundaries 303a offset along the second direction Y toward the first projection (e.g., Figure 17 (as shown in the image).

[0199] Preferably, the first projection of the contact area T further includes: a plurality of second offset boundaries 303b offset from the first projection along the second direction Y (e.g., ...). Figure 17As shown in the figure, each second offset boundary 303b is opposite to one first offset boundary 303a, and the opposite first offset boundary 303a and second offset boundary 303b have the same offset distance.

[0200] Preferably, the length of the second offset boundary 303b is greater than the length of the first offset boundary 303a.

[0201] In this embodiment, the memory structure further includes a second dielectric layer 440 located within the first opening 303 and the second opening 304 (e.g., ...). Figure 23 (As shown).

[0202] In this embodiment, the surface of the second dielectric layer 440 is flush with the surface of the first dielectric layer 430.

[0203] In this embodiment, the memory structure further includes: a contact opening 305 located within the first dielectric layer 430 and the second dielectric layer 440 on the contact area T (e.g., ...). Figure 23 As shown), the bottom of the contact opening 305 exposes the surface of the control gate layer 420 of several composite structures 400 on the contact area T.

[0204] The contact opening 305 has a contact projection on the surface of the substrate 200.

[0205] Preferably, a plurality of the first offset boundaries 303a are within the range of the contact projection.

[0206] In this embodiment, the memory structure further includes a contact layer 421 located on the surface of the control gate layer 420 of the plurality of composite structures 400 exposed by the contact opening 305.

[0207] In this embodiment, the memory structure further includes: a third dielectric layer 450 located within the contact opening 305, on the surface of the composite structure 400, and on the surface of the word line structure 370; and a plurality of conductive structures 460 located within the third dielectric layer 450.

[0208] The conductive structure 460 is electrically connected to the control gate layer 420.

[0209] Specifically, the bottom surface of the conductive structure 460 is in contact with the surface of the contact layer 421.

[0210] Preferably, the conductive structure 460 has a third projection on the surface of the substrate 200, and a portion of the boundary of the third projection is adjacent to or coincides with the first offset boundary 303a.

[0211] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a memory structure, characterized in that, include: A substrate is provided, the substrate including contact regions and cell regions arranged and adjacent to each other along a first direction, the contact regions and cell regions having an initial floating gate layer, an initial control gate layer located on the initial floating gate layer, and an initial first dielectric layer located on the initial control gate layer; A first patterned layer is formed on the initial first dielectric layer; Based on the first patterning layer, a patterning process is performed to form a plurality of word line openings arranged along the second direction in the initial floating gate layer, initial control gate layer and initial first dielectric layer on the cell area, so as to form an intermediate floating gate layer, intermediate control gate layer and intermediate first dielectric layer, wherein the second direction is perpendicular to the first direction. Several character line structures are formed within several of the aforementioned character line openings; A second patterning layer is formed on several of the aforementioned word line structures and the intermediate first dielectric layer; Based on the second patterning layer, a patterning process is performed, forming a plurality of first openings in the intermediate floating gate layer, intermediate control gate layer, and intermediate first dielectric layer on the cell area and the contact area, and forming a plurality of second openings in the intermediate floating gate layer, intermediate control gate layer, and intermediate first dielectric layer on the contact area, so as to form a plurality of independent composite structures arranged along the second direction on the cell area and the contact area, with first openings between adjacent composite structures, and connected word line structures and second openings within the composite structures, the composite structures including floating gate layers, control gate layers, and first dielectric layers located on both sides of the word line structures and second openings in the second direction.

2. The method for forming a memory structure as described in claim 1, characterized in that, The first opening has a first projection on the substrate surface, and in the second direction, the first projection of the cell region has a first width, the first projection of the contact region has a second width, and the first width is greater than the second width.

3. The method for forming a memory structure as described in claim 1, characterized in that, The first opening has a first projection on the substrate surface, and the first projection of the contact area includes a plurality of first offset boundaries offset toward the first projection along a second direction.

4. The method for forming a memory structure as described in claim 3, characterized in that, The first projection of the contact area also includes a number of second offset boundaries offset from the first projection along the second direction, each second offset boundary being opposite to one first offset boundary, and the opposite first offset boundary and second offset boundary having the same offset distance.

5. The method for forming a memory structure as described in claim 3, characterized in that, After forming several composite structures, the method further includes: forming a second dielectric layer within the first opening and the second opening; forming a third patterned layer on the first and second dielectric layers, the third patterned layer exposing the surfaces of the first and second dielectric layers on the contact area; using the third patterned layer as a mask, etching the exposed first and second dielectric layers until the control gate layer surface of several composite structures on the contact area is exposed; forming contact openings within the first and second dielectric layers on the contact area, the contact openings having contact projections on the substrate surface, and several first offset boundaries within the range of the contact projections.

6. The method for forming a memory structure as described in claim 5, characterized in that, After forming the contact opening, the method further includes: forming a contact layer on the surface of the control gate layer of the composite structure exposed by the contact opening using a metal silicide process.

7. The method for forming a memory structure as described in claim 6, characterized in that, After forming the contact layer, the method further includes: forming a third dielectric layer within the contact opening; forming a plurality of conductive structures within the third dielectric layer, wherein the bottom surface of the conductive structures is in contact with the surface of the contact layer, the conductive structures have a third projection on the surface of the substrate, and a portion of the boundary of the third projection is adjacent to or coincides with the first offset boundary.

8. The method for forming a memory structure as described in claim 1, characterized in that, The intermediate control gate layer includes: an initial fourth dielectric film, an initial fifth dielectric film located on the surface of the initial fourth dielectric film, an initial sixth dielectric film located on the surface of the initial fifth dielectric film, and an initial control gate located on the surface of the initial sixth dielectric film.

9. The method for forming a memory structure as described in claim 8, characterized in that, The first patterned layer has a plurality of first patterned openings, the plurality of first patterned openings are arranged along a second direction, and the bottom of the first patterned openings exposes the surface of the initial first dielectric layer on the cell region.

10. The method for forming a memory structure as described in claim 9, characterized in that, The method for patterning based on the first patterning layer includes: using the first patterning layer as a mask, etching an initial first dielectric layer and an initial control gate layer on the cell region until the initial fifth dielectric film is exposed, forming an intermediate sixth dielectric film, an intermediate control gate located on the surface of the intermediate sixth dielectric film, and an intermediate first dielectric layer located on the surface of the intermediate control gate, wherein the intermediate sixth dielectric film, the intermediate control gate, and the intermediate first dielectric layer have a plurality of word line openings; and forming an initial first sidewall gate dielectric on the sidewall surfaces of the word line openings and the first patterning openings. Electric layer; using the initial first sidewall gate dielectric layer and the first patterned layer as masks, the exposed initial fifth dielectric film, initial fourth dielectric film and initial floating gate layer are etched until the substrate surface is exposed to form an intermediate fifth dielectric film, intermediate fourth dielectric film and intermediate floating gate layer. The intermediate fifth dielectric film, intermediate fourth dielectric film and intermediate floating gate layer have a plurality of word line openings. The intermediate fourth dielectric film, intermediate fifth dielectric film, intermediate sixth dielectric film and intermediate control gate constitute the intermediate control gate layer. The word line openings and the word line openings constitute the word line openings.

11. The method for forming a memory structure as described in claim 10, characterized in that, After forming the opening below the word line, the method further includes: removing the first patterning layer and the initial first sidewall gate dielectric layer on the sidewall of the first patterning layer, and forming a first sidewall gate dielectric layer on the sidewall surface of the opening below the word line.

12. The method for forming a memory structure as described in claim 11, characterized in that, After forming the opening under the word line and before forming the word line structure, the method further includes: forming a second sidewall gate dielectric layer on the sidewall surface of the first sidewall gate dielectric layer and the sidewall surface of the opening under the word line.

13. The method for forming a memory structure as described in claim 1, characterized in that, The substrate includes a base and a seventh dielectric film located on the surface of the base.

14. The method for forming a memory structure as described in claim 13, characterized in that, The method for patterning based on the second patterning layer includes: using the second patterning layer as a mask, etching the exposed intermediate first dielectric layer, intermediate control gate layer and intermediate floating gate layer until the seventh dielectric film on the substrate surface is exposed.

15. A memory structure, characterized in that, include: The substrate includes contact areas and unit areas arranged and adjacent to each other along a first direction; A plurality of independent composite structures located on the contact area and the unit area and arranged along a second direction, the second direction being perpendicular to the first direction, with a first opening between adjacent composite structures, and each composite structure having a connected word line opening and a second opening, the word line opening being located on the unit area, the second opening being located on the contact area, and the word line opening having a word line structure, the word line structure being located only on the unit area; The composite structure includes a floating gate layer, a control gate layer, and a first dielectric layer located on both sides of the word line structure and the second opening in a second direction, wherein the control gate layer is located on the floating gate layer and the first dielectric layer is located on the control gate layer.

16. The memory structure as described in claim 15, characterized in that, The first opening has a first projection on the substrate surface, and in the second direction, the first projection of the cell region has a first width, the first projection of the contact region has a second width, and the first width is greater than the second width.

17. The memory structure as described in claim 15, characterized in that, The first opening has a first projection on the substrate surface, and the first projection of the contact area includes a plurality of first offset boundaries offset toward the first projection along a second direction.

18. The memory structure as described in claim 17, characterized in that, The first projection of the contact area also includes a number of second offset boundaries offset from the first projection along the second direction, each second offset boundary being opposite to one first offset boundary, and the opposite first offset boundary and second offset boundary having the same offset distance.

19. The memory structure as described in claim 17, characterized in that, Also includes: A second dielectric layer located within the first opening and the second opening; A contact opening is located within a first dielectric layer and a second dielectric layer on the contact area. The bottom of the contact opening exposes the control gate layer surface of a plurality of composite structures on the contact area. The contact opening has a contact projection on the substrate surface, and a plurality of the first offset boundaries are within the range of the contact projection.

20. The memory structure as described in claim 19, characterized in that, Also includes: The contact layer is located on the surface of the control gate layer of the several composite structures exposed by the contact opening.

21. The memory structure as described in claim 20, characterized in that, Also includes: A third dielectric layer located within the contact opening; a plurality of conductive structures located within the third dielectric layer, the bottom surface of the conductive structures being in contact with the surface of the contact layer, the conductive structures having a third projection on the surface of the substrate, and a portion of the boundary of the third projection being adjacent to or coinciding with the first offset boundary.

22. The memory structure as described in claim 15, characterized in that, The control gate layer includes: a fourth dielectric film, a fifth dielectric film located on the surface of the fourth dielectric film, a sixth dielectric film located on the surface of the fifth dielectric film, and a control gate located on the surface of the sixth dielectric film; and the word line opening includes: a word line opening located in the sixth dielectric film, the control gate, and the first dielectric layer; and a word line opening located in the fifth dielectric film, the fourth dielectric film, and the floating gate layer, wherein the word line opening and the word line opening are connected, and the bottom of the word line opening exposes the surface of the substrate.

23. The memory structure as described in claim 22, characterized in that, Also includes: The first sidewall gate dielectric layer located on the sidewall surface of the opening on the word line; The second sidewall gate dielectric layer is located on the sidewall surface of the first sidewall gate dielectric layer and the opening below the word line.

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