Method of forming a semiconductor device and semiconductor device

Abstract

In an embodiment, a method of forming a semiconductor device includes depositing a protective layer over a source / drain region and a gate mask, the gate mask disposed over a gate structure, the gate structure disposed over a channel region of a substrate, the channel region contiguous to the source / drain region; etching an opening through the protective layer, the opening exposing the source / drain region; depositing a metal in the opening and on the protective layer; annealing the metal to form a metal-semiconductor alloy region on the source / drain region; and removing residue of the metal from the opening using a cleaning process, the protective layer covering the gate mask during the cleaning process. According to other embodiments of the application, a semiconductor device is also provided.

Description

Technical Field

[0001] Embodiments of this application relate to methods for forming semiconductor devices and semiconductor devices themselves. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor material layer on a semiconductor substrate, and then using photolithography to pattern the material layers to form circuit components and elements on these material layers.

[0003] The semiconductor industry is constantly increasing the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the size of the smallest components, thereby enabling more components to be integrated into a specific area. However, as the size of the smallest components decreases, additional problems arise that need to be addressed. Summary of the Invention

[0004] According to embodiments of this application, a method for forming a semiconductor device is provided, comprising: depositing a protective layer on a source / drain region and a gate mask, the gate mask being disposed on a gate structure, the gate structure being disposed on a channel region of a substrate, the channel region being adjacent to the source / drain region; etching an opening through the protective layer, the opening exposing the source / drain region; depositing metal in the opening and on the protective layer; annealing the metal to form a metal-semiconductor alloy region on the source / drain region; and removing metal residue from the opening using a cleaning process, the protective layer covering the gate mask during the cleaning process.

[0005] According to another embodiment of this application, a method for forming a semiconductor device is provided, comprising: depositing a contact etch stop layer (CESL) on a source / drain region; forming an interlayer dielectric (ILD) on the contact etch stop layer; forming a contact opening through the interlayer dielectric and the contact etch stop layer, the contact opening exposing the top surface of the source / drain region and the sidewall of the contact etch stop layer; after forming the contact opening, extending the contact opening by etching the interlayer dielectric using an isotropic etching process; and forming source / drain contacts in the contact opening.

[0006] According to another embodiment of this application, a semiconductor device is provided, comprising: a gate structure on a channel region of a substrate; a gate mask on the gate structure; a source / drain region adjacent to the channel region; a source / drain contact connected to the source / drain region, the source / drain contact having an upper portion with curved sidewalls and a lower portion with straight sidewalls; and a contact spacer surrounding the source / drain contact, the contact spacer contacting a sidewall of the gate mask.

[0007] Embodiments of this application relate to transistor source / drain contacts and methods for forming them. Attached Figure Description

[0008] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0009] Figure 1 An example of a fin field-effect transistor (FinFET) according to some embodiments is shown in a three-dimensional view.

[0010] Figure 2-Figure 21B This is a view of an intermediate stage in the fabrication of a FinFET according to some embodiments.

[0011] Figures 22A-22B This is a view of a FinFET according to some embodiments. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0014] According to various embodiments, the contact openings to the source / drain regions are initially formed with a smaller width and then expanded to a larger width in a separate etching process. This allows for better control of the contact opening width, thereby preventing short circuits between adjacent source / drain regions. Additionally, a protective layer is formed in the contact openings and serves to protect surrounding components during the formation of the metal-semiconductor alloy regions on the source / drain regions. This can thus improve manufacturing yield.

[0015] Figure 1 An example of a FinFET (Fin Field-Effect Transistor) according to some embodiments is shown. Figure 1 This is a three-dimensional view, in which some components of the FinFET are omitted for clarity. The FinFET includes fins 52 extending from a substrate 50 (e.g., a semiconductor substrate), which act as channel regions 58 of the FinFET. Isolation regions 56, such as shallow trench isolation (STI) regions, are disposed between adjacent fins 52, and the fins 52 may protrude above and between adjacent isolation regions 56. Although the isolation regions 56 are described / shown as separate from the substrate 50, as used herein, the term "substrate" may refer to a single semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Additionally, although the bottom portion of the fin 52 is shown as a single continuous material with the substrate 50, the bottom portion of the fin 52 and / or the substrate 50 may comprise a single material or multiple materials. In this document, fin 52 refers to the portion extending between adjacent isolation regions 56.

[0016] Gate dielectric 112 runs along the sidewall of fin 52 and is above the top surface of fin 52. Gate electrode 114 is above gate dielectric 112. Epitaxial source / drain regions 88 are disposed on opposite sides of fin 52 relative to gate dielectric 112 and gate electrode 114. Epitaxial source / drain regions 88 can be shared between individual fins 52. For example, adjacent epitaxial source / drain regions 88 can be electrically connected, for example by epitaxial growth coalescing epitaxial source / drain regions 88, or by coupling epitaxial source / drain regions 88 to the same source / drain contact.

[0017] Figure 1 Reference cross sections used in the following figures are also shown. Cross section A-A' is along the longitudinal axis of fin 52 and, for example, in the direction of current flow between the epitaxial source / drain regions 88 of the FinFET. Cross section B-B' is perpendicular to cross section A-A' and extends through the epitaxial source / drain regions 88 of the FinFET. For clarity, subsequent figures refer to these reference cross sections.

[0018] Some of the embodiments discussed herein are presented in the context of FinFETs formed using a post-gate process. In other embodiments, a pre-gate process may be used. Similarly, some embodiments are contemplated for use in planar devices, such as planar FETs.

[0019] Figure 2-Figure 21B This is a view of an intermediate stage in the fabrication of a FinFET according to some embodiments. Figure 2 , 3 , and 4 are shown to be related to Figure 1 A 3D view similar to a 3D view. Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A and Figure 21A Is along with Figure 1 The cross-sectional view is shown in the reference section A-A'. Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B and Figure 21B Is along with Figure 1 The cross-sectional view is shown in the reference section B-B'.

[0020] exist Figure 2In this embodiment, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., and may be doped (e.g., with p-type or n-type impurities) or undoped. The substrate 50 may be a wafer such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on the substrate (typically a silicon substrate or a glass substrate). Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or combinations thereof; and so on.

[0021] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device such as an NMOS transistor, for example, an n-type FinFET, and the p-type region 50P can be used to form a p-type device such as a PMOS transistor, for example, a p-type FinFET. The n-type region 50N may be physically separated from the p-type region 50P (not shown separately), and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P may be provided.

[0022] Fins 52 are formed in substrate 50. Fins 52 are semiconductor strips. Fins 52 can be formed in substrate 50 by etching trenches in substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral atom beam etching (NBE), or combinations thereof. The etching process can be anisotropic.

[0023] Fin 52 can be patterned using any suitable method. For example, one or more photolithography processes, including dual patterning or multiple patterning processes, can be used to pattern fin 52. Typically, dual patterning or multiple patterning processes combine photolithography with a self-aligned process, thereby allowing the creation of patterns with, for example, a pitch smaller than that that could be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used as a mask to pattern fin 52. In some embodiments, a mask (or other layer) may be retained on fin 52.

[0024] An STI region 56 is formed above the substrate 50 and between adjacent fins 52. The STI region 56 is disposed around the lower portion of the fin 52 such that the upper portion of the fin 52 protrudes between adjacent STI regions 56. In other words, the upper portion of the fin 52 extends above the top surface of the STI region 56. The STI region 56 separates components of adjacent devices.

[0025] The STI region 56 can be formed by any suitable method. For example, an insulating material can be formed over the substrate 50 and between adjacent fins 52. The insulating material can be an oxide (such as silicon oxide), a nitride (such as silicon nitride), or a combination thereof, which can be formed by a chemical vapor deposition (CVD) process (e.g., high-density plasma CVD (HDP-CVD), flowable chemical vapor deposition (FCVD), or a combination thereof). Other insulating materials formed by any acceptable process can be used. In some embodiments, the insulating material is silicon oxide formed by FCVD. Once the insulating material is formed, an annealing process can be performed. Although each of the STI regions 56 is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a pad (not shown separately) can be formed first along the surfaces of the substrate 50 and the fins 52. Subsequently, a filler material, such as those previously described, can be formed over the pad. In embodiments, the insulating material is formed such that excess insulating material covers the fins 52. The insulating material is then subjected to a removal process to remove excess insulating material from the fins 52. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, and combinations thereof can be used. In embodiments where the mask remains on fin 52, a planarization process can expose or remove the mask. After the planarization process, the insulating material and the top surface of the mask (if present) or fin 52 are coplanar (within process variations). Therefore, the top surface of the mask (if present) or fin 52 is exposed through the insulating material. In the illustrated embodiment, no mask remains on fin 52. The insulating material is then recessed to form STI region 56. The insulating material is recessed such that the upper portion of fin 52 protrudes between adjacent portions of the insulating material. Furthermore, the top surface of STI region 56 may have a flat surface, a convex surface, a concave surface (e.g., recessed), or a combination thereof, as shown. The top surface of STI region 56 can be formed as flat, raised, and / or recessed by appropriate etching. Any acceptable etching process (e.g., an etching process selective to the material of the insulating material (e.g., selectively etching the insulating material of STI region 56 at a rate faster than the material of fin 52)) can be used to recess the insulating material. For example, dilute hydrofluoric acid (dHF) can be used for oxide removal.

[0026] The previously described process is merely one example of how the fin 52 and STI region 56 can be formed. In some embodiments, the fin 52 can be formed using a mask and epitaxial growth process. For example, a dielectric layer can be formed above the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. The epitaxial structure can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structure protrudes from the dielectric layer to form the fin 52. In some embodiments where the epitaxial structure is epitaxially grown, the material for epitaxial growth can be in-situ doped during growth, which can avoid pre- and / or subsequent implantation, although in-situ doping and implantation doping can be used together.

[0027] Furthermore, it may be advantageous to epitaxially grow a material different from that in the p-type region 50P in the n-type region 50N. In various embodiments, the upper portion of the fin 52 may be made of silicon-germanium (Si). x Ge 1-x (where x can be in the range of 0 to 1), silicon carbide, pure germanium or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, materials that can be used to form III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0028] Furthermore, suitable wells (not shown separately) may be formed in the fin 52 and / or the substrate 50. The wells may have a conductivity type opposite to that of the source / drain regions subsequently formed in each of the n-type region 50N and the p-type region 50P. In some embodiments, a p-type well is formed in the n-type region 50N, and an n-type well is formed in the p-type region 50P. In some embodiments, a p-type well or an n-type well is formed in both the n-type region 50N and the p-type region 50P.

[0029] In embodiments with different well types, different implantation steps for the n-type region 50N and the p-type region 50P can be implemented using a mask such as photoresist (not shown separately). For example, photoresist can be formed over fin 52 and STI region 56 in the n-type region 50N. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed using a spin coating technique, and patterning can be performed using an acceptable photolithography technique. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist can be used as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurities can be phosphorus, arsenic, antimony, etc., implanted in the region, with a concentration of 10. 13 cm -3 Up to 10 14 cm -3 Within the range. After implantation, the photoresist is removed, such as by any acceptable ashing process.

[0030] After or before implantation of the p-type region 50P, a mask, such as photoresist (not shown separately), is formed over the fins 52 and STI region 56 in the p-type region 50P. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating, and patterning can be performed using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, etc., implanted in the region, with a concentration of 10. 13 cm -3 Up to 10 14 cm -3 Within the range. After implantation, the photoresist is removed, such as by any acceptable ashing process.

[0031] Following implantation in the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments where epitaxial growth of the epitaxial structure is used for fin 52, the grown material can be doped in situ during growth, which can avoid implantation, although in-situ doping and implantation doping can be used together.

[0032] exist Figure 3 In this process, a dummy dielectric layer 62 is formed on fin 52. The dummy dielectric layer 62 can be formed of a dielectric material such as silicon oxide, silicon nitride, or combinations thereof, which can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 64 is formed above the dummy dielectric layer 62, and a mask layer 66 is formed above the dummy gate layer 64. The dummy gate layer 64 can be deposited above the dummy dielectric layer 62 and planarized, for example, by CMP. The mask layer 66 can be deposited above the dummy gate layer 64. The dummy gate layer 64 can be formed of a conductive or non-conductive material, such as amorphous silicon, polysilicon, poly-SiGe, metal, metal nitride, metal silicide, metal oxide, etc., which can be deposited by physical vapor deposition (PVD), CVD, etc. The dummy gate layer 64 can be formed of a material with high etch selectivity to the etching of insulating materials, such as STI region 56 and / or dummy dielectric layer 62. The mask layer 66 can be formed of a dielectric material such as silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 64 and a single mask layer 66 are formed across the n-type region 50N and the p-type region 50P. In the illustrated embodiment, the dummy dielectric layer 62 covers the fin 52 and the STI region 56, such that the dummy dielectric layer 62 extends over the STI region 56 and between the dummy gate layer 64 and the STI region 56. In another embodiment, the dummy dielectric layer 62 only covers the fin 52.

[0033] exist Figure 4In the process, a mask layer 66 is patterned using acceptable photolithography and etching techniques to form a mask 76. The pattern of mask 76 is then transferred to a dummy gate layer 64 using any acceptable etching technique to form a dummy gate 74. The pattern of mask 76 may optionally be further transferred to a dummy dielectric layer 62 using any acceptable etching technique to form a dummy dielectric 72. The dummy gate 74 covers the corresponding channel region 58 of the fin 52. The pattern of mask 76 can be used to physically separate adjacent dummy gates 74. The dummy gate 74 may also have a length direction substantially perpendicular to the longitudinal direction of the fin 52 (within the range of process variations). Mask 76 may be removed during the patterning of the dummy gate 74 or during subsequent processing.

[0034] Figures 5A-21B Various additional steps in the manufacture of the embodiment device are shown. Figures 5A-21B Components of either n-type region 50N or p-type region 50P are shown. For example, the structure shown can be applied to both n-type region 50N and p-type region 50P. The structural differences between n-type region 50N and p-type region 50P (if any) are described in the text accompanying each figure.

[0035] exist Figures 5A-5B In the diagram, above fin 52, gate spacers 82 are formed on the exposed sidewalls of mask 76 (if present), dummy gate 74, and dummy dielectric 72. Gate spacers 82 can be formed by conformally depositing one or more dielectric materials and subsequently etching the dielectric material. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., which can be formed by conformal deposition processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), etc. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, each gate spacer 82 comprises multiple layers, such as a first spacer layer 80A and a second spacer layer 80B. In some embodiments, the first spacer layer 80A and the second spacer layer 80B are made of silicon carbonitride (e.g., SiO2). x N y C 1-x-yA first spacer layer 80A is formed, wherein x and y are in the range of 0 to 1, and the first spacer layer 80A is formed of silicon carbide composition similar to or different from that of the second spacer layer 80B. Any acceptable etching process, such as dry etching, wet etching, or combinations thereof, can be performed to pattern the dielectric material. The etching can be anisotropic. During etching, the dielectric material has portions remaining on the sidewalls of the dummy gate 74 (thus forming the gate spacer 82). In some embodiments, the etching used to form the gate spacer 82 is adjusted such that the dielectric material also has portions remaining on the sidewalls of the fin 52 during etching (thus forming the fin spacer 84). After etching, the fin spacer 84 (if present) and the gate spacer 82 may have straight sidewalls (as shown) or may have curved sidewalls (not shown separately).

[0036] Additionally, implantation can be performed to form lightly doped source / drain (LDD) regions (not shown separately). In embodiments with different device types, similar to the implantation previously described for a well, a mask such as photoresist (not shown separately) can be formed over the n-type region 50N while exposing the p-type region 50P, and an appropriate type (e.g., p-type) impurity can be implanted into the fin 52 exposed in the p-type region 50P. The mask can then be removed. Subsequently, a mask such as photoresist (not shown separately) can be formed over the p-type region 50P while exposing the n-type region 50N, and an appropriate type of impurity (e.g., n-type) can be implanted into the fin 52 exposed in the n-type region 50N. The mask can then be removed. The n-type impurity can be any of the previously described n-type impurities, and the p-type impurity can be any of the previously described p-type impurities. During implantation, the channel region 58 remains covered by the dummy gate 74 such that the channel region 58 remains substantially free of impurities implanted to form the LDD region. The impurity concentration of the LDD region can be 10. 15 cm -3 Up to 10 19 cm -3 Within a certain range. Annealing can be used to repair injected damage and reactivate injected impurities.

[0037] It should be noted that the previously disclosed content generally describes a process for forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different step sequences can be used, additional spacers can be formed and removed, and / or similar methods can be employed. Furthermore, different structures and steps can be used to form n-type and p-type devices.

[0038] exist Figures 6A-6BIn the illustrated embodiment, a source / drain recess 86 is formed in the fin 52. The source / drain recess 86 extends into the fin 52. The source / drain recess 86 may also extend into the substrate 50. In various embodiments, the source / drain recess 86 may extend to the top surface of the substrate 50 without etching the substrate 50; the fin 52 may be etched such that the bottom surface of the source / drain recess 86 is disposed below the top surface of the STI region 56; and so on. The source / drain recess 86 can be formed by etching the fin 52 using an anisotropic etching process (e.g., RIE, NBE, etc.). During the etching process used to form the source / drain recess 86, the gate spacer 82 and the dummy gate 74 jointly mask a portion of the fin 52. After the source / drain recess 86 reaches the desired depth, a timed etching process can be used to stop the etching of the source / drain recess 86. The fin spacer 84 (if present) may be etched during or after the etching of the source / drain recess 86, such that the height of the fin spacer 84 is reduced and the fin spacer 84 covers a portion of the sidewall of the fin 52. The size and dimensions of the source / drain region subsequently formed in the source / drain recess 86 can be controlled by adjusting the height of the fin spacer 84.

[0039] exist Figures 7A-7B In the fin 52, epitaxial source / drain regions 88 are formed in source / drain recesses 86. Therefore, the epitaxial source / drain regions 88 are disposed in the fin 52 such that each dummy gate 74 (and corresponding channel region 58) is between corresponding adjacent pairs of epitaxial source / drain regions 88. Thus, the epitaxial source / drain regions 88 are adjacent to the channel regions 58. In some embodiments, gate spacers 82 are used to separate the epitaxial source / drain regions 88 from the dummy gates 74 by an appropriate lateral distance such that the epitaxial source / drain regions 88 are not short-circuited with the gate of the subsequently formed FinFET. The material of the epitaxial source / drain regions 88 can be selected to apply stress in the respective channel regions 58, thereby improving performance.

[0040] The epitaxial source / drain region 88 in the n-type region 50N can be formed by masking the p-type region 50P. Then, the epitaxial source / drain region 88 in the n-type region 50N is epitaxially grown in the source / drain trench 86 in the n-type region 50N. The epitaxial source / drain region 88 can include any acceptable material suitable for an n-type device. For example, if the fin 52 is silicon, the epitaxial source / drain region 88 in the n-type region 50N can include a material for applying tensile strain to the channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 88 in the n-type region 50N can be referred to as an "n-type source / drain region". The epitaxial source / drain region 88 in the n-type region 50N can have surfaces protruding from various surfaces of the fin 52 and can have facets.

[0041] The epitaxial source / drain region 88 in the p-type region 50P can be formed by masking the n-type region 50N. Then, the epitaxial source / drain region 88 in the p-type region 50P is epitaxially grown in the source / drain trench 86 in the p-type region 50P. The epitaxial source / drain region 88 can include any acceptable material suitable for a p-type device. For example, if the fin 52 is silicon, the epitaxial source / drain region 88 in the p-type region 50P can include a material on which compressive strain is applied to the channel region 58, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 88 in the p-type region 50P can be referred to as a "p-type source / drain region". The epitaxial source / drain region 88 in the p-type region 50P can have surfaces protruding from various surfaces of the fin 52 and can have facets.

[0042] Impurities are implanted into the epitaxial source / drain regions 88 and / or fins 52 to form the source / drain regions, similar to the previously described process for forming LDD regions, followed by annealing. The impurity concentration in the source / drain regions can be up to 10. 19 cm -3 Up to 10 21 cm -3 Within the range. The n-type and / or p-type impurities used for the source / drain regions can be any impurities previously described. In some embodiments, the epitaxial source / drain regions 88 can be doped in situ during growth.

[0043] As a result of the epitaxial process used to form the epitaxial source / drain regions 88, the upper surface of the epitaxial source / drain regions has facets that extend laterally outward beyond the sidewalls of the fins 52. In some embodiments, these facets merge adjacent epitaxial source / drain regions 88, such as... Figure 7B As shown. In some embodiments, adjacent epitaxial source / drain regions 88 remain separated (not shown separately) after the epitaxial process is completed. In the illustrated embodiment, fin spacers 84 are formed to cover a portion of the sidewall of the fin 52 extending over the STI region 56, thereby blocking epitaxial growth. In another embodiment, the spacer etching used to form the gate spacer 82 is adjusted to not form the fin spacer 84, so as to allow the epitaxial source / drain regions 88 to extend to the surface of the STI region 56.

[0044] The epitaxial source / drain region 88 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 88 may each include a pad layer 88A, a main layer 88B, and a finishing layer 88C (or more generally, a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer). The epitaxial source / drain region 88 may use any number of semiconductor material layers. The pad layer 88A, the main layer 88B, and the finishing layer 88C may be formed of different semiconductor materials and may be doped with different impurity concentrations. In some embodiments, the main layer 88B has a higher impurity concentration than the finishing layer 88C, and the finishing layer 88C has a higher impurity concentration than the pad layer 88A. In embodiments where the epitaxial source / drain region 88 includes three semiconductor material layers, the pad layer 88A may be grown in the source / drain trench 86, the main layer 88B may be grown on the pad layer 88A, and the finishing layer 88C may be grown on the main layer 88B. Forming a pad layer 88A with a lower concentration of impurities than the main layer 88B increases adhesion in the source / drain trench 86, and forming a finishing layer 88C with a lower concentration of impurities than the main layer 88B reduces the outward diffusion of dopants from the main layer 88B during subsequent processing.

[0045] exist Figures 8A-8B In this configuration, a first interlayer dielectric (ILD) 94 is deposited over the epitaxial source / drain region 88, the gate spacer 82, and the mask 76 (if present) or dummy gate 74. The first ILD 94 can be formed of a dielectric material, which can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), FCVD, etc. Acceptable dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used.

[0046] In some embodiments, a contact etch stop layer (CESL) 92 is formed between the first ILD 94 and the epitaxial source / drain region 88, the gate spacer 82, and the mask 76 (if present) or dummy gate 74. The CESL 92 may be formed of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which exhibits high etch selectivity for etching the first ILD 94. The CESL 92 may be formed by any suitable method such as CVD, ALD, etc.

[0047] exist Figures 9A-9BIn the planarization process, a removal process is performed to make the top surface of the first ILD 94 flush with the top surface of the mask 76 (if present) or the dummy gate 74. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), etch-back process, or a combination thereof can be used. The planarization process may also remove the mask 76 on the dummy gate 74, as well as portions of the gate spacer 82 along the sidewalls of the mask 76. After the planarization process, the top surfaces of the first ILD 94, CESL 92, gate spacer 82, and mask 76 (if present) or the dummy gate 74 are coplanar (within process variations). Therefore, the top surface of mask 76 (if present) or the dummy gate 74 is exposed through the first ILD 94. In the illustrated embodiment, mask 76 is retained, and the planarization process makes the top surface of the first ILD 94 flush with the top surface of mask 76.

[0048] exist Figures 10A-10B In the etching process, the mask 76 (if present) and the dummy gate 74 are removed to form a recess 96. A portion of the dummy dielectric 72 in the recess 96 may also be removed. In some embodiments, only the dummy gate 74 is removed, while the dummy dielectric 72 remains and is exposed by the recess 96. In some embodiments, the dummy dielectric 72 is removed from the recess 96 in a first region of the die (e.g., a core logic region) and retained in the recess 96 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gate 74 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 74 at a rate faster than etching the first ILD 94 or the gate spacer 82. During removal, the dummy dielectric 72 may be used as an etch stop layer while the dummy gate 74 is being etched. The dummy dielectric 72 is then optionally removed after the dummy gate 74 has been removed. Each recess 96 exposes and / or covers the channel region 58 of the corresponding fin 52.

[0049] exist Figures 11A-11B In the trench 96, a gate dielectric layer 102 is formed. A gate electrode layer 104 is formed on the gate dielectric layer 102. The gate dielectric layer 102 and the gate electrode layer 104 are layers used to replace the gate, and each extends along the sidewall of the channel region 58 and above the top surface.

[0050] A gate dielectric layer 102 is disposed on the sidewalls and / or top surface of the fin 52 and on the sidewalls of the gate spacer 82. The gate dielectric layer 102 may also be formed on the top surface of the first ILD 94 and the gate spacer 82. The gate dielectric layer 102 may comprise oxides (such as silicon oxide or metal oxides), silicates (such as metal silicates), combinations thereof, multilayers thereof, etc. The gate dielectric layer 102 may comprise high-k dielectric materials (e.g., dielectric materials with a k value greater than about 7.0), such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Methods for forming the gate dielectric layer 102 may include molecular beam deposition (MBD), ALD, PECVD, etc. In embodiments where a portion of the dummy dielectric 72 is retained in the recess 96, the gate dielectric layer 102 comprises the material of the dummy dielectric 72 (e.g., silicon oxide). Although a single-layer gate dielectric layer 102 is shown, the gate dielectric layer 102 may comprise any number of interface layers and any number of main layers. For example, gate dielectric layer 102 may include an interface layer and an upper high-k dielectric layer.

[0051] The gate electrode layer 104 may include metallic materials such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, tungsten, cobalt, ruthenium, aluminum, combinations thereof, or multiple layers thereof. Although a single-layer gate electrode layer 104 is shown, the gate electrode layer 104 may include any number of work function tuning layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0052] The formation of the gate dielectric layer 102 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 102 in each region is formed of the same material, and the formation of the gate electrode layer 104 can occur simultaneously, such that the gate electrode layer 104 in each region is formed of the same material. In some embodiments, the gate dielectric layer 102 in each region can be formed by different processes, such that the gate dielectric layer 102 can be made of different materials and / or have different numbers of layers, and / or the gate electrode layer 104 in each region can be formed by different processes, such that the gate electrode layer 104 can be made of different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0053] exist Figures 12A-12BIn this process, a removal process is performed to remove excess material from the gate dielectric layer 102 and the gate electrode layer 104 above the top surfaces of the first ILD 94, CESL 92, and gate spacer 82, thereby forming the gate dielectric 112 and the gate electrode 114. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof can be used. During planarization, the gate dielectric layer 102 has a portion remaining in the recess 96 (thus forming the gate dielectric 112). During planarization, the gate electrode layer 104 has a portion remaining in the recess 96 (thus forming the gate electrode 114). The top surfaces of the gate spacer 82, CESL 92, first ILD 94, gate dielectric 112, and gate electrode 114 are coplanar (within process variations). The gate dielectric 112 and gate electrode 114 form the replacement gate of the resulting FinFET. Each pair of gate dielectrics 112 and gate electrodes 114 may be collectively referred to as the "gate structure". Each gate structure extends along the top surface, sidewalls, and bottom surface of the channel region 58 of the fin 52.

[0054] exist Figures 13A-13B In this configuration, a gate mask 116 is formed over the gate structure (including the gate dielectric 112 and the gate electrode 114) and an optional gate spacer 82. The gate mask 116 is formed from one or more dielectric materials with high etch selectivity for etching the first ILD 94. Acceptable dielectric materials may include silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, etc., which can be formed by conformal deposition processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), etc. Other insulating materials formed by any acceptable process may be used.

[0055] As an example of forming the gate mask 116, any acceptable etching process can be used to recess the gate structure (including the gate dielectric 112 and the gate electrode 114) and the optional gate spacer 82. In the illustrated embodiment, the gate spacer 82 and the gate structure are recessed to the same depth. In another embodiment, the gate structure is recessed to a greater depth than the gate spacer 82. In yet another embodiment, the gate structure is recessed, but the gate spacer 82 is not recessed. The dielectric material is then conformally deposited in the recess and may also be formed on the top surface of the first ILD 94. A removal process is performed to remove excess dielectric material above the top surface of the first ILD 94, thereby forming the gate mask 116. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof can be used. When planarized, the dielectric material has a portion remaining in the recess (thus forming the gate mask 116). Gate contacts are then formed to contact the top surface of the gate electrode 114 through the gate mask 116.

[0056] exist Figures 14A-14B In this process, a contact opening 122 is formed through the first ILD 94 and CESL 92. The contact opening 122 is a source / drain contact opening formed by a self-aligned contact (SAC) process, ensuring that virtually no residue of the first ILD 94 remains in the corner region 122C of the contact opening 122. The corner region 122C of the contact opening 122 is... Figure 14A The corner in the cross section is defined by the sidewall of CESL 92 and the top surface of the epitaxial source / drain region 88.

[0057] As an example of forming the contact opening 122, a contact mask 124 may be formed over the first ILD 94 and the gate mask 116. The contact mask 124 is patterned into a slot opening 126 having a pattern of the contact opening 122. The contact mask 124 may be, for example, a photoresist, such as a single-layer photoresist, a double-layer photoresist, a triple-layer photoresist, etc., which may be patterned using an acceptable photolithography technique to form the slot opening 126. Other types of masks formed by any acceptable process may be used. The slot opening 126 is a strip extending in a longitudinal direction parallel to the fin 52, overlapping the first ILD 94 and the gate mask 116. The contact mask 124 may then be used as an etch mask and CESL 92 as an etch stop layer to etch the first ILD 94. The etching may be any acceptable etch process, such as an etch process that is selective to the material of the first ILD 94 (e.g., selectively etching the material of the first ILD 94 at a faster rate than the materials of CESL 92 and the gate mask 116). The etching process can be anisotropic. The portion of the first ILD 94 not covered by the contact mask 124 (e.g., exposed by the trench opening 126) is thus etched to form the contact opening 122. The contact opening 122 is then extended through CESL 92 by any acceptable etching process to expose the epitaxial source / drain region 88. After the etching process, the contact mask 124 is removed, for example, by any acceptable ashing process.

[0058] Depending on the selectivity of the etching process used to form the contact opening 122, some loss may occur in CESL 92 and / or the gate mask 116. (See reference) Figure 14A The contact opening 122 may have a funnel shape, with the upper portion of the contact opening 122 having curved sidewalls (e.g., tapered sidewalls) and the lower portion having substantially straight sidewalls (e.g., non-tapered sidewalls). The dimensions of CESL 92 and / or gate mask 116 may be reduced. Specifically, the upper portions of gate mask 116 and CESL 92 may have reduced widths, such that the upper portions of gate mask 116 and CESL 92 have curved sidewalls, and the lower portions of gate mask 116 and CESL 92 have substantially straight sidewalls. Furthermore, gate mask 116 and CESL 92 may have reduced heights, and in fact, the top surface of CESL 92 may be recessed below the top surface of gate mask 116, thereby exposing the curved sidewalls of gate mask 116.

[0059] exist Figures 15A-15BIn this process, the contact opening 122 is extended to expand the bonding window of the source / drain contacts that will subsequently be formed in the contact opening 122. For example, before extension, the contact opening 122 may have an initial width in the range of 10 nm to 100 nm, and after extension, the contact opening 122 may have a final width in the range of 11 nm to 105 nm, wherein the final width is 1% to 5% larger than the initial width. Any acceptable etching process can be used to extend the contact opening 122, such as an etching process that is selective to the material of the first ILD 94 (e.g., selectively etching the material of the first ILD 94 at a faster rate than the material of the gate mask 116). The etching process can be isotropic, such that the height of the first ILD 94 is reduced, and the corners of the first ILD 94 are rounded by etching. For example, before etching, the first ILD 94 may have an initial height in the range of 40 nm to 80 nm, and after etching, the first ILD 94 may have a final height in the range of 20 nm to 60 nm, wherein the final height is 25% to 50% smaller than the initial height. The contact opening 122 may also be extended by CESL 92.

[0060] In some embodiments, the etching process is dry etching performed without plasma. For example, when the first ILD 94 is formed of silicon oxide, dry etching can be performed using an etching gas solution comprising hydrogen fluoride (HF) and optionally ammonia (NH3). The etching gas solution can flow through the first ILD 94 and contact opening 122 without generating plasma. The inclusion of ammonia (NH3) in the etching gas solution is optional and includes a reduction in the activation energy of the reaction between the etching gas solution and the material of the first ILD 94, thereby allowing etching to be performed at low temperatures. In some embodiments, dry etching is performed at temperatures not lower than room temperature. For example, when the etching gas solution does not include ammonia (NH3), dry etching can be performed at temperatures in the range of 20°C to 40°C, and when the etching gas solution includes ammonia (NH3), dry etching can be performed at room temperature (e.g., temperatures in the range of 20°C to 40°C). The reaction between the etching gas solution and the material of the first ILD 94 is exothermic, and therefore performing the reaction at low temperatures can improve the efficiency of the reaction. In embodiments where the etching gas solution includes hydrogen fluoride (HF) and ammonia (NH3), the reaction between the etching gas solution and the material of the first ILD 94 includes two diffusions (e.g., gas-phase diffusion and surface diffusion) and two adsorptions (e.g., physisorption and chemisorption), and therefore the reaction can have a growth period that increases the duration of dry etching. For example, dry etching can be performed for a duration of 3 to 20 seconds. Dry etching converts the material of the first ILD 94 into one or more byproducts. Byproducts may include gas-phase byproducts (e.g., silicon tetrafluoride) and / or solid-phase byproducts (e.g., ammonium fluorosilicate). After dry etching, heat treatment can be performed at sufficiently high temperatures and durations to sublimate the solid-phase byproducts and generate additional gas-phase byproducts. For example, heat treatment can be performed at temperatures in the range of 100°C to 180°C for a duration in the range of 60 to 240 seconds. Heat treatment can be performed at temperatures higher than those of dry etching, particularly in embodiments where the etching gas solution includes ammonia (NH3). Once the solid-phase byproducts sublimate into gaseous byproducts, they can be removed from the contact opening 122 via, for example, a vacuum. In some embodiments, the etching process includes multiple cycles of dry etching and heat treatment. These cycles can be performed until the contact opening 122 expands as required. For example, 1 to 10 cycles of dry etching and heat treatment can be performed.

[0061] As described above, the final width of the contact opening 122 is greater than the initial width of the contact opening 122. An isotropic etching process (for...) is used to expand the contact opening 122. Figures 15A-15B (Description) can be compared to the anisotropic etching process used for initially forming the contact opening 122 (for...) Figures 14A-14B(Description) is more ultimately controlled. Initially forming the contact openings 122 with a smaller width and then expanding them to a larger width using a highly controllable etching process avoids short circuits between adjacent epitaxial source / drain regions 88, compared to initially forming the contact openings 122 with a larger width. Furthermore, the isotropic etching process used to expand the contact openings 122 is selective for the first ILD 94, so that the gate mask 116 is essentially not etched by the etching process. Thus, Figure 14B The width of the contact opening 122 in the cross-section increases, but Figure 14A The width of the contact opening 122 in the cross-section remains substantially constant. Therefore, short circuits between the subsequently formed contacts and, for example, the gate electrode 114 can be avoided.

[0062] exist Figures 16A-16B In this process, a protective layer 132 is conformally deposited in the contact opening 122 and on the gate mask 116. The protective layer 132 is disposed on the sidewalls and / or top surface of the epitaxial source / drain region 88, CESL 92, first ILD 94, and gate mask 116. Note that the protective layer 132 is formed to contact the curved sidewalls of the gate mask 116 and CESL 92, which are connected by the contact opening 122 (for initial formation of the contact opening 122). Figures 14A-14B The etch process described above exposes the protective layer 132. The protective layer 132 is formed from one or more dielectric materials with high etch selectivity for etching the epitaxial source / drain regions 88. Acceptable dielectric materials may include silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, etc., which can be formed by conformal deposition processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, the protective layer 132 is formed from silicon nitride via ALD. The protective layer 132 may be formed to a thickness in the range of 1 nm to 3 nm. Such a thickness provides sufficient protection for the underlying components during subsequent processing.

[0063] It is worth noting that the protective layer 132 is deposited in the contact opening 122 after the contact opening 122 is expanded. As described above, expanding the contact opening 122 allows for an increase in the engagement window for the subsequently formed source / drain contacts. Expanding the contact opening 122 before forming the protective layer 132 ensures that the expansion process is not blocked by the protective layer 132. Additionally, as will be described later, forming the protective layer 132 helps to prevent further expansion of the contact opening 122 during subsequent processing.

[0064] exist Figures 17A-17BIn this embodiment, contact opening 122 extends through protective layer 132 to expose epitaxial source / drain region 88. Contact opening 122 can be extended using any acceptable etching process, such as an etching process selectively etching the material of protective layer 132 (e.g., selectively etching the material of protective layer 132 at a faster rate than the material of epitaxial source / drain region 88). The etching process can be anisotropic.

[0065] In some embodiments, the contact opening 122 extends through the protective layer 132 using dry etching with carbonyl sulfide (COS). COS provides high etch selectivity between the insulating material (e.g., silicon nitride) of the protective layer 132 and the semiconductor material having a high impurity concentration. As described above, the epitaxial source / drain region 88 may include a main layer 88B and a finishing layer 88C, wherein the impurity concentration of the main layer 88B is greater than that of the finishing layer 88C. Performing dry etching with COS allows the contact opening 122 to extend through the protective layer 132 and the finishing layer 88C, such that the contact opening 122 exposes the main layer 88B without substantially etching it. The source / drain contacts subsequently formed in the contact opening 122 can thus contact the main layer 88B (e.g., a highly doped region) of the epitaxial source / drain region 88. The source / drain contacts formed to the highly doped region of the epitaxial source / drain region 88 reduce the contact resistance of the device. Furthermore, avoiding etching of the main layer 88B increases the amount of majority carriers available in the epitaxial source / drain regions 88. This can improve device performance.

[0066] In some embodiments, the contact opening 122 extends through the protective layer 132 via a self-aligned process similar to the self-aligned process described for the initial formation of the contact opening 122. For example, a mask with a slot opening pattern may be formed over the protective layer 132 and used as an etching mask to extend the contact opening 122 through the protective layer 132. Thus, the epitaxial source / drain region 88 is exposed through the protective layer 132, but most of the gate mask 116, the first ILD 94, and CESL 92 remain covered by the protective layer 132.

[0067] exist Figures 18A-18B In this context, metal-semiconductor alloy regions 134 are formed in the contact opening 122 and on portions of the epitaxial source / drain regions 88 exposed by the contact opening 122. For example, metal-semiconductor alloy regions 134 are formed when the main layer 88B exposes the epitaxial source / drain regions 88, such that they are on the main layer 88B and extend through the finishing layer 88C (see [link to article]). Figures 17A-17BThe metal-semiconductor alloy region 134 can be a silicide region formed by metal silicides (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed by metal germanides (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), or a silicon-germanium region formed by both metal silicides and metal germanides. The metal-semiconductor alloy region 134 can be formed by depositing metal 136 on the protective layer 132 and in the contact opening 122 (e.g., on the epitaxial source / drain region 88) followed by a thermal annealing process. Metal 136 can be any metal capable of reacting with the semiconductor material of the epitaxial source / drain region 88 (e.g., silicon, silicon-germanium, germanium, etc.) to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. Metal 136 can be deposited using deposition processes such as ALD, CVD, PVD, etc. Following the thermal annealing process, a cleaning process is performed to remove any residue of metal 136 from the surfaces of the metal-semiconductor alloy region 134 and the protective layer 132, for example. The cleaning process can be a wet etching using dilute hydrofluoric acid (dHF).

[0068] As described above, the protective layer 132 is patterned such that the gate mask 116, the first ILD 94, and the CESL 92 remain largely covered by the protective layer 132. Therefore, during the cleaning process used to remove residues of the metal 136, etching of the gate mask 116, the first ILD 94, and the CESL 92 can be avoided, preventing etching of the gate mask 116, the first ILD 94, or the CESL 92 from occurring. Protecting the gate mask 116, the first ILD 94, and the CESL 92 with the protective layer 132 prevents undesirable expansion of the contact opening 122 during the removal of residues of the metal 136 from the contact opening 122. This also prevents short circuits between subsequently formed contacts and, for example, the gate electrode 114.

[0069] exist Figures 19A-19B In the gate mask 116, source / drain contacts 142 are formed in contact openings 122. Source / drain contacts 142 are connected to epitaxial source / drain regions 88 and physically contact metal-semiconductor alloy regions 134. As an example of forming source / drain contacts 142, pads (not shown separately) (such as diffusion barrier layers, adhesion layers, etc.) and conductive materials may be formed in contact openings 122 (e.g., on metal-semiconductor alloy regions 134). Pads may include titanium, titanium nitride, tantalum, tantalum nitride, etc. Conductive materials may be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A removal process is performed to remove excess material from the top surface of the gate mask 116. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof may be used. The remaining pads and conductive materials form source / drain contacts 142 in contact openings 122.

[0070] Because the protective layer 132 protects the gate mask 116 and CESL 92 (for cleaning the contact opening 122) Figures 18A-18B (Description), thus avoiding losses to CESL 92 and / or gate mask 116. Reference Figure 19A The cross-section of the source / drain contact 142 can therefore have a contact opening 122 (for...). Figure 14A A funnel shape similar to that described, wherein the upper portion of the source / drain contact 142 has curved sidewalls (e.g., tapered sidewalls) and the lower portion of the source / drain contact 142 has substantially straight sidewalls (e.g., non-tapered sidewalls).

[0071] The removal process for removing excess material from the source / drain contacts 142 also removes a portion of the protective layer 132 from the top surface of the gate mask 116. The remaining protective layer 132 forms contact spacers 144 around the source / drain contacts 142 within the contact opening 122. The contact spacers 144 are curved along the upper portion of the source / drain contacts 142, while they are straight along the lower portion. Depending on the selectivity of the removal process, some loss may occur in the gate mask 116, resulting in a reduced height. In the illustrated embodiment, the contact spacers 144 extend along and physically contact the curved sidewalls of the remaining portion of the gate mask 116 and the curved sidewalls of the CESL 92. In another embodiment (described in more detail below), the height of the gate mask 116 is reduced until the top surfaces of the gate mask 116 and CESL 92 are coplanar (within a process variation), such that the contact spacer 144 is physically separated from the sidewall of the gate mask 116 by CESL 92.

[0072] exist Figures 20A-20B In this configuration, a second ILD 154 is deposited over the first ILD 94, gate mask 116, source / drain contacts 142, and contact spacers 144. In some embodiments, the second ILD 154 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 154 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., which can be deposited by any suitable method such as CVD, PECVD, etc.

[0073] In some embodiments, an etch stop layer (ESL) 152 is formed between the second ILD 154 and the first ILD 94, the gate mask 116, the source / drain contact 142, and the contact spacer 144. The ESL 152 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which has high etch selectivity for etching the second ILD 154.

[0074] exist Figures 21A-21B In this configuration, source / drain contacts 162 and gate contacts 164 are formed to contact source / drain contacts 142 and gate electrode 114, respectively. Source / drain contacts 162 are physically and electrically coupled to source / drain contacts 142. Gate contacts 164 are physically and electrically coupled to gate electrode 114.

[0075] As an example of forming source / drain contacts 162 and gate contacts 164, an opening is formed through the second ILD 154 and ESL 152. The opening can be formed using acceptable photolithography and etching techniques. A pad (not shown separately), such as a diffusion barrier layer or adhesion layer, and conductive material are formed within the opening. The pad may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP can be performed to remove excess material from the top surface of the second ILD 154. The remaining pad and conductive material form the source / drain contacts 162 and gate contacts 164 within the opening. The source / drain contacts 162 and gate contacts 164 may be formed in different processes or in the same process. Although shown to be formed with the same cross-section, it should be understood that each of the source / drain contacts 162 and the gate contact 164 may be formed with a different cross-section, which avoids short circuits in the contacts.

[0076] Figures 22A-22B This is a view of a FinFET according to some embodiments. This embodiment is similar to... Figures 21A-21B In this embodiment, the contact spacer 144 is physically separated from the sidewall of the gate mask 116 via the CESL 92. Specifically, during the removal process to remove excess material from the source / drain contacts 142, the height of the gate mask 116 is reduced until the top surfaces of the gate mask 116 and the CESL 92 are coplanar (within a process variation), causing the contact spacer 144 to be physically separated from the sidewall of the gate mask 116 via the CESL 92.

[0077] The embodiment offers advantages. Initially forming the contact opening 122 with a smaller width and then expanding it to a larger width, compared to initially forming the contact opening 122 with a larger width, avoids short circuits between adjacent epitaxial source / drain regions 88. Furthermore, forming the protective layer 132 helps protect the gate mask 116, the first ILD 94, and the CESL 92, preventing undesirable expansion of the contact opening 122 during the formation of the metal-semiconductor alloy region 134. Therefore, short circuits between the source / drain contacts 142 and adjacent conductive components are avoided. Specifically, preventing short circuits of the contact opening 122 in… Figure 18AThe expansion in the cross-section can reduce the risk of short circuits between the source / drain contact 142 and the gate electrode 114 or gate contact 164. Similarly, it avoids contact opening 122 in... Figure 18B The expansion in the cross-section reduces the risk of short circuits between adjacent source / drain contacts 142. This can thus improve manufacturing yield. Finally, etching the protective layer 132 with an etchant such as carbonyl sulfide (COS) allows the source / drain contacts 142 to form the main layer 88B (e.g., a highly doped region) to the epitaxial source / drain region 88, while avoiding etching of the main layer 88B. This can thus improve device performance.

[0078] The disclosed FinFET embodiments can also be applied to nanostructured devices, such as nanostructured (e.g., nanosheets, nanowires, all-around gates, etc.) field-effect transistors (NSFETs). In NSFET embodiments, the fins are replaced by nanostructures formed by stacking alternating layers of patterned channel layers and sacrificial layers. The dummy gate structure and source / drain regions are formed in a manner similar to the embodiments described above. After removing the dummy gate structure, the sacrificial layer may be partially or completely removed in the channel region. A replacement gate structure is formed in a manner similar to the embodiments described above, the replacement gate structure may partially or completely fill the opening left by removing the sacrificial layer, and the replacement gate structure may partially or completely surround the channel layer in the channel region of the NSFET device. ILDs and contacts to the replacement gate structure and source / drain regions may be formed in a manner similar to the embodiments described above. Nanostructured devices may be formed as disclosed in U.S. Patent Application Publication No. 2016 / 0365414, the entire contents of which are incorporated herein by reference. See U.S. Patent No. 2016 / 0365414, in one embodiment, the formation of the nanostructured device is described below. Forming a fin comprising a superlattice, the superlattice comprising alternating first and second layers; after forming the fin, selectively etching the first layer, and after selectively etching the first layer, forming a gate dielectric on the second layer; and forming a gate electrode on the gate dielectric, the first and second layers extending between a source region and a drain region. In some embodiments, the selective etching is anisotropic etching. In some embodiments, the selective etching is isotropic etching. In some embodiments, the first layer is compressively strained and the second layer is tensile strained. In some embodiments, the first layer is tensile strained and the second layer is compressively strained. In some embodiments, the method of forming a semiconductor structure further includes: forming a dummy gate stack on the superlattice; forming a dielectric around the dummy gate stack; and removing the dummy gate stack, after which selective etching is performed. In some embodiments, forming the gate dielectric on the second layer includes forming the gate dielectric at least partially between a first lateral surface and a second lateral surface of the first layer. In some embodiments, selective etching of the first layer includes selectively etching the sidewalls of the first layer on a first side of the first layer to offset inward from the sidewalls of the second layer on the first side. In some embodiments, the uppermost first layer of the first layer is interposed between the gate dielectric and the uppermost second layer of the second layer. In another embodiment, the formation of a nanostructure device is described.A fin is formed extending upward from a semiconductor substrate, wherein the fin includes: a first layer; a second layer on the first layer, wherein the first and second layers include different strain types; and a third layer on the second layer, wherein the third layer and the first layer include the same strain type; selectively etching the fin by etching the second layer at a rate different from that of the first and third layers; forming a gate dielectric over the sidewalls of the first, second, and third layers of the fin and extending continuously along the sidewalls of the first, second, and third layers of the fin; and forming a conductive gate over the gate dielectric. In some embodiments, selectively etching the fin includes selectively etching the second layer at a faster rate than that of the first and third layers. In some embodiments, selectively etching the fin includes selectively etching the second layer at a slower rate than that of the first and third layers. In some embodiments, the third layer is the uppermost semiconductor layer of the fin. In some embodiments, selectively etching the fin includes offsetting the sidewalls of the second layer from the sidewalls of the first and third layers, wherein the sidewalls of the second layer and the sidewalls of the first and third layers are disposed on the same side of the fin. In some embodiments, forming the gate dielectric includes forming the gate dielectric at least partially between the first and third layers. In some embodiments, the method of forming a semiconductor device further includes forming a dummy gate structure above and extending along the sidewalls of the channel region of the fin; replacing a first source / drain region of the fin adjacent to the dummy gate structure with an epitaxial source / drain region; forming a dielectric layer above and along the sidewalls of the epitaxial source / drain region; and removing the dummy gate structure to expose the channel region, wherein selectively etching the fin includes selectively etching the channel region of the fin after removing the dummy gate structure. In yet another embodiment, the formation of a nanostructure device is described. A superlattice extending upward from a substrate is formed, wherein the superlattice comprises alternating first and second layers with different strain types; a dummy gate structure is formed covering a first region of the superlattice, wherein a second region of the superlattice is exposed; the second region of the superlattice is replaced with a source / drain region; the dummy gate structure is removed to expose the first region of the superlattice; after removing the dummy gate structure, the first layer of the superlattice is selectively etched at a higher rate than the second layer of the superlattice; a gate dielectric is deposited over and along the sidewalls of the first region of the superlattice; and a conductive gate is formed over the gate dielectric, wherein the conductive gate is not completely separated from adjacent layers of the second layer in the first region. In some embodiments, the first layer is relaxed, tensile-strained, or compressive-strained, and the second layer is relaxed, tensile-strained, or compressive-strained. In some embodiments, selectively etching the first layer of the superlattice comprises removing the first layer of the superlattice. In some embodiments, depositing the gate dielectric comprises depositing at least a portion of the gate dielectric between consecutive second layers.

[0079] In one embodiment, a method includes: depositing a protective layer on a source / drain region and a gate mask, the gate mask being disposed on a gate structure disposed on a channel region of a substrate, the channel region adjacent to the source / drain region; etching an opening through the protective layer, the opening exposing the source / drain region; depositing metal in the opening and on the protective layer; annealing the metal to form a metal-semiconductor alloy region on the source / drain region; and removing metal residue from the opening using a cleaning process, the protective layer covering the gate mask during the cleaning process. In some embodiments of the method, the cleaning process includes wet etching using dilute hydrofluoric acid, and no etching of the gate mask occurs during the wet etching. In some embodiments of the method, the source / drain region includes a master layer and a finishing layer, the method further including: etching an opening through the finishing layer of the source / drain region, the opening exposing the master layer of the source / drain region. In some embodiments of the method, the protective layer includes silicon nitride, and etching the opening includes dry etching using carbonyl sulfide. In some embodiments of this method, no etching of the main layer of the source / drain regions occurs during dry etching. In some embodiments of this method, the protective layer has a thickness in the range of 1 nm to 3 nm. In some embodiments, the method further includes: depositing a contact etch stop layer (CESL) on the source / drain regions; forming an interlayer dielectric (ILD) on the CESL; forming a contact opening through the ILD and the CESL; and, after forming the contact opening, extending the contact opening, wherein the protective layer is deposited in the contact opening after the contact opening is extended. In some embodiments of this method, extending the contact opening includes etching the ILD with hydrogen fluoride and ammonia at room temperature.

[0080] In one embodiment, a method includes: depositing a contact etch stop layer (CESL) on a source / drain region; forming an interlayer dielectric (ILD) on the CESL; forming a contact opening through the ILD and the CESL, the contact opening exposing the top surface of the source / drain region and the sidewalls of the CESL; after forming the contact opening, extending the contact opening by etching the ILD using an isotropic etching process; and forming source / drain contacts in the contact opening. In some embodiments of the method, the isotropic etching process includes: dry etching in the contact opening with an etching gas solution, the dry etching being performed without plasma, the etching gas solution converting the ILD into solid-phase byproducts; performing heat treatment to sublimate the solid-phase byproducts into gaseous-phase byproducts; and venting the gaseous-phase byproducts from the contact opening. In some embodiments of the method, the etching gas solution includes hydrogen fluoride and ammonia, and the dry etching is performed at room temperature. In some embodiments of the method, the etching gas solution includes hydrogen fluoride, and the dry etching is performed at a temperature in the range of 20°C to 40°C. In some embodiments of the method, dry etching is performed at a first temperature, and heat treatment is performed at a second temperature, which is higher than the first temperature. In some embodiments of the method, the ILD comprises silicon oxide, and the solid-state byproduct comprises ammonium fluorosilicate. In some embodiments, the method further includes: forming a gate structure on a channel region of a substrate, the channel region adjacent to a source / drain region; forming a gate mask on the gate structure; depositing a protective layer on the gate mask and within the contact opening after extending a contact opening; extending the contact opening through the protective layer; and forming a metal-semiconductor alloy region in the contact opening while the protective layer covers the gate mask. In some embodiments of the method, forming the metal-semiconductor alloy region includes performing a cleaning process, and no etching of the gate mask occurs during the cleaning process. In some embodiments of the method, extending the contact opening through the protective layer includes etching the contact opening with carbonyl sulfide.

[0081] In one embodiment, a device includes: a gate structure on a channel region of a substrate; a gate mask on the gate structure; a source / drain region adjacent to the channel region; a source / drain contact connected to the source / drain region, the source / drain contact having an upper portion with curved sidewalls and a lower portion with straight sidewalls; and a contact spacer surrounding the source / drain contact, the contact spacer contacting a sidewall of the gate mask. In some embodiments, the device further includes: a gate spacer between the gate structure and the source / drain region; and a contact etch stop layer (CESL) between the gate spacer and the contact spacer, the CESL contacting a sidewall of the gate mask. In some embodiments, the device further includes: a metal-semiconductor alloy region between the source / drain region and the source / drain contact, the contact spacer contacting a sidewall of the metal-semiconductor alloy region.

[0082] According to embodiments of this application, a method for forming a semiconductor device is provided, comprising: depositing a protective layer on a source / drain region and a gate mask, the gate mask being disposed on a gate structure, the gate structure being disposed on a channel region of a substrate, the channel region being adjacent to the source / drain region; etching an opening through the protective layer, the opening exposing the source / drain region; depositing metal in the opening and on the protective layer; annealing the metal to form a metal-semiconductor alloy region on the source / drain region; and removing metal residue from the opening using a cleaning process, the protective layer covering the gate mask during the cleaning process. In some embodiments, the cleaning process includes performing wet etching using dilute hydrofluoric acid, and etching of the gate mask does not occur during the wet etching. In some embodiments, the source / drain region includes a main layer and a finishing layer, the method further comprising: etching an opening through the finishing layer of the source / drain region, the opening exposing the main layer of the source / drain region. In some embodiments, the protective layer includes silicon nitride, and etching the opening includes performing dry etching using carbonyl sulfide. In some embodiments, etching of the main layer of the source / drain regions does not occur during dry etching. In some embodiments, the thickness of the protective layer is in the range of 1 nm to 3 nm. In some embodiments, the method of forming a semiconductor device further includes: depositing a contact etch stop layer (CESL) on the source / drain regions; forming an interlayer dielectric (ILD) on the contact etch stop layer; forming a contact opening through the interlayer dielectric and the contact etch stop layer; and, after forming the contact opening, extending the contact opening, wherein a protective layer is deposited in the contact opening after the contact opening is extended. In some embodiments, extending the contact opening includes etching the interlayer dielectric with hydrogen fluoride and ammonia at room temperature.

[0083] According to another embodiment of this application, a method for forming a semiconductor device is provided, comprising: depositing a contact etch stop layer (CESL) on a source / drain region; forming an interlayer dielectric (ILD) on the contact etch stop layer; forming a contact opening through the interlayer dielectric and the contact etch stop layer, the contact opening exposing the top surface of the source / drain region and the sidewall of the contact etch stop layer; after forming the contact opening, extending the contact opening by etching the interlayer dielectric using an isotropic etching process; and forming source / drain contacts in the contact opening. In some embodiments, the isotropic etching process includes: performing dry etching in the contact opening with an etching gas solution, the dry etching being performed without plasma, the etching gas solution converting the interlayer dielectric into solid-phase byproducts; performing heat treatment to sublimate the solid-phase byproducts into gaseous-phase byproducts; and discharging the gaseous-phase byproducts from the contact opening. In some embodiments, the etching gas solution comprises hydrogen fluoride and ammonia, and dry etching is performed at room temperature. In some embodiments, the etching gas solution comprises hydrogen fluoride, and dry etching is performed at a temperature in the range of 20°C to 40°C. In some embodiments, dry etching is performed at a first temperature, and heat treatment is performed at a second temperature, which is greater than the first temperature. In some embodiments, the interlayer dielectric comprises silicon oxide, and the solid-phase byproduct comprises ammonium fluorosilicate. In some embodiments, the method of forming a semiconductor device further comprises: forming a gate structure on a channel region of a substrate, the channel region adjacent to a source / drain region; forming a gate mask on the gate structure; depositing a protective layer on the gate mask and within the contact opening after extending a contact opening; extending the contact opening through the protective layer; and forming a metal-semiconductor alloy region in the contact opening when the protective layer covers the gate mask. In some embodiments, forming the metal-semiconductor alloy region comprises performing a cleaning process, and no etching of the gate mask occurs during the cleaning process. In some embodiments, extending the contact opening through the protective layer comprises etching the contact opening with carbonyl sulfide.

[0084] According to another embodiment of this application, a semiconductor device is provided, comprising: a gate structure on a channel region of a substrate; a gate mask on the gate structure; a source / drain region adjacent to the channel region; a source / drain contact connected to the source / drain region, the source / drain contact having an upper portion with curved sidewalls and a lower portion with straight sidewalls; and a contact spacer surrounding the source / drain contact, the contact spacer contacting a sidewall of the gate mask. In some embodiments, the semiconductor device further comprises: a gate spacer between the gate structure and the source / drain region; and a contact etch stop layer (CESL) between the gate spacer and the contact spacer, the CESL contacting a sidewall of the gate mask. In some embodiments, the semiconductor device further comprises: a metal-semiconductor alloy region between the source / drain region and the source / drain contact, the contact spacer contacting a sidewall of the metal-semiconductor alloy region.

[0085] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of the invention.

Claims

1. A method for forming a semiconductor device, comprising: A contact opening is formed through the interlayer dielectric, the contact opening exposing the source / drain region; After the contact opening is formed, the contact opening is expanded; After expanding the contact opening, a protective layer is deposited in the contact opening, on the source / drain region and on the gate mask, the gate mask being disposed on the gate structure, the gate structure being disposed on the channel region of the substrate, the channel region being adjacent to the source / drain region; Etch through an opening in the protective layer, the opening exposing the source / drain region; Deposit metal in the opening and on the protective layer; The metal is annealed to form a metal-semiconductor alloy region on the source / drain region; as well as The metal residue is removed from the opening using a cleaning process, during which the protective layer covers the gate mask.

2. The method according to claim 1, wherein, The cleaning process includes performing wet etching using dilute hydrofluoric acid, and the gate mask is not etched during the wet etching process.

3. The method according to claim 1, wherein, The source / drain region includes a master layer and a finishing layer, and the method further includes: The openings in the finishing layer of the source / drain regions are etched through, exposing the main layer of the source / drain regions.

4. The method according to claim 3, wherein, The protective layer comprises silicon nitride, and etching the opening comprises dry etching using carbonyl sulfide.

5. The method according to claim 4, wherein, No etching of the main layer of the source / drain region occurs during the dry etching process.

6. The method according to claim 1, wherein, The thickness of the protective layer is in the range of 1 nm to 3 nm.

7. The method according to claim 1, further comprising: A contact etch stop layer (CESL) is deposited on the source / drain region. The interlayer dielectric (ILD) is formed on the contact etch stop layer. The contact opening is formed through the interlayer dielectric and the contact etch stop layer.

8. The method according to claim 1 or 7, wherein, Expanding the contact opening involves etching the interlayer dielectric with hydrogen fluoride and ammonia at room temperature.

9. A method for forming a semiconductor device, comprising: Deposit a contact etch stop layer (CESL) on the source / drain regions; An interlayer dielectric (ILD) is formed on the contact etch stop layer. A contact opening is formed through the interlayer dielectric and the contact etch stop layer, the contact opening exposing the top surface of the source / drain region and the sidewall of the contact etch stop layer; After the contact opening is formed, the contact opening is expanded by etching the interlayer dielectric using an isotropic etching process; After expanding the contact opening, a protective layer is deposited in the contact opening and on the gate mask, the gate mask being adjacent to the source / drain region; The contact opening extends through the protective layer; When the protective layer covers the gate mask, a metal-semiconductor alloy region is formed in the contact opening; as well as Source / drain contacts are formed in the contact opening.

10. The method according to claim 9, wherein, The isotropic etching process includes: Dry etching is performed in the contact opening using an etching gas solution, the dry etching being carried out without plasma, the etching gas solution converting the interlayer dielectric into solid-phase byproducts. Perform heat treatment to sublimate the solid-phase byproducts into gaseous-phase byproducts; and The gaseous byproducts are discharged from the contact opening.

11. The method according to claim 10, wherein, The etching gas solution comprises hydrogen fluoride and ammonia, and the dry etching is performed at room temperature.

12. The method according to claim 10, wherein, The etching gas solution includes hydrogen fluoride, and the dry etching is performed at a temperature in the range of 20°C to 40°C.

13. The method according to claim 10, wherein, The dry etching is performed at a first temperature, and the heat treatment is performed at a second temperature, which is greater than the first temperature.

14. The method of claim 10, wherein, The interlayer dielectric comprises silicon oxide, and the solid phase byproduct comprises ammonium fluorosilicate.

15. The method of claim 9, further comprising: A gate structure is formed on a channel region of a substrate, the channel region being adjacent to the source / drain region; The gate mask is formed on the gate structure.

16. The method according to claim 9 or 15, wherein, Forming the metal-semiconductor alloy region includes performing a cleaning process, during which the gate mask is not etched.

17. The method according to claim 9 or 15, wherein, Extending the contact opening through the protective layer includes etching the contact opening with carbonyl sulfide.

18. A semiconductor device, comprising: The gate structure is located in the channel region of the substrate; A gate mask, on the gate structure; The source / drain region is adjacent to the channel region; A source / drain contact is connected to the source / drain region, the source / drain contact having an upper portion with curved sidewalls and a lower portion with straight sidewalls; A contact spacer surrounds the source / drain contact and contacts the sidewall of the gate mask; as well as A metal-semiconductor alloy region is disposed between the source / drain region and the source / drain contact through the contact spacer, and the metal-semiconductor alloy region contacts the source / drain region and the source / drain contact.

19. The semiconductor device of claim 18, further comprising: A gate spacer is located between the gate structure and the source / drain region; as well as A contact etch stop layer (CESL) is provided between the gate spacer and the contact spacer, and the contact etch stop layer contacts the sidewall of the gate mask.

20. The semiconductor device according to claim 18, wherein, The contact spacer contacts the sidewall of the metal-semiconductor alloy region.

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