Method for improving uniformity of mask pattern generation

Abstract

A method (400) for determining a mask pattern for a target pattern to be printed on a substrate is described herein. The method comprises: partitioning (P401) a portion of a design layout (401) including a target pattern into a plurality of cells (402) with reference to a given location on the target pattern; allocating (P403) a plurality of variables (403) within a specific cell of the plurality of cells, the specific cell including the target pattern or a portion of the target pattern; and determining (P405) a mask pattern (405) for the target pattern based on values ​​of the plurality of variables such that a performance metric of a patterning process using the mask pattern is within a desired performance range.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. application 62 / 947,707, filed December 13, 2019, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to photolithography, and more particularly to a mechanism for generating patterning device patterns. Background Art

[0004] A lithographic apparatus is a machine that applies a desired pattern to a target portion of a substrate. Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In that case, a patterning device (alternatively referred to as a mask or reticle) can be used to produce a circuit pattern corresponding to a single layer of the IC, and this pattern can be imaged onto a target portion (e.g., a portion comprising a die, a die, or several dies) on a substrate (e.g., a silicon wafer) having a layer of radiation-sensitive material (resist). Typically, a single substrate contains a network of adjacent target portions that are exposed sequentially. Known lithographic apparatus include so-called steppers, in which each target location is irradiated by exposing the entire pattern to the target location at once, and so-called scanners, in which each target location is irradiated by simultaneously scanning the substrate parallel or antiparallel to a given direction (the "scanning" direction) while the beam scans the pattern in that direction.

[0005] Before the circuit pattern is transferred from the patterning device to the substrate, the substrate may undergo various processes such as priming, resist coating, and soft baking. After exposure, the substrate may undergo other processes such as post-exposure baking (PEB), development, hard baking, and measurement / inspection of the transferred circuit pattern. This array of processes serves as the basis for forming a single layer of a device (e.g., an IC device). The substrate may then undergo various processes to produce the single layer of the device, such as etching, ion implantation (doping), metallization, oxidation, chemical mechanical polishing, etc. If several layers are required in the device, the entire procedure or a variation thereof may be repeated for each layer. Ultimately, a device will be present in each target portion on the substrate. These devices are then separated from each other by techniques such as dicing or sawing so that the individual devices can be mounted on a carrier, connected to pins, etc.

[0006] Therefore, manufacturing semiconductor devices typically involves processing a substrate (e.g., a semiconductor wafer) using multiple manufacturing processes to form the various features and multiple layers of the device. Such layers and features are typically fabricated and processed using, for example, deposition, lithography, etching, chemical mechanical polishing, and ion implantation. Multiple devices can be fabricated on multiple dies on a substrate and then separated into individual devices. Device fabrication typically includes a patterning process. The patterning process involves a patterning step (such as optical lithography and / or nanoimprint lithography using a patterning device (e.g., a mask) in a lithographic apparatus) to transfer the pattern on the patterning device to the substrate, and typically, but optionally, involves one or more associated pattern processing steps, such as developing the resist using a developer, baking the substrate using a bake tool, etching the pattern using an etching apparatus, and the like. Summary of the Invention

[0007] In an embodiment, a method for determining a mask pattern for a target pattern to be printed on a substrate is provided. The method includes dividing a portion of a design layout including the target pattern into a plurality of cells, each cell having a relationship to a given location on the target pattern; assigning a plurality of variables within a specific cell of the plurality of cells, the specific cell including the target pattern or a portion of the target pattern; and determining a mask pattern for the target pattern based on values ​​of the plurality of variables such that a performance metric of a patterning process using the mask pattern is within a desired performance range. In an embodiment, determining the mask pattern includes simulating a patterning process using the target pattern and the plurality of variables to determine values ​​of the plurality of variables such that the performance metric of the patterning process is within the desired performance range; and generating the mask pattern for the target pattern based on the determined values ​​of the plurality of variables.

[0008] Furthermore, in an embodiment, a non-transitory computer-readable medium is provided, the non-transitory computer-readable medium including instructions that, when executed by one or more processors, result in operations including: dividing a portion of a design layout including a target pattern into a plurality of cells, each cell having a relationship with a given location or a selected location on the target pattern; allocating a plurality of variables within a specific cell of the plurality of cells, the specific cell including the target pattern or a portion of the target pattern; and determining a mask pattern for the target pattern based on values ​​of the plurality of variables such that a performance metric of a patterning process using the mask pattern is within a desired performance range. Determining the mask pattern includes simulating a patterning process using the target pattern and the plurality of variables to determine values ​​of the plurality of variables such that the performance metric of the patterning process is within the desired performance range; and generating a mask pattern for the target pattern based on the determined values ​​of the plurality of variables. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0010] Figure 1 shows a block diagram of various subsystems of a lithography system according to an embodiment;

[0011] Figure 2 depicts an example flow chart for modeling and / or simulating at least a portion of a patterning process according to an embodiment;

[0012] Figure 3A and Figure 3B shows exemplary grid-dependent errors associated with a simulated patterning process according to an embodiment;

[0013] Figure 4A and Figure 4B is a flow chart for generating a mask pattern according to an embodiment;

[0014] Figure 5 is an example of conversion between a first coordinate system and a second coordinate system according to an embodiment;

[0015] Figure 6 According to the embodiment Figure 4A Examples of methods related to dividing cells and allocating multiple variables within cells;

[0016] Figure 7A is based on Figure 4A An exemplary design layout space partitioned by the method;

[0017] Figure 7B is an example of a variable in a non-repeating pattern according to an embodiment;

[0018] Figure 7C shows examples of variables in a repeating pattern according to an embodiment;

[0019] Figure 8 is used Figure 4A An exemplary continuous transmission map (CTM) generated by the method;

[0020] Figure 9 is used according to the embodiment Figure 4A A flowchart of an exemplary method for determining a mask pattern for a full chip based on the results of the method;

[0021] Figure 10 is a block diagram of an exemplary computer system according to an embodiment;

[0022] Figure 11 is a diagram of an exemplary lithographic projection apparatus according to an embodiment;

[0023] Figure 12 is a diagram of an exemplary extreme ultraviolet (EUV) lithography projection apparatus according to an embodiment;

[0024] Figure 13 According to the embodiment Figure 12 A more detailed view of an exemplary device in FIG; and

[0025] Figure 14 According to the embodiment Figure 12 and Figure 13 A more detailed view of the source collector module for a device. DETAILED DESCRIPTION

[0026] Figure 1 An exemplary lithographic projection apparatus 10A according to an embodiment of the present invention is shown. Apparatus 10A includes a radiation source 12A, which may be a deep ultraviolet (DUV) excimer laser source, or other types of sources, including extreme ultraviolet (EUV) sources. However, as described above, in some other embodiments, the radiation source may not be an integral part of the lithographic projection apparatus itself. Apparatus 10A also includes illumination optics, which, for example, define partial coherence (expressed as sigma) and may include optics 14A, 16Aa, and 16Ab configured to shape radiation from source 12A; a patterning device 18A; and transmission optics 16Ac, which project an image of the patterning device pattern onto substrate plane 22A. An adjustable filter or aperture 20A at the pupil plane of the projection optics can limit the range of beam angles projected onto the substrate plane 22A, where the maximum possible angle defines the numerical aperture NA = n sin(Θmax) of the projection optics, where n is the refractive index of the medium between the substrate and the last element of the projection optics, and Θmax is the maximum angle of the beam emitted from the projection optics that can still be projected onto the substrate plane 22A.

[0027] In a lithographic projection apparatus, a source provides illumination (i.e., radiation) to a patterning device, and projection optics shape the illumination onto a substrate via the patterning device. The lithographic projection apparatus may include at least some of the optical devices 14A, 16Aa, 16Ab, and the transmission optics 16Ac. The aerial image (AI) is the radiation intensity distribution at the substrate level. A resist layer on the substrate is exposed, and the aerial image is transferred to the resist layer as a latent "resist image" (RI). The resist image (RI) can be defined as the spatial distribution of the solubility of the resist in the resist layer. A resist model can be used to calculate the resist image based on the aerial image. An example of this can be found in U.S. Patent Application Publication No. US20090157360, the disclosure of which is incorporated herein by reference in its entirety. The resist model is related to the properties of the resist layer (e.g., the influence of chemical processes occurring during exposure, PEB, and development). The optical characteristics of the lithographic projection apparatus (e.g., the properties of the source, patterning device, and projection optics) determine the aerial image. Since the patterning device used in a lithographic projection apparatus can be varied, it may be desirable to decouple the optical properties of the patterning device from the optical properties of the rest of the lithographic projection apparatus (including at least the source and projection optics).

[0028] In embodiments, assist features (sub-resolution assist features and / or printable resolution assist features) can be placed into a design layout based on how the design layout is optimized according to the methods of the present disclosure. In embodiments, a machine learning-based model is used to determine the patterning device pattern. The machine learning model can be a neural network (such as a convolutional neural network) that can be trained in a specific manner to quickly obtain accurate predictions, thereby enabling full-chip patterning process simulation.

[0029] A neural network can be trained (i.e., its parameters are determined) using a training dataset. The training data can include or consist of a set of training examples. Each example can be a pair of an input object (typically a vector, which can be called a feature vector) and a desired output value (also called a management signal). A training algorithm analyzes the training data and adjusts the neural network's behavior by adjusting its parameters (e.g., the weights of one or more layers) based on the training data. The trained neural network can then be used to map new examples.

[0030] In the case of determining a patterning device pattern, the feature vector may include one or more characteristics of a design layout included or formed by the patterning device (e.g., shape, arrangement, size, etc.), one or more characteristics of the patterning device (e.g., one or more physical properties such as size, refractive index, material composition, etc.), and one or more characteristics of the illumination used in the lithography process (e.g., wavelength). The management signal may include one or more characteristics of the patterning device pattern (e.g., CD, profile, etc. of the patterning device pattern).

[0031] Given the form {(x1, y1),(x2, y2),…,(x N , y N )}, where x i is the eigenvector of the i-th example, and y i is the supervisory signal for the i-th example. The training algorithm seeks a neural network g:X→Y, where X is the input space and Y is the output space. A feature vector can be an n-dimensional vector representing the numerical characteristics of some object. The vector space associated with these vectors is often called the feature space. Sometimes, for convenience, a scoring function f:X×Y→R is used to represent g, where g is defined to return the value y that gives the highest score: . Let F denote the space of scoring functions.

[0032] Neural networks can be probabilistic, where g takes the form of a conditional probability model g(x)=P(y|x), or f takes the form of a joint probability model f(x, y)=P(x, y).

[0033] Two approaches can be used to select f or g: empirical risk minimization and structural risk minimization. Empirical risk minimization seeks the neural network that best fits the training data. Structural risk minimization includes a penalty function that controls the bias / variance tradeoff. For example, in one embodiment, the penalty function can be based on a cost function, such as squared error, number of defects, EPE, etc. The function (or weights within it) can be modified to minimize or reduce variance.

[0034] In both cases, it is assumed that the training set consists of or is composed of independent and identically distributed pairs (x i , y i ) is composed of one or more samples. In an embodiment, in order to measure the degree to which the function fits the training data, a loss function is defined For the training sample (x i , y i ), predicted value The loss is .

[0035] The risk R(g) of a function g is defined as the expected loss of g. This can be estimated from the training data as .

[0036] In embodiments, a machine learning model of a patterning process can be trained to predict, for example, the profile, pattern, CD of a mask pattern, and / or the profile, CD, edge placement (e.g., edge positioning error) in a resist and / or etch image on a wafer. The goal of the training is to achieve accurate predictions of, for example, the profile, aerial image intensity slope, and / or CD of the printed pattern on the wafer. The intended design (e.g., a wafer target layout to be printed on a wafer) is typically defined as a pre-optical proximity correction (OPC) design layout, which can be provided in a standardized digital file format (e.g., GDSII or OASIS or other file formats).

[0037] Figure 2 An exemplary flow chart for modeling and / or simulating portions of a patterning process is shown in . As will be appreciated, models can represent different patterning processes and need not include all of the models described below. Source model 1200 represents the optical characteristics of the illumination applied to the patterning device (including the radiation intensity distribution, bandwidth, and / or phase distribution). Source model 1200 can represent the optical characteristics of the illumination including, but not limited to, numerical aperture settings, illumination sigma (σ) settings, and any specific illumination shape (e.g., off-axis illumination shapes such as toroidal, quadrupole, dipole, etc.), where σ (sigma) is the outer radial extent of the illuminator.

[0038] Projection optics model 1210 represents the optical properties of the projection optics (including changes in the radiation intensity distribution and / or phase distribution caused by the projection optics). Projection optics model 1210 can represent the optical properties of the projection optics including aberrations, distortion, one or more refractive indices, one or more physical sizes, one or more physical dimensions, etc.

[0039] The patterning device / design layout model module 1220 captures how design features are laid out in the pattern of the patterning device and may include a representation of the detailed physical properties of the patterning device, as described, for example, in U.S. Patent No. 7,587,704, which is incorporated herein by reference in its entirety. In embodiments, the patterning device / design layout model module 1220 represents the optical properties (including the variations in radiation intensity distribution and / or phase distribution resulting from a given design layout) of a design layout (e.g., a device layout corresponding to features of an integrated circuit, memory device, electronic device, etc.) formed by or representing the arrangement of features on the patterning device. Because the patterning device used in a lithographic projection apparatus can vary, it is desirable to separate the optical properties of the patterning device from those of the rest of the lithographic projection apparatus (including at least the source and projection optics). The goal of simulations is typically to accurately predict, for example, edge placement and CD, which can then be compared to the device design. This device design is typically defined as a pre-OPC patterning device layout that can be provided in a standardized digital file format, such as GDSII or OASIS.

[0040] An aerial image 1230 can be simulated using a source model 1200, a projection optics model 1210, and a patterning device / design layout model 1220. The aerial image (AI) is the radiation intensity distribution at the substrate level. The optical characteristics of the lithographic projection apparatus (e.g., the properties of the illumination, patterning device, and projection optics) determine the aerial image.

[0041] A resist layer on a substrate is exposed using an aerial image, and the aerial image is transferred to the resist layer as a potential "resist image" (RI) in the resist layer. The resist image (RI) can be defined as the spatial distribution of the solubility of the resist in the resist layer. A resist image 1250 can be simulated from the aerial image 1230 using a resist model 1240. The resist model 1240 can be used to calculate a resist image based on the aerial image, an example of which can be found in U.S. patent application publication number US20090157360, the disclosure of which is incorporated herein by reference in its entirety. The resist model typically describes the effects of chemical processes occurring during resist exposure, post-exposure baking (PEB), and development in order to predict, for example, the profile of a resist feature formed on the substrate, and therefore the profile of the resist feature is typically only related to these properties of the resist layer (e.g., the effects of chemical processes occurring during resist exposure, post-exposure baking, and development). In an embodiment, the optical properties of the resist layer (eg, refractive index, film thickness, propagation, and polarization effects) may be captured as part of the projection optics model 1210 .

[0042] Typically, the connection between the optics and the resist model is the simulated aerial image intensity within the resist layer, which results from radiation projection onto the substrate, refraction at the resist interface, and multiple reflections within the resist film stack. The radiation intensity distribution (aerial image intensity) is converted into a potential "resist image" by absorbing the incident energy, which can be further modified by diffusion processes and various loading effects. Efficient simulation methods fast enough for full-chip applications approximate the true 3D intensity distribution in the resist stack via the 2D aerial image (and resist image).

[0043] In an embodiment, the resist image may be used as input to the post-pattern transfer process model module 1260. The post-pattern transfer process model module 1260 defines the performance of one or more post-resist development processes (eg, etching, developing, etc.).

[0044] Simulations of the patterning process can, for example, predict the profile, CD, edge placement (e.g., edge positioning error) in the resist and / or etch image. Thus, the goal of the simulation is to accurately predict, for example, edge placement of the printed pattern, and / or the slope of the aerial image intensity, and / or the CD. These values ​​can be compared with the intended design to, for example, correct the patterning process, identify locations where defects are predicted to occur, etc. The intended design is typically defined as a pre-OPC design layout, which can be provided in a standardized digital file format (such as GDSII or OASIS or other file formats).

[0045] Thus, the model formula describes most (if not all) of the known physics and chemistry of the entire process, and each model parameter ideally corresponds to a different physical or chemical effect. The model formula can therefore set an upper limit on the extent to which the model can be used to simulate the entire manufacturing process.

[0046] Continuous Transmission Mask (CTM) technology is an inverse lithography solution that can generate grayscale guidance maps of mask patterns. Based on the grayscale guidance maps, auxiliary features and modifications of the primary features of the design layout can be extracted. In embodiments, this guidance map can be used to generate polygonal features (e.g., primary features, auxiliary features, SRAFs, SERIFs, etc.). Masks fabricated using patterns generated using CTM+ technology are referred to as curved masks. In embodiments, CTM+ technology involves using a level set method to determine the guidance map, where level set thresholding aids in determining curved polygonal features (e.g., primary features, auxiliary features, SRAFs, SERIFs, etc.).

[0047] An example method for generating a curved mask is discussed in PCT Patent Publication No. WO 2019179747 A1, which is incorporated herein by reference in its entirety. In an example method (e.g., CTM, CTM+, or a combined CTM and CTM+), a guidance map is generated by optimizing a grayscale image for lithography-related performance metrics (e.g., EPE, sidelobes, etc.). This method can be used to generate an optimized curved mask pattern that includes a curved polygon traced from the grayscale image.

[0048] In another example approach, full-chip capabilities can be achieved by utilizing patch boundary processing, as discussed in U.S. patent application Ser. No. 62 / 785,981, filed Dec. 28, 2018, which is incorporated herein by reference in its entirety. The approach discussed ensures seamless transitions between different patch results without any degradation to the results introduced by patch boundaries.

[0049] In another example approach, to ensure mask manufacturability, an image-based MRC approach is discussed in U.S. patent application Ser. No. 62 / 773,475, filed on Nov. 30, 2018, which is incorporated herein by reference in its entirety. This example approach facilitates adjusting the mask pattern geometry so that MRC is satisfied.

[0050] To reduce the runtime for full-chip mask generation using the aforementioned method, a machine learning-based approach can be used, as discussed in PCT Patent Publication No. WO 2018215188 A1, which is incorporated herein by reference in its entirety. The machine learning-based approach trains a machine learning model to predict a grayscale image corresponding to the optimized mask pattern using a DCNN framework. The predicted grayscale image is very close to the "ground truth," so the final curved mask pattern can be generated with only a small number of iterations (e.g., fewer than required in an inverse lithography solution).

[0051] The aforementioned CTM and CTM+ techniques involve iterative optimization using grid-based pattern modification. This grid-based modification can generate a different CTM of the target pattern if the target pattern's grid positions are changed. Furthermore, inverse lithography is known to suffer from the problem of multiple solutions. When judged by lithographic performance (DOF, PVB, etc.), solutions with small or even clear differences may be considered acceptable.

[0052] Figures 3A-3B Example pattern shifts relative to the grid that cause grid-dependent errors are shown. Figure 3A and 3BPredicted profiles 301 / 311 (dashed lines) and input profiles 302 / 312 (eg, designed or desired profiles) are shown. Figure 3A In , the entire input contour 301 is on the grid, whereas in Figure 3B In Figure 3, a portion of input contour 311 deviates from the grid (e.g., at a corner point). This can cause discrepancies between contours 302 and 312 predicted by the model. In embodiments, such as in lithography manufacturability checking (LMC) or OPC applications, the same pattern may be repeatedly presented at different locations on the grid, and it is desirable to have an invariant model prediction regardless of the pattern's location. However, achieving perfect shift invariance can be difficult for a model. Some ill-conditioned models can result in large contour differences due to pattern shifts.

[0053] In an embodiment, grid dependent (GD) error may be measured as follows. To measure the GD error, the pattern and gauge are shifted together along the profile in sub-pixel steps. For example, for a pixel size = 14 nm, the pattern / gauge may be shifted by 1 nm in the x and / or y direction per step. With each shift, the model predicted CD along the gauge is measured. The change in the model predicted CD concentration is then indicative of the grid dependent error. From a user perspective, such a difference in the predicted profile may be unacceptable. Customers, OPC engineers, or other patterning process related users may prefer to use the same mask for the same target pattern to ensure better control of process variations.

[0054] The grid dependency issue can extend to inverse lithography applications, such as those used to generate CTMs and CTM+. As the CTM / CTM+ generation process undergoes iterative optimization to generate results (corresponding grayscale mask maps and / or curve masks), the results for the same target pattern can become increasingly divergent during optimization due to the effects of model grid dependency at each iteration step, as well as due to other processing of the CTM / CTM+ at each iteration step that can introduce additional grid dependency. The grid dependency issue can also extend to the application of machine learning-based methods used to accelerate, for example, sub-resolution assist feature (SRAF) generation. For example, the presence of varying solutions in the ground truth data itself can make it difficult for machine learning model training to converge to a better model with a lower RMS based on the ground truth results. Furthermore, when machine learning-based methods are applied to predict results, they can also be a source of grid dependency. In this disclosure, methods (e.g., 400) are discussed to reduce the variation in CTM / CTM+ results, thereby improving consistency.

[0055] Figure 4AThe present invention is a flow chart of an exemplary method for determining one or more mask patterns for any design layout including one or more target patterns, according to an embodiment of the present disclosure. For example, a mask layout can be generated that includes one or more mask patterns corresponding to one or more target patterns (such as memory circuits). Further, a mask using the mask layout can be used to print the target patterns onto a substrate.

[0056] In an embodiment, method 400 includes several steps or processes and, when executed (eg, via a processor or computer hardware system), generates a mask pattern of a desired pattern (eg, a target pattern).

[0057] Process P401 involves partitioning a portion of a design layout 401 into a plurality of cells 402, each of which has a relationship with a given location (or selected location) on a target pattern. In embodiments, the relationship may be a symmetric relationship (e.g., a symmetric relationship) that each cell satisfies. In embodiments, the relationship may be expressed as a function between a given location and a boundary, such as the minimum distance between each cell's boundary and the given location. This relationship may be used to determine the boundary of each cell that derives the partitioning of the design layout 401. In embodiments, the given location is the center of the target pattern, a point on the edge of the target pattern, or any point determined by a predefined geometric relationship with the target pattern (e.g., distance, trigonometric function, etc.). In embodiments, the design layout 401 includes multiple target patterns (e.g., holes, bars, lines, etc.), and their given locations may be the center of the target pattern, a point on the edge of the target pattern, or points having the same geometric relationship with the target pattern.

[0058] In an embodiment, the partitioning of the portion of the design layout is based on geometric partitioning (e.g., by using a Voronoi method), wherein a boundary of each cell in the plurality of cells 402 is determined based on a distance between the boundary of the cell and a given location on the target pattern. In an embodiment, the boundary of each cell in the plurality of cells 402 is determined such that a point in each cell is closest to the given location compared to other locations within the design layout.

[0059] In an embodiment, the design layout is associated with a first coordinate system, and the plurality of cells 402 are associated with a second coordinate system. In an embodiment, the first coordinate system refers to a coordinate system used in existing methods (e.g., the CTM / CTM+ methods in the previously mentioned patent publication WO 2019179747A1, and patent applications PCT / EP2019 / 081574 and PCT / EP2019 / 079562).

[0060] In an embodiment, the second coordinate system is defined such that the origin is located at a base point of the cell (e.g., a point or corner from the target design), the first axis is perpendicular to an edge of the target feature, and the second axis is perpendicular to the first axis (or other equivalent choices for defining the coordinate system). In an embodiment, for example, the base point can be a point placed at an edge of the target pattern. In an embodiment, the design layout includes multiple target patterns; a base point can be placed at each edge or partitioned edge of each target pattern to define the origin of a particular cell; and coordinates can be defined relative to the origin associated with each of the target patterns.

[0061] Figure 5 An exemplary first coordinate system and an exemplary second coordinate system according to an embodiment of the present disclosure are shown. For example, the first coordinate system can be represented as a grid of a patch 510 of a design layout. In an embodiment, the origin in the first coordinate system can be a corner of the patch 510 (e.g., the lower left corner), and the x-direction and the y-direction can be along the horizontal and vertical lines of the grid. As shown, the grid is defined by placing equidistant vertical lines and equidistant horizontal lines. When a target pattern (e.g., T1) is placed on such a grid, the target pattern can be described using the grid. The grid of the patch 510 is similar to the grid of the design layout. Figure 3A and 3B Discussion grid.

[0062] refer to Figure 5 In the inset 520 in FIG. 5 , the second coordinate system is defined such that the origin O1 is at the edge of the target pattern T1, the x direction is perpendicular to the edge, and the y direction is parallel to the edge. In an embodiment, the origin may be an evaluation point or geometric point associated with the edge of the target pattern T1 or the edge of a partition. In an embodiment, the evaluation point is an intended measurement point (e.g., placed at the edge of the target pattern) for determining a physical property (such as CD, EPE, etc.). For example, the origin O1 may be an EPE evaluation point located at the center of the edge of the target pattern. Thus, any variable (e.g., the center point of the partitioned edge) may be described with reference to the origin (e.g., the center point of the partitioned edge). Figure 5 ) within the cell C1 in , thereby providing a consistent reference point for any similar target pattern (e.g., T2). In an embodiment, each point corresponds to a discrete position (e.g., a pixel position), which is a variable. In an embodiment, each point corresponds to a value associated with each discrete position (e.g., the intensity value of the pixel at that position), which can be a variable. On the other hand, using a grid of patches 510 does not provide this consistency. Instead, a grid of patches 510 (or Figure 3A and 3B grid) will introduce grid-dependent errors in the evaluation and the resulting OPC pattern.

[0063] Return Reference Figure 4A , process P403 involves allocating a plurality of variables 403 within a specific unit in the plurality of units 402, the specific unit including the target pattern or a portion of the target pattern. In an embodiment, the allocating further includes assigning initial values ​​to the plurality of variables 403. Figure 5 As shown, cell C1 includes a portion of target pattern T1. Multiple variables 403 may be referred to as CTM variables. The values ​​of the CTM variables can be modified (e.g., during a patterning process simulation, a CTM / CTM+ simulation, etc.) based on performance metrics (e.g., used in a process simulation) to achieve desired performance. Initial values ​​for the multiple variables may be assigned in any suitable manner, such as user-defined values, random values, or other initial values ​​determined for faster convergence of a CTM / CTM+ simulation, without departing from the scope of this disclosure. In an embodiment, multiple variables 403 correspond to multiple pixels, and the value of a given variable in the multiple variables is the intensity associated with a given pixel or combination of pixels in the multiple pixels. The intensity value of a pixel may indicate an edge of a feature profile (e.g., an OPC feature such as an SRAF). For example, if intensity values ​​are expressed on a scale of 0 to 1, an intensity value greater than or equal to 0.75 indicates an edge pixel, while an intensity value less than 0.75 may indicate a non-edge pixel. In other words, as the intensity value changes, edges may appear or disappear, ultimately producing a pattern (e.g., an SRAF) to be used in a mask pattern.

[0064] In an embodiment, the values ​​of the plurality of variables 403 are in the second coordinate system and can be converted to values ​​in the first coordinate system. Figure 5 Let's discuss an exemplary conversion.

[0065] Process P405 includes determining a mask pattern 405 of a target pattern based on the values ​​of the plurality of variables 403 such that a performance metric of a patterning process using the mask pattern is within a desired range. In an embodiment, determining the mask pattern 405 includes simulating a patterning process using the target pattern and the plurality of variables 403 to determine the values ​​of the plurality of variables 403 such that the performance metric of the patterning process is within the desired performance range; and generating the mask pattern 405 of the target pattern based on the determined values ​​of the plurality of variables 403.

[0066] In an embodiment, determining the mask pattern involves an iterative process. Figure 4B An example flow diagram of process P405 is shown that includes sub-processes (such as P411 - P419 ) discussed in detail below.

[0067] Process P411 involves adjusting the value of one or more variables in the plurality of variables 403 for a particular cell. In an embodiment, adjusting the value of one or more variables involves adjusting the intensity within the particular cell. Adjusting means changing the value of one or more variables within the particular cell associated with the target pattern. For example, referring to Figure 5 , the values ​​of the variable set V1 are changed (e.g., increased or decreased). In embodiments, the values ​​of one or more variables (e.g., in set V1) can be any value between 0 and 1, -1 and 1, 0 and 100, 100 and 1000, or any other range of real or integer values. For example, variables near the edge of target pattern T1 can be changed to relatively higher values ​​than variables farther away from target pattern T1. In a first iteration, the initial values ​​of the variable set can remain the same. In subsequent iterations, the values ​​of variables at the edge can be increased, while values ​​farther away from the edge can be decreased. In further subsequent iterations, the variable values ​​can be increased or decreased based on the values ​​in the previous iteration. In embodiments, a gradient map associated with a performance metric (e.g., CD, EPE) can be used as a guide for changing the values ​​of the variables. For example, the gradient map can be a map of the first-order derivative of EPE with respect to variable V1. In embodiments, process P411 is repeated for all cells (e.g., cells C1-C4 in FIG. 4 ).

[0068] Process P413 involves converting the adjusted values ​​of one or more variables to a first coordinate system of the design layout. For example, a cell (e.g., Figure 5 The adjusted values ​​of one or more variables (e.g., V1) in C1, C2, C3, C4) can be transformed into the first coordinate system of the patch in the mask image or GDS format so that the impact of the adjusted values ​​of the variables can be evaluated. For example, the effect of the adjusted values ​​of the variables can be evaluated by simulating e.g. Figure 2 The impact of the patterning process discussed can be evaluated. In embodiments, the impact can be evaluated using a CTM or CTM+ simulation process flow (e.g., as discussed in the previously mentioned patent applications WO 2019179747 A1, 62 / 785981, and 62 / 773475). Thus, converting the adjusted values ​​from the second coordinate system to the first coordinate system allows their impact on the performance metric to be evaluated, so that the desired performance can be achieved.

[0069] In an embodiment, converting the adjusted values ​​of the one or more variables involves establishing a correlation between a first coordinate system of the design layout and a second coordinate system of the plurality of cells 402. For example, referring to Figure 5A correlation is established between the cells (e.g., C1, C2, C3, etc.) of slug 520 and the grid of slug 510. In embodiments, the correlation may be a mathematical function that maps the geometry of a target pattern described in a first coordinate system to the geometry described in a second coordinate system. Based on the correlation, adjusted values ​​of one or more variables may be transformed from the second coordinate system to the first coordinate system of the design layout. Using the transformed values ​​of the one or more variables, a simulated patterning process may then be performed to determine a performance metric.

[0070] In an embodiment, the plurality of variables 403 is associated with the plurality of pixels, and the value of a given variable in the plurality of variables is an intensity associated with a given pixel or combination of pixels in the plurality of pixels.

[0071] Figure 5 An example of converting values ​​between a first coordinate system and a second coordinate system is shown. For example, the first coordinate system refers to a coordinate system used to describe a design layout. In an embodiment, the first coordinate system describes a target pattern relative to a predetermined grid (such as, the grid of the slug 510 of the design layout). Typically, the grid of the slug 510 includes equidistant vertical lines and equidistant horizontal lines. The position (e.g., coordinates, relative position relative to adjacent features, etc.) and / or geometry (e.g., shape, size, etc.) of the target pattern (e.g., T1 and T2) can then be described relative to the grid. In an embodiment, the target pattern T1 (or T2) may fully occupy, partially occupy, or may not occupy a cell of the grid. In existing methods for determining CTM / CTM+ for OPC, the position of the target pattern relative to the grid or the first coordinate system may not be expected to be critical when determining optical proximity correction (OPC) for generating a mask pattern. For example, as shown in reference Figure 3A and Figure 3B As discussed, grid-dependent errors may be introduced into the OPC. Such grid-dependent errors lead to inconsistent mask patterns. For example, a mask pattern may have different OPCs corresponding to multiple identical target patterns (e.g., 40nm contact holes).

[0072] On the other hand, according to an embodiment of the present disclosure, a design layout patch is partitioned, for example, as shown in patch 520. Patch 520 includes a target feature T1, and the space of patch 520 is divided into cells C1, C2, C3, C4, and so on. In an example, patch 520 can be partitioned by applying a Voronoi method, thereby obtaining cells C1, C2, C3, and C4 surrounding target pattern T1. These Voronoi cells are in a coordinate system different from the first coordinate system of 510. Therefore, any variables defined within a particular cell (e.g., C1) of patch 520 (e.g., variable sets V1 and V2) will have different positioning relative to the grid of patch 510. In patch 520, variable set V1 is represented by points, where each point represents a different variable. In an embodiment, one or more point pixels and the value can be a pixel intensity.

[0073] Therefore, in this example, the values ​​of variables (such as V1 and V2) are converted to values ​​corresponding to the grid of patch 510. In an embodiment, variable set V1 is a plurality of pixels, and the value of a given variable in the plurality of variables is an intensity. The value of variable V1 can then be converted to a first coordinate system (e.g., the coordinate system of 510) by summing or weighted summing the intensities of the pixels associated with target pattern T1 in patch 520. Similarly, values ​​in the first coordinate system can be converted to a second coordinate system, for example, by taking the inverse of a mathematical function. Therefore, when the patterning process simulation determines an OPC correction at the edge of target pattern T1 or assist features around target pattern T1, the OPC correction can be converted based on the value of variable V1, and vice versa.

[0074] Return Reference Figure 4B Process P415 involves determining a performance metric of the patterning process by simulating the patterning process using the transformed values ​​of one or more variables. In one embodiment, the performance metric includes an edge positioning error between a target pattern and a simulated pattern generated by the simulated patterning process, a critical dimension (CD) of the simulated pattern, and / or a CD error between the simulated pattern and the target pattern. In one embodiment, the performance metric may be the number of overprinted (e.g., assist features) and underprinted (e.g., incomplete features) mask features compared to the target pattern. Process P417 involves determining whether the performance metric is within a desired performance range. Process P419 involves, in response to the performance metric being within the desired performance range, determining the mask pattern 405 based on the adjusted values. In one embodiment, in response to the performance metric not being within the desired performance range or the iteration step not reaching a desired set value (e.g., 100), steps P411-P417 are repeated until the desired performance metric is achieved or a desired number of iterations (e.g., 100) is reached. Figure 8 An example CTM map generated using the exemplary method 400 according to an embodiment of the present disclosure is shown.

[0075] In an embodiment, generating a mask pattern 405 of a target pattern involves converting values ​​of a plurality of variables into a pixelated image that is a mathematical representation of a grayscale mask image (e.g., CTM) or that generates a curved mask pattern as a level set function (e.g., CTM+).

[0076] In an embodiment, method 400 involves applying values ​​of a plurality of variables determined using a target pattern to other instances of the target pattern in a design layout; and determining a mask pattern 405 based on the values ​​applied to the instances of the target pattern such that all instances of the target pattern are modified in a consistent manner to generate the mask pattern. For example, referring to Figure 5 , the value of variable V1 associated with target feature T1 is used to generate the grayscale image. In an embodiment, target feature T1 may appear at multiple locations in the design layout, and the same value of V1 can then be used for multiple patterns, thereby generating mask patterns with consistent OPC correction for the same target pattern.

[0077] In an embodiment, the method 400 further includes: determining a symmetric portion between the plurality of cells or within a particular cell; and assigning the same set of variables to the symmetric portion of each cell in the plurality of cells. In an embodiment, the symmetric portion may be determined based on geometric similarity between the plurality of cells 402 or within a particular cell. For example, if Figure 5 If the target pattern in is a repeating contact array, then all cells like C1, C2, C3, and C4 are symmetric and can therefore be represented by the same set of variables. Additionally, if each cell is flip / mirror symmetric, then variable V1 in a portion of cell C1 (the triangular portion) can represent another portion, such as a mirror-symmetric portion with variable V2 (e.g., another triangular portion).

[0078] Employing this symmetry-based variable allocation can advantageously reduce the size of the variable set by several orders of magnitude. For example, if there are 1,000 cell instances that are all symmetric to one another, and there are 100 variables in each cell, then by using symmetry-based variable allocation, the number of variables is reduced by a factor of 1,000. Consequently, the simulation of the patterning process is based on this reduced number of variables, making the patterning process simulation or OPC determination much faster than using the full set of variables. Furthermore, the results of the OPC associated with this reduced number of variables (e.g., 100 variables) can be used at many target features throughout the design layout (e.g., 1,000 instances), thereby achieving consistency in the mask pattern using the determined OPC.

[0079] Figure 6 Different examples of space partitioning and symmetry-based variable allocation according to embodiments of the present disclosure are shown. Figure 6 In FIG, a patch of a design pattern includes target features T1, T2, T3, T4, and T5, all of which are part of an infinitely repeating contact array pattern. The patch is divided into multiple cells based on the pitch repeatability between the target patterns in the space to be divided, and a particular cell 600 (e.g., a square covering or partially covering target features T1-T5) is shown. Within cell 600, dots represent variables assigned to the cell. In an embodiment, symmetric portions (e.g., triangular portions) are assigned the same set of variables 610. For example, cell 600 includes 16 symmetric portions (e.g., represented by triangles). In this example, variable sets 610 are assigned within the triangular portions (an example of symmetric portions), and these same variables 610 can be applied to the rest of cell 600. In an embodiment, the symmetric portions with variables 610 can be referred to as repeating patterns, as the values ​​of variables 610 can be repeated to cover the entire space of infinitely repeating contact array patterns. In an embodiment, as an alternative to geometric partitioning based on the target pattern geometry, the method may be used for the center of an array pattern (which may be represented by an infinite array) with a given repeating pitch.

[0080] In an embodiment, method 400 further involves performing an optical proximity correction (OPC) process using mask pattern 405 as an initial pattern, wherein the OPC process involves modifying the mask pattern to determine an optical proximity corrected mask pattern. In an embodiment, the mask pattern is modified to improve a performance metric of the patterning process. For example, improving the performance metric may include minimizing edge positioning errors between a target pattern and a simulated pattern generated by a simulation of the patterning process, minimizing the number of overprints and underprints of mask features compared to the target pattern, minimizing CD errors between the simulated pattern and the target pattern, or a combination thereof. It will be understood that any other suitable OPC process or mechanism for improving the performance metric may be used without departing from the scope of the present disclosure.

[0081] Figures 7A-7C A graphical comparison of a repeating pattern (eg, symmetrical portions) and a non-repeating pattern (eg, no symmetrical portions are used) is shown. Figure 7A An example design layout 710 is shown that is divided into a plurality of cells 712 (eg, Voronoi cells using a Voronoi method). Figure 7B A plurality of variables 722 (eg, shaded areas) assigned to each of the plurality of cells 712 are shown. Since the plurality of variables in each cell are processed independently without considering symmetry, the number of variables may be very large. On the other hand, as in the embodiment of the present disclosure, Figure 7CAs shown, when symmetrical portions are identified, the number of variables is significantly reduced. For example, the variables at 732, 733, 734, 735, and 736 need to be adjusted. The results associated with the variables at 732-736 can then be applied to their respective symmetrical portions in different cells. Therefore, a comparison of the shaded portion of the non-repeating pattern (in 7B) with the shaded portion of the repeating pattern (in 7C) shows a significant reduction in size or the number of variables. This significantly improves the consistency of the mask pattern.

[0082] Figure 9 The following is a flow chart of an exemplary full-chip OPC simulation process using the results of method 400 according to an embodiment of the present disclosure. For example, the results (e.g., adjusted values) associated with multiple variables 403 of a cell can be categorized by the geometry of the corresponding target pattern (e.g., having specific holes, lines with specific CDs, distances between adjacent features, etc.) and stored as a database. This database can then be loaded during OPC determination of the mask pattern. The results stored in the database can then be applied to the geometrically matching target pattern. The stored results can be applied directly or with minor adjustments without having to rerun a lengthy simulation process.

[0083] In an embodiment, the results associated with the plurality of cells associated with the target pattern (e.g., Figure 5 T1 and T2) can also be used to train a machine learning model. As previously mentioned, to reduce the runtime of full-chip mask pattern generation using CTM / CTM+ processes, methods based on machine learning using deep convolutional neural networks (DCNNs) (e.g., as discussed in U.S. patent application Ser. No. 16 / 606,791) have been developed to predict grayscale images corresponding to optimized mask patterns that are very close to "ground truth." However, mask consistency requirements may not be met using OPC tools. To improve CTM and CTM+ consistency, method 400 can be used to train a machine learning model, as it may enable new approaches for full-chip applications. Figure 9 The training method 900 advantageously has the ability to produce results with greater consistency in shorter runtimes and is fully compatible with existing methods of curve mesh boundary processing and machine learning methods (e.g., Newron Freeform). Figure 9 The proposed method provides significant benefits for handling highly repetitive layouts (like memory patterns) and is also beneficial for random logic layouts. The method is also applicable to CTM methods and can be used as a complement to SRAF methods based on machine learning, for example.

[0084] Figure 9The method can be divided into two phases: (i) a data generation phase in which a "result library" is generated using method 400, and (ii) a full-chip application phase in which the "result library" is applied together with a machine learning model to a full design layout or a target layout to generate a curve model. These phases are discussed in detail below.

[0085] In process 900, selected segments of a target pattern 901 can be used to generate an initial CTM / CTM+ map 903 for use in a CTM / CTM+ generation or optimization process 905. In embodiments, the initial CTM / CTM+ map 903 can be optimized using the optimization process 905 to generate an optimized image 907 for the CTM, and an optimized image 907 phi (φ) (e.g., a polygon from a level set output) and a curved mask pattern for the CTM+. The results can be used to train a machine learning model 909, as discussed in U.S. patent application Ser. No. 16 / 606,791, which is incorporated herein by reference in its entirety.

[0086] In embodiments, the optimization process 905 may involve simulations based on inverse lithography (e.g., such as CTM in PCT patent publication WO2019179747 A1), simulations based on level set methods (e.g., CTM+), CTM generation based on machine learning models (e.g., in U.S. patent application Ser. No. 16 / 606,791), or a combination thereof. In embodiments, the method 400 may be integrated with the optimization process 905, such as in Figure 4A and 4B As discussed in [ 901 ], the selected target pattern 901 can be divided into a plurality of cells, where each cell can include a plurality of CTM variables. The values ​​of the CTM variables can then be adjusted according to an optimization process 905 (e.g., to improve a performance metric such as EPE). The values ​​of such CTM variables for each cell (or symmetrical portion of a cell) can be associated with the selected target pattern 901 and stored in a results library 906.

[0087] In one embodiment, the results library 906 includes optimized CTM variable values ​​for selected target patterns. In one embodiment, the design layout may include other target patterns. In one embodiment, the selected target patterns may be patterns that frequently appear at different locations in the design layout, key patterns, hotspot patterns, and the like. In one embodiment, a coverage analysis may be performed to select a few patterns from the design layout that represent the entire design layout or cover, for example, more than 90% of the patterns. For example, the design layout may include millions or even billions of patterns, and only 100,000, 10,000, or 1,000 patterns may be selected as target patterns. Therefore, for each selected pattern (e.g., 1,000 patterns), the results library may include cells (e.g., 1,000 cells corresponding to 100 patterns) and corresponding variable values. For example, each selected target pattern may be associated with a unique cell identifier to facilitate locating the corresponding result from the results library 906.

[0088] In the second step of method 900, result library 906 can be used to generate a full chip layout 911 and a mask pattern for the full chip is generated. In an embodiment, the full chip layout includes multiple target patterns, for example, including one or more selected target patterns 901 for which result library 906 was generated in the first step.

[0089] In the second step, the full chip layout 911 can be divided into multiple cells in the same manner as in the first step. Then, during mask pattern generation, results can be loaded from the result library 906 for one or more cells of the full chip layout 911 corresponding to the selected target pattern 901. For other patterns for which results are not available in the result library 906, a separate CTM process can be performed, including CTM generation 903 and CTM optimization 905. The results from the CTM optimization 905 and the result library 906 can be combined to generate a final mask pattern 920 corresponding to the full chip layout 911. This mask pattern 920 can be generated with less runtime cost (because no optimization is required) and is easier to handle edges (because the results are more consistent).

[0090] For full-chip layouts that include highly repetitive patterns (eg, memory layouts), results for all possible cells can be generated, so no additional optimization is required when generating the full-chip mask pattern.

[0091] However, for full-chip layouts with more pattern variations (typically, as in random logic layouts), it may be difficult to generate results for all cells in the full-chip layout within a reasonable computational cost. In such cases, a results library can be generated by selecting, for example, relatively critical, repetitive, or typical layouts. Then, for cells included in the results library (e.g., 906), the results can be directly loaded during, for example, a CTM / CTM+ optimization or generation process. For other cells, the CTM / CTM+ generation process 903 can be initialized using, for example, machine learning model predictions, allowing for several iterations of optimization 905 to produce good lithographic performance. Therefore, method 900 of implementing method 400 is compatible with existing deep learning-based CTM or CTM+ generation methods.

[0092] In an embodiment, the methods discussed herein may be provided as a computer program product or non-transitory computer-readable medium having instructions recorded thereon that, when executed by a computer, perform the operations of methods 400 and 900 as described above.

[0093] For example, Figure 10 The example computer system 100 in the embodiment includes a non-transitory computer-readable medium (e.g., a memory) including instructions that, when executed by one or more processors (e.g., 104), result in operations including: dividing a portion of a design layout including a target pattern into a plurality of cells, each cell having a relationship to a given location on the target pattern; allocating a plurality of variables within a specific cell of the plurality of cells, the specific cell including the target pattern or a portion of the target pattern; and determining a mask pattern for the target pattern based on values ​​of the plurality of variables such that a performance metric of a patterning process using the mask pattern is within a desired performance range. In an embodiment, determining the mask pattern includes: simulating a patterning process for determining values ​​of the plurality of variables using the target pattern and the plurality of variables such that a performance metric of the patterning process is within a desired performance range; and generating the mask pattern for the target pattern based on the determined values ​​of the plurality of variables.

[0094] In an embodiment, as previously described, partitioning portions of the design layout is based on geometric partitioning, such as a Voronoi method, where the boundaries of each of a plurality of cells are determined based on a distance to a given location on a target pattern.

[0095] In an embodiment, as previously described, the design layout is associated with a first coordinate system, and the plurality of cells are associated with a second coordinate system, wherein the values ​​of the plurality of variables are expressed in the second coordinate system and are convertible to values ​​expressed in the first coordinate system. In an embodiment, the second coordinate system is defined such that the origin is at the base point of each cell, the first axis is perpendicular to the edge, and the second axis is perpendicular to the first axis.

[0096] In an embodiment, as described above, determining a mask pattern is an iterative process, including: (a) adjusting the value of one or more variables among a plurality of variables of a specific cell; (b) converting the adjusted values ​​of the one or more variables to a first coordinate system of a design layout; (c) determining a performance metric of the patterning process by simulating a patterning process using the converted values ​​of the one or more variables; (d) determining whether the performance metric is within a desired performance range; (e) in response to the performance metric being within the desired performance range, determining a mask pattern based on the adjusted values; and (f) in response to the performance metric not being within the desired performance range, performing (a) to (e).

[0097] In an embodiment, as described above, converting the adjusted values ​​of one or more variables includes: establishing a correlation between a first coordinate system of the design layout and a second coordinate system of the plurality of cells; converting the adjusted values ​​of the one or more variables from the second coordinate system to the first coordinate system of the design layout based on the correlation; and simulating a patterning process using the converted values ​​of the one or more variables.

[0098] In an embodiment, as previously described, the plurality of variables corresponds to the plurality of pixels, and the value of a given variable in the plurality of variables is an intensity associated with a given pixel or combination of pixels in the plurality of pixels.

[0099] In an embodiment, the non-transitory computer-readable medium further stores executable instructions that cause operations including: applying values ​​of a plurality of variables determined using the target pattern to other instances of the target pattern in the design layout; and determining a mask pattern based on the values ​​applied to the instances of the target pattern such that all instances of the target pattern are modified in a consistent manner to generate the mask pattern.

[0100] In an embodiment, the non-transitory computer-readable medium further stores executable instructions causing operations including: determining symmetric portions between a plurality of cells or within a particular cell; and assigning the same set of variables to the symmetric portions of each of the plurality of cells.

[0101] In an embodiment, the non-transitory computer-readable medium further stores executable instructions, the operations caused by the executable instructions including: classifying the values ​​of multiple variables of multiple cells based on the geometry of the corresponding target pattern; storing the values ​​of the multiple variables in a result library; and determining a mask pattern corresponding to the full chip layout based on the result library.

[0102] In an embodiment, as described above, determining the mask pattern of the full chip layout includes: identifying the pattern of the full chip layout by geometrically matching the full chip layout with a target pattern stored in a result library; extracting values ​​of multiple variables corresponding to the identified pattern; and applying the extracted values ​​to determine the mask pattern of the full chip layout.

[0103] Figure 10 is a block diagram illustrating an exemplary computer system 100 configured to facilitate implementation of the methods and processes disclosed herein, according to an embodiment of the present disclosure. Computer system 100 includes a bus 102 or other communication mechanism for communicating information, and a processor 104 (or multiple processors 104 and 105) coupled to bus 102 for processing information. Computer system 100 also includes a main memory 106, such as a random access memory (RAM) or other dynamic storage device, coupled to bus 102 for storing instructions and information to be executed by processor 104. Main memory 106 may also be used to store temporary variables or other intermediate information during the execution of instructions to be executed by processor 104. Computer system 100 also includes a read-only memory (ROM) 108 or other static storage device coupled to bus 102 for storing static information and instructions for processor 104. A storage device 110, such as a magnetic disk or optical disk, is provided and coupled to bus 102 for storing information and instructions.

[0104] The computer system 100 can be coupled via bus 102 to a display 112, such as a cathode ray tube (CRT) or a flat-panel display or a touch panel display, for displaying information to a computer user. An input device 114, including alphanumeric keys and other keys, is coupled to bus 102 for communicating information and command selections to processor 104. Another type of user input device is a cursor control 116, such as a mouse, trackball, or cursor direction keys, for communicating directional information and command selections to processor 104 and for controlling cursor movement on display 112. Such input devices typically have two degrees of freedom along two axes, namely a first axis (e.g., x) and a second axis (e.g., y), which allow the device to specify a position in a plane. A touch panel (screen) display can also be used as an input device.

[0105] According to one embodiment, portions of the process may be performed by the computer system 100 in response to the processor 104 executing one or more sequences of one or more instructions contained in the main memory 106. These instructions may be read into the main memory 106 from another computer-readable medium, such as the storage device 110. Execution of the sequences of instructions contained in the main memory 106 causes the processor 104 to perform the process steps described herein. One or more processors in a multi-processing arrangement may also be employed to execute the sequences of instructions contained in the main memory 106. In alternative embodiments, hard-wired circuitry may be used in place of or in combination with software instructions. Thus, the description herein is not limited to any specific combination of hardware circuitry and software.

[0106] As used herein, the term "computer-readable medium" refers to any medium that participates in providing instructions to processor 104 for execution. Such media can take many forms, including, but not limited to, non-volatile media, volatile media, and transmission media. Non-volatile media include, for example, optical or magnetic disks, such as storage device 110. Volatile media include dynamic memory, such as main memory 106. Transmission media include coaxial cables, copper wire, and fiber optics, including the wires comprising bus 102. Transmission media can also take the form of sound or light waves, such as those generated during radio frequency (RF) and infrared (IR) data communications. Common forms of computer-readable media include, for example, floppy disks, flexible disks, hard disks, magnetic tape, any other magnetic medium, CD-ROMs, DVDs, any other optical medium, punch cards, paper tape, any other physical medium with a pattern of holes, RAM, PROMs and EPROMs, FLASH-EPROMs, any other memory chip or cartridge, a carrier wave as described below, or any other medium that can be read by a computer.

[0107] Various forms of computer-readable media may be involved in carrying one or more sequences of one or more instructions to processor 104 for execution. For example, the instructions may initially be carried on a disk of a remote computer. The remote computer may load the instructions into its dynamic memory and send the instructions over a telephone line using a modem. A modem local to computer system 100 may receive the data on the telephone line and convert the data into an infrared signal using an infrared transmitter. An infrared detector coupled to bus 102 may receive the data carried in the infrared signal and place the data on bus 102. Bus 102 carries the data to main memory 106, from which processor 104 retrieves and executes the instructions. The instructions received by main memory 106 may optionally be stored on storage device 110 before or after execution by processor 104.

[0108] The computer system 100 also desirably includes a communication interface 118 coupled to the bus 102. The communication interface 118 provides a two-way data communication coupling to a network link 120 connected to a local area network 122. For example, the communication interface 118 can be an integrated services digital network (ISDN) card or a modem to provide a data communication connection to a corresponding type of telephone line. As another example, the communication interface 118 can be a local area network (LAN) card to provide a data communication connection to a compatible LAN. A wireless link can also be implemented. In any such implementation, the communication interface 118 sends and receives electrical, electromagnetic, or optical signals that carry digital data streams representing various types of information.

[0109] Network link 120 typically provides data communication to other data devices through one or more networks. For example, network link 120 may provide a connection through local network 122 to a host computer 124 or to data equipment operated by an Internet Service Provider (ISP) 126. ISP 126, in turn, provides data communication services through the global packet data communication network, now commonly referred to as the "Internet" 128. Both local network 122 and Internet 128 use electrical, electromagnetic, or optical signals to carry digital data streams. The signals passing through the various networks and the signals on network link 120 and through communication interface 118, which carry the digital data to and from computer system 100, are exemplary forms of carrier waves transporting the information.

[0110] Computer system 100 can send messages and receive data, including process code, via the network, network link 120, and communication interface 118. In the Internet example, server 1630 might transmit the requested code for an application via Internet 128, ISP 126, local area network 122, and communication interface 118. For example, one such downloaded application might provide illumination optimization for an embodiment. The received code can be executed by processor 104 upon receipt and / or stored in storage device 110 or other non-volatile storage device for later execution. In this manner, computer system 100 can obtain application code in the form of a carrier wave.

[0111] Figure 11 An exemplary lithographic projection apparatus incorporating the techniques described herein according to an embodiment of the present disclosure is depicted. The apparatus comprises:

[0112] - an illumination system IL for conditioning the radiation beam B. In this particular case, the illumination system further comprises a radiation source SO;

[0113] a first target table (e.g., patterning device table) MT provided with a patterning device holder to hold the patterning device MA (e.g., reticle) and connected to a first positioner to accurately position the patterning device with respect to the item PS;

[0114] a second target table (substrate table) WT provided with a substrate holder to hold a substrate W (e.g. a resist-coated silicon wafer) and connected to a second positioner for accurately positioning the substrate relative to the item PS;

[0115] - A projection system ("lens") PS (eg, a refractive, reflective, or catadioptric optical system) for imaging the illuminated portion of the patterning device MA onto a target portion C of the substrate W (eg, comprising one or more dies).

[0116] As described herein, the device is transmissive (i.e., having a transmissive patterning device). However, in general, the device can also be reflective, for example (having a reflective patterning device). The device can employ different types of patterning devices to form a typical mask; examples include a programmable mirror array or an LCD matrix.

[0117] A radiation beam is generated by a source SO (e.g., a mercury lamp or an excimer laser, an LPP (laser produced plasma) EUV source). This beam is supplied to an illumination system (illuminator) IL, for example, directly or after passing through a conditioning device (such as a beam expander Ex). The illuminator IL may include an conditioning device AD ​​for setting the outer and / or inner radial extent of the intensity distribution in the beam (commonly referred to as σ-outer and σ-inner, respectively). Furthermore, the illuminator IL typically includes various other components, such as an integrator IN and a condenser CO. In this manner, the beam B projected onto the patterning device MA has a desired uniformity and intensity distribution in its cross-section.

[0118] about Figure 11 It should be noted that the source SO can be an integral part of the lithographic projection apparatus, for example within the housing of the lithographic projection apparatus (for example, this is usually the case when the source SO is a mercury lamp), but the source SO can also be at a distance from the lithographic projection apparatus, the radiation beam generated by the source SO being introduced into the apparatus (for example, with the aid of suitable guiding mirrors); the latter case is usually the case when the source SO is an excimer laser (for example, based on KrF, ArF or F2 laser).

[0119] The beam PB then intersects the patterning device MA which is held on the patterning device table MT. After passing the patterning device MA, the beam B passes through a lens PL which focuses the beam B onto a target portion C of the substrate W. With the aid of the second positioning device (and the interferometry device IF) the substrate table WT can be accurately moved, for example in order to position a different target portion C in the path of the beam PB. Similarly, the first positioning device can be used to accurately position the patterning device MA relative to the path of the beam B, for example after mechanical retrieval of the patterning device MA from a patterning device library or during a scan. Typically movement of the target table MT, WT will be realized with the aid of a long-stroke module (coarse positioning) and a short-stroke module (fine positioning), which is not described in detail in the accompanying drawings. Figure 11 However, in the case of a stepper (as opposed to a step-and-scan tool), the patterning device table MT may be connected to a short-stroke actuator only, or may be fixed.

[0120] The depicted tool can be used in two different modes:

[0121] - in step mode, the patterning device table MT is held essentially stationary and the entire patterning device image is projected at once (i.e. a single "flash") onto a target portion C. The substrate table WT is then shifted in the x and / or y direction so that a different target portion C can be illuminated by the beam PB;

[0122] In scan mode, essentially the same situation applies, except that a given target portion C is not exposed in a single "flash." Instead, the patterning device table MT can be moved in a given direction (the so-called "scanning direction," e.g., the y-direction) at a speed v, so that the projection beam B is scanned across the patterning device image. Simultaneously, the substrate table WT is simultaneously moved in the same or opposite direction at a speed V=Mv, where M is the magnification of the lens PL (typically, M=1 / 4 or 1 / 5). In this way, a relatively large target portion C can be exposed without sacrificing resolution.

[0123] Figure 12 Another exemplary lithographic projection apparatus 1000 according to an embodiment of the present disclosure is depicted. The apparatus 1000 comprises:

[0124] - A source collector module SO for providing radiation.

[0125] - An illumination system (illuminator) IL configured to condition the radiation beam B (eg EUV radiation) coming from the source collector module SO.

[0126] a support structure (e.g., mask table) MT configured to support a patterning device (e.g., mask or reticle) MA and connected to a first positioner PM configured to accurately position the patterning device;

[0127] a substrate table (eg, wafer stage) WT configured to hold a substrate (eg, a resist-coated wafer) W and connected to a second positioner PW configured to accurately position the substrate; and

[0128] A projection system (eg, a refractive projection system) PS configured to project the pattern imparted to the radiation beam B by the patterning device onto a target portion C of the substrate W (eg, comprising one or more dies).

[0129] As described herein, apparatus 1000 is reflective (e.g., employing a reflective mask). It should be noted that because most materials absorb in the EUV wavelength range, the patterning device can have a multilayer reflector comprising, for example, a multilayer stack of molybdenum and silicon. In one example, the multi-stack reflector has 40 layers of molybdenum and silicon pairs, each layer being a quarter wavelength thick. Even smaller wavelengths can be produced using X-ray lithography. Because most materials absorb in EUV and X-ray wavelengths, a thin layer of patterned absorbing material (e.g., a TaN absorber on top of the multilayer reflector) on the patterning device topography defines where features will be printed (positive resist) or not (negative resist).

[0130] refer to Figure 12 The illuminator IL receives a beam of extreme ultraviolet radiation from a source collector module SO. Methods of generating EUV radiation include, but are not necessarily limited to, converting a material into a plasma state having at least one element (e.g., xenon, lithium, or tin) with one or more emission lines in the EUV range. In one such method, a plasma (often referred to as laser produced plasma ("LPP")) can be generated by irradiating a fuel (e.g., a droplet, stream, or cluster of material having line emitting elements) with a laser beam. The source collector module SO can be a laser ( Figure 12 The fuel excitation system comprises a portion of an EUV radiation system (not shown) for providing a laser beam for excitation of the fuel. The resulting plasma emits output radiation (e.g., EUV radiation), which is collected using a radiation collector disposed in a source collector module. For example, when a CO2 laser is used to provide the laser beam for fuel excitation, the laser and source collector module may be separate entities.

[0131] In this case, the laser is not considered to form part of the lithographic apparatus, and the radiation beam is delivered from the laser to the source collector module by means of a beam delivery system comprising, for example, suitable directing mirrors and / or a beam expander. In other cases, such as when the radiation source is a discharge produced plasma EUV generator (commonly referred to as a DPP radiation source), the radiation source may be an integral part of the source collector module.

[0132] The illuminator IL may include an adjuster for adjusting the angular intensity distribution of the radiation beam. Typically, at least the outer radial extent and / or the inner radial extent (commonly referred to as σ-outer and σ-inner, respectively) of the intensity distribution in a pupil plane of the illuminator can be adjusted. In addition, the illuminator IL may include various other components, such as a faceted field mirror arrangement and a faceted pupil mirror arrangement. The illuminator can be used to condition the radiation beam to have a desired uniformity and intensity distribution in its cross-section.

[0133] A radiation beam B is incident on a patterning device (e.g., mask) MA, which is held on a support structure (e.g., mask table) MT, and is patterned by the patterning device MA. After being reflected from the patterning device (e.g., mask) MA, the radiation beam B passes through a projection system PS, which focuses the beam onto a target portion C of a substrate W. With the aid of a second positioner PW and a position sensor PS2 (e.g., an interferometry device, a linear encoder, or a capacitive sensor), the substrate table WT can be accurately moved (e.g., to position a different target portion C in the path of the radiation beam B). Similarly, a first positioner PM and another position sensor PS1 can be used to accurately position the patterning device (e.g., mask) MA relative to the path of the radiation beam B. The patterning device (e.g., mask) MA and substrate W can be aligned using patterning device alignment marks M1, M2 and substrate alignment marks P1, P2.

[0134] The described device 1000 can be used in at least one of the following modes:

[0135] 1. In step mode, the support structure (e.g. mask table) MT and substrate table WT are held substantially stationary (i.e. a single static exposure) while the entire pattern imparted to the radiation beam is projected at one time onto a target portion C. The substrate table WT is then shifted in the X and / or Y direction so that a different target portion C can be exposed.

[0136] 2. In scan mode, the support structure (e.g. mask table) MT and substrate table WT are scanned synchronously (i.e. single dynamic exposure) as a pattern imparted to the radiation beam is projected onto a target portion C. The velocity and direction of the substrate table WT relative to the support structure (e.g. mask table) MT may be determined by the (de-)magnification and image reversal properties of the projection system PS.

[0137] 3. In another mode, the support structure (e.g., mask table) MT is held substantially stationary, thereby holding the programmable patterning device, and the substrate table WT is moved or scanned, while a pattern imparted to the radiation beam is projected onto a target portion C. In this mode, a pulsed radiation source is typically employed, and the programmable patterning device is updated as required after each movement of the substrate table WT, or between successive radiation pulses during a scan. This mode of operation can be readily applied to maskless lithography employing a programmable patterning device, such as a programmable mirror array of the type mentioned above.

[0138] Figure 13The apparatus 100 is shown in more detail, comprising a source collector module SO, an illumination system IL, and a projection system PS. The source collector module SO is constructed and arranged so that a vacuum environment can be maintained within the enclosed structure 20 of the source collector module SO. The EUV radiation emitting plasma 210 can be formed by a discharge-generated plasma radiation source. EUV radiation can be generated by a gas or vapor (e.g., Xe gas, Li vapor, or Sn vapor), wherein a very hot plasma 210 is formed to emit radiation in the EUV range of the electromagnetic spectrum. For example, the very hot plasma 210 is formed by a discharge that causes an at least partially ionized plasma. A partial pressure of, for example, 10 Pa of Xe, Li, Sn vapor, or any other suitable gas or vapor may be required to effectively generate the radiation. In an embodiment, an excited tin (Sn) plasma is provided to generate the EUV radiation.

[0139] Radiation emitted by plasma 210 passes from source chamber 211 into collector chamber 212 via an optional gas barrier or contamination trap 230 (also referred to in some cases as a contamination barrier or fin trap), which is positioned in or behind an opening of source chamber 211. Contamination trap 230 may include a channel structure. Contamination trap 230 may also include a gas barrier or a combination of a gas barrier and a channel structure. Herein, contamination trap 230 or contamination barrier is further referred to as including at least a channel structure, as is known in the art.

[0140] The collector chamber 212 may include a radiation collector CO, which may be a so-called grazing incidence collector. The radiation collector CO has an upstream radiation collector side 251 and a downstream radiation collector side 252. Radiation passing through the collector CO may be reflected by the grating spectral filter 240 to be focused at a virtual source point IF along the optical axis indicated by the dotted line 'O'. The virtual source point IF is often referred to as an intermediate focus, and the source collector module is arranged such that the intermediate focus IF is positioned at or near the opening 219 of the enclosure structure 220. The virtual source point IF is an image of the radiation-emitting plasma 210.

[0141] The radiation then passes through an illumination system IL, which may include a faceted field mirror arrangement 22 and a faceted pupil mirror arrangement 24, which are arranged to provide a desired angular distribution of the radiation beam 21 at the patterning device MA, and a desired uniformity of radiation intensity at the patterning device MA. When the radiation beam 21 reflects at the patterning device MA (held by the support structure MT), a patterned beam 26 is formed, and the patterned beam 26 is imaged by the projection system PS via reflective elements 28, 30 onto a substrate W held by a substrate table WT.

[0142] Typically, more elements may be present in the illumination optics unit IL and the projection system PS than shown. A grating spectral filter 240 may optionally be present depending on the type of lithographic apparatus. Furthermore, more mirrors may be present than shown in the figures, e.g., more than 100 mirrors may be present. Figure 13 As shown in , there may be 1 to 6 additional reflective elements in the projection system PS.

[0143] like Figure 13 The collector optic CO shown in FIG is depicted as a nested collector with grazing incidence reflectors 253, 254, and 255, which is merely an example of a collector (or collector mirror). The grazing incidence reflectors 253, 254, and 255 are arranged axially symmetrically about the optical axis O, and this type of collector optic CO is desirably used in conjunction with a discharge produced plasma radiation source.

[0144] Alternatively, the source collector module SO may be as follows Figure 14 Part of an LPP radiation system is shown. The laser LAS is arranged to deposit laser energy into a fuel such as xenon (Xe), tin (Sn), or lithium (Li), thereby generating a highly ionized plasma 210 with an electron temperature of several 10 eV. Energetic radiation generated during deexcitation and recombination of these ions is emitted from the plasma, collected by collector optics CO at near normal incidence, and focused onto an opening 221 in an enclosure 220.

[0145] The concepts disclosed herein can simulate or mathematically model any general imaging system for imaging sub-wavelength features and may be particularly useful for emerging imaging technologies capable of producing wavelengths of progressively smaller sizes. Emerging technologies already in use include EUV (extreme ultraviolet) lithography, which can produce wavelengths of 193 nm using ArF lasers and even 157 nm using fluorine lasers. Furthermore, EUV lithography can produce wavelengths in the 20 nm to 5 nm range using synchrotrons or by bombarding materials (solid or plasma) with high-energy electrons, thereby generating photons in this range.

[0146] Although the concepts disclosed herein may be used for imaging on substrates such as silicon wafers, it should be understood that the disclosed concepts may be used in any type of lithographic imaging system, for example, a lithographic imaging system for imaging on substrates other than silicon wafers.

[0147] Although specific reference may be made herein to the use of embodiments in IC manufacturing, it should be understood that the embodiments herein may have many other possible applications. For example, they may be applied to the manufacture of integrated optical systems, guidance and detection patterns for magnetic domain memories, liquid crystal displays (LCDs), thin-film magnetic heads, microelectromechanical systems (MEMs), and the like. Those skilled in the art will understand that, in the context of such alternative applications, any use of the terms "reticle," "wafer," or "die" herein may be considered synonymous or interchangeable with the more general terms "patterning device," "substrate," or "target portion," respectively. The substrates referred to herein may be processed before or after exposure in, for example, a track unit (a tool that typically applies a resist layer to a substrate and develops the exposed resist), a metrology tool, and / or an inspection tool. Where applicable, the disclosure herein may be applied to these and other substrate processing tools. Furthermore, a substrate may be processed more than once, for example to form a multi-layer IC, such that the term "substrate" as used herein may also refer to a substrate that already contains multiple processed layers.

[0148] In this document, the terms "radiation" and "beam" as used herein encompass all types of electromagnetic radiation, including ultraviolet radiation (e.g., having a wavelength of about 365 nm, about 248 nm, about 193 nm, about 157 nm, or about 126 nm) and extreme ultraviolet (EUV) radiation (e.g., having a wavelength in the range of 5 nm-20 nm); and particle beams (such as ion beams or electron beams).

[0149] As used herein, the terms "optimize" and "optimize" refer to or indicate adjusting a patterning apparatus (e.g., a lithographic apparatus), a patterning process, or the like so that the result and / or process has more desirable properties, such as a more accurate projection of the design pattern on the substrate, a larger process window, or the like. Thus, as used herein, the terms "optimize" and "optimize" refer to or indicate identifying one or more values ​​of one or more parameters that provide an improvement in at least one relevant metric compared to an initial setting of one or more values ​​of the one or more parameters (e.g., a local optimization). "Optimal" and other related terms should be interpreted accordingly. In embodiments, optimization steps may be applied iteratively to provide further improvements in one or more metrics.

[0150] Aspects of the present invention may be implemented in any form factor. For example, embodiments may be implemented by one or more suitable computer programs carried on a suitable carrier medium, which may be a tangible carrier medium (e.g., a disk) or an intangible carrier medium (e.g., a communication signal). Embodiments of the present invention may be implemented using a suitable device, particularly a programmable computer running a computer program configured to implement the methods described herein. Thus, embodiments of the present disclosure may be implemented in hardware, firmware, software, or any combination thereof. Embodiments of the present disclosure may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by one or more processors. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing device). For example, a machine-readable medium may include read-only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustic, or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.), and the like. Furthermore, firmware, software, programs, and instructions may be described herein as performing specific actions. However, it should be understood that these descriptions are for convenience only and that these actions actually result from a computing device, processor, controller or other device executing firmware, software, routines, instructions or the like.

[0151] In the block diagrams, the components shown are depicted as discrete functional blocks, but the embodiments are not limited to systems in which the functionality described herein is organized as shown. The functionality provided by each component may be provided by software or hardware modules organized differently than currently depicted, for example, such software or hardware may be mixed, combined, replicated, decomposed, distributed (e.g., within a data center or geographically), or otherwise organized differently. The functionality described herein may be provided by one or more processors of one or more computers executing code stored on a tangible, non-transitory, machine-readable medium. In some cases, a third-party content delivery network may host some or all of the information transmitted over the network, in which case, when information (e.g., content) is deemed to be supplied or otherwise provided, the information may be provided by sending instructions to retrieve the information from the content delivery network.

[0152] Unless otherwise specifically stated, as is apparent from the discussion, discussions throughout this specification utilizing terms such as "process," "compute," "calculate," "determine," etc., will be understood to refer to actions or processes of a specific apparatus, such as a special purpose computer or similar special purpose electronic processing / computing device.

[0153] The embodiments of the present disclosure can be further described by the following clauses.

[0154] 1. A method for determining a mask pattern for a target pattern to be printed on a substrate, the method comprising:

[0155] dividing a portion of a design layout including a target pattern into a plurality of cells with reference to a given position on the target pattern;

[0156] allocating a plurality of variables within a specific cell among the plurality of cells, the specific cell including the target pattern or a portion of the target pattern; and

[0157] Determining a mask pattern for the target pattern based on a performance metric of a patterning process based on the values ​​of the plurality of variables, wherein determining the mask pattern comprises:

[0158] simulating the patterning process using the target pattern and the plurality of variables to determine values ​​of the plurality of variables based on the performance metric; and

[0159] A mask pattern for the target pattern is generated based on the determined values ​​of the plurality of variables.

[0160] 2. The method of clause 1, wherein partitioning the portion of the design layout is based on a Voronoi method, wherein a boundary of each of the plurality of cells is determined based on a distance between the boundary and a given location on the target pattern.

[0161] 3. The method of clause 2, wherein the boundaries of each cell in the plurality of cells are defined such that a point in each cell is closest to the given location compared to other locations within the design layout.

[0162] 4. A method according to any of clauses 1 to 3, wherein the given position is the centre of the target pattern, a point on an edge of the target pattern, or a point having a predefined geometric relationship with the target pattern.

[0163] 5. A method as described in any of clauses 1-4, wherein the design layout is associated with a first coordinate system and the plurality of cells are associated with a second coordinate system, wherein values ​​of the plurality of variables are expressed in the second coordinate system and can be converted into values ​​expressed in the first coordinate system.

[0164] 6. A method according to clause 5, wherein the second coordinate system comprises: an origin at a base point of each cell; a first axis perpendicular to the edge; and a second axis perpendicular to the first axis.

[0165] 7. A method according to clause 6, wherein the base point of the unit is a point placed at an edge of the target pattern.

[0166] 8. The method of any one of clauses 5-7, wherein determining the mask pattern is an iterative process comprising:

[0167] (a) adjusting the value of one or more variables among a plurality of variables of the specific unit;

[0168] (b) converting the adjusted values ​​of the one or more variables to a first coordinate system of the design layout;

[0169] (c) determining a performance metric of the patterning process by simulating the patterning process using the transformed values ​​of the one or more variables;

[0170] (d) determining whether the performance metric is within an expected performance range;

[0171] (e) in response to the performance metric being within a desired performance range, determining the mask pattern based on the adjusted value; and

[0172] (f) In response to the performance metric not being within the desired performance range, performing (a)-(e).

[0173] 9. The method of clause 8, wherein converting the adjusted values ​​of the one or more variables comprises:

[0174] establishing a correlation between a first coordinate system of the design layout and a second coordinate system of the plurality of cells;

[0175] transforming the adjusted values ​​of the one or more variables from the second coordinate system to a first coordinate system of the design layout based on the correlation; and

[0176] The patterning process is simulated using the transformed values ​​of the one or more variables.

[0177] 10. A method according to any one of clauses 1 to 9, wherein the plurality of variables are associated with a plurality of pixels and the value of a given variable in the plurality of variables is an intensity associated with a given pixel or combination of pixels in the plurality of pixels, wherein the intensity indicates an edge of a feature to be included in the mask pattern.

[0178] 11. The method of any one of clauses 1-10, wherein generating a mask pattern for the target pattern comprises:

[0179] The values ​​of the plurality of variables are converted into a pixelated image that is a mathematical representation of a grayscale mask image or that generates a curved mask pattern as a level set function.

[0180] 12. The method of any one of clauses 1 to 11, further comprising:

[0181] applying the values ​​of the plurality of variables determined using the target pattern to other instances of the target pattern in the design layout; and

[0182] A mask pattern is determined based on the values ​​applied to the instances of the target pattern to cause the plurality of instances of the target pattern to be modified to generate the mask pattern.

[0183] 13. The method of any one of clauses 1 to 12, further comprising:

[0184] determining a symmetric portion between the plurality of cells or within the specific cell; and

[0185] The symmetric portion of each of the plurality of cells is assigned the same set of variables.

[0186] 14. A method according to item 13, wherein the symmetric part is determined based on geometric similarity between the multiple units or within the specific unit.

[0187] 15. The method of any one of clauses 1 to 14, further comprising:

[0188] An optical proximity correction (OPC) process is performed using the mask pattern as an initial pattern, wherein the OPC process includes modifying the mask pattern to determine an optical proximity corrected mask pattern.

[0189] 16. A method according to any one of clauses 1 to 15, wherein the performance metric includes: an edge positioning error between the target pattern and a simulated pattern generated by a simulated patterning process, a number of overprints and underprints of a mask pattern compared to the target pattern, a critical dimension (CD) of the simulated pattern, and / or a CD error between the simulated pattern and the target pattern.

[0190] 17. The method of any one of clauses 1 to 16, further comprising:

[0191] classifying the values ​​of the plurality of variables of the plurality of cells based on the geometry of the corresponding target pattern;

[0192] storing the values ​​of the plurality of variables in a result store; and

[0193] A mask pattern corresponding to the full chip layout is determined based on the result library.

[0194] 18. The method of clause 17, wherein determining a mask pattern for the full chip layout comprises:

[0195] identifying a pattern of the full-chip layout by geometrically matching the full-chip layout with a target pattern stored in the result library;

[0196] extracting values ​​of a plurality of variables corresponding to the identified pattern; and

[0197] The extracted values ​​are applied to determine a mask pattern for the full chip layout.

[0198] 19. A non-transitory computer-readable medium comprising instructions that, when executed by one or more processors, result in operations comprising:

[0199] dividing a portion of a design layout including a target pattern into a plurality of cells with reference to a given position on the target pattern;

[0200] allocating a plurality of variables within a specific cell among the plurality of cells, the specific cell including the target pattern or a portion of the target pattern; and

[0201] Determining a mask pattern for the target pattern based on the values ​​of the plurality of variables such that a performance metric of a patterning process using the mask pattern is within a desired performance range, wherein determining the mask pattern comprises:

[0202] simulating the patterning process using the target pattern and the plurality of variables to determine values ​​of the plurality of variables that result in a performance metric of the patterning process within a desired performance range; and

[0203] A mask pattern for the target pattern is generated based on the determined values ​​of the plurality of variables.

[0204] 20. The non-transitory computer-readable medium of clause 19, wherein partitioning a portion of the design layout is based on a Voronoi method, wherein a boundary of each of the plurality of cells is determined based on a distance between the boundary and a given location on the target pattern.

[0205] 21. The non-transitory computer-readable medium of any of clauses 19-20, wherein the design layout is associated with a first coordinate system and the plurality of cells are associated with a second coordinate system, wherein values ​​of the plurality of variables are in the second coordinate system and are convertible to values ​​in the first coordinate system.

[0206] 22. The non-transitory computer-readable medium of clause 21, wherein the second coordinate system is defined such that the origin is at a base point of each cell, a first axis is perpendicular to an edge, and a second axis is perpendicular to the first axis.

[0207] 23. The non-transitory computer-readable medium of any of clauses 21-22, wherein determining the mask pattern is an iterative process comprising:

[0208] (a) adjusting the value of one or more variables among a plurality of variables of the specific unit;

[0209] (b) converting the adjusted values ​​of the one or more variables to a first coordinate system of the design layout;

[0210] (c) determining a performance metric of the patterning process by simulating the patterning process using the transformed values ​​of the one or more variables;

[0211] (d) determining whether the performance metric is within an expected performance range;

[0212] (e) in response to the performance metric being within a desired performance range, determining the mask pattern based on the adjusted value; and

[0213] (f) In response to the performance metric not being within the desired performance range, performing (a)-(e).

[0214] 24. The non-transitory computer-readable medium of clause 23, wherein converting the adjusted values ​​of the one or more variables comprises:

[0215] establishing a correlation between a first coordinate system of the design layout and a second coordinate system of the plurality of cells;

[0216] transforming the adjusted values ​​of the one or more variables from the second coordinate system to a first coordinate system of the design layout based on the correlation; and

[0217] The patterning process is simulated using the transformed values ​​of the one or more variables.

[0218] 25. A non-transitory computer-readable medium according to any of clauses 19-24, wherein the plurality of variables are associated with a plurality of pixels, and the value of a given variable in the plurality of variables is an intensity associated with a given pixel or combination of pixels in the plurality of pixels, wherein the intensity indicates an edge of a feature to be included in the mask pattern.

[0219] 26. The non-transitory computer-readable medium of any of clauses 19-25, further causing operations comprising:

[0220] applying the values ​​of the plurality of variables determined using the target pattern to other instances of the target pattern in the design layout; and

[0221] A mask pattern is determined based on the values ​​applied to the instances of the target pattern such that all instances of the target pattern are modified in a consistent manner to generate the mask pattern.

[0222] 27. The non-transitory computer-readable medium of any of clauses 19-26, further causing operations comprising:

[0223] determining a symmetric portion between the plurality of cells or within the specific cell; and

[0224] The symmetric portion of each of the plurality of cells is assigned the same set of variables.

[0225] 28. The non-transitory computer-readable medium of any of clauses 19-27, further comprising:

[0226] classifying the values ​​of the plurality of variables of the plurality of cells based on the geometry of the corresponding target pattern;

[0227] storing the values ​​of the plurality of variables in a result store; and

[0228] A mask pattern corresponding to the full chip layout is determined based on the result library.

[0229] 29. The non-transitory computer-readable medium of clause 28, wherein determining a mask pattern for the full chip layout comprises:

[0230] identifying a pattern of the full-chip layout by geometrically matching the full-chip layout with a target pattern stored in the result library;

[0231] extracting values ​​of a plurality of variables corresponding to the identified pattern; and

[0232] The extracted values ​​are applied to determine a mask pattern for the full chip layout.

[0233] The reader should understand that this application describes several inventions. These inventions are not separated into multiple isolated patent applications, but rather the inventions are grouped into a single file because their related subject matter contributes to the economy of the application process. However, the unique advantages and aspects of these inventions should not be lumped together. In some cases, embodiments solve all of the deficiencies mentioned herein, but it should be understood that the invention is independently useful and some embodiments only solve a subset of these problems or provide other unmentioned benefits that will be apparent to those skilled in the art reviewing this disclosure. Due to cost constraints, some of the inventions disclosed herein may not be claimed at present and may be claimed in a later filing, such as a continuing application or by amendment of the present claims. Similarly, due to space limitations, neither the Abstract nor the Summary of the Invention section of this document should be considered to include a comprehensive enumeration of all of these inventions or all aspects of these inventions.

[0234] It should be understood that the description and drawings are not intended to limit the disclosure to the particular forms disclosed, but on the contrary, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

[0235] In view of this description, modifications and alternative embodiments of various aspects of the present invention will be apparent to those skilled in the art. Therefore, this description and the drawings are to be interpreted as illustrative only and are intended to teach those skilled in the art about the general manner of carrying out the invention. It should be understood that the forms of the invention shown and described herein are to be regarded as examples of embodiments. The elements and materials shown and described herein may be substituted, parts and processes may be reversed or omitted, certain features may be utilized independently, and embodiments or features of embodiments may be combined, all of which will be apparent to those skilled in the art after having the benefit of this description. Changes may be made to the elements described herein without departing from the spirit and scope of the invention as described in the appended claims. The headings used herein are for organizational purposes only and are not meant to limit the scope of the specification.

[0236] As used throughout this application, the word "may" is used in a permissive sense (i.e., indicating a possibility), rather than a mandatory sense (i.e., indicating a must). Words such as "include," "comprise," and "including" include, but are not limited to. As used throughout this application, the singular forms "a," "an," and "the" include plural representations unless the context clearly indicates otherwise. Thus, for example, although other terms and phrases (such as "one or more") are used with respect to one or more elements, references to "a" or "an" element also include combinations of two or more elements. Unless otherwise specified, the term "or" is non-exclusive, i.e., encompasses both "and" and "or." Terms describing conditional relationships (e.g., "in response to X, Y," "on X, Y," "if X, Y," "when X, Y," etc.) encompass causal relationships, where the antecedent is a necessary causal condition, the antecedent is a sufficient causal condition, or the antecedent is a common causal condition of the result, e.g., "state X occurs when condition Y is achieved" is common to "X occurs only when Y occurs" and "X occurs when Y and Z occur." Such conditional relationships are not limited to results obtained immediately following the antecedent, as some results may be delayed, and in conditional statements, antecedents are linked to their results, e.g., the antecedent is related to the likelihood of the result occurring. Unless otherwise specified, a statement that multiple properties or functions are mapped to multiple objects (e.g., one or more processors performing steps A, B, C, and D) encompasses all such properties or functions mapped to all such objects, as well as subsets of properties or functions mapped to subsets of properties or functions (e.g., all processors each performing steps A-D, and processor 1 performing steps A, processor 2 performing steps B and a portion of step C, and processor 3 performing a portion of step C and step D). Furthermore, unless otherwise specified, a statement that a value or action is "based on" another condition or value encompasses both cases where the condition or value is the sole factor and cases where the condition or value is one factor among multiple factors. Unless otherwise specified, a statement that "every" instance of some set has some property should not be construed to exclude cases where some other identical or similar members of the larger set do not have that property; that is, "each" does not necessarily mean "every" and "everyone." References to selections from a range include the endpoints of the range.

[0237] In the above description, any process, description or box in the flowchart should be understood to represent a module, segment or portion of code including one or more executable instructions for implementing specific logical functions or steps in the process, and alternative implementations are included within the scope of the exemplary embodiments of this improvement, in which functions may not be performed in the order shown or discussed, including substantially simultaneously or in the reverse order, depending on the functions involved, as will be understood by those skilled in the art.

[0238] To the extent that particular U.S. patents, U.S. patent applications, PCT patent applications, or publications or other materials (e.g., articles) are incorporated by reference, the text of such U.S. patents, U.S. patent applications, and other materials is incorporated by reference only to the extent that there is no conflict between such materials and the statements and drawings set forth herein. In the event of a conflict, any such conflicting text in the incorporated by reference U.S. patents, U.S. patent applications, and other materials is expressly not incorporated by reference herein.

[0239] Although certain embodiments have been described, these embodiments are provided by way of example only and are not intended to limit the scope of the present disclosure. Indeed, the novel methods, devices, and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions, and changes in the form of the methods, devices, and systems described herein may be made without departing from the spirit of the present disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as fall within the scope and spirit of the present disclosure.

Claims

1. A method for determining a mask pattern for a target pattern to be printed on a substrate, the method comprising: dividing a portion of a design layout including the target pattern into a plurality of cells with reference to a given position on the target pattern; allocating a plurality of variables within a specific cell among the plurality of cells, the specific cell including the target pattern or a portion of the target pattern; as well as Determining a mask pattern for the target pattern based on a performance metric of a patterning process based on the values ​​of the plurality of variables, wherein determining the mask pattern comprises: simulating the patterning process using the target pattern and the plurality of variables to determine values ​​of the plurality of variables based on the performance metric; and generating a mask pattern for the target pattern based on the determined values ​​of the plurality of variables; The design layout is associated with a first coordinate system, and the plurality of cells are associated with a second coordinate system, wherein values ​​of the plurality of variables are represented in the second coordinate system and can be converted into values ​​represented in the first coordinate system.

2. The method according to claim 1, wherein Partitioning the design layout in part is based on a Voronoi method, wherein a boundary of each of the plurality of cells is determined based on a distance between the boundary and a given location on the target pattern.

3. The method according to claim 2, wherein: Boundaries of each cell of the plurality of cells are defined such that a point in each cell is closest to the given location compared to other locations within the design layout.

4. The method according to claim 1, wherein The given position is the center of the target pattern, a point on an edge of the target pattern, or a point having a predefined geometric relationship with the target pattern.

5. The method according to claim 1, wherein Determining the mask pattern is an iterative process, the iterative process comprising: (a) adjusting the value of one or more variables among a plurality of variables of the specific unit; (b) converting the adjusted values ​​of the one or more variables to a first coordinate system of the design layout; (c) determining a performance metric of the patterning process by simulating the patterning process using the transformed values ​​of the one or more variables; (d) determining whether the performance metric is within an expected performance range; (e) in response to the performance metric being within a desired performance range, determining the mask pattern based on the adjusted value; and (f) In response to the performance metric not being within the desired performance range, performing (a)-(e).

6. The method according to claim 5, wherein: Converting the adjusted values ​​of the one or more variables includes: establishing a correlation between a first coordinate system of the design layout and a second coordinate system of the plurality of cells; transforming the adjusted values ​​of the one or more variables from the second coordinate system to a first coordinate system of the design layout based on the correlation; and The patterning process is simulated using the transformed values ​​of the one or more variables.

7. The method according to claim 1, wherein The plurality of variables are associated with a plurality of pixels, and a value of a given variable of the plurality of variables is an intensity associated with a given pixel or combination of pixels of the plurality of pixels, wherein the intensity is indicative of an edge of a feature to be included in the mask pattern.

8. The method according to claim 1, wherein Generating a mask pattern for the target pattern includes: The values ​​of the plurality of variables are converted into a pixelated image that is a mathematical representation of a grayscale mask image or that generates a curved mask pattern as a level set function.

9. The method according to claim 1, further comprising: applying the values ​​of the plurality of variables determined using the target pattern to other instances of the target pattern in the design layout; as well as A mask pattern is determined based on the values ​​applied to the instances of the target pattern to cause the plurality of instances of the target pattern to be modified to generate the mask pattern.

10. The method according to claim 1, further comprising: determining a symmetric portion between the plurality of units or within the specific unit; as well as The symmetric portion of each of the plurality of cells is assigned the same set of variables.

11. The method according to claim 10, wherein: The symmetric portion is determined based on geometric similarities between the plurality of cells or within the specific cell.

12. The method according to claim 1, wherein The performance metrics include edge positioning error between the target pattern and a simulated pattern generated by a simulated patterning process, number of overprinting and underprinting of mask features compared to the target pattern, critical dimension (CD) of the simulated pattern, and / or CD error between the simulated pattern and the target pattern.

13. The method according to claim 1, further comprising: classifying the values ​​of the plurality of variables of the plurality of cells based on the geometry of the corresponding target pattern; storing the values ​​of the plurality of variables in a result store; as well as A mask pattern corresponding to the full chip layout is determined based on the result library.

14. The method according to claim 13, wherein Determining a mask pattern for the full chip layout includes: identifying a pattern of the full-chip layout by geometrically matching the full-chip layout with a target pattern stored in the result library; extracting values ​​of a plurality of variables corresponding to the identified pattern; and The extracted values ​​are applied to determine a mask pattern for the full chip layout.

15. A non-transitory computer-readable medium comprising instructions that, when executed by one or more processors, cause the one or more processors to perform the method according to any one of claims 1-14.

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