Shift register, driving method thereof, gate driver, and display device

Abstract

Provided are a shift register, a driving method thereof, a gate driver, and a display device. The shift register includes: an input circuit that transmits an input signal to a first node and transmits a first power supply signal to a second node under the control of a first clock signal, and transmits the first clock signal to the second node under the control of the level of the first node; a control circuit that transmits a second power supply signal to the first node under the control of the level of the second node and a second clock signal, transmits the second clock signal to a third node under the control of the level of a fourth node and / or the first node, and transmits the second power supply signal to the third node under the control of the level of the second node; a pull-down control circuit; and an output circuit that transmits a fourth power supply signal to a signal output terminal under the control of the level of the third node, and transmits a third power supply signal to the signal output terminal under the control of the level of a fifth node. The pull-down control circuit controls the level of the fifth node independently of the first clock signal.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly relates to a shift register, a driving method thereof, a gate driver, and a display device. Background Art

[0002] In a display panel using a self-luminous device such as a light-emitting diode (LED), the luminous efficiency of the self-luminous device decreases as the current density decreases. When the current flowing through the self-luminous device reaches a certain amount or less, a phenomenon of uneven brightness occurs, thereby affecting the display effect of the display panel at low gray levels. Therefore, it is necessary to use a Pulse Width Modulation (PWM) signal to control the light-emitting time to achieve low gray level display.

[0003] However, when using a high-frequency PWM signal to control the LED light-emitting time in a display panel, the shift register circuit adopted by the existing gate driver has defects. Summary of the Invention

[0004] In one aspect, the present disclosure provides a shift register, including: an input circuit connected to a signal input terminal, a first clock terminal, a first power supply terminal, a first node, and a second node, and configured to transmit an input signal provided by the signal input terminal to the first node under the control of a first clock signal input from the first clock terminal, transmit a first power supply signal provided by the first power supply terminal to the second node under the control of the first clock signal, and transmit the first clock signal to the second node under the control of the level at the first node; a control circuit connected to the first node, the second node, a second power supply terminal, a second clock terminal, a third node, and a fourth node, and configured to transmit a second power supply signal provided by the second power supply terminal to the first node under the control of the level at the second node and a second clock signal input from the second clock terminal, transmit the second clock signal to the third node under the control of the level at at least one of the fourth node and the first node, and transmit the second power supply signal to the third node under the control of the level at the second node; a pull-down control circuit connected to the second clock terminal, the first power supply terminal, the second power supply terminal, the third node, and a fifth node; and an output circuit connected to the third node, a third power supply terminal, a fourth power supply terminal, the fifth node, and a signal output terminal, and configured to transmit a fourth power supply signal provided by the fourth power supply terminal to the signal output terminal under the control of the level at the third node, and transmit a third power supply signal provided by the third power supply terminal to the signal output terminal under the control of the level at the fifth node. The pull-down control circuit is configured to control the level of the fifth node independently of the first clock signal.

[0005] In some embodiments, the pull-down control circuit is configured to provide a current path between the second power supply terminal and the fifth node under the control of the level at the third node, provide a current path between the first power supply terminal and the fifth node under the control of the first power supply signal, and maintain a voltage difference between the fifth node and the second clock terminal when the fifth node is floating. Among them, the ability of the pull-down control circuit to drive the fifth node through the current path between the second power supply terminal and the fifth node is greater than the ability to drive the fifth node through the current path between the first power supply terminal and the fifth node.

[0006] In some embodiments, the pull-down control circuit includes: a first pull-down control transistor, a second pull-down control transistor, and a pull-down control capacitor. The control electrode of the first pull-down control transistor is connected to the third node, the first electrode is connected to the second power supply terminal, and the second electrode is connected to the fifth node. The control electrode of the second pull-down control transistor is connected to the first power supply terminal, the first electrode is connected to the fifth node, and the second electrode is connected to the first power supply terminal. The first electrode of the pull-down control capacitor is connected to the fifth node, and the second electrode is connected to the second clock terminal.

[0007] In some embodiments, the aspect ratio of the first pull-down control transistor is greater than the aspect ratio of the second pull-down control transistor.

[0008] In some embodiments, the control circuit is configured to transmit the second clock signal to the third node under the control of the level at the fourth node. The shift register further includes: an anti-leakage circuit, which is connected to the first node, the first power supply terminal, and the fourth node, and is configured to control the electrical connection between the first node and the fourth node under the control of the first power supply signal.

[0009] In some embodiments, the anti-leakage circuit includes an anti-leakage transistor, the control electrode of the anti-leakage transistor is connected to the first power supply terminal, the first electrode is connected to the first node, and the second electrode is connected to the fourth node.

[0010] In some embodiments, the control circuit is configured to transmit the second clock signal to the third node under the control of the level at the fourth node, and includes: a first control sub-circuit connected to the second node, the second clock terminal, the second power supply terminal, and the first node, and configured to transmit the second power supply signal to the first node under the control of the level at the second node and the second clock signal; a second control sub-circuit connected to the fourth node, the second clock terminal, and the third node, and configured to transmit the second clock signal to the third node under the control of the level at the fourth node, and maintain the voltage difference between the fourth node and the third node when the fourth node is floating; and a third control sub-circuit connected to the second node, the second power supply terminal, and the third node, and configured to transmit the second power supply signal to the third node under the control of the level at the second node, and maintain the voltage difference between the second node and the second power supply terminal when the second node is floating.

[0011] In some embodiments, the first control sub-circuit includes a first control transistor and a second control transistor. The control electrode of the first control transistor is connected to the second node, the first electrode is connected to the second power supply terminal, and the second electrode is connected to the first electrode of the second control transistor. The control electrode of the second control transistor is connected to the second clock terminal, and the second electrode is connected to the first node.

[0012] In some embodiments, the second control sub-circuit includes a third control transistor and a first control capacitor. The control electrode of the third control transistor is connected to the fourth node, the first electrode is connected to the third node, and the second electrode is connected to the second clock terminal. The first electrode of the first control capacitor is connected to the fourth node, and the second electrode is connected to the third node.

[0013] In some embodiments, the third control sub-circuit includes a fourth control transistor and a second control capacitor. The control electrode of the fourth control transistor is connected to the second node, the first electrode is connected to the second power supply terminal, and the second electrode is connected to the third node. The first electrode of the first control capacitor is connected to the second node, and the second electrode is connected to the second power supply terminal.

[0014] In some embodiments, the input circuit includes: a first input sub-circuit connected to the signal input terminal, the first clock terminal, and the first node, and configured to transmit the input signal to the first node under the control of the first clock signal; and a second input sub-circuit connected to the first power supply terminal, the first clock terminal, the first node, and the second node, and configured to transmit the first power supply signal to the second node under the control of the first clock signal, and transmit the first clock signal to the second node under the control of the level at the first node.

[0015] In some embodiments, the first input sub-circuit includes a first input transistor, a control electrode of the first input transistor is connected to the first clock terminal, a first pole is connected to the signal input terminal, and a second pole is connected to the first node.

[0016] In some embodiments, the second input sub-circuit includes a second input transistor and a third input transistor. A control electrode of the second input transistor is connected to the first node, a first pole is connected to the second node, and a second pole is connected to the first clock terminal. A control electrode of the third input transistor is connected to the first clock terminal, a first pole is connected to the first power supply terminal, and a second pole is connected to the second node.

[0017] In some embodiments, the output circuit includes: a first output sub-circuit connected to the third node, the fourth power supply terminal, and the signal output terminal, and configured to transmit the fourth power supply signal to the signal output terminal under the control of the level at the third node, and a second output sub-circuit connected to the fifth node, the third power supply terminal, and the signal output terminal, and configured to transmit the third power supply signal to the signal output terminal under the control of the level at the fifth node.

[0018] In some embodiments, the first output sub-circuit includes a first output transistor, a control electrode of the first output transistor is connected to the third node, a first pole is connected to the fourth power supply terminal, and a second pole is connected to the signal output terminal.

[0019] In some embodiments, the second output sub-circuit includes a second output transistor, a control electrode of the second output transistor is connected to the fifth node, a first pole is connected to the signal output terminal, and a second pole is connected to the third power supply terminal.

[0020] On the other hand, the present disclosure provides a gate driver including a plurality of cascaded shift registers, and the shift register is the above-mentioned shift register.

[0021] On the other hand, the present disclosure provides a display device including the above-mentioned gate driver.

[0022] In another aspect, the present disclosure provides a method for driving a shift register, where the shift register is the above-mentioned shift register. The method includes: in a first period, applying an input signal with an effective level to the signal input terminal, applying a first clock signal with an effective level to the first clock terminal, and applying a second clock signal with an ineffective level to the second clock terminal, so that the signal output from the output terminal of the shift register has a first level; in a second period, applying an input signal with an ineffective level to the signal input terminal, applying a first clock signal with an ineffective level to the first clock terminal, and applying a second clock signal with an effective level to the second clock terminal, so that the signal output from the output terminal of the shift register has a second level different from the first level; in a third period, applying an input signal with an ineffective level to the signal input terminal, applying a first clock signal with an ineffective level to the first clock terminal, and applying a second clock signal with an ineffective level to the second clock terminal, so that the signal output from the output terminal of the shift register has a first level; in a fourth period, applying an input signal with an ineffective level to the signal input terminal, applying a first clock signal with an effective level to the first clock terminal, and applying a second clock signal with an ineffective level to the second clock terminal, so that the signal output from the output terminal of the shift register has a first level; and in a fifth period, applying an input signal with an ineffective level to the signal input terminal, applying a first clock signal with an ineffective level to the first clock terminal, and applying a second clock signal with an effective level to the second clock terminal, so that the signal output from the output terminal of the shift register has a first level. The first period, the second period, the third period, the fourth period, and the fifth period are periods arranged in chronological order in terms of time. During the first period to the fifth period, applying a first power signal with a constant ineffective level to the first power terminal, applying a second power signal with a constant effective level to the second power terminal, applying a third power signal with a constant first level to the third power terminal, and applying a fourth power signal with a constant second level to the fourth power terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawings are used to provide a further understanding of the present disclosure, and constitute a part of the specification, and are used to explain the present disclosure together with the following embodiments, but do not constitute a limitation to the present disclosure.

[0024] Figure 1A and Figure 1B is a block diagram of a shift register according to some embodiments of the present disclosure;

[0025] Figure 2 is a block diagram of a shift register according to some embodiments of the present disclosure;

[0026] Figure 3 is a circuit diagram of a shift register according to some embodiments of the present disclosure;

[0027] Figure 4 is a timing diagram showing the operation of a shift register according to some embodiments of the present disclosure;

[0028] Figure 5 is a block diagram of a gate driver according to some embodiments of the present disclosure;

[0029] Figure 6 is a timing diagram showing the operation of a gate driver according to some embodiments of the present disclosure;

[0030] Figure 7 is a circuit diagram of a shift register of a comparative example; and

[0031] Figure 8 is a timing diagram of a gate driver applying the shift register of the comparative example. Detailed Embodiments

[0032] To enable those skilled in the art to better understand the technical solutions of the present disclosure, the present disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0033] In this document, "effective level" refers to a voltage that can control the conduction of a corresponding transistor, and "invalid level" refers to a voltage that can control the turn-off of a corresponding transistor. For example, when the transistor is an N-type transistor, the effective level can refer to a high level, and the invalid level can refer to a low level. For example, when the transistor is a P-type transistor, the effective level can refer to a low level, and the invalid level can refer to a high level.

[0034] In this document, for a transistor element, the control electrode refers to the gate of the transistor, and one of the first electrode and the second electrode is the source of the transistor, and the other is the drain of the transistor.

[0035] In this document, taking each transistor as a P-type transistor as an example, the circuit structure and working principle of the shift register in the embodiments of the present disclosure are described. However, the present disclosure is not limited thereto, and those skilled in the art can use one or more N-type transistors to implement the circuits in the embodiments of the present disclosure and make corresponding adjustments to the levels of various signals such as input signals, control signals, and / or clock signals. These circuit implementation manners and signal level adjustments also fall within the protection scope of the present disclosure.

[0036] In this document, when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be an intermediate element.

[0037] In self-emitting device display technologies such as active matrix organic light emitting diode (AMOLED) displays and micro light emitting diode (MicroLED) displays, two types of gate drivers (Gate driver On Array, GOA) are usually required. One is the GOA circuit that controls the opening or closing of the gate lines connected to each row of pixels, simply referred to as Gate GOA. The other is the emission control GOA circuit that controls the light emission of each row of pixels, simply referred to as the Emission GOA circuit. The Emission GOA is usually formed by cascading multiple shift registers to transmit the light emission control signals for pixel rows row by row.

[0038] To achieve a better low gray-scale display effect, a combination of pulse width modulation and pulse amplitude modulation is usually used to control light emission. When using a pulse width modulation signal to control the light emission time of a self-emitting device, to reduce flicker, a high-frequency PWM signal (referred to as the Hf signal hereinafter) can be used to control the light emission time of the LED. To minimize signal interference, during the input period of the Hf signal, other signals (such as clock signals, etc.) need to be set to an invalid level all the time. However, a shift register is usually designed to output normally based on a pair of continuously working clock signals (for example, these two clock signals alternately have an effective level). If both of these clock signals are at an invalid level during the input period of the Hf signal, the shift register cannot output the desired signal. When such a shift register is used to form the Emission GOA, it will cause the pulse widths of the light emission control signals of different pixel rows to be different, resulting in different light emission brightnesses of different pixel rows and affecting the display quality.

[0039] For example, in one working cycle of the Emission GOA, the desired output waveform of each shift register is: having an invalid level pulse during the output period and maintaining an effective level during other periods. The output periods of each stage of the shift register appear sequentially in time and do not overlap with each other. During the input period of the Hf signal, a normal shift register cannot maintain an effective level as expected. Especially when the input period of the Hf signal immediately follows the output period of this shift register, during the input period of the Hf signal, the output waveform of the shift register is still the above-mentioned invalid level pulse during the output period, rather than the expected effective level.

[0040] Therefore, the present disclosure particularly provides a shift register, its driving method, a gate driver, and a display device, which basically eliminate one or more of the problems caused by the limitations and deficiencies of the prior art.

[0041] In one aspect, the present disclosure provides a shift register, which includes an input circuit, a control circuit, an output circuit, and a pull-down control circuit, wherein the pull-down control circuit is configured to control the level of the fifth node independently of the first clock signal.

[0042] Figure 1A and Figure 1B FIG. shows a block diagram of a shift register according to an embodiment of the present disclosure.

[0043] Referring to Figure 1A , the shift register includes an input circuit 1, a control circuit 2, an output circuit 3, and a pull-down control circuit 4.

[0044] The input circuit 1 is connected to a signal input terminal INPUT, a first clock terminal CK, a first power supply terminal VL, a first node N1, and a second node N2, and is configured to transmit an input signal provided by the signal input terminal INPUT to the first node N1 under the control of a first clock signal input from the first clock terminal CK, transmit a first power supply signal provided by the first power supply terminal VL to the second node N2 under the control of the first clock signal, and transmit the first clock signal to the second node N2 under the control of the level at the first node N1.

[0045] The control circuit 2 is connected to the first node N1, the second node N2, a second power supply terminal VH, a second clock terminal CB, and a third node Carry_Out, and is configured to transmit a second power supply signal provided by the second power supply terminal VH to the first node N1 under the control of the level at the second node N2 and a second clock signal input from the second clock terminal CB, transmit the second clock signal to the third node Carry_Out under the control of the level at the first node N1, and transmit the second power supply signal to the third node Carry_Out under the control of the level at the second node N2.

[0046] The output circuit 3 is connected to the third node Carry_Out, a third power supply terminal VL1, a fourth power supply terminal VH1, a fifth node N5, and a signal output terminal OUTPUT, and is configured to transmit a fourth power supply signal provided by the fourth power supply terminal VH1 to the signal output terminal OUTPUT under the control of the level at the third node Carry_Out, and transmit a third power supply signal provided by the third power supply terminal VL1 to the signal output terminal OUTPUT under the control of the level at the fifth node N5.

[0047] The pull-down control circuit 4 is connected to the second clock terminal CB, the first power supply terminal VL, the second power supply terminal VH, the third node Carry_Out, and the fifth node N5, and is configured to control the level of the fifth node N5 independently of the first clock signal CK.

[0048] In some embodiments, the pull - down control circuit 4 is configured to provide a current path between the second power supply terminal VH and the fifth node N5 under the control of the level at the third node Carry_Out. The pull - down control circuit 4 is further configured to provide a current path between the first power supply terminal VL and the fifth node N5 under the control of the first power signal, and to maintain the voltage difference between the fifth node N5 and the second clock terminal CB when the fifth node N5 is floating. The ability of the pull - down control circuit 4 to drive the fifth node N5 through the current path between the second power supply terminal VH and the fifth node N5 is greater than the ability to drive the fifth node N5 through the current path between the first power supply terminal VL and the fifth node N5.

[0049] For example, for the case where the invalid level is high, the valid level is low, and the corresponding transistor is a P - type transistor, the pull - down control circuit 4 charges the fifth node N5 under the control of the level at the third node Carry_Out, discharges the fifth node N5 under the control of the first power signal VL, and the charging speed of the pull - down control circuit 4 for the fifth node N5 is greater than the discharging speed for the fifth node N5.

[0050] The first power signal provided by the first power supply terminal VL may have a constant valid level, and the second power signal provided by the second power supply terminal VH may have a constant invalid level. For example, when the valid level is low and the invalid level is high, the first power signal is a low - level power signal, and the second power signal is a high - level power signal.

[0051] Specifically, it is necessary to combine the function of the circuit connected to the output terminal of the shift register and the characteristics of the electronic components in the circuit. For example, if the circuit connected to the output terminal of the shift register is a pixel driving circuit in a display panel, and the electronic components in this circuit include transistors, then it is necessary to design the third power signal provided by the third power supply terminal VL1 to have a constant valid level and the fourth power signal provided by the fourth power supply terminal VH1 to have a constant invalid level according to the working timing of the pixel driving circuit and the conduction type of the transistors. That is, according to the function of the circuit connected to the output terminal of the shift register and the characteristics of the electronic components in the circuit, to determine whether the valid level of the third power signal is high or low, and whether the invalid level of the fourth power signal is high or low. For example, when the output terminal of the shift register is used to provide an enabling signal to a P - type transistor in the pixel driving circuit, the third power signal is a low - level power signal, and the fourth power signal is a high - level power signal.

[0052] In some embodiments, the third power supply terminal VL1 and the first power supply terminal VL may be the same power supply terminal or may be electrically connected to each other, and the fourth power supply terminal VH1 and the second power supply terminal VH may be the same power supply terminal or may be electrically connected to each other. In this case, the transistors constituting the shift register and the transistors in the circuit connected to the output terminal of the shift register have the same conductivity type.

[0053] Figure 1B Another block diagram of a shift register according to an embodiment of the present disclosure is shown. Figure 1B The shown shift register is different from Figure 1A the shown shift register in that Figure 1B the shown shift register further includes a leakage prevention circuit 5, and the control circuit 2 transmits the second clock signal to the third node Carry_Out under the control of the level at the fourth node N4. The other components of the shift register are the same as those described with reference to Figure 1A and the repeated description thereof is omitted herein.

[0054] With reference to Figure 1B , the leakage prevention circuit 5 is connected to the first node N1, the first power supply terminal VL, and the fourth node N4, and is configured to control the electrical connection between the first node N1 and the fourth node N4 under the control of the first power signal. The leakage prevention circuit 5 can reduce the leakage of the corresponding components in the input circuit 1. The control circuit 2 is also connected to the fourth node N4, and different from Figure 1A , the control circuit 2 transmits the second clock signal to the third node Carry_Out under the control of the voltage at the fourth node N4 instead of the first node N1.

[0055] Since the pull-down control circuit 4 can control the level of the fifth node N5 independently of the first clock signal CK, when after the invalid level is output at the signal output terminal OUTPUT (for example, after the period (such as Figure 4 the period t2) immediately following the output of the invalid level at the signal output terminal OUTPUT), when the first clock signal CK and the second clock signal CB are both set to the invalid level, the pull-down control circuit 4 can provide the desired valid level for the fifth node N5, thereby ensuring that the signal output terminal OUTPUT outputs the desired valid level.

[0056] Figure 2 is a block diagram of a shift register according to some embodiments of the present disclosure, which further shows the constitution of the shift register.

[0057] With reference to Figure 2, in some embodiments, the input circuit 1 may include a first input sub-circuit 11 and a second input sub-circuit 12. The first input sub-circuit 11 is connected to the signal input terminal INPUT, the first clock terminal CK, and the first node N1, and is configured to transmit an input signal to the first node N1 under the control of the first clock signal. The second input sub-circuit 12 is connected to the first power supply terminal VL, the first clock terminal CK, the first node N1, and the second node N2, and is configured to transmit a first power supply signal to the second node N2 under the control of the first clock signal, and transmit the first clock signal to the second node N2 under the control of the level at the first node N1.

[0058] In some embodiments, referring to Figure 2 , the control circuit 2 may include a first control sub-circuit 21, a second control sub-circuit 22, and a third control sub-circuit 23. The first control sub-circuit 21 is connected to the second node N2, the second clock terminal CB, the second power supply terminal VH, and the first node N1, and is configured to transmit a second power supply signal to the first node N1 under the control of the level at the second node N2 and the second clock signal. The second control sub-circuit 22 is connected to the fourth node N4, the second clock terminal CB, and the third node Carry_Out, and is configured to transmit the second clock signal to the third node Carry_Out under the control of the level at the fourth node N4, and maintain the voltage difference between the fourth node N4 and the third node Carry_Out when the fourth node N4 is floating. The third control sub-circuit 23 is connected to the second node N2, the second power supply terminal VH, and the third node Carry_Out, and is configured to transmit a second power supply signal to the third node Carry_Out under the control of the level at the second node N2, and maintain the voltage difference between the second node N2 and the second power supply terminal VH when the second node N2 is floating.

[0059] In some embodiments, referring to Figure 2 , the output circuit 3 may include a first output sub-circuit 31 and a second output sub-circuit 32. The first output sub-circuit 31 is connected to the third node Carry_Out, the second power supply terminal VH, and the signal output terminal OUTPUT, and is configured to transmit a fourth power supply signal to the signal output terminal OUTPUT under the control of the level at the third node Carry_Out. The second output sub-circuit 32 is connected to the fifth node N5, the first power supply terminal VL, and the signal output terminal OUTPUT, and is configured to transmit a third power supply signal to the signal output terminal OUTPUT under the control of the level at the fifth node N5.

[0060] It should be noted that although Figure 2 the connection relationships of the circuits in Figure 1B correspond to the shift register shown in Figure 2Each of the sub - circuits shown can be applied to Figure 1A the shift register shown. In this case, the second control sub - circuit 22 is connected to the first node N1 (instead of the fourth node N4), the second clock terminal CB, and the third node Carry_Out, and is configured to transmit the second clock signal to the third node Carry_Out under the control of the level at the first node N1, and maintain the voltage difference between the first node N1 and the third node Carry_Out when the first node N1 is floating. The connection relationships and functions of other sub - circuits can be referred to the description above.

[0061] Figure 3 The circuit diagram of a shift register according to some embodiments of the present disclosure is shown.

[0062] In some embodiments, referring to Figure 3 , the pull - down control circuit 4 may include a first pull - down control transistor M9, a second pull - down control transistor M10, and a pull - down control capacitor C3. The control electrode of the first pull - down control transistor M9 is connected to the third node Carry_Out, the first electrode is connected to the second power supply terminal VH, and the second electrode is connected to the fifth node N5. The control electrode of the second pull - down control transistor M10 is connected to the first power supply terminal VL, the first electrode is connected to the fifth node N5, and the second electrode is connected to the first power supply terminal VL. The first electrode of the pull - down control capacitor C3 is connected to the fifth node N5, and the second electrode is connected to the second clock terminal CB.

[0063] The aspect ratios of the first pull - down control transistor M9 and the second pull - down control transistor M10 can be set such that the driving ability of the first pull - down control transistor M9 is greater than that of the second pull - down control transistor M10, so that the ability of the pull - down control circuit 4 to drive the fifth node Carry_Out through the second power supply terminal VH is greater than the ability to drive the fifth node N5 through the first power supply terminal VL. For example, when the first pull - down control transistor M9 and the second pull - down control transistor M10 are both transistors of the same conduction type, the aspect ratio of the first pull - down control transistor M9 can be greater than that of the second pull - down control transistor M10. As a schematic example, the aspect ratio of the first pull - down control transistor M9 can be 15μm / 5μm, and the aspect ratio of the second pull - down control transistor M10 can be 7μm / 10μm.

[0064] For example, referring to Figure 3, when the first pull-down control transistor M9 and the second pull-down control transistor M10 are turned on simultaneously, since the driving ability of the first pull-down control transistor M9 is greater than that of the second pull-down control transistor M10, the speed at which the pull-down control circuit 4 charges the fifth node N5 is greater than the speed at which it discharges the fifth node N5, and the fifth node N5 is at a high level. When the first pull-down control transistor M9 is turned off and the second pull-down control transistor M10 is turned on, the fifth node N5 can be set to a low level through the second pull-down control transistor M10 until the level of the fifth node N5 drops to turn off the second pull-down control transistor M10. The pull-down control capacitor C3 can maintain the voltage difference between the fifth node N5 and the second clock terminal CB when the fifth node N5 is floating (i.e., both the first pull-down control transistor M9 and the second pull-down control transistor M10 are turned off), thereby maintaining the low level of the fifth node N5.

[0065] In this way, the pull-down control circuit 4 can control the level of the fifth node N5 independently of the first clock signal CK. Therefore, after an invalid level is output at the signal output terminal OUTPUT (for example, after a period (such as Figure 4 the period t2) immediately following the output of the invalid level at the signal output terminal OUTPUT), when the first clock signal CK and the second clock signal CB are both set to the invalid level simultaneously, the pull-down control circuit 4 can provide the desired valid level for the fifth node N5, thereby ensuring that the signal output terminal OUTPUT outputs the desired valid level.

[0066] Continuing to refer to Figure 3 , in some embodiments, the anti-leakage circuit 5 may include an anti-leakage transistor M8. The control electrode of the anti-leakage transistor M8 is connected to the first power supply terminal VL, the first pole is connected to the first node N1, and the second pole is connected to the fourth node N4.

[0067] The anti-leakage transistor M8 can be used to prevent or reduce the leakage of other circuit modules. For example, for the case where the valid level is a low level, when the voltage at the fourth node N4 is too low, the anti-leakage transistor M8 is turned off, thereby electrically disconnecting the first node N1 from the fourth node N4. In this way, the voltage at the first node N1 can be prevented from being too low, thereby alleviating the leakage of other circuit modules such as the input circuit 1.

[0068] Continuing to refer to Figure 3 , in some embodiments, the first control sub-circuit 21 may include a first control transistor M6 and a second control transistor M7. The control electrode of the first control transistor M6 is connected to the second node N2, the first pole is connected to the second power supply terminal VH, and the second pole is connected to the first pole of the second control transistor M7. The control electrode of the second control transistor M7 is connected to the second clock terminal CB, and the second pole is connected to the first node N1.

[0069] In some embodiments, the second control sub - circuit 22 may include a third control transistor M5 and a first control capacitor C1. The control electrode of the third control transistor M5 is connected to the fourth node N4, the first electrode is connected to the third node Carry_Out, and the second electrode is connected to the second clock terminal CB. The first electrode of the first control capacitor C1 is connected to the fourth node N4, and the second electrode is connected to the third node Carry_Out.

[0070] In some embodiments, the third control sub - circuit 23 may include a fourth control transistor M4 and a second control capacitor C2. The control electrode of the fourth control transistor M4 is connected to the second node N2, the first electrode is connected to the second power supply terminal VH, and the second electrode is connected to the third node Carry_Out. The first electrode of the second control capacitor C2 is connected to the second node N2, and the second electrode is connected to the second power supply terminal VH.

[0071] In some embodiments, the first input sub - circuit 11 may include a first input transistor M1. The control electrode of the first input transistor M1 is connected to the first clock terminal CK, the first electrode is connected to the signal input terminal INPUT, and the second electrode is connected to the first node N1.

[0072] In some embodiments, the second input sub - circuit 12 includes a second input transistor M2 and a third input transistor M3. The control electrode of the second input transistor M2 is connected to the first node N1, the first electrode is connected to the second node N2, and the second electrode is connected to the first clock terminal CK. The control electrode of the third input transistor M3 is connected to the first clock terminal CK, the first electrode is connected to the first power supply terminal VL, and the second electrode is connected to the second node N2.

[0073] In some embodiments, the first output sub - circuit 31 includes a first output transistor M11. The control electrode of the first output transistor M11 is connected to the third node Carry_Out, the first electrode is connected to the fourth power supply terminal VH1, and the second electrode is connected to the signal output terminal OUTPUT.

[0074] In some embodiments, the second output sub - circuit 32 includes a second output transistor M12. The control electrode of the second output transistor M12 is connected to the fifth node N5, the first electrode is connected to the signal output terminal OUTPUT, and the second electrode is connected to the third power supply terminal VL1.

[0075] It should be noted that although Figure 3 the circuit diagram corresponds to the Figure 1B and Figure 2 block diagrams shown, however, the specific circuit elements other than the anti - leakage circuit 5 shown in Figure 3 and their connection relationships can be applied to the Figure 1A shift register shown. And in this case, the first node N1 and the fourth node N4 are the same node.

[0076] The following will describe the working process of the shift register according to the embodiments of the present disclosure in conjunction with Figure 1B , Figure 2 , Figure 3 and Figure 4 . It should be noted that the following description of the working process takes all transistors as P-type transistors, the effective level as low level, and the invalid level as high level as an example, but the present disclosure is not limited thereto.

[0077] In the first time period t1, the input signal provided by the signal input terminal INPUT is low level, the first clock signal input by the first clock terminal CK is low level, and the second clock signal input by the second clock terminal CB is high level.

[0078] At this time, the input circuit 1 transmits the input signal to the first node N1, transmits the low-level power supply signal VL to the second node N2, and transmits the first clock signal to the second node N2. The control circuit 2 transmits the second clock signal to the third node Carry_Out, and transmits the high-level power supply signal VH to the third node Carry_Out. The pull-down control circuit 4 discharges the fifth node N5 to low level. The output circuit 3 transmits the low-level power supply signal VL1 to the signal output terminal OUTPUT. The anti-leakage circuit 5 electrically connects the first node N1 and the fourth node N4.

[0079] Specifically, referring to Figure 3 and Figure 4 , the first input transistor M1 is turned on, the first node N1 is at low level, the second input transistor M2 and the third input transistor M3 are turned on, and the second node N2 is at low level. Under the control of the first power supply signal provided by the first power supply terminal VL, the anti-leakage transistor M8 is turned on, and the fourth node N4 is at low level. In response to the low level of the fourth node N4, the third control transistor M5 is turned on, and in response to the low level of the second node N2, the fourth control transistor M4 is turned on, so that the third node Carry_Out is at high level. In response to the high level of the third node Carry_Out, the first pull-down control transistor M9 and the first output transistor M11 are turned off. Under the control of the first power supply signal provided by the first power supply terminal VL, the second pull-down control transistor M10 is turned on until the fifth node N5 is pulled down to low level. In response to the low level of the fifth node N5, the second output transistor M12 is turned on, so that the signal output from the signal output terminal OUTPUT is low level.

[0080] In the second time period t2, the input signal provided by the signal input terminal INPUT is high level, the first clock signal input by the first clock terminal CK is high level, and the second clock signal input by the second clock terminal CB is low level.

[0081] At this time, the input circuit 1 transmits the first clock signal to the second node N2. The control circuit 2 transmits the second clock signal to the third node Carry_Out. The pull-down control circuit 4 charges the fifth node N5 to a high level under the control of the third node Carry_Out. The output circuit 3 transmits the high-level power supply signal VH1 to the signal output terminal OUTPUT. The anti-leakage circuit electrically disconnects the first node N1 and the fourth node N4.

[0082] Specifically, referring to Figure 3 and Figure 4 , the first input transistor M1 and the third input transistor M3 are turned off. Due to the holding effect of the first control capacitor C1, the third control transistor M5 remains conducting under the control of the level of the fourth node N4, and the low-level second clock signal CB is transmitted to the third node Carry_Out through the third control transistor M5, making the third node Carry_Out at a low level. At this time, the fourth node N4 becomes a lower low level than in the first time period t1 under the coupling effect of the first control capacitor C1, thereby turning off the anti-leakage transistor M8. In this way, the lower low level at the fourth node N4 is not transmitted to the first node N1. In response to the low voltage at the first node N1, the second input transistor M2 is turned on, making the second node N2 at a high level, thereby turning off the fourth control transistor M4. In response to the low level at the third node Carry_Out, the first pull-down control transistor M9 is turned on. At the same time, since the driving ability of the first pull-down control transistor M9 is greater than that of the second pull-down control transistor M10, the fifth node N5 is at a high level. In response to the high level at the fifth node N5, the second output transistor M12 is turned off, and in response to the low level at the third node Carry_Out, the first output transistor M11 is turned on, so that the signal output from the signal output terminal OUTPUT is at a high level.

[0083] In the third time period t3, the input signal provided by the signal input terminal INPUT is at a high level, the first clock signal input by the first clock terminal CK is at a high level, and the second clock signal input by the second clock terminal CB is at a high level.

[0084] At this time, the input circuit 1 transmits the first clock signal to the second node N2. The control circuit 2 transmits the second clock signal to the third node Carry_Out. The pull-down control circuit 4 discharges the fifth node N5 to a low level. The output circuit 3 transmits the low-level power supply signal VL1 to the signal output terminal OUTPUT.

[0085] Specifically, the first input transistor M1 and the third input transistor M3 remain off, the first node N1 remains at the low level of the previous stage, the second node N2 remains at the high level of the previous stage, the fourth control transistor M4 remains off, and the third control transistor M5 remains on. The high level input at the second clock terminal CB is transmitted to the third node Carry_Out through the third control transistor M5, thereby turning off the first pull-down control transistor M9. Under the control of the first power signal provided by the first power terminal VL, the second pull-down control transistor M10 conducts until the fifth node N5 is pulled down to the low level. In response to the low level of the fifth node N5, the second output transistor M12 conducts, and in response to the high level of the third node Carry_Out, the first output transistor M11 turns off, so that the signal output from the signal output terminal OUTPUT is at the low level.

[0086] In the fourth time period t4, the input signal provided by the signal input terminal INPUT is at the high level, the first clock signal input at the first clock terminal CK is at the low level, and the second clock signal input at the second clock terminal CB is at the high level.

[0087] At this time, the input circuit 1 transmits the input signal to the first node N1 and transmits the low-level power signal VL to the second node N2. The control circuit 2 transmits the high-level power signal VH to the third node Carry_Out. The pull-down control circuit 4 maintains the low level of the fifth node N5. The output circuit 3 transmits the low-level power signal VL1 to the signal output terminal OUTPUT. The anti-leakage circuit 5 electrically connects the first node N1 and the fourth node N4.

[0088] Specifically, the first input transistor M1 conducts, the first node N1 is at the high level, turning off the second input transistor M2; the third input transistor M3 conducts, and the second node N2 is at the low level. In response to the low level of the second node N2, the fourth control transistor M4 conducts, so that the third node Carry_Out is at the high level. Under the control of the first power signal provided by the first power terminal VL, the anti-leakage transistor M8 conducts, making the fourth node N4 at the high level. In response to the high level of the fourth node N4, the third control transistor M5 turns off. In response to the high level of the third node Carry_Out, the first pull-down control transistor M9 and the first output transistor M11 turn off. Under the holding action of the pull-down control capacitor C3, the fifth node N5 is at the low level. In response to the low level of the fifth node N5, the second output transistor M12 conducts, so that the signal output from the signal output terminal OUTPUT is at the low level.

[0089] In the fifth time period t5, the input signal provided by the signal input terminal INPUT is at the high level, the first clock signal input at the first clock terminal CK is at the high level, and the second clock signal input at the second clock terminal CB is at the low level.

[0090] At this time, the control circuit 2 transmits the high-level power supply signal VH to the third node Carry_Out and transmits the high-level power supply signal VH to the first node N1. The pull-down control circuit 4 controls the fifth node N5 to a low level. The output circuit 3 transmits the low-level power supply signal VL1 to the signal output terminal OUTPUT. The anti-leakage circuit 5 electrically connects the first node N1 and the fourth node N4.

[0091] Specifically, the first input transistor M1 and the third input transistor M3 are turned off. The second node N2 remains at a low level, the first control transistor M6 remains conductive, and in response to the low level of the second clock terminal CB, the second control transistor M7 is turned on, so that the first node N1 is at a high level. Under the control of the first power supply signal provided by the first power supply terminal VL, the anti-leakage transistor M8 is turned on, so that the fourth node N4 is at a high level. In response to the high level of the fourth node N4, the third control transistor M5 is turned off. Since the second node N2 is at a low level, the fourth control transistor M4 is turned on, and the third node Carry_Out is at a high level. In response to the high level of the third node Carry_Out, the first pull-down control transistor M9 and the first output transistor M11 are turned off. The fifth node N5 becomes a lower low level than in the fourth stage t4 under the coupling action of the pull-down control capacitor C3, and the second pull-down control transistor M10 is turned off. In response to the low level of the fifth node N5, the second output transistor M12 is turned on, so that the signal output from the signal output terminal OUTPUT is at a low level.

[0092] Thereafter, the fourth time period t4 and the fifth time period t5 are repeated until the next third time period t3 is performed in response to an external signal (for example, an external signal that makes both the clock signal CK and the clock signal CB at an invalid level), and then the fourth time period t4 and the fifth time period t5 are continued to be repeated; and / or until the next first time period t1 is performed in response to a change in the input signal (for example, the next valid level pulse of the input signal).

[0093] In the shift register according to the embodiment of the present disclosure, by adopting the above-mentioned pull-down control circuit 4, the level of the fifth node N5 can be controlled independently of the first clock signal CK, so that the signal output terminal OUTPUT can still output a desired level (for example, a valid level) when the first clock signal CK and the second clock signal CB are both set to an invalid level at the same time. When such a shift register is used to form an Emission GOA, the pulse widths of the light emission control signals of different pixel rows are the same, thus ensuring normal display. In addition, when the shift register further includes an anti-leakage circuit 5, leakage can be reduced, thereby reducing power consumption and ensuring display quality.

[0094] Next, refer to Figure 7 andFigure 8 , a shift register according to some embodiments of the present disclosure is compared with a comparative example and described. Figure 7 The shift register of the comparative example is shown. Figure 8 is applied Figure 7 The timing diagram of Emission GOA using the shift register shown. As an example of the comparative example, Figure 7 All transistors in are P-type transistors.

[0095] Referring to Figure 7 and Figure 8 , the control electrode of transistor T10 is connected to the first clock terminal CK, and the driving of the fifth node is directly related to the first clock signal CK. As shown in Figure 8 , during the input of the Hf signal, the clock signals of the first clock terminal CK and the second clock terminal CB are both high level, and before the input period of the Hf signal, the fifth-stage shift register of Emission GOA has just output a high-level pulse through its output terminal. In this case, referring to the shift register circuit shown in Figure 7 , node N4 is set to high level via transistor T5, and transistor T9 is turned off under the control of the high-level clock signal CK, so that the output terminal OUTPUT of the shift register remains high-level output due to capacitors C3 and C4 and cannot output a low-level signal as expected. In addition, due to the presence of capacitor C4, node N3 is affected by both the clock signal CB and the output signal OUTPUT. Once the clock signals CK and CB cannot work alternately normally, node N3 cannot become low level during the period when the output terminal OUTPUT is expected to output a low-level signal.

[0096] However, referring to Figures 1A to 4 and the above description, in the shift register according to the embodiments of the present disclosure, by controlling the level of the fifth node N5 independently of the first clock signal CK by the pull-down control circuit 4, when the signals of the first clock terminal CK and the second clock terminal CB are both high level after a high-level pulse is output at the output terminal, the signal output terminal OUTPUT of the shift register can output a low-level signal as expected. In this way, when this shift register is applied to Emission GOA, the pulse widths of the light emission control signals of different pixel rows are the same, thus ensuring normal display.

[0097] In addition, referring to Figure 7 and Figure 8 , during the period when the output terminal OUTPUT of the shift register outputs a high-level pulse, the first node N1 will be set to a lower low level due to capacitive coupling, which will cause leakage of other circuit components such as transistor T1. However, referring to Figures 1B to 4As described above, in the shift register according to an embodiment of the present disclosure, by providing the anti-leakage circuit 5, the level of the first node N1 is prevented from becoming lower, thereby preventing or reducing the leakage of other circuit components.

[0098] On the other hand, the present disclosure provides a gate driver including a plurality of cascaded shift registers, where the shift register is any one of the above shift registers.

[0099] For example, referring to Figure 5 , the gate driver includes N cascaded shift registers. A scan start signal EM_STV is applied to the signal input terminal of the first-stage shift register (refer to Figure 6 ), the signal input terminal of the i-th stage shift register is connected to the signal output terminal of the (i - 1)-th stage shift register (2 ≤ i ≤ N), and each stage of the shift register outputs signals EM_OUT<1> to EM_OUT of its own stage <n>. For example, when the gate driver is an Emission GOA, each stage of the shift register outputs a light emission control signal for the corresponding pixel row. The first clock terminal CK and the second clock terminal CB of each stage of the shift register are alternately connected to the first clock signal line EM_CK and the second clock signal line EM_CB, respectively. For example, referring to Figure 5 , the first clock terminal CK of the odd-numbered stage shift register is connected to the first clock signal line EM_CK, and the second clock terminal CB is connected to the second clock signal line EM_CB; the first clock terminal CK of the even-numbered stage shift register is connected to the second clock signal line EM_CB, and the second clock terminal CB is connected to the first clock signal line EM_CK. Figure 6 shows Figure 5 the operating timing of the gate driver shown. Among them, the Hf period represents the period when both the first GOA clock signal EM_CK and the second GOA clock signal EM_CB are at an invalid level. For example, when the gate driver is an Emission GOA and a high-frequency PWM signal is applied for light emission time control, the Hf period represents the period when the high-frequency PWM signal is input. In addition, all the shift registers of the gate driver operate in response to the same set of clock signals. For example, when the gate driver is an Emission GOA, all the shift registers operate in response to the same set of clock signals, and this set of clock signals becomes invalid in response to the same high-frequency PWM signal. Therefore, for each shift register, the period when the first clock signal CK and the second clock signal CB of the shift register are both at an invalid level (i.e., the period t3 in the above text) is not the same.

[0100] In the gate driver according to the embodiments of the present disclosure, since each shift register includes the pull-down control circuit as described above, even when a high-frequency PWM signal is applied for light emission control, the pulse widths of the light emission control signals of different pixel rows are the same, thus ensuring normal display.

[0101] On the other hand, the present disclosure provides a display device including the above-mentioned gate driver.

[0102] In some embodiments, the display device may be a micro-LED display device.

[0103] For example, the display device may be any product or component with a display function, such as a display, a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, etc.

[0104] On the other hand, the present disclosure provides a driving method for the above-mentioned shift register. The method includes: in a first period, applying an input signal with an effective level to the signal input terminal, applying a first clock signal with an effective level to the first clock terminal, and applying a second clock signal with an ineffective level to the second clock terminal, so that the signal output from the output terminal of the shift register has a first level; in a second period, applying an input signal with an ineffective level to the signal input terminal, applying a first clock signal with an ineffective level to the first clock terminal, and applying a second clock signal with an effective level to the second clock terminal, so that the signal output from the output terminal of the shift register has a second level different from the first level; in a third period, applying an input signal with an ineffective level to the signal input terminal, applying a first clock signal with an ineffective level to the first clock terminal, and applying a second clock signal with an ineffective level to the second clock terminal, so that the signal output from the output terminal of the shift register has a first level; in a fourth period, applying an input signal with an ineffective level to the signal input terminal, applying a first clock signal with an effective level to the first clock terminal, and applying a second clock signal with an ineffective level to the second clock terminal, so that the signal output from the output terminal of the shift register has a first level; and in a fifth period, applying an input signal with an ineffective level to the signal input terminal, applying a first clock signal with an ineffective level to the first clock terminal, and applying a second clock signal with an effective level to the second clock terminal, so that the signal output from the output terminal of the shift register has a first level. Wherein, the first period, the second period, the third period, the fourth period and the fifth period are sequentially arranged periods in time, and during the first period to the fifth period, a first power signal with a constant ineffective level is applied to the first power terminal, and a second power signal with a constant effective level is applied to the second power terminal.

[0105] For example, referring to Figure 4 , the above-mentioned first period to fifth period are Figure 4 the periods t1 to t5 shown in Figure 4 , the first clock signal is the Figure 4 signal CK shown in Figure 4 , the second clock signal is the Figure 4 signal CB shown in

[0106] According to the above-mentioned shift register driving method of the present disclosure, the shift register outputs a high-level pulse in the second period t2, and outputs a low-level pulse in the third period t3 when both the first clock signal and the second clock signal are ineffective levels. Thus, when this shift register driving method is applied to Emission GOA, the pulse widths of the light emission control signals of different pixel rows are the same, thereby ensuring normal display.

[0107] It is understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principles of the present disclosure, and the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also regarded as the protection scope of the present disclosure.< / n>

Claims

1. A shift register, comprising: An input circuit, connected to a signal input terminal, a first clock terminal, a first power supply terminal, a first node, and a second node, and configured to transmit an input signal provided by the signal input terminal to the first node under the control of a first clock signal input from the first clock terminal, transmit a first power supply signal provided by the first power supply terminal to the second node under the control of the first clock signal, and transmit the first clock signal to the second node under the control of the level at the first node; A control circuit, connected to the first node, the second node, a second power supply terminal, a second clock terminal, a third node, and a fourth node, and configured to transmit a second power supply signal provided by the second power supply terminal to the first node under the control of the level at the second node and a second clock signal input from the second clock terminal, transmit the second clock signal to the third node under the control of the level at at least one of the fourth node and the first node, and transmit the second power supply signal to the third node under the control of the level at the second node; A pull - down control circuit, connected to the second clock terminal, the first power supply terminal, the second power supply terminal, the third node, and a fifth node; And An output circuit, connected to the third node, a third power supply terminal, a fourth power supply terminal, the fifth node, and a signal output terminal, and configured to transmit a fourth power supply signal provided by the fourth power supply terminal to the signal output terminal under the control of the level at the third node, and transmit a third power supply signal provided by the third power supply terminal to the signal output terminal under the control of the level at the fifth node, wherein the pull - down control circuit is configured to control the level of the fifth node independently of the first clock signal; The pull - down control circuit is configured to provide a current path between the second power supply terminal and the fifth node under the control of the level at the third node, provide a current path between the first power supply terminal and the fifth node under the control of the first power supply signal, and maintain a voltage difference between the fifth node and the second clock terminal when the fifth node is floating, and wherein the ability of the pull - down control circuit to drive the fifth node through the current path between the second power supply terminal and the fifth node is greater than the ability to drive the fifth node through the current path between the first power supply terminal and the fifth node.

2. The shift register according to claim 1, wherein, The pull - down control circuit includes: a first pull - down control transistor, a second pull - down control transistor, and a pull - down control capacitor, The control electrode of the first pull - down control transistor is connected to the third node, the first electrode is connected to the second power supply terminal, and the second electrode is connected to the fifth node, The control electrode of the second pull - down control transistor is connected to the first power supply terminal, the first electrode is connected to the fifth node, and the second electrode is connected to the first power supply terminal, and The first electrode of the pull - down control capacitor is connected to the fifth node, and the second electrode is connected to the second clock terminal.

3. The shift register according to claim 2, wherein, The width-to-length ratio of the first pull-down control transistor is greater than that of the second pull-down control transistor.

4. The shift register according to any one of claims 1 to 3, wherein, The control circuit is configured to transmit the second clock signal to the third node under the control of the level at the fourth node, and the shift register further includes: A leakage prevention circuit, which is connected to the first node, the first power supply terminal, and the fourth node, and is configured to control the electrical connection between the first node and the fourth node under the control of the first power supply signal.

5. The shift register according to claim 4, wherein, The leakage prevention circuit includes a leakage prevention transistor. The control electrode of the leakage prevention transistor is connected to the first power supply terminal, the first pole is connected to the first node, and the second pole is connected to the fourth node.

6. The shift register according to claim 1, wherein, The control circuit is configured to transmit the second clock signal to the third node under the control of the level at the fourth node, and includes: A first control sub-circuit, which is connected to the second node, the second clock terminal, the second power supply terminal, and the first node, and is configured to transmit the second power supply signal to the first node under the control of the level at the second node and the second clock signal; A second control sub-circuit, which is connected to the fourth node, the second clock terminal, and the third node, and is configured to transmit the second clock signal to the third node under the control of the level at the fourth node, and maintain the voltage difference between the fourth node and the third node when the fourth node is floating; and A third control sub-circuit, which is connected to the second node, the second power supply terminal, and the third node, and is configured to transmit the second power supply signal to the third node under the control of the level at the second node, and maintain the voltage difference between the second node and the second power supply terminal when the second node is floating.

7. The shift register according to claim 6, wherein, The first control sub-circuit includes a first control transistor and a second control transistor. The control electrode of the first control transistor is connected to the second node, the first pole is connected to the second power supply terminal, the second pole is connected to the first pole of the second control transistor, and The control electrode of the second control transistor is connected to the second clock terminal, and the second pole is connected to the first node.

8. The shift register according to claim 6 or 7, wherein The second control sub-circuit includes a third control transistor and a first control capacitor. The control electrode of the third control transistor is connected to the fourth node, the first pole is connected to the third node, the second pole is connected to the second clock terminal, and The first pole of the first control capacitor is connected to the fourth node, and the second pole is connected to the third node.

9. The shift register according to claim 8, wherein, The third control sub-circuit includes a fourth control transistor and a second control capacitor. The control electrode of the fourth control transistor is connected to the second node, the first pole is connected to the second power supply terminal, the second pole is connected to the third node, and The first pole of the second control capacitor is connected to the second node, and the second pole is connected to the second power supply terminal.

10. The shift register according to claim 1, wherein, The input circuit includes: A first input sub - circuit, connected to the signal input terminal, the first clock terminal, and the first node, and configured to transmit the input signal to the first node under the control of the first clock signal; and A second input sub - circuit, connected to the first power supply terminal, the first clock terminal, the first node, and the second node, and configured to transmit the first power supply signal to the second node under the control of the first clock signal, and transmit the first clock signal to the second node under the control of the level at the first node.

11. The shift register according to claim 10, wherein, The first input sub - circuit includes a first input transistor, The control electrode of the first input transistor is connected to the first clock terminal, the first electrode is connected to the signal input terminal, and the second electrode is connected to the first node.

12. The shift register according to claim 10 or 11, wherein, The second input sub - circuit includes a second input transistor and a third input transistor, The control electrode of the second input transistor is connected to the first node, the first electrode is connected to the second node, the second electrode is connected to the first clock terminal, and The control electrode of the third input transistor is connected to the first clock terminal, the first electrode is connected to the first power supply terminal, and the second electrode is connected to the second node.

13. The shift register according to claim 1, wherein, The output circuit includes: A first output sub - circuit, connected to the third node, the fourth power supply terminal, and the signal output terminal, and configured to transmit the fourth power supply signal to the signal output terminal under the control of the level at the third node, and A second output sub - circuit, connected to the fifth node, the third power supply terminal, and the signal output terminal, and configured to transmit the third power supply signal to the signal output terminal under the control of the level at the fifth node.

14. The shift register according to claim 13, wherein, The first output sub - circuit includes a first output transistor, The control electrode of the first output transistor is connected to the third node, the first electrode is connected to the fourth power supply terminal, and the second electrode is connected to the signal output terminal.

15. The shift register according to claim 13 or 14, wherein, The second output sub - circuit includes a second output transistor, The control electrode of the second output transistor is connected to the fifth node, the first electrode is connected to the signal output terminal, and the second electrode is connected to the third power supply terminal.

16. A gate driver, including a plurality of cascaded shift registers, where the shift register is the shift register according to any one of claims 1 - 15.

17. A display device, including the gate driver according to claim 16.

18. A method for driving a shift register, where the shift register is the shift register according to any one of claims 1 - 15, and the method includes: In a first time period, applying an input signal with an effective level to the signal input terminal, applying a first clock signal with an effective level to the first clock terminal, and applying a second clock signal with an invalid level to the second clock terminal, so that the signal output from the output terminal of the shift register has a first level; In a second time period, an input signal with an invalid level is applied to the signal input terminal, a first clock signal with an invalid level is applied to the first clock terminal, and a second clock signal with a valid level is applied to the second clock terminal, so that the signal output from the output terminal of the shift register has a second level different from the first level; In a third time period, an input signal with an invalid level is applied to the signal input terminal, a first clock signal with an invalid level is applied to the first clock terminal, and a second clock signal with an invalid level is applied to the second clock terminal, so that the signal output from the output terminal of the shift register has the first level; In a fourth time period, an input signal with an invalid level is applied to the signal input terminal, a first clock signal with a valid level is applied to the first clock terminal, and a second clock signal with an invalid level is applied to the second clock terminal, so that the signal output from the output terminal of the shift register has the first level; And In a fifth time period, an input signal with an invalid level is applied to the signal input terminal, a first clock signal with an invalid level is applied to the first clock terminal, and a second clock signal with a valid level is applied to the second clock terminal, so that the signal output from the output terminal of the shift register has the first level, wherein, the first time period, the second time period, the third time period, the fourth time period and the fifth time period are time-ordered time periods, and during the first time period to the fifth time period, a first power supply signal with a constant invalid level is applied to the first power supply terminal, a second power supply signal with a constant valid level is applied to the second power supply terminal, a third power supply signal with the constant first level is applied to the third power supply terminal, and a fourth power supply signal with the constant second level is applied to the fourth power supply terminal.

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