Display panel, display device and driving method

Abstract

A display panel (10), a display device and a driving method, relating to the technical field of display. The display panel (10) comprises a plurality of pixel rows (101), a plurality of gating units (102), a gate driving circuit (103) and a control circuit (104). Each pixel row (101) comprises a plurality of pixel circuits (1011), and corresponds to a plurality of gating units (102). The gate driving circuit (103) comprises a plurality of row shift registers (1031). Each row shift register (1031) is electrically connected to the pixel circuits (1011) in the corresponding pixel row (101), respectively. Each gating unit (102) is electrically connected to one or more pixel circuits (1011) in the corresponding pixel row (101), is electrically connected to the row shift register (1031) corresponding to the pixel row (101), and is further electrically connected to the control circuit (104). Each gating unit (102) is used for sending a refreshing control signal to the corresponding pixel circuits (1011) on the basis of a scanning signal sent by the corresponding row shift register (1031), and a gating signal sent by the control circuit (104). Moreover, each pixel circuit (1011) is used for, when the refreshing control signal represents refreshing display, performing refreshing display in response to the scanning signal sent by the corresponding row shift register (1031).

Description

Display panel, display device and driving method

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410692562.0, filed on May 30, 2024, entitled “Display Panel, Display Device and Driving Method”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of display technology, and in particular to a display panel, display device and driving method. Background Technology

[0004] Modern smartphones, tablets, laptops, and other display devices can implement partitioned display functionality. For example, foldable phones can display only the smaller folded screen when folded. Partitioned display devices are suitable for diverse usage scenarios, reducing power consumption and extending standby time.

[0005] Overview

[0006] This application provides a display panel, a display device, and a driving method.

[0007] In a first aspect, this application provides a display panel, the display panel comprising: a plurality of pixel rows, a plurality of gating units, a gate driving circuit, and a control circuit;

[0008] The pixel row includes multiple pixel circuits;

[0009] The pixel row corresponds to multiple gating units;

[0010] The gate drive circuit includes multiple row shift registers;

[0011] The row shift register is electrically connected to each pixel circuit in the corresponding pixel row;

[0012] The gating unit is electrically connected to one or more pixel circuits in the pixel row, the gating unit is electrically connected to the row shift register corresponding to the pixel row, and the gating unit is also electrically connected to the control circuit;

[0013] The gating unit is used to send a refresh control signal to the pixel circuit based on the scan signal sent by the row shift register and the gating signal sent by the control circuit; and

[0014] The pixel circuit is used to refresh the display in response to the scan signal sent by the row shift register when the refresh control signal indicates that the display is refreshed.

[0015] Optionally, the gating unit and the pixel circuit connected to the gating unit constitute an array unit; and

[0016] The array unit corresponding to the pixel row is arranged in the row direction of the pixel row.

[0017] Optionally, the pixel circuit includes: a light-emitting element, a driving module, a refresh module, and a refresh control module;

[0018] The control terminal of the driving module is electrically connected to the first node, the first terminal of the driving module is electrically connected to the second node, and the second terminal of the driving module is electrically connected to the light-emitting element through the third node.

[0019] The driving module is used to generate a current that drives the light-emitting element to emit light under the potential control of the first node;

[0020] The control terminal of the refresh module is electrically connected to the first scan signal line, the first terminal of the refresh module is electrically connected to the third node, and the second terminal of the refresh module is electrically connected to the first terminal of the refresh control module.

[0021] The refresh module is used to refresh the potential of the first node;

[0022] The first scan signal line connects the row shift register and the pixel circuit.

[0023] The control terminal of the refresh control module is electrically connected to the gating unit, and the second terminal of the refresh control module is electrically connected to the first node; and

[0024] The refresh control module is used to respond to the refresh control signal sent by the gating unit and control the connection and disconnection between the refresh module and the first node.

[0025] Optionally, the driving module includes a first transistor;

[0026] The refresh module includes a second transistor;

[0027] The refresh control module includes a third transistor;

[0028] The control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the second node, and the second electrode of the first transistor is electrically connected to the third node;

[0029] The control electrode of the second transistor is electrically connected to the first scan signal line, the first electrode of the second transistor is electrically connected to the third node, and the second electrode of the second transistor is electrically connected to the first electrode of the third transistor; and

[0030] The control electrode of the third transistor is electrically connected to the gating unit, and the second electrode of the third transistor is electrically connected to the first node.

[0031] Optionally, the pixel circuit further includes: a data writing module, a first light emission control module, a second light emission control module, a first reset module, a second reset module, and a third reset module;

[0032] The data writing module is electrically connected to the second scan signal line, the data signal line and the second node respectively;

[0033] The second scan signal line connects the row shift register and the pixel circuit.

[0034] The first light-emitting control module is electrically connected to the light-emitting control signal line, the first power signal line, and the second node, respectively;

[0035] The second light-emitting control module is electrically connected to the light-emitting control signal line, the third node, and the fourth node, respectively;

[0036] The first reset module is electrically connected to the first reset control signal line, the first initial voltage line, and the third node, respectively.

[0037] The second reset module is electrically connected to the second reset control signal line, the second initial voltage line, and the fourth node, respectively; and

[0038] The third reset module is electrically connected to the second reset control signal line, the third initial voltage line, and the second node, respectively.

[0039] Optionally, the gating unit includes: a control subunit and an output subunit;

[0040] The control terminal of the control subunit is electrically connected to the control circuit, and the output terminal of the control subunit is electrically connected to the control terminal of the output subunit.

[0041] The control terminal of the output subunit is also electrically connected to the row shift register corresponding to the pixel row;

[0042] The output terminal of the output subunit is electrically connected to the pixel circuit; and

[0043] The control subunit is used to control the output subunit to send the refresh control signal to the pixel circuit according to the scan signal when the strobe signal indicates refresh display.

[0044] Optionally, the control subunit includes a fourth transistor; and

[0045] The control electrode of the fourth transistor is electrically connected to the control circuit, the first electrode of the fourth transistor is electrically connected to the first control terminal of the output subunit, and the second electrode of the fourth transistor is electrically connected to the second control terminal of the output subunit.

[0046] The second control terminal is also electrically connected to the row shift register corresponding to the pixel row.

[0047] Optionally, the output sub-unit includes a fifth transistor, a sixth transistor, and a seventh transistor;

[0048] The control electrode of the fifth transistor is electrically connected to the output terminal of the control subunit, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the pixel circuit.

[0049] The control electrode of the sixth transistor is electrically connected to the output terminal of the control subunit, the first electrode of the sixth transistor is electrically connected to the second power supply terminal, and the second electrode of the sixth transistor is electrically connected to the pixel circuit; and

[0050] The control electrode of the seventh transistor is electrically connected to the output terminal of the control subunit and the row shift register, the first electrode of the seventh transistor is electrically connected to the pixel circuit, and the second electrode of the seventh transistor is electrically connected to the second power supply terminal.

[0051] Optionally, the fifth transistor is an N-type transistor, and the sixth and seventh transistors are both P-type transistors;

[0052] Alternatively, the fifth transistor may be a P-type transistor, and the sixth and seventh transistors may both be N-type transistors.

[0053] Optionally, the plurality of row shift registers are cascaded;

[0054] The row shift register of the nth level is electrically connected to each pixel circuit in the nth row of pixels; and

[0055] The row shift register of the nth level is also electrically connected to the gating unit corresponding to the pixel row of the nth row;

[0056] Where n is a positive integer.

[0057] Optionally, the control circuit includes: a column shift register disposed in the column direction corresponding to the gating unit;

[0058] The gating unit is electrically connected to the column shift register in the corresponding column direction; and

[0059] The column shift register is used to generate a gating signal for the gating unit in the corresponding column direction, and to send the gating signal to the gating unit;

[0060] Alternatively, the control circuit is an integrated circuit in the display panel.

[0061] Optionally, when the scanning signal indicates refresh display of the pixel row and the gating signal indicates refresh display of the pixel circuit, the gating unit generates a refresh control signal with a first level, wherein the refresh control signal with the first level indicates refresh display; and

[0062] When the pixel circuit receives the refresh control signal of the first level, it refreshes the display in response to the scan signal sent by the row shift register.

[0063] Optionally, when the scanning signal indicates that the pixel row should not be refreshed, or when the gating signal indicates that the pixel circuit should not be refreshed, the gating unit generates a refresh control signal with a second level, wherein the refresh control signal with the second level indicates that the display should be maintained; and

[0064] When the pixel circuit receives the second-level refresh control signal, it maintains the display state of the previous frame and does not refresh the display.

[0065] Optionally, the plurality of pixel rows and the gating unit corresponding to each pixel row are disposed in the display area of ​​the display panel.

[0066] Optionally, the central area of ​​the display panel is provided with a high density of the gating units, and the surrounding area of ​​the display panel is provided with a low density of the gating units.

[0067] Optionally, the display panel is divided into a high-frequency display area and a low-frequency display area, wherein the high-frequency display area has a high refresh rate and the low-frequency display area has a low refresh rate.

[0068] Secondly, this application provides a display device, the display device including a display panel as described in the first aspect.

[0069] Thirdly, this application provides a driving method applied to a display panel as described in the first aspect, the driving method comprising:

[0070] The row shift register in the gate driving circuit generates the scan signal and sends the scan signal to each pixel circuit in the pixel row and the gating unit corresponding to the pixel row.

[0071] The control circuit generates the gating signal corresponding to each gating unit according to the partition display information of the current frame, and sends the gating signal to the corresponding gating unit.

[0072] The gating unit generates the refresh control signal based on the scan signal and the gating signal, and sends the refresh control signal to the connected pixel circuit; and

[0073] The pixel circuit refreshes the display in response to the scanning signal when the refresh control signal indicates that the display is refreshed.

[0074] Optionally, the partition display information includes the refresh display area and the hold display area of ​​the display panel within the current frame; and

[0075] The control circuit generates a gating signal corresponding to each gating unit based on the partition display information of the current frame, and sends the gating signal to the corresponding gating unit, including:

[0076] The control circuit generates a gating signal with a first level and sends the gating signal with the first level to the gating unit corresponding to the refresh display area, so that the pixel circuit in the refresh display area refreshes the display state of the current frame; and

[0077] The control circuit generates a gating signal with a second level and sends the gating signal with the second level to the gating unit corresponding to the holding display area, so that the pixel circuit in the holding display area maintains the display state of the previous frame.

[0078] Fourthly, this application provides a computing processing device, comprising:

[0079] Memory containing computer-readable code; and

[0080] One or more processors, when the computer-readable code is executed by the one or more processors, the computing processing device performs the driving method described above.

[0081] Fifthly, this application provides a computer program including computer-readable code, which, when run on a computing processing device, causes the computing processing device to execute the aforementioned driving method.

[0082] Sixthly, this application provides a computer-readable medium storing the aforementioned computer program.

[0083] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application.

[0084] Brief description of the attached diagram

[0085] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0086] Figure 1 illustrates, exemplarily, a schematic diagram of a partitioned display of a display device in the related art;

[0087] Figure 2 exemplarily illustrates one of the structural schematic diagrams of a display panel provided in an embodiment of this application;

[0088] Figure 3 illustrates, by way of example, a schematic diagram of the structure of an array unit provided in an embodiment of this application;

[0089] Figure 4 illustrates, by way of example, a schematic diagram of the display area of ​​a display panel provided in an embodiment of this application;

[0090] Figure 5 illustrates, by way of example, a second structural schematic diagram of a display panel provided in an embodiment of this application;

[0091] Figure 6 illustrates, by way of example, a schematic diagram of a pixel circuit provided in an embodiment of this application;

[0092] Figure 7 illustrates, by way of example, a structural schematic diagram of a gating unit provided in an embodiment of this application;

[0093] Figure 8 illustrates a timing diagram of a display panel provided in an embodiment of this application;

[0094] Figure 9 illustrates, by way of example, a flowchart of a driving method provided in an embodiment of this application;

[0095] Figure 10 schematically shows a block diagram of a computing processing apparatus for performing the method according to this application; and

[0096] Figure 11 schematically illustrates a storage unit for holding or carrying program code that implements the method according to this application.

[0097] Detailed description

[0098] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0099] With the rapid development of smart technology, the usage scenarios for smartphones, tablets, and other smart terminals have become increasingly diverse to meet user expectations and needs. Users are pursuing personalized specifications for display devices, such as large screen sizes, full-screen displays, and high resolutions. In related technologies, to optimize display effects, partitioned display on display devices can reduce power consumption, extend standby time, and is suitable for diverse usage scenarios. For example, foldable handheld products such as foldable phones can display the entire screen when fully open, and only display the folded portion when folded. This increases user flexibility while reducing power consumption, thereby extending standby time.

[0100] Figure 1 exemplarily illustrates a partitioned display diagram of a display device in the related art. When using the display device, a user may simultaneously open multiple applications displayed on the screen, such as video software, game software, social software, and reading software. As shown in Figure 1, the screen of the display device can be divided into multiple display areas, simultaneously displaying the interfaces or windows of various applications. In the related art, different display areas can employ different refresh rates due to varying user needs. For example, the display area of ​​a reading software can use a low refresh rate, while the display area of ​​a game software can use a high refresh rate.

[0101] During use, users typically don't fixate on the display area division of a display device; the desired display area can be flexibly adjusted based on user operations. This necessitates that the display panel has the capability for arbitrary partitioned display. However, current display panels generally achieve partitioned display by controlling the refresh of the entire row or column. This results in fixed and monotonous shapes and positions of the partitioned display areas, lacking flexibility and leading to poor partitioned display effects.

[0102] In some embodiments, multiple signals have a first level and a second level. The first level and the second level only represent that the signal level has two states, and do not represent that the first level or the second level has a specific value. The valid level can be either the first level or the second level. The valid level can be either high or low.

[0103] In some embodiments, the transistor used may be a thin-film transistor (TFT) or a metal-oxide-semiconductor (MOS) field-effect transistor. For example, an N-channel MOS transistor or a P-channel MOS transistor, i.e., an NMOS (N-channel Metal Oxide Semiconductor) or a PMOS (P-channel Metal Oxide Semiconductor), or an N-channel TFT or a P-channel TFT.

[0104] Figure 2 illustrates a schematic diagram of the structure of a display panel 10 provided in an embodiment of this application. As shown in Figure 2, the display panel 10 includes: a plurality of pixel rows 101, a plurality of gating units 102, a gate driving circuit 103, and a control circuit 104.

[0105] Pixel row 101 includes multiple pixel circuits 1011; pixel row 101 corresponds to multiple gating units 102;

[0106] The gate drive circuit 103 includes multiple row shift registers 1031; the row shift registers 1031 are electrically connected to each pixel circuit 1011 in the corresponding pixel row 101.

[0107] The gating unit 102 is electrically connected to one or more pixel circuits 1011 in pixel row 101, the gating unit 102 is electrically connected to the row shift register 1031 corresponding to pixel row 101, and the gating unit 102 is also electrically connected to the control circuit 104.

[0108] The gating unit 102 is used to send a refresh control signal to the pixel circuit 1011 according to the scan signal sent by the row shift register 1031 and the gating signal sent by the control circuit 104.

[0109] The pixel circuit 1011 is used to refresh the display in response to the scan signal sent by the row shift register 1031 when the refresh control signal indicates that the display is refreshed.

[0110] In some embodiments, the display panel 10 includes a plurality of pixel circuits 1011, which are arrayed to form a plurality of pixel rows 101 and a plurality of pixel columns. Each pixel row 101 may correspond to one or more gating units 102, and each gating unit 102 may be electrically connected to one or more pixel circuits 1011 in the pixel row 101. For example, if one pixel row 101 corresponds to one gating unit 102, then the gating unit 102 is electrically connected to each pixel circuit 1011 in the pixel row 101. Alternatively, one pixel row 101 may correspond to multiple gating units 102, and any gating unit 102 may be electrically connected to one or more pixel circuits 1011 in the pixel row 101. This is merely an example, and the embodiments of this application do not limit the scope of the invention.

[0111] In some embodiments, pixel circuits 1011 and gating units 102 can be connected one-to-one, allowing for precise refresh display control down to the individual pixel circuit 1011. Of course, in existing pixel density units (Pixels Per Inch, PPI) layouts, due to limitations in layout space and transmittance, multiple pixel circuits 1011 can be connected to the gating unit 102. Here, PPI represents the number of pixels per inch.

[0112] In some embodiments, the number of row shift registers 1031 in the gate driving circuit 103 is equal to the number of pixel rows 101, and there is a one-to-one correspondence between the row shift registers 1031 and the pixel rows 101. Scan signal lines can be provided between the row shift registers 1031 and the pixel circuits 1011. The row shift registers 1031 are electrically connected to each pixel circuit 1011 in the corresponding pixel row 101 via the scan signal lines, and send scan signals to each pixel circuit 1011 via the scan signal lines. The row shift registers 1031 can also be electrically connected to the gating unit 102 via the scan signal lines, and send scan signals to the gating unit 102 via the scan signal lines.

[0113] In some embodiments, the control circuit 104 may be an integrated circuit (IC), such as an IC in the timing control circuit of the display panel 10, for example, a timing controller (TCON). Alternatively, the control circuit 104 may include multiple shift registers, one of which may be connected to one or more gating units 102. The shift register may be electrically connected to the integrated circuit (IC) of the display device, or the shift register may be electrically connected to an IC in the timing control circuit of the display panel 10, such as a timing controller (TCON). The integrated circuit (IC) may send control signals to the shift registers according to the partition display information of the display panel 10, and the shift registers may generate gating signals in response to the control signals and send the gating signals to the connected gating units 102.

[0114] In some embodiments, the multiple shift registers in the control circuit 104 can be arranged in the row direction or column direction of the pixel array, and this application embodiment does not limit this. The multiple shift registers in the control circuit 104 can be arranged on the same side or opposite side of the gate driving circuit 103. Alternatively, the row shift register 1031 in the gate driving circuit 103 is arranged in the row direction, while the shift register in the control circuit 104 is arranged in the column direction, and is called a column shift register. This is only an example, and this application embodiment does not limit this.

[0115] In some embodiments, the gating unit 102 can generate a refresh control signal with a first level when the scan signal indicates that the pixel row 101 is being refreshed and the gating signal indicates that the pixel circuit 1011 is being refreshed. The first-level refresh control signal indicates refreshed display. Upon receiving the first-level refresh control signal, the pixel circuit 1011 refreshes and displays in response to the scan signal sent by the row shift register 1031.

[0116] In some embodiments, the gating unit 102 can generate a refresh control signal with a second level when the scan signal indicates that the pixel row 101 should not be refreshed, or when the gating signal indicates that the pixel circuit 1011 should not be refreshed. The second-level refresh control signal indicates that the display should be maintained. Upon receiving the second-level refresh control signal, the pixel circuit 1011 can maintain the display state of the previous frame, i.e., it will not refresh the display.

[0117] In this embodiment, the row shift register 1031 in the gate driving circuit 103 sends a scan signal to the pixel circuit 1011 in the pixel row 101 and the gating unit 102 corresponding to the pixel row 101. The gating unit 102 determines whether the pixel circuit 1011 connected to it should be refreshed based on the scan signal and the gating signal sent by the control circuit 104, and sends a refresh control signal to the pixel circuit 1011. The refresh control signal controls whether the pixel circuit 1011 responds to the scan signal to refresh the display, thereby realizing refresh control of the pixel circuit 1011. Compared with the display panel 10 in related technologies, this application can achieve pixel-level local refresh display by setting the number of gating units 102 corresponding to the pixel row 101 and the number of pixel circuits 1011 connected to the gating unit 102. This allows users to flexibly divide different display areas and improves the partitioned display effect of the display panel 10.

[0118] In some embodiments, the gating unit 102 may be disposed in the display area. Specifically, the gating unit 102 may be disposed in a pixel array composed of pixel circuits 1011. The position of the gating unit 102 in the pixel array can be determined according to the position and number of pixel circuits 1011 connected to the gating unit 102. If the gating unit 102 is connected to only one pixel circuit 1011, the gating unit 102 may be disposed in an adjacent position to that pixel circuit 1011. If the gating unit 102 is connected to multiple pixel circuits 1011, the position of the gating unit 102 can be determined according to the position of the multiple pixel circuits 1011. For example, if the gating unit 102 is connected to multiple pixel circuits 1011 consecutively arranged in pixel row 101, the consecutively arranged multiple pixel circuits 1011 can be considered as a group of pixel circuits 1011, and the gating unit 102 may be disposed in an adjacent position to this group of pixel circuits 1011. If the selection unit 102 connects multiple non-contiguous pixel circuits 1011 in the pixel row 101, the position of the selection unit 102 can be determined based on factors such as trace distance, overlap area, and trace length in actual applications. Adjacent positions can be the side of the pixel circuit 1011 furthest from the edge of the display area, or the side of the pixel circuit 1011 closest to the edge of the display area. This is merely an example, and the embodiments of this application do not impose limitations on this.

[0119] Optionally, the gating unit 102 and the pixel circuit 1011 connected to the gating unit 102 constitute an array unit;

[0120] The array unit corresponding to pixel row 101 is set in the row direction of pixel row 101.

[0121] In some embodiments, the pixel circuits 1011 and gating units 102 in the display area can be arrayed using array units. An array unit consists of a gating unit 102 and its connected pixel circuits 1011. The number of array units corresponding to each pixel row 101 is equal to the number of gating units 102 corresponding to that pixel row 101. Multiple array units corresponding to a pixel row 101 can be sequentially arranged along the row direction of the pixel row 101. For example, if a pixel row 101 corresponds to two gating units 102, then that pixel row 101 corresponds to two array units, and these two array units can be arranged adjacent to each other along the row direction of the pixel row 101.

[0122] In some embodiments, when the gating unit 102 in the array unit connects to multiple pixel circuits 1011, the gating unit 102 can be located in the middle of the multiple pixel circuits 1011. Alternatively, the multiple pixel circuits 1011 can be grouped into a set of pixel circuits 1011, and the gating unit 102 can be located adjacent to the set of pixel circuits 1011. This embodiment does not impose any limitations on this. This shortens the trace length, reduces the transmission distance of the refresh control signal, increases the signal transmission speed, and reduces the refresh time difference between the pixel circuits 1011 connected to the gating unit 102, thereby improving the refresh display effect of the pixel circuits 1011. Furthermore, since the gating signal sent by the control circuit 104 does not directly enter the pixel circuits 1011, but is received by the gating unit 102, which then generates the refresh control signal based on the scan signal and the gating signal, the problem of gating signal transitions affecting the refresh display of the pixel circuits 1011 can be avoided, thus preventing screen display crosstalk.

[0123] Figure 3 illustrates a schematic diagram of an array unit provided in an embodiment of this application. As shown in Figure 3, the array unit includes a gating unit 102 and four pixel circuits 1011. The gating unit 102 is electrically connected to the four pixel circuits 1011. The gating unit 102 can receive a scan signal sent by the row shift register 1031 and a gating signal sent by the control circuit 104, and send refresh control signals to the four pixel circuits 1011. When both the scan signal and the gating signal indicate refresh display, the gating unit 102 can control the four pixel circuits 1011 to perform refresh display through the refresh control signals.

[0124] In this embodiment, since the gating unit 102 and the pixel circuit 1011 connected to the gating unit 102 constitute an array unit, the array unit corresponding to the pixel row 101 is set in the row direction of the pixel row 101. In this way, the routing distance between the gating unit 102 and the connected pixel circuit 1011 can be shortened, the refresh synchronization of the pixel circuit 1011 in the array unit can be improved, and the refresh display effect of the pixel circuit 1011 can be improved.

[0125] Figure 4 illustrates, by way of example, a display area of ​​a display panel 10 provided in an embodiment of this application. As shown in Figure 4, the display area includes multiple array units, the structure of which is shown in Figure 3.

[0126] In this embodiment, by setting multiple pixel rows 101 and the gating unit 102 corresponding to each pixel row 101 in the display area of ​​the display panel 10, it is convenient to lay wiring between the pixel circuit 1011 and the gating unit 102 to transmit refresh control signals, which can shorten the wiring length, increase the transmission speed of refresh control signals, thereby improving the refresh display speed of the pixel circuit 1011 and improving the refresh display effect of the display panel 10.

[0127] Optionally, multiple row shift registers 1031 can be cascaded;

[0128] The nth-level row shift register 1031 is electrically connected to each pixel circuit 1011 in the nth pixel row 101;

[0129] The nth-level row shift register 1031 is also electrically connected to the gating unit 102 corresponding to the nth pixel row 101; where n is a positive integer.

[0130] In some embodiments, the gate drive circuit 103 may employ multiple cascaded row shift registers 1031. In the cascaded multiple row shift registers 1031, the input terminal of the first-stage row shift register 1031 can be electrically connected to the scan enable terminal of the gate drive circuit 103 to receive a scan enable signal, such as an STV (Source Termination Voltage) pulse signal. Except for the first-stage row shift register 1031, the signal output terminal of the previous-stage row shift register 1031 is electrically connected to the input terminal of the next-stage row shift register 1031; that is, the signal output terminal of the (n-1)th-stage row shift register 1031 is electrically connected to the input terminal of the nth-stage row shift register 1031, thereby realizing the cascading of multiple row shift registers 1031.

[0131] For example, the row shift register 1031 can be a gate driver on array (GOA) integrated circuit. The gate driver circuit 103 can use multiple cascaded GOAs. The nth level GOA is electrically connected to the pixel circuit 1011 in the nth pixel row 101, and the nth level GOA is also electrically connected to the gating unit 102 corresponding to the nth pixel row 101, where n is a positive integer.

[0132] It should be noted that in related technologies, if the display panel controls pixel row refresh display through cascaded GOA, when the scan enable signal of each frame is in refresh display state, each pixel row in the next frame is in refresh display state, thus the refresh rate of the entire display panel is consistent. However, the display panel 10 provided in this application embodiment can control whether the pixel circuits 1011 in pixel row 101 are refreshed through the gating unit 102 corresponding to pixel row 101. Even if the scan signal indicates refresh display of pixel row 101, the gating unit 102 will only control the connected pixel circuits 1011 to refresh display through a valid refresh control signal if the gating signal simultaneously indicates refresh display of pixel circuit 1011. Therefore, the display panel 10 provided in this application embodiment can achieve pixel-level local refresh display.

[0133] In this embodiment, multiple row shift registers 1031 are cascaded. The nth-level row shift register 1031 is electrically connected to each pixel circuit 1011 in the nth pixel row 101, and is also electrically connected to the gating unit 102 corresponding to the nth pixel row 101, where n is a positive integer. Thus, the cascaded row shift registers 1031 can send the scan signals corresponding to each pixel row 101 of the current frame to the pixel circuit 101 and the gating unit 102, respectively. This allows the gating unit 102 to send refresh control signals to the connected pixel circuits 1011 based on the scan signals and gating signals, thereby achieving refresh control of the pixel circuits 1011 that need to be refreshed in the current frame. Compared to related technologies where cascaded shift registers control the entire display panel 10 to refresh within a frame, the display panel 10 provided in this application embodiment can conveniently control the pixel circuits 1011 that need to be refreshed within a frame by setting the gating unit 102 corresponding to the pixel row 101, thereby achieving flexible division of the display area and improving the partitioned display effect of the display panel 10.

[0134] Optionally, the control circuit 104 includes: a column shift register 1041 disposed in the column direction corresponding to the gating unit 102;

[0135] The gating unit 102 is electrically connected to the column shift register 1041 in the corresponding column direction;

[0136] The column shift register 1041 is used to generate a gating signal for the gating unit 102 in the corresponding column direction and send the gating signal to the gating unit 102.

[0137] Alternatively, the control circuit 104 is an integrated circuit in the display panel 10.

[0138] In some embodiments, a column shift register 1041 may be connected to one or more gating units 102 in the corresponding column direction. A refresh signal line may be provided between the column shift register 1041 and the gating unit 102. The column shift register 1041 can be electrically connected to the gating unit 102 through the refresh signal line to send gating signals to one or more gating units 102 in the corresponding column direction. The column shift register 1041 may be electrically connected to the timing control circuit of the display panel 10. The timing control circuit can determine the partition display information of the current frame based on the image data signal, and then send control signals to each column shift register 1041 according to the partition display information to make the display panel 10 display partitions. Specifically, the column shift register 1041 may generate gating signals in response to the control signals sent by the timing control circuit and send the gating signals to the gating units 102 in the corresponding column direction. Alternatively, the control circuit 104 may be an integrated circuit (IC) in the display panel 10, such as a timing controller (TCON) in the timing control circuit.

[0139] In some embodiments, for multiple pixel circuits 1011 in any pixel column, if the gating units 102 corresponding to each of the multiple pixel circuits 1011 are located in the same column, the gating units 102 of this column can be controlled by a column shift register 1041 in the corresponding column direction. The column shift register 1041 can send gating signals to the gating units 102 in the corresponding column direction, thus saving shift register resources, reducing the hardware cost of the display panel 10, and enabling simultaneous refresh and display of multiple pixel circuits 1011 in a pixel column within one frame. The gating signal can be an AC signal, which allows the gating unit 102 to control the refresh of pixel circuits 1011 that need to be refreshed, or to control the non-refreshing of pixel circuits 1011 that should be blocked. The number of pixel circuits 1011 connected to each gating unit 102 in the column direction of a column shift register 1041 can be the same or different; this embodiment does not impose any limitation on this.

[0140] In some embodiments, the control circuit 104 may include a plurality of cascaded column shift registers 1041. Among the plurality of column shift registers 1041, the input terminal of the first-stage column shift register 1041 may be electrically connected to the timing control circuit of the display panel 10, and the signal output terminal of the (n-1)th-stage column shift register 1041 is electrically connected to the input terminal of the nth-stage column shift register 1041.

[0141] The timing control circuit can send control signals to the input of the first-stage column shift register 1041, causing the cascaded column shift registers 1041 to generate strobe signals for the corresponding column direction. For example, if the column shift register 1041 can be a GOA, then the control circuit 104 can use multiple cascaded GOAs. The strobe signal generated by the current column GOA, when passed as an input signal to the next column GOA, will not have any effect, allowing for convenient partial refresh display.

[0142] For example, the display panel 10 can be configured with selection units 102 of different densities. For instance, the central area can have a high density of selection units 102, while the surrounding areas can have a low density. For example, the selection units 102 in the central area can connect to a single-digit number of pixel circuits 1011, or even have a one-to-one correspondence between the selection units 102 and pixel circuits 1011, thereby achieving fine-grained local refresh display. In contrast, the selection units 102 in the surrounding areas can connect to a dozen or even dozens of pixel circuits 1011, also achieving fine-grained local refresh display. Thus, the central area can be divided into display areas more flexibly compared to the surrounding areas. In this application scenario, multiple pixel circuits 1011 located in different pixel rows 101 but in the same pixel column, if the selection units 102 connected to these multiple pixel circuits 1011 are in the same column, can be controlled by the column shift register 1041 in the corresponding column direction.

[0143] Figure 5 illustrates a schematic diagram of the structure of a display panel 10 provided in an embodiment of this application. As shown in Figure 5, the gate driving circuit 103 includes a plurality of cascaded row shift registers 1031, the control circuit 104 includes a plurality of column shift registers 1041, and the display area includes a plurality of array units. The row shift registers 1031 are electrically connected to the pixel circuits 1011 in the corresponding pixel rows 101, the gating units 102 in the array units are electrically connected to each pixel circuit 1011, and the column shift registers 1041 are electrically connected to the gating units 102 in the corresponding column direction.

[0144] For example, in a 3×3 array of cells as shown in Figure 5, only the middle cell in the second row and second column can be masked, so that the pixel circuits 1011 in this cell are not refreshed, while the surrounding cells can be refreshed. Specifically, the row shift register 1031 in the gate drive circuit 103 can generate a scan signal corresponding to each pixel row 101 in response to the control signal sent by the timing control circuit, and then send the scan signal to the pixel row 101 and the corresponding gating unit 102. The scan signal corresponding to each pixel row 101 in the 3×3 array cell indicates that the pixel circuits 1011 in that pixel row 101 are refreshed.

[0145] Furthermore, the column shift register 1041 in the control circuit 104 can respond to the control signal sent by the timing control circuit to generate a gating signal for the gating unit 102 in the corresponding column direction, and then send the gating signal to each gating unit 102. Specifically, for the middle array unit in a 3×3 array, if the gating signal received by the gating unit 102 in this array unit indicates no refresh display, then the level of the refresh control signal generated by the gating unit 102 should also indicate no refresh display. The gating unit 102 generates a refresh control signal with the corresponding level and sends it to the connected pixel circuits 1011, so that the pixel circuits 1011 in the middle array unit do not refresh display. For the surrounding array units, the column shift register 1041 can control the gating units 102 in the array unit through the gating signal, so that the pixel circuits 1011 refresh display in response to the scan signal when the refresh control signal sent by the gating unit 102 indicates refresh display. In this way, it is convenient to control any area in the display panel 10 for partial refresh display.

[0146] In this embodiment, the column shift register 1041, located in the control circuit 104 in the column direction corresponding to the gating unit 102, generates gating signals for the gating unit 102 in the corresponding column direction and sends these signals to the gating unit 102. Thus, the gating signals sent by the column shift register 1041 can control each gating unit 102 in the corresponding column direction, conveniently controlling whether the connected pixel circuits 1011 are refreshed and displayed. This increases the number of pixel circuits 1011 controlled by the scan signal and improves the control efficiency of the control circuit 104.

[0147] Optionally, the pixel circuit 1011 includes: a light-emitting element, a driving module, a refresh module, and a refresh control module;

[0148] The control terminal of the drive module is electrically connected to the first node, the first terminal of the drive module is electrically connected to the second node, and the second terminal of the drive module is electrically connected to the light-emitting element through the third node; the drive module is used to generate a current to drive the light-emitting element to emit light under the potential control of the first node.

[0149] The control terminal of the refresh module is electrically connected to the first scan signal line, the first terminal of the refresh module is electrically connected to the third node, and the second terminal of the refresh module is electrically connected to the first terminal of the refresh control module; the refresh module is used to refresh the potential of the first node; wherein, the first scan signal line is connected to the row shift register 1031 and the pixel circuit 1011;

[0150] The control terminal of the refresh control module is electrically connected to the gating unit 102, and the second terminal of the refresh control module is electrically connected to the first node. The refresh control module is used to respond to the refresh control signal sent by the gating unit 102 and control the connection and disconnection between the refresh module and the first node.

[0151] In some embodiments, multiple first scan signal lines may be provided between the gate driving circuit 103 and the multiple pixel rows 101. The row shift register 1031 can be electrically connected to each pixel circuit 1011 in the corresponding pixel row 101 through the first scan signal. The row shift register 1031 can also be electrically connected to the gating unit 102 corresponding to the pixel row 101 through the first scan signal lines, and send the scan signal corresponding to the pixel row 101 to the pixel circuit 101 and the gating unit 102.

[0152] In some embodiments, the light-emitting element can be a light-emitting diode, such as an organic light-emitting diode (OLED). The driving module can generate a driving current and send the driving current to the light-emitting element, thereby driving the light-emitting element to emit light. The refresh module can receive a scan signal sent from the first scan signal line and, in response to a valid scan signal, turn on the third node and the refresh control module. The refresh control module can, in response to a valid refresh control signal, turn on the refresh module and the first node. When the third node and the first node are turned on, the potential of the first node can be refreshed.

[0153] The pixel circuit 1011 of this application embodiment can be implemented by adding a refresh control module between the refresh module and the first node on the basis of an existing pixel circuit. By sending a refresh control signal to the refresh control module, the on / off state of the refresh module and the first node is controlled, thereby controlling whether the refresh module refreshes the potential of the first node. For example, a TFT can be added to the 7T1C pixel circuit to control whether the potential of the node connected to the gate of the driving transistor is refreshed, thereby controlling whether the pixel circuit refreshes the display. This is merely an example, and the embodiments of this application do not limit the scope of the application.

[0154] Optionally, the driving module includes a first transistor; the refresh module includes a second transistor; and the refresh control module includes a third transistor.

[0155] The control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the second node, and the second electrode of the first transistor is electrically connected to the third node.

[0156] The control electrode of the second transistor is electrically connected to the first scan signal line, the first electrode of the second transistor is electrically connected to the third node, and the second electrode of the second transistor is electrically connected to the first electrode of the third transistor.

[0157] The control electrode of the third transistor is electrically connected to the gating unit 102, and the second electrode of the third transistor is electrically connected to the first node.

[0158] In some embodiments, when the level of the scan signal sent from the first scan signal line to the second transistor is at an active level for the second transistor, the second transistor is turned on, thereby connecting the third node to the first terminal of the third transistor. When the level of the refresh control signal sent from the turn-on unit 102 to the third transistor is at an active level for the third transistor, the third transistor is turned on, thereby connecting the second transistor to the first node, allowing the potential of the first node to be refreshed.

[0159] In some embodiments, the first transistor is a driving transistor for the light-emitting element, capable of generating a driving current to drive the light-emitting element to emit light. When the potential of the first node connected to the control electrode of the first transistor is at the effective potential of the first transistor, the first transistor turns on, thereby connecting the second and third nodes. The second node can be connected to a power supply terminal. When the power supply terminal and the current path of the light-emitting element are connected, a driving current is generated in the circuit, thereby driving the light-emitting element to emit light.

[0160] In this embodiment, the control electrode of the second transistor is electrically connected to the first scan signal line, the first electrode of the second transistor is electrically connected to the third node, and the second electrode of the second transistor is electrically connected to the first electrode of the third transistor. Thus, when the scan signal transmitted from the first scan signal line to the second transistor is at an effective level, the second transistor can be turned on, thereby connecting the third node and the third transistor. Similarly, the control electrode of the third transistor is electrically connected to the gating unit 102, and the second electrode of the third transistor is electrically connected to the first node. Thus, when the gating signal sent by the gating unit 102 is at an effective level, the third transistor can be turned on, thereby connecting the third transistor and the first node. This allows for convenient control of whether the potential of the first node is refreshed via the scan signal and the gating signal. Since the control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the second node, and the second electrode of the first transistor is electrically connected to the third node, when the potential of the first node is refreshed to an effective level, the first transistor can be controlled to generate a current that drives the light-emitting element to emit light, thereby driving the pixel circuit 1011 to refresh the display, improving the practicality of the display panel 10.

[0161] Optionally, the pixel circuit 1011 further includes: a data writing module, a first light emission control module, a second light emission control module, a first reset module, a second reset module, and a third reset module;

[0162] The data writing module is electrically connected to the second scan signal line, the data signal line, and the second node, respectively; wherein, the second scan signal line is connected to the row shift register 1031 and the pixel circuit 1011;

[0163] The first light-emitting control module is electrically connected to the light-emitting control signal line, the first power signal line, and the second node, respectively.

[0164] The second light-emitting control module is electrically connected to the light-emitting control signal line, the third node, and the fourth node, respectively.

[0165] The first reset module is electrically connected to the first reset control signal line, the first initial voltage line, and the third node, respectively.

[0166] The second reset module is electrically connected to the second reset control signal line, the second initial voltage line, and the fourth node, respectively.

[0167] The third reset module is electrically connected to the second reset control signal line, the third initial voltage line, and the second node, respectively.

[0168] In some embodiments, the pixel circuit 1011 may include: a light-emitting element, a driving module, a refresh module, a refresh control module, a data writing module, a first light-emitting control module, a second light-emitting control module, a first reset module, a second reset module, and a third reset module. The control terminal of the data writing module can be electrically connected to the second scan signal line, the first terminal of the data writing module can be electrically connected to the data signal line, and the second terminal of the data writing module can be electrically connected to the second node. The data writing module is used to control the connection and disconnection of the data signal line and the second node in response to the scan signal sent by the second scan signal. The second scan signal line can be connected to the row shift register 1031 in the gate driving circuit 103 to transmit the scan signal sent by the row shift register 1031.

[0169] In some embodiments, the control terminal of the first light-emitting control module can be electrically connected to the light-emitting control signal line, the first end of the first light-emitting control module can be connected to the first power signal line, and the second end of the first light-emitting control module can be connected to the second node. The first light-emitting control module can control the on / off state of the first power signal line and the second node in response to the first light-emitting control signal transmitted via the light-emitting control signal line. The control terminal of the second light-emitting control module can be electrically connected to the light-emitting control signal line, the first end of the second light-emitting control module can be connected to the third node, and the second end of the second light-emitting control module can be connected to the light-emitting element. The second light-emitting control module can control the on / off state of the third node and the light-emitting element in response to the second light-emitting control signal transmitted via the light-emitting control signal line. The first light-emitting control signal and the light-emitting control signal line can be connected to the timing control circuit of the display panel 10, and the timing control circuit performs the light-emitting control.

[0170] In some embodiments, the control terminal of the first reset module can be connected to a first reset control signal line, the first terminal of the first reset module can be connected to a first initial voltage line, and the second terminal of the first reset module can be connected to a third node. The first reset module can control the connection and disconnection of the first initial voltage line and the third node in response to a first reset control signal transmitted via the first reset control signal line. When the first initial voltage line is connected to the third node, the first initial voltage transmitted via the first initial voltage line can reset the potential of the third node. Similarly, when the second initial voltage line is connected to the fourth node, the second initial voltage transmitted via the second initial voltage line can reset the potential of the fourth node, and when the third initial voltage line is connected to the second node, the third initial voltage transmitted via the third initial voltage line can reset the potential of the second node. The first, second, and third initial voltage lines can be connected to the timing control circuit of the display panel 10, and the timing control circuit performs the reset control.

[0171] In some embodiments, the pixel circuit 1011 can be based on the 8T1C pixel circuit 1011 with the addition of a refresh control module. The refresh control module controls whether the refresh module refreshes the node potential connected to the gate of the driving transistor. As shown in FIG6, this embodiment provides a 9T1C pixel circuit 1011, including a light-emitting diode, a storage capacitor, a first transistor T3, a second transistor T2, a third transistor T9, a data writing module including a transistor T4, a first light-emitting control module including a transistor T5, a second light-emitting control module including a transistor T6, a first reset module including a transistor T1, a second reset module including a transistor T7, and a third reset module including a transistor T8. The first transistor T3 is electrically connected to the first node N1, the storage capacitor, the second node N2, and the third node N3. The second transistor T2 is electrically connected to the first scan signal line (scan signal Gate_N), the third node N3, and the third transistor T9. The control electrode of the second transistor T2 is electrically connected to the gating unit 102 and can receive the refresh control signal CL. The second transistor T2 is also electrically connected to the first node N1.

[0172] As shown in Figure 6, transistor T4 is electrically connected to the second scan signal line (scan signal Gate_P), the data signal line (scan signal Date), and the second node N2. Transistor T5 is electrically connected to the light emission control signal line (light emission control signal EM), the first power supply signal line VDD, and the second node N2. Transistor T6 is electrically connected to the light emission control signal line (EM), the third node N3, and the fourth node N4. The fourth node N4 is electrically connected to the anode of the light-emitting diode (LED), and the cathode of the LED is electrically connected to the first power supply signal line VSS. Transistor T1 is electrically connected to the first reset control signal line (reset control signal Reset_P), the first initial voltage line (initialization voltage Vinit1), and the third node N3. Transistor T7 is electrically connected to the second reset control signal line (reset control signal Reset_H), the second initial voltage line (initialization voltage Vinit2), and the fourth node N4. Transistor T8 is electrically connected to the second reset control signal line (reset control signal Reset_H), the third initial voltage line (initialization voltage Vinit3), and the second node N2.

[0173] As shown in Figure 6, the second transistor T2 is an N-type transistor, active high, and the third transistor T9 is a P-type transistor, active low. The refresh control signal CL received by the gate of the third transistor T9 is generated by the gating unit 102. The refresh control signal CL is a signal related to the scan signal Gate_N received by the second transistor T2. When the second transistor T2 is on, when low-frequency display is required, the first node N1 does not need to be refreshed, and the refresh control signal CL is a high-level signal in phase with the scan signal Gate_N. At this time, the third transistor T9 is off, and the pixel circuit 1011 does not refresh the display. When high-frequency display is required, the first node N1 needs to be refreshed, and the refresh control signal CL is a low-level signal in the opposite phase of the scan signal Gate_N. At this time, the third transistor T9 is on, and the pixel circuit 1011 refreshes the display.

[0174] It should be noted that the 8T1C pixel circuit adds a TFT reset drive circuit to the traditional 7T1C pixel circuit. By periodically performing three compensation and reset actions on the pixel circuit 1011 at a base frequency of 120Hz, the pixel status display frequency is increased from 120Hz to 360Hz, resulting in better pixel consistency and a clearer, more transparent display quality. The 9T1C pixel circuit provided in this embodiment can further improve the zoned display effect, enabling pixel-level local refresh display, suitable for diverse application scenarios, and providing users with a better visual experience.

[0175] In this embodiment, the refresh control module in the pixel circuit 1011, under the control of the refresh control signal sent by the gating unit 102, can control whether the refresh module is connected to the first node, thereby controlling whether the refresh module refreshes the potential of the first node. Since the driving module can generate a current to drive the light-emitting element to emit light under the control of the potential of the first node, when the refresh module is connected to the first node and refreshes the potential of the first node in response to the scanning signal, the driving current of the light-emitting element can be refreshed, thereby refreshing the pixel current for display. In this way, pixel-level refresh display control can be easily realized, improving the flexibility of dividing the display area.

[0176] Optionally, the gating unit 102 includes: a control subunit and an output subunit;

[0177] The control terminal of the control subunit is electrically connected to the control circuit 104, and the output terminal of the control subunit is electrically connected to the control terminal of the output subunit.

[0178] The control terminal of the output subunit is also electrically connected to the row shift register 1031 corresponding to pixel row 101; the output terminal of the output subunit is electrically connected to the pixel circuit 1011.

[0179] The control subunit is used to control the output subunit to send a refresh control signal to the pixel circuit 1011 according to the scan signal when the strobe signal indicates refresh display.

[0180] In some embodiments, the control terminal of the control subunit is electrically connected to the control circuit 104 and can receive the gating signal sent by the control circuit 104. The output terminal of the control subunit is electrically connected to the control terminal of the output subunit. The control subunit can generate a corresponding control signal according to the level state of the gating signal, so that the output subunit outputs refresh control signals with different level states in response to the control signal.

[0181] If the strobe signal is at a valid level, it indicates that the pixel circuit 1011 connected to the strobe unit 102 is refreshing the display. The control subunit can send a first control signal to the output subunit, which controls the output subunit to send a valid refresh control signal to the pixel circuit 1011 according to the scan signal. If the strobe signal is at an invalid level, it indicates that the pixel circuit 1011 connected to the strobe unit 102 is not refreshing the display. The control subunit can send a second control signal to the output subunit, which controls the output subunit to send an invalid refresh control signal to the pixel circuit 1011 according to the scan signal.

[0182] In some embodiments, the control terminal of the output subunit is also electrically connected to the row shift register 1031 corresponding to the pixel row 101, and can receive the scan signal sent by the row shift register 1031. When the control subunit sends a first control signal to the output subunit, the output subunit can send a valid refresh control signal to the pixel circuit 1011 according to the scan signal, and control the refresh control module through the valid refresh control signal to connect the refresh module to the first node. When the control subunit sends a second control signal to the output subunit, the output subunit can send an invalid refresh control signal to the pixel circuit 1011 according to the scan signal, and control the refresh control module through the invalid refresh control signal to disconnect the refresh module from the first node.

[0183] Optionally, the control subunit includes a fourth transistor;

[0184] The control electrode of the fourth transistor is electrically connected to the control circuit 104, the first electrode of the fourth transistor is electrically connected to the first control terminal of the output sub-unit, and the second electrode of the fourth transistor is electrically connected to the second control terminal of the output sub-unit; wherein, the second control terminal is also electrically connected to the row shift register 1031 corresponding to the pixel row 101.

[0185] In some embodiments, the control terminal of the fourth transistor is electrically connected to the control circuit 104 and can receive a strobe signal sent by the control circuit 104. If the strobe signal is at an active level, the fourth transistor is turned on, activating the first and second control terminals of the output sub-unit. The scan signal sent by the row shift register 1031 can be simultaneously input to the first and second control terminals of the output sub-unit, so that the output sub-unit sends an active refresh control signal to the pixel circuit 1011 according to the scan signal. If the strobe signal is at an inactive level, the fourth transistor is turned off, disconnecting the first and second control terminals of the output sub-unit. The scan signal can only be input to the second control terminal, so that the output sub-unit sends an inactive refresh control signal to the pixel circuit 1011 according to the scan signal.

[0186] In this embodiment, the fourth transistor can conveniently control whether the scan signal sent by the row shift register 1031 is simultaneously transmitted to the first control terminal and the second control terminal of the output sub-unit, so that the output sub-unit can output refresh control signals with different level states under the control of the fourth transistor, which can improve the practicality of the display panel 10.

[0187] Optionally, the output sub-unit includes a fifth transistor, a sixth transistor, and a seventh transistor;

[0188] The control electrode of the fifth transistor is electrically connected to the output terminal of the control subunit, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the pixel circuit 1011.

[0189] The control electrode of the sixth transistor is electrically connected to the output terminal of the control subunit, the first electrode of the sixth transistor is electrically connected to the second power supply terminal, and the second electrode of the sixth transistor is electrically connected to the pixel circuit 1011.

[0190] The control electrode of the seventh transistor is electrically connected to the output terminal of the control subunit and the row shift register 1031, the first electrode of the seventh transistor is electrically connected to the pixel circuit 1011, and the second electrode of the seventh transistor is electrically connected to the second power supply terminal.

[0191] In some embodiments, the control electrode of the fifth transistor is electrically connected to the output terminal of the control subunit, specifically, it can be electrically connected to the first electrode of the fourth transistor. When the fifth transistor is turned on, it can connect the first power supply terminal to the control terminal of the refresh control module in the pixel circuit 1011, sending a refresh control signal with a level corresponding to the first power supply terminal to the refresh control module. The control electrode of the sixth transistor is electrically connected to the output terminal of the control subunit, specifically, it can also be electrically connected to the first electrode of the fourth transistor. When the sixth transistor is turned on, it can connect the second power supply terminal to the control terminal of the refresh control module in the pixel circuit 1011, sending a refresh control signal with a level corresponding to the second power supply terminal to the refresh control module. The control electrodes of the fifth and sixth transistors are the first control terminals of the output subunit.

[0192] In some embodiments, the control electrode of the seventh transistor is electrically connected to the output terminal of the control subunit; specifically, it can also be electrically connected to the second electrode of the fourth transistor. When the seventh transistor is turned on, it can connect the second power supply terminal to the control terminal of the refresh control module in the pixel circuit 1011, sending a refresh control signal with a level corresponding to the second power supply terminal to the refresh control module. The control electrode of the seventh transistor is the second control terminal of the output subunit.

[0193] Optionally, the fifth transistor is an N-type transistor, and the sixth and seventh transistors are both P-type transistors;

[0194] Alternatively, the fifth transistor may be a P-type transistor, while the sixth and seventh transistors may both be N-type transistors.

[0195] In some embodiments, the sixth and seventh transistors have the same effective voltage level, which can be either high or low; this application does not limit this. The fifth transistor has the opposite effective voltage level to these two transistors. Specifically, if the fifth transistor is an N-type transistor, then the sixth and seventh transistors are both P-type transistors; if the fifth transistor is a P-type transistor, then the sixth and seventh transistors are both N-type transistors. N-type transistors are active high, and P-type transistors are active low.

[0196] Figure 7 exemplarily illustrates a schematic diagram of a gating unit 102 provided in an embodiment of this application. The control subunit includes a fourth transistor T10, and the output subunit includes a fifth transistor T11, a sixth transistor T12, and a seventh transistor T13. As shown in Figure 7, the fourth transistor T10, the sixth transistor T12, and the seventh transistor T13 are P-type transistors, active low, while the fifth transistor T11 is an N-type transistor, active high. The control electrode of the fourth transistor T10 is connected to the control circuit 104 and can receive the gating signal MS sent by the control circuit 104. The control electrode of the seventh transistor T13 can be connected to the first scan signal line Gate_N. The first power supply terminal is a low-level power supply terminal VGL, and the second power supply terminal is a high-level power supply terminal VGH. This gating unit 102 can output a refresh control signal CL to the refresh control module in the pixel circuit 1011.

[0197] In this embodiment, when the fifth transistor is turned on, it can send a refresh control signal corresponding to the first power supply level to the pixel circuit 1011. When the sixth or seventh transistor is turned on, it can send a refresh control signal corresponding to the second power supply level to the pixel circuit 1011. Since the control electrodes of the fifth and sixth transistors are electrically connected to the output terminal of the control subunit, and the control electrode of the seventh transistor is electrically connected to both the output terminal of the control subunit and the row shift register 1031, the gating unit 102 can output refresh control signals with different power supply levels by sending a gating signal to the control subunit and a scan signal to the seventh transistor in the output subunit, thereby improving the practicality of the display panel 10.

[0198] Figure 8 exemplarily illustrates a timing diagram of a display panel 10 provided in an embodiment of this application. As shown in Figure 8, the waveform of the refresh control signal CL is determined by the scan signal Gate_N and the gating signal MS. Combining the pixel circuit 1011 shown in Figure 6 and the gating unit 102 shown in Figure 7, when the scan signal Gate_N represents refresh display, i.e., when the scan signal Gate_N is high, the refresh control signal CL sent by the gating unit 102 to the third transistor T9 can be controlled to be a low-level signal by controlling the high / low level of the gating signal MS, thereby controlling whether the third transistor T9 is turned on, similar to a "filter". In Figure 8, the horizontal axis represents time in milliseconds (ms), and the vertical axis represents voltage in volts (V).

[0199] In some embodiments, based on the requirements for partitioned display such as split-screen display and frequency-division display in any horizontal and vertical direction (X+Y), the display panel 10 needs to have the function of refreshing arbitrary local areas at the pixel level. This application proposes a display panel 10 that controls whether to refresh the node potential connected to the gate of the driving transistor by adding a transistor for refresh control to the pixel circuit 1011. The display panel 10 is applied to an active-matrix organic light-emitting diode (AMOLED) display panel. AMOLED display panels can be applied to smart terminals and continue to develop towards low power consumption, low cost, and large size.

[0200] As shown in Figure 6, the gate of the third transistor T9 receives the refresh control signal CL, which is generated by the gating unit 102. The gating unit 102 added to the display panel 10 of this application can receive the gating signal MS sent by the control circuit 104 to control whether the pixel circuit 1011 is refreshed. When the gating signal MS is high, the gating unit 102 outputs a high-level refresh control signal CL, the third transistor T9 is turned off, and the potential of the first node N1 is not refreshed, resulting in low-frequency display. When the gating signal MS is low, the gating unit 102 outputs a low-level signal with the opposite phase to the scanning signal Gate_N of the second transistor T2. At this time, the third transistor T9 is turned on, and the potential of the first node N1 is refreshed, resulting in high-frequency display. This achieves a pixel-level refresh mode in the X+Y direction, which can flexibly divide the display area and display in any partition, thereby improving the partition display effect of the display panel 10.

[0201] This application provides a driving method applied to the display panel 10 as described in the above embodiment, as shown in FIG9. The driving method includes:

[0202] In step S1, the row shift register 1031 in the gate drive circuit 103 generates a scan signal and sends the scan signal to each pixel circuit 101 in the pixel row 101 and the gating unit 102 corresponding to the pixel row 101.

[0203] In step S2, the control circuit 104 generates a gating signal corresponding to each gating unit 102 based on the partition display information of the current frame, and sends the gating signal to the corresponding gating unit 102.

[0204] In step S3, the gating unit 102 generates a refresh control signal based on the scanning signal and the gating signal, and sends the refresh control signal to the connected pixel circuit 1011;

[0205] In step S4, when the refresh control signal indicates refresh display, the pixel circuit 1011 refreshes the display in response to the scan signal.

[0206] In some embodiments, the row shift register 1031 in the gate driving circuit 103 can generate a scan signal corresponding to each pixel row 101 according to the control signal sent by the timing control circuit of the display panel 10, and then send the scan signal to the pixel row 101 and the gating unit 102 corresponding to the pixel row 101. The column shift register 1041 in the control circuit 104 can generate a gating signal for the gating unit 102 in the corresponding column direction according to the control signal sent by the timing control circuit of the display panel 10, and then send the gating signal to each gating unit 102.

[0207] In some embodiments, the gating unit 102 can determine whether to refresh the connected pixel circuit 1011 based on the level state of the scan signal and the level state of the gating signal, then generate a refresh control signal with the corresponding level state, and send the refresh control signal to the connected pixel circuit 1011. When the refresh control signal indicates refresh display, the pixel circuit 1011 can refresh the potential of the first node connected to the gate of the driving transistor in response to the scan signal, so that the pixel circuit 1011 refreshes the display.

[0208] Optionally, the partition display information includes the refresh display area and the hold display area of ​​the current frame display panel 10; step S2 may include the following sub-steps:

[0209] In sub-step A1, the control circuit 104 generates a gating signal with a first level and sends the gating signal with the first level to the gating unit 102 corresponding to the refresh display area, so that the pixel circuit 1011 in the refresh display area refreshes the display state of the current frame.

[0210] In sub-step A2, the control circuit 104 generates a gating signal with a second level and sends the gating signal with the second level to the gating unit 102 corresponding to the holding display area, so that the pixel circuit 1011 in the holding display area maintains the display state of the previous frame.

[0211] In some embodiments, the display panel 10 is divided into a high-frequency display area and a low-frequency display area, with the high-frequency display area having a high refresh rate and the low-frequency display area having a low refresh rate. For example, the display area of ​​a chat application is a low-frequency display area, while the display area of ​​a video application is a high-frequency display area. Within the current frame, the high-frequency display area needs to be refreshed, while the low-frequency display area can maintain the display state of the previous frame, i.e., it does not need to be refreshed.

[0212] In some embodiments, the partition display information may be the display screen information of the current frame, which may include the refresh display area and the hold display area of ​​the display panel 10 within the current frame. The timing control circuit of the display panel 10 can determine the refresh display area and the hold display area of ​​the display panel 10 within the current frame based on the image data signal, and send corresponding control signals to the column shift register 1041 in the control circuit 104.

[0213] In some embodiments, a gating signal with a first level can be generated for the column shift register 1041 corresponding to the refresh display area, and this first-level gating signal can be sent to the gating unit 102 corresponding to the refresh display area. The first-level gating signal represents refresh display. The gating unit 102 can then generate a refresh control signal with an effective level based on the first-level gating signal and the scan signal, controlling the pixel circuit 1011 to refresh the display. In this way, the pixel circuit 1011 in the refresh display area can refresh the display state of the current frame.

[0214] In some embodiments, for the column shift register 1041 corresponding to the display area, a gating signal with a second level can be generated and sent to the gating unit 102 corresponding to the refresh display area. The second-level gating signal indicates that the display is maintained and no refresh is performed. The gating unit 102 can then generate an invalid-level refresh control signal based on the second-level gating signal and the scan signal, controlling the pixel circuit 1011 to maintain the display state of the previous frame. Thus, the pixel circuit 1011 in the display area can maintain the display state of the previous frame.

[0215] The driving method provided in this application embodiment can achieve the same technical effect as the display panel 10 in the foregoing embodiment. To avoid repetition, it will not be described again here.

[0216] This application provides a display device, which includes a display panel 10 as described in the foregoing embodiments.

[0217] The display device provided in this application embodiment can achieve the same technical effect as the display panel 10 in the foregoing embodiment. To avoid repetition, it will not be described again here.

[0218] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0219] Although alternative embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make further changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the alternative embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.

[0220] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes the element.

[0221] The above provides a detailed description of a display panel, display device, and driving method provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

[0222] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0223] The various component embodiments of this application can be implemented in hardware, or as software modules running on one or more processors, or a combination thereof. Those skilled in the art will understand that microprocessors or digital signal processors (DSPs) can be used in practice to implement some or all of the functions of some or all of the components in the computing processing device according to the embodiments of this application. This application can also be implemented as a device or apparatus program (e.g., a computer program and computer program product) for performing part or all of the methods described herein. Such an implementation of this application can be stored on a computer-readable medium, or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, provided on a carrier signal, or provided in any other form.

[0224] For example, Figure 10 illustrates a computing processing device that can implement the methods according to this application. This computing processing device conventionally includes a processor 1010 and a computer program product or computer-readable medium in the form of a memory 1020. The memory 1020 can be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read-Only Memory), EPROM, hard disk, or ROM. The memory 1020 has storage space 1030 for program code 1031 for performing any of the method steps described above. For example, the storage space 1030 for the program code can include various program codes 1031 respectively for implementing the various steps in the methods described above. These program codes can be read from or written to one or more computer program products. These computer program products include program code carriers such as hard disks, compact discs (CDs), memory cards, or floppy disks. Such computer program products are typically portable or fixed storage units as described with reference to Figure 11. This storage unit can have storage segments, storage spaces, etc., arranged similarly to the memory 1020 in the computing processing device of Figure 10. The program code can be compressed, for example, in a suitable form. Typically, the storage unit includes computer-readable code 1031', which is code that can be read by a processor such as 1010, which, when run by a computing processing device, causes the computing processing device to perform the various steps in the method described above.

[0225] The terms "an embodiment," "embodiment," or "one or more embodiments" as used herein mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this application. Furthermore, please note that the examples of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0226] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0227] In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0228] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel (10), wherein, The display panel (10) includes: multiple pixel rows (101), multiple gating units (102), gate driving circuit (103), and control circuit (104); The pixel row (101) includes a plurality of pixel circuits (1011); The pixel row (101) corresponds to a plurality of the gating units (102); The gate drive circuit (103) includes multiple row shift registers (1031); The row shift register (1031) is electrically connected to each pixel circuit (1011) in the corresponding pixel row (101); The gating unit (102) is electrically connected to one or more pixel circuits (1011) in the pixel row (101), the gating unit (102) is electrically connected to the row shift register (1031) corresponding to the pixel row (101), and the gating unit (102) is also electrically connected to the control circuit (104). The gating unit (102) is used to send a refresh control signal to the pixel circuit (1011) according to the scan signal sent by the row shift register (1031) and the gating signal sent by the control circuit (104); and The pixel circuit (1011) is used to refresh the display in response to the scan signal sent by the row shift register (1031) when the refresh control signal indicates refresh display.

2. The display panel (10) according to claim 1, wherein, The gating unit (102) and the pixel circuit (1011) connected to the gating unit (102) constitute an array unit; and The array unit corresponding to the pixel row (101) is arranged in the row direction of the pixel row (101).

3. The display panel (10) according to claim 1, wherein, The pixel circuit (1011) includes: a light-emitting element, a driving module, a refresh module, and a refresh control module; The control terminal of the driving module is electrically connected to the first node, the first terminal of the driving module is electrically connected to the second node, and the second terminal of the driving module is electrically connected to the light-emitting element through the third node. The driving module is used to generate a current that drives the light-emitting element to emit light under the potential control of the first node; The control terminal of the refresh module is electrically connected to the first scan signal line, the first terminal of the refresh module is electrically connected to the third node, and the second terminal of the refresh module is electrically connected to the first terminal of the refresh control module. The refresh module is used to refresh the potential of the first node; The first scan signal line connects the row shift register and the pixel circuit. The control terminal of the refresh control module is electrically connected to the gating unit (102), and the second terminal of the refresh control module is electrically connected to the first node; and The refresh control module is used to control the connection and disconnection between the refresh module and the first node in response to the refresh control signal sent by the gating unit (102).

4. The display panel (10) according to claim 3, wherein, The driving module includes a first transistor; The refresh module includes a second transistor; The refresh control module includes a third transistor; The control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the second node, and the second electrode of the first transistor is electrically connected to the third node; The control electrode of the second transistor is electrically connected to the first scan signal line, the first electrode of the second transistor is electrically connected to the third node, and the second electrode of the second transistor is electrically connected to the first electrode of the third transistor; and The control electrode of the third transistor is electrically connected to the gating unit (102), and the second electrode of the third transistor is electrically connected to the first node.

5. The display panel (10) according to claim 3, wherein, The pixel circuit (1011) further includes: a data writing module, a first light emission control module, a second light emission control module, a first reset module, a second reset module, and a third reset module; The data writing module is electrically connected to the second scan signal line, the data signal line and the second node respectively; The second scan signal line connects the row shift register and the pixel circuit. The first light-emitting control module is electrically connected to the light-emitting control signal line, the first power signal line, and the second node, respectively; The second light-emitting control module is electrically connected to the light-emitting control signal line, the third node, and the fourth node, respectively; The first reset module is electrically connected to the first reset control signal line, the first initial voltage line, and the third node, respectively. The second reset module is electrically connected to the second reset control signal line, the second initial voltage line, and the fourth node, respectively; and The third reset module is electrically connected to the second reset control signal line, the third initial voltage line, and the second node, respectively.

6. The display panel (10) according to any one of claims 1-5, wherein, The gating unit (102) includes: a control subunit and an output subunit; The control terminal of the control subunit is electrically connected to the control circuit (104), and the output terminal of the control subunit is electrically connected to the control terminal of the output subunit; The control terminal of the output subunit is also electrically connected to the row shift register (1031) corresponding to the pixel row (101); The output terminal of the output subunit is electrically connected to the pixel circuit (1011); and The control subunit is used to control the output subunit to send the refresh control signal to the pixel circuit (1011) according to the scan signal when the strobe signal indicates refresh display.

7. The display panel (10) according to claim 6, wherein, The control subunit includes a fourth transistor; and The control electrode of the fourth transistor is electrically connected to the control circuit (104), the first electrode of the fourth transistor is electrically connected to the first control terminal of the output subunit, and the second electrode of the fourth transistor is electrically connected to the second control terminal of the output subunit. The second control terminal is also electrically connected to the row shift register (1031) corresponding to the pixel row (101).

8. The display panel (10) according to claim 6, wherein, The output sub-unit includes a fifth transistor, a sixth transistor, and a seventh transistor; The control electrode of the fifth transistor is electrically connected to the output terminal of the control subunit, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the pixel circuit (1011). The control electrode of the sixth transistor is electrically connected to the output terminal of the control subunit, the first electrode of the sixth transistor is electrically connected to the second power supply terminal, and the second electrode of the sixth transistor is electrically connected to the pixel circuit (1011); and The control electrode of the seventh transistor is electrically connected to the output terminal of the control subunit and the row shift register (1031), the first electrode of the seventh transistor is electrically connected to the pixel circuit (1011), and the second electrode of the seventh transistor is electrically connected to the second power supply terminal.

9. The display panel (10) according to claim 8, wherein, The fifth transistor is an N-type transistor, and the sixth and seventh transistors are both P-type transistors; Alternatively, the fifth transistor may be a P-type transistor, and the sixth and seventh transistors may both be N-type transistors.

10. The display panel (10) according to any one of claims 1-5, wherein, The multiple row shift registers (1031) are cascaded; The row shift register (1031) of the nth level is electrically connected to each pixel circuit (1011) in the pixel row (101) of the nth row; and The row shift register (1031) of the nth level is also electrically connected to the gating unit (102) corresponding to the pixel row (101) of the nth row; Where n is a positive integer.

11. The display panel (10) according to any one of claims 1-5, wherein, The control circuit (104) includes: a column shift register (1041) disposed in the column direction corresponding to the gating unit (102); The gating unit (102) is electrically connected to the column shift register (1041) in the corresponding column direction; and The column shift register (1041) is used to generate a gating signal for the gating unit (102) in the corresponding column direction and send the gating signal to the gating unit (102); Alternatively, the control circuit (104) is an integrated circuit in the display panel (10).

12. The display panel (10) according to claim 1, wherein the gating unit (102) generates a refresh control signal having a first level when the scan signal indicates refresh display of the pixel row (101) and the gating signal indicates refresh display of the pixel circuit (1011), wherein, The first level refresh control signal characterizes the refresh display; and When the pixel circuit (1011) receives the refresh control signal of the first level, it refreshes the display in response to the scan signal sent by the row shift register (1031).

13. The display panel (10) according to claim 1, wherein the gating unit (102) generates a refresh control signal having a second level when the scan signal indicates that the pixel row (101) is not refreshed, or when the gating signal indicates that the pixel circuit (1011) is not refreshed, wherein, The second level refresh control signal indicates that the display is maintained; and When the pixel circuit (1011) receives the refresh control signal of the second level, it maintains the display state of the previous frame and does not refresh the display.

14. The display panel (10) according to claim 1, wherein the plurality of pixel rows (101) and the gating unit (102) corresponding to each pixel row (101) are disposed in the display area of ​​the display panel (10).

15. The display panel (10) according to claim 1, wherein a high density of the gating units (102) is provided in the central region of the display panel (10), and a low density of the gating units (102) is provided in the surrounding region of the display panel (10).

16. The display panel (10) according to claim 1, wherein the display panel (10) is divided into a high-frequency display area and a low-frequency display area, wherein the high-frequency display area has a high refresh rate and the low-frequency display area has a low refresh rate.

17. A display device, wherein, The display device includes a display panel (10) as described in any one of claims 1 to 16.

18. A driving method, wherein, Applied to a display panel (10) as described in any one of claims 1-16, the driving method includes: The row shift register (1031) in the gate driving circuit (103) generates the scanning signal and sends the scanning signal to each pixel circuit (101) in the pixel row (101) and the gating unit (102) corresponding to the pixel row (101); The control circuit (104) generates the gating signal corresponding to each gating unit (102) according to the partition display information of the current frame, and sends the gating signal to the corresponding gating unit (102); The gating unit (102) generates the refresh control signal based on the scan signal and the gating signal, and sends the refresh control signal to the connected pixel circuit (1011); and The pixel circuit (1011) refreshes the display in response to the scanning signal when the refresh control signal indicates that the display is refreshed.

19. The driving method according to claim 18, wherein, The partition display information includes the refresh display area and the maintained display area of ​​the display panel (10) within the current frame; and The control circuit (104) generates a gating signal corresponding to each gating unit (102) based on the partition display information of the current frame, and sends the gating signal to the corresponding gating unit (102), including: The control circuit (104) generates a gating signal with a first level and sends the gating signal with the first level to the gating unit (102) corresponding to the refresh display area, so that the pixel circuit (1011) in the refresh display area refreshes the display state of the current frame; and The control circuit (104) generates a gating signal with a second level and sends the gating signal with the second level to the gating unit (102) corresponding to the holding display area, so that the pixel circuit (1011) in the holding display area maintains the display state of the previous frame.

20. A computing processing device, wherein, include: Memory containing computer-readable code; as well as One or more processors, wherein when the computer-readable code is executed by the one or more processors, the computing processing device performs the driving method as described in any one of claims 18-19.

21. A computer program comprising computer-readable code, which, when executed on a computing processing device, causes the computing processing device to perform the driving method according to any one of claims 18-19.

22. A computer-readable medium storing the computer program as claimed in claim 21.

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