Gate driver and vehicle display

Abstract

A gate driver and a vehicle display are disclosed herein. The gate driver comprises a shift register module and a selection module. The shift register module includes first to fourth dummy shift register circuits and N shift register circuits. The first dummy shift register circuit is configured to output a first dummy signal. The second dummy shift register circuit is configured to output a second dummy signal. The third dummy shift register circuit is configured to output a third dummy signal. The fourth dummy shift register circuit is configured to output a fourth dummy signal. The selection module is configured to selectively output one of the first dummy signal and the third dummy signal and one of the second dummy signal and the fourth dummy signal according to the forward scan signal and the reverse scan signal.

Description

Technical Field

[0001] This disclosure relates to a gate driver, and more particularly to a gate driver that includes dummy shift register circuitry. Background Technology

[0002] Display panels typically include multiple scan lines and data lines, interleaved to define multiple pixel units. Gate drivers, located in the non-display area or peripheral area of ​​the display panel, sequentially output scan signals. These scan signals are transmitted via scan lines to the switching elements of the pixel units to control their on / off states, thereby driving the pixel units to display corresponding grayscale levels. Gate drivers may include multiple cascaded shift register circuits. Each shift register stage, through the coordination of timing and start signals, sequentially generates scan signals to drive the pixel units in the corresponding row. This cascaded structure allows the gate driver to achieve high-speed and stable scanning operations with a simplified circuit architecture. Summary of the Invention

[0003] This disclosure provides a gate driver comprising a shift register module and a selection module. The shift register module includes a first dummy shift register circuit, a second dummy shift register circuit, a third dummy shift register circuit, a fourth dummy shift register circuit, and N shift register circuits. The first dummy shift register circuit is configured to output a first dummy signal. The second dummy shift register circuit is configured to output a second dummy signal. The third dummy shift register circuit is configured to output a third dummy signal. The fourth dummy shift register circuit is configured to output a fourth dummy signal. The N shift register circuits, including the first to Nth shift register circuits arranged sequentially, are used to output first to Nth scan signals, respectively, where N is a positive integer. The shift register module is configured to sequentially output a first dummy signal, a second dummy signal, a first scan signal to an Nth scan signal, a third dummy signal, and a fourth dummy signal based on the forward scan signal, and sequentially output a fourth dummy signal, a third dummy signal, an Nth scan signal to a first scan signal, a second dummy signal, and a first dummy signal based on the reverse scan signal. The selection module is configured to selectively output one of the first dummy signal and the third dummy signal, and one of the second dummy signal and the fourth dummy signal, based on the forward scan signal and the reverse scan signal.

[0004] According to some embodiments of this disclosure, the third dummy shift register circuit is further configured to output a third dummy signal based on a first timing signal. The fourth dummy shift register circuit is further configured to output a fourth dummy signal based on a second timing signal. The first dummy shift register circuit is further configured to output a first dummy signal based on a third timing signal. The second dummy shift register circuit is further configured to output a second dummy signal based on a fourth timing signal.

[0005] According to some embodiments of this disclosure, the (4K-3)th shift register circuit in the N shift register circuits is further configured to output a first scan signal to the (4K-3)th scan signal in the Nth scan signal according to a first timing signal. The (4K-2)th shift register circuit in the N shift register circuits is further configured to output a first scan signal to the (4K-2)th scan signal in the Nth scan signal according to a second timing signal. The (4K-1)th shift register circuit in the N shift register circuits is further configured to output a first scan signal to the (4K-1)th scan signal in the Nth scan signal according to a third timing signal. The 4Kth shift register circuit in the N shift register circuits is further configured to output a first scan signal to the 4Kth scan signal in the Nth scan signal according to a fourth timing signal, where 1≤K≤N / 4, and K is a positive integer.

[0006] According to some embodiments of this disclosure, the selection module includes a first selection circuit electrically connected to a first dummy shift register circuit and a third dummy shift register circuit. The first selection circuit is configured to output a third dummy signal based on a forward scan signal and a third timing signal, and is configured to output a first dummy signal based on a reverse scan signal and a first timing signal.

[0007] According to some embodiments of this disclosure, the selection module further includes a second selection circuit electrically connected to the second dummy shift register circuit and the fourth dummy shift register circuit. The second selection circuit is configured to output a fourth dummy signal based on the forward scan signal and the fourth timing signal, and is configured to output a second dummy signal based on the reverse scan signal and the second timing signal.

[0008] According to some embodiments of this disclosure, the first selection circuit includes a first transistor, a second transistor, and a third transistor. The first transistor includes a control terminal configured to receive a third timing signal, and a first terminal and a second terminal configured to receive a forward scan signal. The second transistor includes a control terminal electrically connected to a second terminal of the first transistor, and a first terminal and a second terminal configured to receive a third dummy signal. The third transistor includes a control terminal electrically connected to a second terminal of the first transistor, a first terminal electrically connected to a second terminal of the second transistor, and a first terminal and a first output terminal electrically connected to the first terminal and a first output terminal of the third transistor.

[0009] According to some embodiments of this disclosure, the first selection circuit further includes a fourth transistor, a fifth transistor, and a sixth transistor. The fourth transistor includes a control terminal configured to receive a first timing signal, a first terminal configured to receive a backscan signal, and a second terminal. The fifth transistor includes a control terminal electrically connected to the second terminal of the fourth transistor, and a first terminal and a second terminal configured to receive a first dummy signal. The sixth transistor includes a control terminal electrically connected to the second terminal of the fourth transistor, a first terminal electrically connected to the second terminal of the fifth transistor, and a second terminal electrically connected to the first terminal and the first output terminal of the sixth transistor.

[0010] According to some embodiments of this disclosure, the second selection circuit includes a seventh transistor, an eighth transistor, and a ninth transistor. The seventh transistor includes a control terminal configured to receive a fourth timing signal, a first terminal configured to receive a forward scan signal, and a second terminal. The eighth transistor includes a control terminal electrically connected to the second terminal of the seventh transistor, and a first terminal and a second terminal configured to receive a fourth dummy signal. The ninth transistor includes a control terminal electrically connected to the second terminal of the seventh transistor, a first terminal electrically connected to the second terminal of the eighth transistor, and a second terminal electrically connected to the first terminal and the second output terminal of the ninth transistor.

[0011] According to some embodiments of this disclosure, the second selection circuit further includes a tenth transistor, an eleventh transistor, and a twelfth transistor. The tenth transistor includes a control terminal configured to receive a second timing signal, a first terminal configured to receive a backscan signal, and a second terminal. The eleventh transistor includes a control terminal electrically connected to the second terminal of the tenth transistor, a first terminal electrically connected to the second terminal of the eleventh transistor, and a second terminal electrically connected to the first terminal and the second output terminal of the twelfth transistor.

[0012] Another aspect of this disclosure is to provide an automotive display, comprising a substrate, a pixel array, a gate driver as described in any of the above embodiments, and an automotive chip. The pixel array, gate driver, and automotive chip are disposed on the substrate. The pixel array includes a first row of pixel units to an Nth row of pixel units arranged sequentially. A first scan signal to an Nth scan signal are respectively output to the first row of pixel units to the Nth row of pixel units. The automotive chip includes a first pin and a second pin. The first pin is configured to receive one of a first dummy signal and a third dummy signal. The second pin is configured to receive one of a second dummy signal and a fourth dummy signal. Attached Figure Description

[0013] The nature of this disclosure can be understood from the following detailed description and accompanying drawings. It should be noted that many features are not drawn to industry-standard scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0014] Figure 1A This is a schematic diagram of an automotive display according to an embodiment of the present disclosure.

[0015] Figure 1B This is a schematic diagram of an automotive display according to another embodiment of the present disclosure.

[0016] Figure 2 This is a schematic diagram of an automotive display according to yet another embodiment of the present disclosure.

[0017] Figure 3 This is a schematic diagram of a shift register illustrated according to an embodiment of the present disclosure.

[0018] Figure 4A This is a circuit architecture diagram of a first selection circuit illustrated according to an embodiment of the present disclosure.

[0019] Figure 4B This is a circuit architecture diagram of a second selection circuit illustrated according to an embodiment of the present disclosure.

[0020] Figure 5A This is a signal timing diagram illustrating a first selection circuit and a second selection circuit scanning in a forward scan manner according to an embodiment of the present disclosure.

[0021] Figure 5B This is a signal timing diagram illustrating a first selection circuit and a second selection circuit scanning in a reverse scan manner according to an embodiment of the present disclosure.

[0022] [Symbol Explanation]

[0023] 100A, 100B, 200: Automotive displays

[0024] 110, 210: pixel array

[0025] 130, 230: Automotive chips

[0026] 131, 132, 133, 134, 231, 232: Pins

[0027] 250: Select Module

[0028] 251: First Selection Circuit

[0029] 252: Second Selection Circuit

[0030] 270: Shift Register Module

[0031] 290:Substrate

[0032] 300: Shift Register

[0033] 310: Selection Circuit

[0034] 330: Pull-up circuit

[0035] 350: Pull-down circuit

[0036] 370: Output Circuit

[0037] D2U: Backscan signal

[0038] DR1, DR2, DR3, DR4: Dummy shift register circuits

[0039] HC1, HC2, HC3, HC4: Timing signals

[0040] GOA: Gate Driver

[0041] N1, N2, N3, N4: Nodes

[0042] Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12: Transistors

[0043] RP1, RP2, RP3, RP4, RP(N-3), RP(N-2), RP(N-1), RPN: Row Pixel Unit

[0044] SAS1, SAS2: Output terminals

[0045] SIN: Input signal

[0046] SOUT: Output signal

[0047] SD1, SD2, SD3, SD4: Dummy signals

[0048] SG1, SG2, SG3, SG4, SG(N-3), SG(N-2), SG(N-1), SGN: Scan signal

[0049] SR1, SR2, SR3, SR4, SR(N-3), SR(N-2), SR(N-1), SRN: Shift register circuit

[0050] U2D: Forward Scan Signal Detailed Implementation

[0051] This disclosure will be described in detail with reference to the following embodiments. It should be noted that the descriptions of the embodiments in this disclosure are for illustrative purposes only and are not intended to exhaustively disclose all embodiments or limit the specific embodiments of this disclosure. For example, the phrase "a first feature is formed on a second feature" includes various implementations, encompassing both direct contact between the first and second features and additional features formed between the first and second features so that they are not in direct contact. Furthermore, the same element symbols used in the drawings and specification will, as far as possible, represent the same or similar elements.

[0052] It is understood that while terms such as "first" and "second" may be used in this document to describe various features, these terms should not limit these features. These terms are only used to distinguish one feature from another.

[0053] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of the claims. Unless otherwise limited, the singular forms of “a” or “the” may also be used to denote the plural forms.

[0054] Please refer to Figure 1A . Figure 1AThis is a schematic diagram of an automotive display 100A according to an embodiment of the present disclosure. The automotive display 100A may include N shift register circuits SR1-SRN, dummy shift register circuits DR1-DR4, a pixel array 110, and an automotive chip 130. The pixel array 110 may include N rows of pixel units (not shown), each row having pixel units arranged sequentially according to the column number. The shift register circuits SR1-SRN are configured to output scan signals to each pixel unit in the corresponding row, for example, to turn on the switching transistors (not shown) of these pixel units, so that the corresponding data signals can be transmitted to the pixel electrodes (not shown) of these pixel units, thereby displaying the corresponding grayscale. The dummy shift register circuits DR1-DR4 are configured to output corresponding dummy signals to adjust the timing of all scan signals in a frame display phase. In addition, the dummy shift register circuits DR1-DR4 may also have electrostatic discharge (ESD) protection. When an ESD event occurs, the dummy shift register circuits located above and below the shift register circuits SR1 to SRN are affected first, protecting SR1 to SRN and preventing them from affecting the circuitry within the pixel array 110 (the two are connected via scan lines). Therefore, the dummy signals output by the dummy shift register circuits DR1 to DR4 are not transmitted to the pixel array 110, but are transmitted to the corresponding shift register circuits according to the design. In this embodiment, an odd-even interleaving method is used to transmit the start signal between the dummy shift register circuits DR1 to DR4 and the shift register circuits SR1 to SRN, thereby preventing a delay in one scan time from causing a delay in the next adjacent scan time. For example, the dummy signal output by the dummy shift register circuit DR1 will be passed to the shift register circuit SR1 instead of the dummy shift register circuit DR2. The shift register circuit SR1 will be enabled by using the dummy signal output by the dummy shift register circuit DR1 as a start signal to output a scan signal, and this scan signal will be passed to the shift register circuit SR3. Similarly, the scan signal output by the shift register circuit SR(N-3) will be passed to the shift register circuit SR(N-1), and the scan signal output by the shift register circuit SR(N-1) will be passed to the dummy shift register circuit DR3.Similarly, the dummy signal output by the dummy shift register circuit DR2 is passed to the shift register circuit SR2. The shift register circuit SR2 is enabled by the dummy signal output by the dummy shift register circuit DR2 as a start signal to output a scan signal, and this scan signal is passed to the shift register circuit SR4. In this way, the scan signal output by the shift register circuit SR(N-2) is passed to the shift register circuit SRN, and the scan signal output by the shift register circuit SRN is passed to the dummy shift register circuit DR4, thereby controlling the shift register circuits SR1 to SRN to output scan signals in sequence.

[0055] On the other hand, when the number of pixel units in each row of the pixel array 110 is too large (i.e., the resolution is 4K, 8K or higher), the scan signal output by the shift register circuit on one side will experience a voltage drop due to line impedance. This results in insufficient voltage for the scan signal to reach the later pixel units in the same row to activate the switching transistors of these pixel units. Accordingly, Figure 1A The illustrated dummy shift register circuits DR1-DR4 and SR1-SRN are each in pairs and are positioned on both sides of the pixel array 110. The scan signal output from the same shift register circuit on both sides of the pixel array 110 is transmitted to the same row of pixel cells to improve the scan signal voltage drop problem. This architecture can also be called a dual-gate drive circuit architecture.

[0056] It should be noted that, in Figure 1A In this embodiment, when the start signal is transmitted along the direction of the virtual shift register circuit DR1, the odd-numbered shift register circuit to the virtual shift register circuit DR3, and along the direction of the virtual shift register circuit DR2, the even-numbered shift register circuit to the virtual shift register circuit DR4, the shift register circuits SR1 to SRN sequentially output scanning signals to the row pixel units. This scanning sequence is called the "forward scan" direction in this embodiment.

[0057] In this embodiment, the automotive chip 130 may include pins 131 to 134. These pins are used to detect whether the scanning of all rows of pixel units in the pixel array 110 has been completed during a frame display phase, thereby determining whether a display abnormality has occurred. Because Figure 1AIn this embodiment, a forward scan is used. Therefore, pins 131 and 133 are electrically connected to the output of the dummy shift register circuit DR3, and pins 132 and 134 are electrically connected to the output of the dummy shift register circuit DR4. If at least one of pins 131 to 134 does not receive a signal output from the dummy shift register circuit DR3 or DR4, the scan is determined to be incomplete, and an abnormal notification is issued. In one embodiment, pins 131 to 134 of the automotive chip 130 may be Automotive Safety Integrity Level (ASIL) pins.

[0058] Please refer to Figure 1B . Figure 1B This is a schematic diagram of an automotive display 100B according to another embodiment of the present disclosure. The components included in the automotive display 100B are the same as those in the automotive display 100A, and will not be described again here. The difference between the two lies in... Figure 1B In this process, the start signal is transmitted along the virtual shift register circuit DR4, from the even-numbered shift register circuit to the virtual shift register circuit DR2, and along the virtual shift register circuit DR3, from the odd-numbered shift register circuit to the virtual shift register circuit DR1. This causes the shift register circuits SRN to SR1 to output scan signals to the row pixel units in sequence. This scanning sequence is called the "reverse scan" direction in this embodiment. For this scanning direction, pins 131 and 133 of the automotive chip 130 must be electrically connected to the output of the virtual shift register circuit DR1, and pins 132 and 134 must be electrically connected to the virtual shift register circuit DR2 in order to detect whether the pixel scanning is complete and to determine whether the display has malfunctioned.

[0059] However, due to the limited number of pins in the automotive chip 130, therefore... Figure 1A and Figure 1B This dual-gate drive circuit architecture can only provide a maximum of four ASIL pins to detect whether the scan is complete. However, each manufacturer has its own design preferences for automotive displays, and even the same manufacturer may use different scanning methods for different models to perform pixel scanning operations. As mentioned earlier, the virtual shift register circuit electrically connected to the ASIL pin of the automotive chip 130 is different for forward and reverse scanning directions. Therefore, the circuit layout design must be changed for different scanning sequences. Even if the circuits of other components are the same, the traces connected to the ASIL pins still need to be modified accordingly. And just modifying the traces requires at least modifying the layout of three photomasks, which increases manufacturing costs.

[0060] Please refer to Figure 2 . Figure 2 This is a schematic diagram of an automotive display 200 according to another embodiment of the present disclosure. The automotive display 200 may include a pixel array 210, an automotive chip 230, a gate driver GOA, and a substrate 290. The pixel array 210, the automotive chip 230, and the gate driver GOA may be disposed on the substrate 290. In one embodiment, the pixel array 210 may be located in the display area (or in-plane area) of the automotive display 200, while the automotive chip 230 and the gate driver GOA may be located in the non-display area (or out-of-plane area or peripheral area) of the automotive display 200. The substrate 290 may be, for example, a transparent rigid substrate and may be formed of glass, quartz, sapphire, or other suitable materials. In other embodiments, the substrate 290 may also be a transparent flexible substrate, the material of which may include polyimide (PI), polyethylene terephthalate (PET), or other suitable materials.

[0061] Similarly, pixel array 210 may include N rows of pixel units RP1 to RPN, each row having pixel units arranged sequentially according to column number. Each pixel unit may include an electrically connected switching transistor and a pixel electrode (not shown). Gate driver GOA may include selection module 250 and shift register module 270. Shift register module 270 may include N shift register circuits SR1 to SRN and dummy shift register circuits DR1 to DR4. Shift register circuits SR1 to SRN are configured to output scan signals SG1 to SGN to each pixel unit in the row of pixel units RP1 to RPN via scan lines, respectively. For example, scan signal SG1 is transmitted to row pixel unit RP1, scan signal SG2 to row pixel unit RP2, scan signal SG3 to row pixel unit RP3, scan signal SG4 to row pixel unit RP4, ..., scan signal SG(N-3) to row pixel unit RP(N-3), scan signal SG(N-2) to row pixel unit RP(N-2), scan signal SG(N-1) to row pixel unit RP(N-1), and scan signal SGN to row pixel unit RPN. The switching transistors of these pixel units are turned on according to the scan signal, so that data signals are received via data lines and transmitted to the pixel electrodes to display the corresponding grayscale. The dummy shift register circuits DR1 to DR4 are configured to output dummy signals SD1 to SD4 respectively, thereby adjusting the time of all scan signals SG1 to SGN in one frame display phase.

[0062] Similarly, shift register module 270 uses an odd-even interleaving method to transmit the start signal between the dummy shift register circuits DR1-DR4 and the shift register circuits SR1-SRN, thereby preventing a delay in one scan time from causing a delay in the next adjacent scan time. For example, Figure 2 The illustration shows an example of scanning in the forward scan direction. The dummy signal SD1 output by the dummy shift register circuit DR1 is passed to the shift register circuit SR1. SR1 is enabled by SD1 as a start signal to output the scan signal SG1. SG1 is then passed to the shift register circuit SR3, and so on. The scan signal SG(N-1) output by the shift register circuit SR(N-1) is passed to the dummy shift register circuit DR3 as a start signal. Similarly, the dummy signal SD2 output by the dummy shift register circuit DR2 is passed to the shift register circuit SR2. SR2 is enabled by SD2 as a start signal to output the scan signal SG2, which is then passed to the shift register circuit SR4, and so on. The scan signal output by the shift register circuit SRN is passed to the dummy shift register circuit DR4 as a start signal. This controls the shift register circuits SR1 to SRN to sequentially output scan signals to the row pixel units RP1 to RPN.

[0063] The selection module 250 is electrically connected to the output terminals of the dummy shift register circuits DR1 to DR4, and is configured to selectively output one of the dummy signals SD1 and SD3 via output terminal SAS1 and one of the dummy signals SD2 and SD4 via output terminal SAS2, based on the forward scan signal U2D and the reverse scan signal D2U.

[0064] The automotive chip 230 may include pins 231 and 232, which are electrically connected to the output terminals SAS1 and SAS2 of the selection module 250, respectively. In other words, pin 231 may receive one of dummy signals SD1 and SD3 via output terminal SAS1. Pin 232 may receive one of dummy signals SD2 and SD4 via output terminal SAS2. In this way, by detecting these dummy signals, it can be determined whether the scanning of all row pixel units RP1 to RPN of the pixel array 210 has been completed, and thereby determine whether any abnormality has occurred in the display of the automotive display 200. In one embodiment, pins 231 and 232 of the automotive chip 230 may be ASIL pins.

[0065] Figure 2 The gate driver GOA shown is one and located on one side of the pixel array 210, therefore the corresponding number of ASIL pins on the connected automotive chip 230 is two. However, the automotive display 200 can also adopt... Figure 1A and Figure 1B The dual-gate drive circuit architecture shown means that the automotive display 200 may also include another gate driver GOA located on the other side of the pixel array 210. The number of ASIL pins connecting the automotive chip 230 to the two gate drivers GOA can also be increased to four.

[0066] It should be noted that, Figure 2 The gate driver GOA shown is an example of a forward scan sequence; however, the gate driver GOA can also operate in a reverse scan sequence without changing the connection relationship of all components included in the selection module 250 and the shift register module 270.

[0067] Please refer to the above as well. Figure 3 . Figure 3 This is a schematic diagram illustrating a shift register 300 according to an embodiment of the present disclosure. The shift register 300 can be applied to... Figure 2 The shift register module 270 includes shift register circuits SR1-SRN and dummy shift register circuits DR1-DR4. The shift register 300 includes a selection circuit 310, a pull-up circuit 330, a pull-down circuit 350, and an output circuit 370. The selection circuit 310 is configured to provide the received input signal SIN to the pull-up circuit 330 based on the forward scan signal U2D or the reverse scan signal D2U. The pull-up circuit 330 is configured to pull up the input signal SIN, which is at a logic high level, to a higher level and provide the pulled-up input signal to the output circuit 370. The output circuit 370 is configured to provide the pulled-up input signal as the output signal SOUT to the corresponding element based on one of the timing signals HC1-HC4. The pull-down circuit 350 is configured to pull down the output signal SOUT to a logic low level based on one of the timing signals HC1-HC4. In simple terms, since this example uses an alternating parity pass method for scanning, when the output circuit 370 of each shift register circuit or the dummy shift register circuit receives timing signal HC1, the corresponding pull-down circuit 350 receives timing signal HC3; if the output circuit 370 receives timing signal HC2, the corresponding pull-down circuit 350 receives timing signal HC4; if the output circuit 370 receives timing signal HC3, the corresponding pull-down circuit 350 receives timing signal HC1; and if the output circuit 370 receives timing signal HC4, the corresponding pull-down circuit 350 receives timing signal HC2.

[0068] In one embodiment, timing signals HC1 to HC4 can each be a pulse signal with a quarter-cycle of the enable time (i.e., the time when the logic is high), such as... Figure 5A and Figure 5B As shown, timing signals HC1 to HC4 can each be sequentially high for a quarter of a cycle, thereby controlling the timing of the output signals of each shift register circuit SR1 to SRN and the dummy shift register circuit DR1 to DR4.

[0069] Furthermore, the dummy shift register circuit DR1 is also configured to output a dummy signal SD1 based on timing signal HC3. The dummy shift register circuit DR2 is also configured to output a dummy signal SD2 based on timing signal HC4. The dummy shift register circuit DR3 is also configured to output a dummy signal SD3 based on timing signal HC1. The dummy shift register circuit DR4 is also configured to output a dummy signal SD4 based on timing signal HC2.

[0070] For example, the shift register module 270 uses a forward scan sequence with alternating parity (e.g.) Figure 2 Taking the scanning process shown as an example, when shift register 300 is used as a dummy shift register circuit DR1, the input signal SIN can be the first start signal. The selection circuit 310 is enabled according to the forward scan signal U2D and outputs the first start signal to the pull-up circuit 330. The pull-up circuit 330 pulls the first start signal, which is at a logic high level, to a higher level and then passes it to the output circuit 370. The output circuit 370, which is the dummy shift register circuit DR1, receives the timing signal HC3 and, when the timing signal HC3 is at a logic high level, outputs the pulled-up first start signal as the output signal SOUT (i.e., the dummy signal SD1) and passes it to the shift register circuit SR1. In addition, the pull-down circuit 350, which is the dummy shift register circuit DR1, receives the timing signal HC1 and pulls the dummy signal SD1 down to a logic low level when the timing signal HC1 is at a logic high level, so as to prevent the dummy signal SD1 from remaining at a logic high level.

[0071] When shift register 300 functions as a dummy shift register circuit DR2, the input signal SIN can be the second enable signal. Selection circuit 310 is enabled by the forward scan signal U2D and outputs the second enable signal to pull-up circuit 330. Pull-up circuit 330 pulls the second enable signal, which is currently at a logic high level, to a higher level and then passes it to output circuit 370. Output circuit 370, acting as the dummy shift register circuit DR2, receives timing signal HC4 and, when timing signal HC4 is at a high logic level, outputs the pulled-up second enable signal as the output signal SOUT (i.e., the dummy signal SD2) and passes it to shift register circuit SR2. Furthermore, pull-down circuit 350, acting as the dummy shift register circuit DR2, receives timing signal HC2 and, when timing signal HC2 is at a high logic level, pulls the dummy signal SD2 down to a logic low level to prevent the dummy signal SD2 from remaining at a logic high level.

[0072] When shift register 300 functions as a dummy shift register circuit DR3, the input signal SIN can be the scan signal SG(N-1) output by shift register circuit SR(N-1). Selection circuit 310 is enabled by the forward scan signal U2D and outputs the scan signal SG(N-1) to pull-up circuit 330. Pull-up circuit 330 pulls the scan signal SG(N-1), which is at a logic high level, to a higher level and then passes it to output circuit 370. Output circuit 370, acting as the dummy shift register circuit DR3, outputs the pulled-up scan signal SG(N-1) as the output signal SOUT (i.e., the dummy signal SD3) and passes it to selection module 250 when timing signal HC1 is at a high logic level. Furthermore, pull-down circuit 350, acting as the dummy shift register circuit DR3, pulls the output signal SOUT (i.e., the pulled-up scan signal SG(N-1)) to a low logic level when timing signal HC3 is at a high logic level, to prevent the dummy signal SD3 from remaining at a logic high level.

[0073] When shift register 300 functions as a dummy shift register circuit DR4, the input signal SIN can be the scan signal SGN output by shift register circuit SRN. Selection circuit 310 is enabled by the forward scan signal U2D and outputs the scan signal SGN to pull-up circuit 330. Pull-up circuit 330 pulls the scan signal SGN, which is at a logic high level, to a higher level and then passes it to output circuit 370. Output circuit 370, acting as the dummy shift register circuit DR4, outputs the pulled-up scan signal SGN as the output signal SOUT (i.e., the dummy signal SD4) and passes it to selection module 250 when timing signal HC2 is at a high logic level. Furthermore, pull-down circuit 350, acting as the dummy shift register circuit DR4, pulls the output signal SOUT (i.e., the pulled-up scan signal SGN) to a low logic level when timing signal HC4 is at a high logic level, to prevent the dummy signal SD4 from remaining at a logic high level.

[0074] In the example of operation using a reverse scan sequence, selection circuit 310 is enabled according to the reverse scan signal D2U. The input signal SIN received by dummy shift register circuit DR4 is the first enable signal, and its output signal SOUT is passed to shift register circuit SRN. The input signal SIN received by dummy shift register circuit DR3 is the second enable signal, and its output signal SOUT is passed to shift register circuit SR(N-1). The input signal SIN received by dummy shift register circuit DR2 is the scan signal SG2, and its output signal SOUT is passed to selection module 250. The input signal SIN received by dummy shift register circuit DR1 is the scan signal SG1, and its output signal SOUT is passed to selection module 250. Other operations are similar to those described above and will not be repeated here.

[0075] In one embodiment, shift register circuit SR(4K-3) of the N shift register circuits SR1 to SRN included in shift register module 270 is further configured to output scan signal SG(4K-3) according to timing signal HC1. Shift register circuit SR(4K-2) is further configured to output scan signal SG(4K-2) according to timing signal HC2. Shift register circuit SR(4K-1) is further configured to output scan signal SG(4K-3) according to timing signal HC3. Shift register circuit SR(4K) is further configured to output scan signal SG(4K) according to timing signal HC4. 1≤K≤N / 4, where K and N are both positive integers.

[0076] For example, the shift register module 270 also uses a forward scan sequence with alternating parity (e.g.) Figure 2Taking the scanning process shown as an example, with shift register 300 as shift register circuit SR(4K-3), taking shift register circuit SR1 as an example, the input signal SIN can be a dummy signal SD1. Selection circuit 310 is enabled according to the forward scan signal U2D and outputs the dummy signal SD1 to pull-up circuit 330. Pull-up circuit 330 pulls the dummy signal SD1, which is at a logic high level, to a higher level and passes it to output circuit 370. Output circuit 370 receives timing signal HC1 and, when timing signal HC1 is at a high logic level, outputs the pulled-up dummy signal SD1 as output signal SOUT (i.e., scan signal SG1). In addition to being passed to row pixel unit RP1 of pixel array 210 (e.g., via scan line), scan signal SG1 is also passed to shift register circuit SR3. The pull-down circuit 350 receives the timing signal HC3 and pulls the output signal SOUT (i.e., the scan signal SG1) down to the logic low level when the timing signal HC3 is at a high logic level, so as to prevent the scan signal SG1 from still being at a high logic level. The operation of other shift register circuits SR(4K-3) can be deduced in the same way, and will not be described in detail here.

[0077] Similarly, when shift register 300 functions as shift register circuit SR(4K-2), taking shift register circuit SR2 as an example, the input signal SIN can be a dummy signal SD2. Selection circuit 310 is enabled by the forward scan signal U2D and outputs the dummy signal SD2 to pull-up circuit 330. Pull-up circuit 330 pulls the dummy signal SD2, which is at a logic high level, to a higher level and then passes it to output circuit 370. Output circuit 370 receives timing signal HC2 and, when timing signal HC2 is at a high logic level, outputs the pulled-up dummy signal SD2 as output signal SOUT (i.e., scan signal SG2). In addition to being passed to the row pixel unit RP2 of pixel array 210, scan signal SG1 is also passed to shift register circuit SR4. The pull-down circuit 350 receives the timing signal HC4 and pulls the output signal SOUT (i.e., the scan signal SG2) down to the logic low level when the timing signal HC4 is at a high logic level, so as to prevent the scan signal SG2 from still being at a high logic level. The operation of other shift register circuits SR(4K-2) can be deduced in the same way, and will not be described in detail here.

[0078] When shift register 300 is used as shift register circuit SR(4K-1) or SR(4K), the timing signals and specific operations received by its output circuit 370 and pull-down circuit 350 can be referred to the aforementioned embodiments, and will not be repeated here.

[0079] In one embodiment, the selection module 250 may include a first selection circuit 251 and a second selection circuit 252. The first selection circuit 251 is electrically connected to the outputs of the dummy shift register circuits DR1 and DR3. The first selection circuit 251 is configured to output a dummy signal SD3 based on the forward scan signal U2D and the timing signal HC3, and to output a dummy signal SD1 based on the reverse scan signal D2U and the timing signal HC1. The second selection circuit 252 is electrically connected to the outputs of the dummy shift register circuits DR2 and DR4. The second selection circuit 252 is configured to output a dummy signal SD4 based on the forward scan signal U2D and the timing signal HC4, and to output a dummy signal SD2 based on the reverse scan signal D2U and the timing signal HC2.

[0080] Please refer to the above as well. Figure 4A and Figure 4B . Figure 4A This is a circuit architecture diagram of a first selection circuit 251 illustrated according to an embodiment of the present disclosure. Figure 4B This is a circuit architecture diagram of the second selection circuit 252 illustrated according to an embodiment of the present disclosure.

[0081] In one embodiment, the first selection circuit 251 may include transistors Q1 to Q6. Transistor Q1 includes a control terminal configured to receive timing signal HC3, and a first terminal and a second terminal configured to receive forward scan signal U2D. Transistor Q2 includes a control terminal electrically connected to the second terminal of transistor Q1, and a first terminal and a second terminal configured to receive dummy signal SD3. Transistor Q3 includes a control terminal electrically connected to the second terminal of transistor Q1, a first terminal electrically connected to the second terminal of transistor Q2, and a second terminal electrically connected to the first terminal of transistor Q3 and the output terminal SAS1. Transistor Q4 includes a control terminal configured to receive timing signal HC1, and a first terminal and a second terminal configured to receive reverse scan signal D2U. Transistor Q5 includes a control terminal electrically connected to the second terminal of transistor Q4, and a first terminal and a second terminal configured to receive dummy signal SD1. Transistor Q6 includes a control terminal electrically connected to the second terminal of transistor Q4, a first terminal electrically connected to the second terminal of transistor Q5, and a first terminal electrically connected to the first terminal of transistor Q6 and the output terminal SAS1.

[0082] In one embodiment, the second selection circuit 252 may include transistors Q7 to Q12. Transistor Q7 includes a control terminal configured to receive timing signal HC4, and a first terminal and a second terminal configured to receive forward scan signal U2D. Transistor Q8 includes a control terminal electrically connected to the second terminal of transistor Q7, and a first terminal and a second terminal configured to receive dummy signal SD4. Transistor Q9 includes a control terminal electrically connected to the second terminal of transistor Q7, a first terminal electrically connected to the second terminal of transistor Q8, and a second terminal electrically connected to the first terminal of transistor Q9 and the output terminal SAS2. Transistor Q10 includes a control terminal configured to receive timing signal HC2, and a first terminal and a second terminal configured to receive reverse scan signal D2U. Transistor Q11 includes a control terminal electrically connected to the second terminal of transistor Q10, and a first terminal and a second terminal configured to receive dummy signal SD2. Transistor Q12 includes a control terminal electrically connected to the second terminal of transistor Q10, a first terminal electrically connected to the second terminal of transistor Q11, and a first terminal electrically connected to the first terminal of transistor Q12 and the second terminal SAS2.

[0083] The operation of the first selection circuit 251 and the second selection circuit 252 will be further described below. It should be noted that, in this disclosure, the transistors used in the selection circuits are N-type metal-oxide-semiconductor (NMOS). Therefore, the term "high logic level" as used herein refers to the level at which the transistor is turned on, while "low logic level" refers to the level at which the transistor is turned off. However, the above definitions may vary depending on the type of transistor used.

[0084] Please refer to the above as well. Figure 5A and Figure 5B . Figure 5A This is a signal timing diagram illustrating the first selection circuit 251 and the second selection circuit 252 scanning in a forward scan manner according to an embodiment of the present disclosure. Figure 5B This is a signal timing diagram illustrating the first selection circuit 251 and the second selection circuit 252 scanning in a reverse scan manner according to an embodiment of the present disclosure.

[0085] exist Figure 5A In this process, the forward scan signal U2D is maintained at a high logic level, while the reverse scan signal D2U is maintained at a low logic level. Accordingly, the gate driver GOA scans in a forward scan mode. In one operation, for the first selection circuit 251, when transistor Q1 is turned on, the potential of node N3 is pulled up to a high logic level according to the forward scan signal U2D. Since the first terminal (e.g., drain) and the second terminal (e.g., source) of transistor Q3 are short-circuited, it effectively acts as a capacitor to maintain the potential of node N3 at a high logic level. Figure 5AThe signal at node N3 is at a high logic level at all times except when a pulse is generated. Therefore, transistor Q2 remains normally on (conducting). Conversely, when transistor Q4 is on, the potential of node N1 is pulled down to a low logic level according to the backscan signal D2U, and transistor Q6 maintains the potential of node N1 at a low logic level. Therefore, transistor Q5 remains normally off (cutoff). The operation is the same for the second selection circuit 252, so the potential of node N4 is maintained at a high logic level ( Figure 5A The signal at node N4 is at a high logic level at all times except when a pulse is generated, while the potential of node N2 is maintained at a low logic level. That is, transistor Q8 remains normally on and transistor Q11 remains normally off.

[0086] When the dummy shift register circuit DR1 is enabled by receiving the first enable signal, and when the timing signal HC3 is at a high logic level, it passes the dummy signal SD1 to the shift register circuit SR1. At this time, the dummy signal SD1, being the first enable signal pulled up, is also at a high logic level. However, since transistor Q5 is in the off state, the dummy signal SD1 is not passed to the output terminal SAS1. Then, the dummy signal SD1 remains at a low logic level after the next timing. The shift register circuit SR1 passes the scan signal SG1 to the shift register circuit SR3 in a similar operation until the shift register circuit SR(N-1) passes the scan signal SG(N-1) to the dummy shift register circuit DR3. When the dummy shift register circuit DR3 is enabled by receiving the scan signal SG(N-1), and when the timing signal HC1 is at a high logic level, it passes the dummy signal SD3 to the first terminal of transistor Q2 of the first selection circuit 251. At this time, the dummy signal SD3, being the scan signal SG(N-1) pulled up, is also at a high logic level. Since transistor Q2 is in the ON state, the dummy signal SD3, which is at a high logic level, can be passed to the output terminal SAS1 and transmitted to pin 231 of the automotive chip 230. However, due to the characteristics of the transistor, the dummy signal SD3 will have a voltage drop at the second terminal of the ON transistor Q2 (the critical voltage of transistor Q2). To avoid the automotive chip 230 misjudging the situation where the potential of the dummy signal SD3 output from the output terminal SAS1 is insufficient due to the aforementioned voltage drop, the first selection circuit 251 also includes transistor Q3, with its first and second terminals short-circuited to effectively form a capacitor. When transistor Q2 receives the dummy signal SD3 when the timing signal HC1 is at a high logic level, transistor Q1 is turned off because the timing signal HC3 is at a low logic level, and node N3 is in a floating state. Here, the potential of node N3 can be further pulled up to a higher level through the coupling effect of the capacitor (i.e., transistor Q3) to compensate for the voltage drop loss of the dummy signal SD3 when it passes through transistor Q2.

[0087] The operation is similar for the second selection circuit 252. When the dummy shift register circuit DR2 is enabled by receiving the second enable signal, and the timing signal HC4 is at a high logic level, it passes the dummy signal SD2 to the shift register circuit SR2. At this time, the dummy signal SD2 is also at a high logic level as the second enable signal is pulled up. However, since transistor Q11 is in the off state, the dummy signal SD2 is not passed to the output terminal SAS2. The dummy signal SD2 remains at a low logic level after the next timing. The shift register circuit SR2 passes the scan signal SG2 to the shift register circuit SR4 in a similar operation until the shift register circuit SRN passes the scan signal SGN to the dummy shift register circuit DR4. When the dummy shift register circuit DR4 is enabled by receiving the scan signal SGN, and the timing signal HC2 is at a high logic level, it passes the dummy signal SD4 to transistor Q8 of the second selection circuit 252. At this time, the dummy signal SD4 is also at a high logic level as the scan signal SGN is pulled up. Since transistor Q8 is on and transistor Q7 is off due to timing signal HC4 being at a low logic level, the potential of node N4 can be further pulled up to a higher level through the coupling effect of transistor Q9, which is equivalent to a capacitor. In this way, the voltage drop loss of the dummy signal SD4, which is at a high logic level, through transistor Q8 can be compensated, and the signal is transmitted to pin 232 of the automotive chip 230 via output SAS2.

[0088] When pins 231 and 232 of the automotive chip 230 both receive high logic level signals, it can be determined that the scan has been completed. Through the above operation, the first selection circuit 251 and the second selection circuit 252 can correctly transmit the signal indicating the end of the forward scan (i.e., dummy signals SD3 and SD4) instead of the signal indicating the end of the reverse scan (i.e., dummy signals SD1 and SD2) to the ASIL pin (e.g., pins 231 and 232) of the automotive chip 230 when the forward scan signal U2D is at a high logic level, so that it can determine that the scan of this frame signal has been completed and the display is normal.

[0089] exist Figure 5B In this process, the forward scan signal U2D remains at a low logic level, while the reverse scan signal D2U remains at a high logic level. Accordingly, the gate driver GOA performs a reverse scan. Under these conditions, the operation of transistors Q1 to Q12 will be related to... Figure 5A Conversely, the first selection circuit 251 can transmit the signal indicating the end of the reverse scan (i.e., the dummy signal SD1) and the second selection circuit 252 can transmit the signal indicating the end of the reverse scan (i.e., the dummy signal SD2) to the ASIL pin (i.e., pins 231 and 232) of the automotive chip 230. For specific details, please refer to the foregoing implementation, which will not be repeated here.

[0090] Therefore, regardless of whether the gate driver GOA is laid out in a forward or reverse scan manner, the circuit layouts of the first selection circuit 251 and the second selection circuit 252, as described above, can be designed together. In other words, when designing the photomask, only the layouts of the first selection circuit 251 and the second selection circuit 252 need to be designed together, and then there is no need to change the pattern design of the photomask for the forward or reverse scan gate driver circuit, thereby reducing manufacturing costs.

[0091] Although the embodiments of this disclosure have been disclosed above, they are not intended to limit the embodiments of this disclosure. Those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the embodiments of this disclosure. Therefore, the protection scope of the embodiments of this disclosure shall be determined by the scope defined in the appended claims.

Claims

1. A gate driver, comprising: The shift register module includes: The first dummy shift register circuit is configured to output the first dummy signal; The second dummy shift register circuit is configured to output the second dummy signal; The third dummy shift register circuit is configured to output the third dummy signal; The fourth dummy shift register circuit is configured to output the fourth dummy signal; and N shift register circuits, including the first shift register circuit to the Nth shift register circuit arranged in sequence, are used to output the first scan signal to the Nth scan signal respectively, where N is a positive integer; The shift register module is configured to sequentially output the first dummy signal, the second dummy signal, the first scan signal to the Nth scan signal, the third dummy signal, and the fourth dummy signal according to the forward scan signal, and sequentially output the fourth dummy signal, the third dummy signal, the Nth scan signal to the first scan signal, the second dummy signal, and the first dummy signal according to the reverse scan signal; and The selection module is configured to selectively output one of the first dummy signal and the third dummy signal, and one of the second dummy signal and the fourth dummy signal, based on the forward scan signal and the reverse scan signal.

2. The gate driver of claim 1, wherein the third dummy shift register circuit is further configured to output the third dummy signal according to the first timing signal, the fourth dummy shift register circuit is further configured to output the fourth dummy signal according to the second timing signal, the first dummy shift register circuit is further configured to output the first dummy signal according to the third timing signal, and the second dummy shift register circuit is further configured to output the second dummy signal according to the fourth timing signal.

3. The gate driver as claimed in claim 2, wherein the (4K-3)th shift register circuit of the N shift register circuits is further configured to output the first scan signal to the (4K-3)th scan signal of the Nth scan signal according to the first timing signal, the (4K-2)th shift register circuit of the N shift register circuits is further configured to output the first scan signal to the (4K-2)th scan signal of the Nth scan signal according to the second timing signal, the (4K-1)th shift register circuit of the N shift register circuits is further configured to output the first scan signal to the (4K-1)th scan signal of the Nth scan signal according to the third timing signal, and the (4K)th shift register circuit of the N shift register circuits is further configured to output the first scan signal to the (4K)th scan signal of the Nth scan signal according to the fourth timing signal, wherein 1≤K≤N / 4, and K is a positive integer.

4. The gate driver of claim 2, wherein the selection module comprises: A first selection circuit is electrically connected to the first dummy shift register circuit and the third dummy shift register circuit, and is configured to output the third dummy signal according to the forward scan signal and the third timing signal, and to output the first dummy signal according to the reverse scan signal and the first timing signal.

5. The gate driver of claim 4, wherein the selection module further comprises: The second selection circuit is electrically connected to the second dummy shift register circuit and the fourth dummy shift register circuit, and is configured to output the fourth dummy signal according to the forward scan signal and the fourth timing signal, and to output the second dummy signal according to the reverse scan signal and the second timing signal.

6. The gate driver of claim 4, wherein the first selection circuit comprises: The first transistor includes: The control terminal is configured to receive this third timing signal; The first end is configured to receive the forward scan signal; and The second end; The second transistor includes: The control terminal is electrically connected to the second terminal of the first transistor; The first end is configured to receive the third dummy signal; and The second end; and The third transistor includes: The control terminal is electrically connected to the second terminal of the first transistor; The first terminal is electrically connected to the second terminal of the second transistor; and The second terminal is electrically connected to the first terminal and the first output terminal of the third transistor.

7. The gate driver of claim 6, wherein the first selection circuit further comprises: The fourth transistor includes: The control terminal is configured to receive the first timing signal; The first end is configured to receive the reverse scan signal; and The second end; The fifth transistor includes: The control terminal is electrically connected to the second terminal of the fourth transistor; The first end is configured to receive the first dummy signal; and The second end; and The sixth transistor includes: The control terminal is electrically connected to the second terminal of the fourth transistor; The first terminal is electrically connected to the second terminal of the fifth transistor; and The second terminal is electrically connected to the first terminal and the first output terminal of the sixth transistor.

8. The gate driver of claim 5, wherein the second selection circuit comprises: The seventh transistor includes: The control terminal is configured to receive this fourth timing signal; The first end is configured to receive the forward scan signal; and The second end; The eighth transistor includes: The control terminal is electrically connected to the second terminal of the seventh transistor; The first end is configured to receive the fourth dummy signal; and The second end; and The ninth transistor includes: The control terminal is electrically connected to the second terminal of the seventh transistor; The first terminal is electrically connected to the second terminal of the eighth transistor; and The second terminal is electrically connected to the first terminal and the second output terminal of the ninth transistor.

9. The gate driver of claim 8, wherein the second selection circuit further comprises: The tenth transistor includes: The control terminal is configured to receive the second timing signal; The first end is configured to receive the reverse scan signal; and The second end; The eleventh transistor includes: The control terminal is electrically connected to the second terminal of the tenth transistor; The first end is configured to receive the second dummy signal; and The second end; and The twelfth transistor includes: The control terminal is electrically connected to the second terminal of the tenth transistor; The first terminal is electrically connected to the second terminal of the eleventh transistor; and The second terminal is electrically connected to the first terminal and the second output terminal of the twelfth transistor.

10. A vehicle display, comprising: substrate; A pixel array is disposed on the substrate and includes a first column row of pixel units to a Nth row of pixel units arranged sequentially. The gate driver as described in any one of claims 1 to 9 is disposed on the substrate, wherein the first scan signal to the Nth scan signal are respectively used to output to the first column pixel unit to the Nth row pixel unit; and An automotive chip, disposed on the substrate, includes: The first pin is configured to receive one of the first dummy signal and the third dummy signal; and The second pin is configured to receive one of the second dummy signal and the fourth dummy signal.

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