Shift register unit and driving method therefor, gate driving circuit, and display apparatus

Abstract

Provided are a shift register unit and a driving method therefor, a gate driving circuit, and a display apparatus, which belong to the technical field of display. In the shift register unit, a register circuit can transmit signals of different potentials to a control node in different time periods under the control of signals such as an input signal and a clock signal, such that a transmission circuit and an output circuit can both output signals of different potentials by means of a connected output end in different time periods under the control of the potential of the control node. Therefore, it can be seen that the shift register unit can be a hybrid circuit of a P-type transistor and an N-type transistor, thereby achieving the overall simple circuit structure and a relatively good output reliability.

Description

Shift register unit and its driving method, gate driving circuit, display device

[0001] This application claims priority to Chinese Patent Application No. 202411612335.9, filed on November 12, 2024, entitled "Shift Register Unit and Driving Method Thereof, Gate Driving Circuit, Display Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and in particular to a shift register unit and its driving method, gate driving circuit, and display device. Background Technology

[0003] A gate drive circuit is a circuit used to transmit gate drive signals to multiple rows of pixels in a display panel to drive the pixels to emit light. Furthermore, with the development of display technology, and considering narrow bezel designs, gate drive on array (GOA) technology is often used to integrate the gate drive circuit onto the display panel. Accordingly, the gate drive circuit can also be called a GOA circuit.

[0004] Currently, GOA circuits typically include multiple cascaded shift register units (also called GOA units). These GOA units are connected one-to-one with multiple rows of pixels and are used to output gate drive signals to the multiple rows of pixels row by row to drive the pixels to emit light. However, the current GOA unit structure is relatively complex. Summary of the Invention

[0005] A shift register unit and its driving method, a gate driving circuit, and a display device are provided. The technical solution is as follows:

[0006] On the one hand, a shift register unit is provided, the shift register unit comprising:

[0007] A register circuit is connected to an input terminal, a first clock terminal, a second clock terminal, a first power supply terminal, a second power supply terminal, and a control node, respectively. It is used to control the connection and disconnection between the first power supply terminal and the control node in response to the input signal provided by the input terminal, the first clock signal provided by the first clock terminal, and the second clock signal provided by the second clock terminal. The first power supply terminal and the second power supply terminal are connected to the control node at different time periods.

[0008] The transmission circuit is connected to the control node, the third clock terminal, the third power supply terminal, and the cascade output terminal respectively, and is used to control the on / off state of the third clock terminal and the cascade output terminal in response to the potential of the control node, and to control the on / off state of the third power supply terminal and the cascade output terminal, so as to output cascade signals to other cascaded shift register units through the cascade output terminal, and the third clock terminal and the third power supply terminal are respectively connected to the cascade output terminal in different time periods;

[0009] The output circuit is connected to the control node, the fourth clock terminal, the fourth power supply terminal, and the scan output terminal respectively, and is used to control the on / off state of the fourth clock terminal and the scan output terminal in response to the potential of the control node, and to control the on / off state of the fourth power supply terminal and the scan output terminal, so as to output a scan signal to the pixels in the display panel through the scan output terminal, and the fourth clock terminal and the fourth power supply terminal are respectively connected to the scan output terminal at different time periods.

[0010] Optionally, the register circuit includes:

[0011] The first register circuit is connected to the input terminal, the first clock terminal, the first power supply terminal, the second power supply terminal, the first intermediate node, the second intermediate node, and the third intermediate node, respectively, and is used to control the on / off state of the first power supply terminal and the first intermediate node in response to the input signal, and to control the on / off state of the first power supply terminal and the second intermediate node, and to control the on / off state of the second power supply terminal and the third intermediate node in response to the first clock signal.

[0012] The second register circuit is connected to the input terminal, the first clock terminal, the second clock terminal, the first intermediate node, the second intermediate node, the third intermediate node, and the control node, respectively. It is used to control the connection and disconnection between the first intermediate node and the control node in response to the first clock signal, control the connection and disconnection between the second intermediate node and the control node in response to the second clock signal, and control the connection and disconnection between the third intermediate node and the control node in response to the input signal.

[0013] Optionally, the first register circuit includes: a first transistor, a second transistor, and a third transistor; and the first transistor and the second transistor are type I transistors, and the third transistor is a type II transistor;

[0014] The gate of the first transistor is connected to the input terminal, the first electrode of the first transistor is connected to the first power supply terminal, and the second electrode of the first transistor is connected to the first intermediate node.

[0015] The gate of the second transistor is connected to the input terminal, the first terminal of the second transistor is connected to the first power supply terminal, and the second terminal of the second transistor is connected to the second intermediate node;

[0016] The gate of the third transistor is connected to the first clock terminal, the first terminal of the third transistor is connected to the second power supply terminal, and the second terminal of the third transistor is connected to the third intermediate node.

[0017] Optionally, the second register circuit includes a fourth transistor, a fifth transistor, and a sixth transistor; and the fifth transistor is a type I transistor, while the fourth transistor and the sixth transistor are type II transistors.

[0018] The gate of the fourth transistor is connected to the first clock terminal, the first electrode of the fourth transistor is connected to the first intermediate node, and the second electrode of the fourth transistor is connected to the control node.

[0019] The gate of the fifth transistor is connected to the second clock terminal, the first terminal of the fifth transistor is connected to the second intermediate node, and the second terminal of the fifth transistor is connected to the control node;

[0020] The gate of the sixth transistor is connected to the input terminal, the first terminal of the sixth transistor is connected to the third intermediate node, and the second terminal of the sixth transistor is connected to the control node.

[0021] Optionally, the transmission circuit includes a seventh transistor and an eighth transistor; and the seventh transistor is a type I transistor, and the eighth transistor is a type II transistor.

[0022] The gate of the seventh transistor is connected to the control node, the first terminal of the seventh transistor is connected to the third power supply terminal, and the second terminal of the seventh transistor is connected to the cascaded output terminal.

[0023] The gate of the eighth transistor is connected to the control node, the first terminal of the eighth transistor is connected to the third clock terminal, and the second terminal of the eighth transistor is connected to the cascaded output terminal.

[0024] Optionally, the output circuit includes a ninth transistor and a tenth transistor; and the ninth transistor is a type I transistor, and the tenth transistor is a type II transistor.

[0025] The gate of the ninth transistor is connected to the control node, the first terminal of the ninth transistor is connected to the fourth power supply terminal, and the second terminal of the ninth transistor is connected to the scan output terminal.

[0026] The gate of the tenth transistor is connected to the control node, the first terminal of the tenth transistor is connected to the fourth clock terminal, and the second terminal of the tenth transistor is connected to the scan output terminal.

[0027] Optionally, the shift register unit further includes:

[0028] A signal enhancement circuit is connected between the output circuit and the scan output terminal, and is also connected to the fifth power supply terminal and the sixth power supply terminal respectively. It is used to enhance the scan signal output by the output circuit based on the fifth power supply signal provided by the fifth power supply terminal and the sixth power supply signal provided by the sixth power supply terminal, and then transmit it to the scan output terminal.

[0029] Optionally, the signal enhancement circuit includes: an even number of cascaded inverters;

[0030] Each of the inverters includes an eleventh transistor and a twelfth transistor connected in series between the fifth power supply terminal and the sixth power supply terminal; and the eleventh transistor is a type I transistor and the twelfth transistor is a type II transistor.

[0031] Optionally, among the even number of inverters, the potential of the fifth power signal provided by the fifth power supply terminal connected to the last inverter is greater than the potential of the fifth power signal provided by the fifth power supply terminals connected to the other inverters (excluding the last inverter), and the potential of the sixth power signal provided by the sixth power supply terminal connected to the last inverter is greater than or equal to the potential of the sixth power signal provided by the sixth power supply terminals connected to the other inverters. The output terminal of the last inverter is directly connected to the scan output terminal.

[0032] Optionally, the third power supply terminal, the fourth power supply terminal, and the fifth power supply terminal connected to the other inverters are all shared with the first power supply terminal;

[0033] And / or, the sixth power supply terminal connected to the other inverters is shared with the second power supply terminal;

[0034] And / or, the third clock terminal is shared with the first clock terminal.

[0035] Optionally, in the shift register unit, the type I transistor is an N-type transistor and the type II transistor is a P-type transistor.

[0036] Optionally, the shift register unit further includes a capacitor connected between the second power supply terminal and the control node.

[0037] On the other hand, a method for driving a shift register unit is provided, for driving the shift register unit as described in the above aspect; the method includes:

[0038] In the first stage, the register circuit responds to the input signal provided by the input terminal, the first clock signal provided by the first clock terminal, and the second clock signal provided by the second clock terminal, to control the first power supply terminal to be connected to the control node and to control the second power supply terminal to be disconnected from the control node. The transmission circuit responds to the potential of the control node to control the third power supply terminal to be connected to the cascaded output terminal and to control the third clock terminal to be disconnected from the cascaded output terminal. The output circuit responds to the potential of the control node to control the fourth power supply terminal to be connected to the scan output terminal and to control the fourth clock terminal to be disconnected from the scan output terminal, so that the third power signal provided by the third power supply terminal is transmitted to the cascaded output terminal and the fourth power signal provided by the fourth power supply terminal is transmitted to the scan output terminal.

[0039] In the second stage, the register circuit responds to the input signal, the first clock signal, and the second clock signal by controlling the first power supply terminal to disconnect from the control node and controlling the second power supply terminal to connect to the control node. The transmission circuit responds to the potential of the control node by controlling the third power supply terminal to disconnect from the cascaded output terminal and controlling the third clock terminal to connect to the cascaded output terminal. The output circuit responds to the potential of the control node by controlling the fourth power supply terminal to disconnect from the scan output terminal and controlling the fourth clock terminal to connect to the scan output terminal, so that the third clock signal provided by the third clock terminal is transmitted to the cascaded output terminal and the fourth clock signal provided by the fourth clock terminal is transmitted to the scan output terminal.

[0040] In another aspect, a gate driving circuit is provided, the gate driving circuit comprising: a plurality of cascaded shift register units as described in the above aspect, wherein the cascaded output terminal of each stage of the shift register unit is connected to the input terminal of the other cascaded stages of the shift register unit;

[0041] Furthermore, the cascaded multiple shift register units include multiple groups of shift register units, and each group of shift register units includes at least two cascaded shift register units;

[0042] The at least two shift register units are sequentially and alternately connected to at least two fourth clock terminals in a one-to-one correspondence, and the multiple shift register units share the at least two fourth clock terminals.

[0043] Optionally, each group of shift register units includes two shift register units, and the two shift register units are alternately connected to two fourth clock terminals in a one-to-one correspondence.

[0044] In another aspect, a display device is provided, the display device comprising: a display panel, and a gate driving circuit as described in yet another aspect above; the display panel comprising a plurality of pixels;

[0045] The gate driving circuit is connected to the plurality of pixels via the scan output terminal and is used to transmit gate driving signals to the plurality of pixels to drive the plurality of pixels to emit light. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 is a schematic diagram of the structure of a shift register unit provided in an embodiment of this application;

[0048] Figure 2 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0049] Figure 3 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0050] Figure 4 is a schematic diagram of the circuit structure of a shift register unit provided in an embodiment of this application;

[0051] Figure 5 is a schematic flowchart of a driving method for a shift register unit provided in an embodiment of this application;

[0052] Figure 6 is a timing diagram of a shift register unit provided in an embodiment of this disclosure;

[0053] Figure 7 is a timing simulation diagram of a shift register unit provided in an embodiment of this disclosure;

[0054] Figure 8 is a timing simulation diagram of another shift register unit provided in an embodiment of this disclosure;

[0055] Figure 9 is a schematic diagram of a gate driving circuit provided in an embodiment of this disclosure;

[0056] Figure 10 is a schematic diagram of a display device structure provided in an embodiment of this disclosure. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0058] It should be noted that the transistors used in the embodiments of this application can all be thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. For example, a field-effect transistor can be a metal-oxide-semiconductor (MOS) field-effect transistor, also known as a MOS transistor. Furthermore, based on their function in the circuit, the transistors used in the embodiments of this application are mainly switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of this application, the source can be referred to as the first electrode, and the drain as the second electrode. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is the control electrode, also known as the gate; the signal input terminal is the source, and the signal output terminal is the drain. In addition, the switching transistors used in the embodiments of this application can include any of P-type transistors and N-type transistors. A P-type transistor conducts when the gate is at a low potential and is cut off when the gate is at a high potential; an N-type transistor conducts when the gate is at a high potential and is cut off when the gate is at a low potential. Furthermore, multiple signals in the various embodiments of this application correspond to a first potential and a second potential. The first potential and the second potential only represent that the potential of the signal has two state quantities, and do not mean that the first potential or the second potential has a specific value in the whole text.

[0059] Figure 1 is a schematic diagram of a shift register unit provided in an embodiment of this application. As shown in Figure 1, the shift register unit includes: a register circuit 01, a transmission circuit 02, and an output circuit 03.

[0060] Register circuit 01 is connected to input terminal IN, first clock terminal CK1, second clock terminal CK2, first power supply terminal V1, second power supply terminal V2, and control node PU. Furthermore, register circuit 01 is used to control the on / off state of the first power supply terminal V1 and control node PU in response to the input signal provided by input terminal IN, the first clock signal provided by first clock terminal CK1, and the second clock signal provided by second clock terminal CK2. The first power supply terminal V1 and the second power supply terminal V2 are connected to control node PU at different times.

[0061] For example, register circuit 01 can control the first power supply terminal V1 to conduct with the control node PU and control the second power supply terminal V2 to disconnect from the control node PU when the input signal provided by the input terminal IN is at a first potential, the first clock signal provided by the first clock terminal CK1 is at a second potential, and the second clock signal provided by the second clock terminal CK2 is at the first potential, so that the first power signal provided by the first power supply terminal V1 can be transmitted to the control node PU. Register circuit 01 can also control the first power supply terminal V1 to disconnect from the control node PU and control the second power supply terminal V2 to conduct with the control node PU when the input signal provided by the input terminal IN is at a second potential, the first clock signal provided by the first clock terminal CK1 is at a second potential, and the second clock signal provided by the second clock terminal CK2 is at a first potential, so that the second power signal provided by the second power supply terminal V2 can be transmitted to the control node PU. Thus, under the control of register circuit 01, the first power supply terminal V1 and the second power supply terminal V2 can be conducted with the control node PU at different times. Of course, this is only a schematic illustration of part of the working principle of register circuit 01.

[0062] Optionally, in this embodiment, the first potential can be a higher potential relative to the second potential. That is, the first potential can be a high potential, and the second potential can be a low potential. Furthermore, as described above, for an N-type transistor, a high potential can be an effective potential, and a low potential can be an ineffective potential. For a P-type transistor, a low potential can be an effective potential, and a high potential can be an ineffective potential. Of course, in some other embodiments, the first potential can also be a low potential relative to the second potential. Based on this and the working principle of the register circuit 01 described above, it can be seen that the register circuit 01 includes both N-type transistors and P-type transistors.

[0063] Optionally, the first clock signal provided by the first clock terminal CK1 and the second clock signal provided by the second clock terminal CK2 can be inverted clock signals. That is, during the same period, the potentials of the first clock signal and the second clock signal can be exactly opposite. For example, when the potential of the first clock signal is a first potential (e.g., high potential), the potential of the second clock signal can be a second potential (e.g., low potential); conversely, when the potential of the first clock signal is low, the potential of the second clock signal can be high.

[0064] Optionally, the potential of the first power signal provided by the first power terminal V1 can be low, and the potential of the second power signal provided by the second power terminal V2 can be high. Correspondingly, in this embodiment, the first power terminal V1 can also be referred to as the pull-down power terminal VGL, and the second power terminal V2 as the pull-up power terminal VGH. Thus, based on the register circuit 01 controlling the first power terminal V1 and the second power terminal V2 to be connected to the control node PU at different time periods, the potential of the control node PU can be controlled to be high or low at different time periods. Of course, in some other embodiments, the potential of the first power signal provided by the first power terminal V1 can also be high, and the potential of the second power signal provided by the second power terminal V2 can also be low.

[0065] The transmission circuit 02 is connected to the control node PU, the third clock terminal CK3, the third power supply terminal V3, and the cascade output terminal Next, respectively. Furthermore, the transmission circuit 02 is used to control the switching between the third clock terminal CK3 and the cascade output terminal Next in response to the potential of the control node PU, and to control the switching between the third power supply terminal V3 and the cascade output terminal Next, so as to output cascaded signals to other cascaded shift register units via the cascade output terminal Next. The third clock terminal CK3 and the third power supply terminal V3 are respectively turned on and off with the cascade output terminal Next at different time periods.

[0066] For example, when the control node PU's potential is at the first potential, the transmission circuit 02 can control the third power supply terminal V3 to be connected to the cascaded output terminal Next, and control the third clock terminal CK3 to be disconnected from the cascaded output terminal Next. This allows the third power supply signal provided by the third power supply terminal V3 to be transmitted to other cascaded shift register units via the cascaded output terminal Next. In other words, the cascaded signal transmitted to other shift register units at this time is the third power supply signal. When the control node PU's potential is at the second potential, the transmission circuit 02 can control the third power supply terminal V3 to be disconnected from the cascaded output terminal Next, and control the third clock terminal CK3 to be connected to the cascaded output terminal Next. This allows the third clock signal provided by the third clock terminal CK3 to be transmitted to other cascaded shift register units via the cascaded output terminal Next. In other words, the cascaded signal transmitted to other shift register units at this time is the third clock signal. Thus, under the control of the transmission circuit 02, the third clock terminal CK3 and the third power supply terminal V3 can be connected to the cascaded output terminal Next at different time periods. Based on this, it can also be determined that the transmission circuit 02 can include both N-type transistors and P-type transistors.

[0067] Optionally, the third clock signal provided by the third clock terminal CK3 and the first clock signal provided by the first clock terminal CK1 can be in-phase clock signals. That is, the potential of the third clock signal and the potential of the first clock signal can be exactly the same during the same period. For example, when the potential of the first clock signal is a first potential (e.g., a high potential), the potential of the third clock signal can also be a first potential (e.g., a high potential); conversely, when the potential of the first clock signal is a low potential, the potential of the third clock signal can also be a low potential. Based on this, in some embodiments, the third clock terminal CK3 and the first clock terminal CK1 can be shared.

[0068] Optionally, the potential of the third power supply signal provided by the third power supply terminal V3 can be a low potential. Accordingly, in the embodiments of this application, the third power supply terminal V3 can also be referred to as the pull-down power supply terminal VGL.

[0069] Optionally, the cascade output terminal Next can be connected to the input terminal IN of other cascaded shift register units to provide input signals to the input terminals IN of other shift register units. That is, the cascaded signal output by the cascade output terminal Next can be used as an input signal. For the first-stage shift register unit, as shown in Figure 1, its input terminal IN can be connected to a separate enable signal terminal GSTV to receive the enable signal provided by the enable signal terminal GSTV, and in response to the enable signal, output the cascaded signal through the cascade output terminal Next to realize cascaded driving.

[0070] Optionally, the cascaded output Next of the i-th stage shift register unit can be connected to the input IN of the (i+L)-th stage shift register unit. Here, 1 ≤ i ≤ ML, M is the total number of cascaded shift register units, M ≥ 1, and L is a positive integer greater than or equal to 1. For example, L can be 1, meaning that every two adjacent shift register units can be cascaded together.

[0071] Output circuit 03 is connected to control node PU, fourth clock terminal CK4, fourth power supply terminal V4, and scan output terminal Gate, respectively. Furthermore, output circuit 03, in response to the potential of control node PU, controls the switching between fourth clock terminal CK4 and scan output terminal Gate, and also controls the switching between fourth power supply terminal V4 and scan output terminal Gate, so as to output scan signals to the pixels in the display panel via scan output terminal Gate. The fourth clock terminal CK4 and the fourth power supply terminal V4 are respectively turned on with scan output terminal Gate during different time periods.

[0072] For example, when the potential of the control node PU is at the first potential, the output circuit 03 can control the fourth power supply terminal V4 to be connected to the scan output terminal Gate, and control the fourth clock terminal CK4 to be disconnected from the scan output terminal Gate. This allows the fourth power supply signal provided by the fourth power supply terminal V4 to be transmitted to the pixel via the scan output terminal Gate. In other words, the scan signal transmitted to the pixel at this time is the fourth power supply signal. Alternatively, when the potential of the control node PU is at the second potential, the output circuit 03 can control the fourth power supply terminal V4 to be disconnected from the scan output terminal Gate, and control the fourth clock terminal CK4 to be connected to the scan output terminal Gate. This allows the fourth clock signal provided by the fourth clock terminal CK4 to be transmitted to the pixel via the scan output terminal Gate. In other words, the scan signal transmitted to the pixel at this time is the fourth clock signal. This achieves single-pulse output. That is, under the control of the output circuit 03, the fourth clock terminal CK4 and the fourth power supply terminal V4 can be connected to the scan output terminal Gate at different time periods. Based on this, it can also be determined that the output circuit 03 can include both N-type transistors and P-type transistors.

[0073] Optionally, the fourth clock input CK4 can be independent of the other clock inputs. At least two cascaded shift register units can be connected to different fourth clock inputs CK4.

[0074] Optionally, the potential of the fourth power signal provided by the fourth power supply terminal V4 can be a low potential. Accordingly, in the embodiments of this application, the fourth power supply terminal V4 can also be referred to as the pull-down power supply terminal VGL.

[0075] Optionally, the scan output gate can be used to connect to the pixel circuit in the pixel to control the pixel circuit to drive the light-emitting element in the pixel to emit light based on the received scan signal.

[0076] For example, a display panel may include multiple rows and columns of pixels. The scan output terminal (Gate) of each shift register unit can be connected to the data writing transistor included in the pixel circuit of a row of pixels via a gate line to transmit a gate drive signal to the data writing transistor. The data writing transistor, in response to the gate drive signal, controls the data line to transmit a data signal to the driving transistor in the pixel circuit, so that the driving transistor drives the light-emitting element to emit light based on the data signal. The multi-stage shift register unit can transmit the gate drive signal to multiple rows of pixels row by row to scan the pixels and achieve scan driving. Correspondingly, this gate drive signal is also called a scan signal. Furthermore, since the potential of the fourth power supply signal provided by the fourth power supply terminal V4 is low, the scan signal here can refer to the gate drive signal transmitted to the P-type data writing transistor. That is, this shift register unit can realize the shift output of a P-gate, belonging to a P-gate shift register unit. Of course, the signal type here is only illustrative. For example, in some embodiments, the signal output through the scan output terminal (Gate) can also be the light-emitting control signal EM transmitted to the light-emitting control transistor in the pixel circuit. This application does not limit this aspect.

[0077] As can be seen from the above examples, the shift register unit provided in this application includes both P-type transistors and N-type transistors. Based on the P-type transistor being PMOS and the N-type transistor being NMOS, this shift register unit can be a hybrid CMOS architecture. Furthermore, in the shift register unit provided in this application, since different circuits respond to the potential of the same control node PU, the required input signals are output to other shift register units via the cascade output terminal Next, and the required scan signals are output to the pixel circuit via the scan output terminal Gate. That is, the cascade drive and scan drive can be controlled independently without affecting each other. Therefore, compared to embodiments that output cascade signals and scan signals via a single output terminal, the cascade function can avoid being affected by a large load, improving load resistance. This results in better output flexibility and reliability of the shift register unit, enabling the shift register unit to reliably drive pixel emission while simultaneously reliably implementing cascade drive.

[0078] In summary, this application provides a shift register unit. Because the register circuit in this shift register unit can transmit signals of different potentials to the control node at different time periods under the control of input signals and clock signals, both the transmission circuit and the output circuit can output signals of different potentials through the connected output terminals at different time periods under the potential control of the control node. Therefore, it can be seen that this shift register unit can be a hybrid circuit of P-type and N-type transistors, with a simple overall circuit structure and good output reliability.

[0079] Optionally, Figure 2 is a schematic diagram of another shift register unit provided in an embodiment of this application. As shown in Figure 2, the register circuit 01 may include: a first register sub-circuit 011 and a second register sub-circuit 012.

[0080] The first register circuit 011 can be connected to the input terminal IN, the first clock terminal CK1, the first power supply terminal V1, the second power supply terminal V2, the first intermediate node N1, the second intermediate node N2, and the third intermediate node N3, respectively. Furthermore, the first register circuit 011 can be used to control the on / off state of the first power supply terminal V1 and the first intermediate node N1 in response to the input signal, and to control the on / off state of the first power supply terminal V1 and the second intermediate node N2, and to control the on / off state of the second power supply terminal V2 and the third intermediate node N3 in response to the first clock signal.

[0081] For example, the first register circuit 011 can control the first power supply terminal V1 to conduct with the first intermediate node N1 and control the first power supply terminal V1 to conduct with the second intermediate node N2 when the input signal potential is a first potential, so that the low-potential first power signal provided by the first power supply terminal V1 can be transmitted to the first intermediate node N1 and the second intermediate node N2. That is, it can control the potentials of the first intermediate node N1 and the second intermediate node N2 to be low potentials. It can also control the first power supply terminal V1 to disconnect from the first intermediate node N1 and control the first power supply terminal V1 to disconnect from the second intermediate node N2 when the input signal potential is a second potential. The first register circuit 011 can control the first power supply terminal V1 to disconnect from the first intermediate node N1 when the first clock signal potential is a first potential; and it can control the second power supply terminal V2 to conduct with the third intermediate node N3 when the first clock signal potential is a second potential, so that the high-potential second power signal provided by the second power supply terminal V2 can be transmitted to the third intermediate node N3. That is, it can control the potential of the third intermediate node N3 to be high potentials. Based on this, it can also be determined that the first register circuit 011 can include both N-type transistors and P-type transistors.

[0082] The second register circuit 012 can be connected to the input terminal IN, the first clock terminal CK1, the second clock terminal CK2, the first intermediate node N1, the second intermediate node N2, the third intermediate node N3, and the control node PU, respectively. Furthermore, the second register circuit 012 can control the on / off state of the first intermediate node N1 and the control node PU in response to the first clock signal, control the on / off state of the second intermediate node N2 and the control node PU in response to the second clock signal, and control the on / off state of the third intermediate node N3 and the control node PU in response to the input signal.

[0083] For example, the second register circuit 012 can control the first intermediate node N1 to disconnect from the control node PU when the potential of the first clock signal is a first potential; and can control the first intermediate node N1 to turn on the control node PU when the potential of the first clock signal is a second potential, so that the low-potential first power signal transmitted to the first node N1 can be further transmitted to the control node PU, that is, the potential of the control node PU can be controlled to be low. The second register circuit 012 can control the second intermediate node N2 to turn on the control node PU when the potential of the second clock signal is a first potential, so that the low-potential first power signal transmitted to the second intermediate node N2 can be further transmitted to the control node PU, that is, the potential of the control node PU can be controlled to be low; and can control the second intermediate node N2 to disconnect from the control node PU when the potential of the second clock signal is a second potential. The second register circuit 012 can disconnect the third intermediate node N3 from the control node PU when the input signal potential is the first potential; and can connect the third intermediate node N3 to the control node PU when the input signal potential is the second potential, so that the high-potential second power signal transmitted to the third intermediate node N3 can be further transmitted to the control node PU, that is, the potential of the control node PU can be controlled to be high. Based on this, it can also be determined that the second register circuit 012 can include both N-type transistors and P-type transistors.

[0084] Thus, with the cooperation of the first register sub-circuit 011 and the second register sub-circuit 012, the first power supply terminal V1 and the second power supply terminal V2 can be turned on to the control node PU at different time periods, thereby outputting a low-potential first power supply signal and a high-potential second power supply signal to the control node PU at different time periods, so as to control the potential of the control node PU to be low or high.

[0085] Optionally, Figure 3 is a schematic diagram of another shift register unit provided in an embodiment of this application. As shown in Figure 3, the shift register unit may further include a signal enhancement circuit 04.

[0086] The signal enhancement circuit 04 can be connected between the output circuit 03 and the scan output terminal Gate, and is also connected to the fifth power supply terminal V5 and the sixth power supply terminal V6 respectively. Furthermore, the signal enhancement circuit 04 can enhance the scan signal output by the output circuit 03 based on the fifth power supply signal provided by the fifth power supply terminal V5 and the sixth power supply signal provided by the sixth power supply terminal V6 before transmitting it to the scan output terminal Gate.

[0087] For example, the enhancement process can be an inversion process. Of course, to ensure that the potential after enhancement is the same as the potential before enhancement, the signal enhancement circuit 04 can invert the scan signal output by the output circuit 03 an even number of times before transmitting it to the scan output terminal Gate. This enhances the driving capability of the shift register unit, enabling it to reliably output the required scan signal to the pixel circuit via the scan output terminal Gate, thereby allowing the pixel circuit to reliably drive the light-emitting element to emit light. Of course, in some other embodiments, the signal enhancement circuit 04 can also be similarly connected between the transmission circuit 02 and the cascaded output terminal Next to achieve the same enhancement effect and improve the cascaded driving capability of the shift register unit.

[0088] Optionally, in Figure 3, the connection point between the signal enhancement circuit 04 and the output circuit 03 is labeled as node PD. Based on this, it can be understood that the output circuit 03 can respond to the potential of the control node PU by controlling the switching of each terminal in the fourth power supply terminal V4 and the fourth clock terminal CK4 with the node PD; that is, it can control the potential of the node PD. Then, the signal enhancement circuit 04 amplifies the potential of the node PD and outputs it through the scan output terminal Gate.

[0089] Optionally, the potential of the fifth power signal provided by the fifth power terminal V5 can be a low potential, and the potential of the sixth power signal provided by the sixth power terminal V6 can be a high potential. Accordingly, in the embodiments of this application, the fifth power terminal V5 can also be referred to as the pull-down power terminal VGL, and the sixth power terminal V6 can be referred to as the pull-up power terminal VGH.

[0090] Optionally, Figure 4 is a schematic diagram of the circuit structure of a shift register unit provided in an embodiment of this application. As shown in Figure 4, the first register sub-circuit 011 may include: a first transistor T1, a second transistor T2, and a third transistor T3. Furthermore, the first transistor T1 and the second transistor T2 can be type I transistors, and the third transistor T3 can be type II transistors.

[0091] The gate of the first transistor T1 can be connected to the input terminal IN, the first electrode of the first transistor T1 can be connected to the first power supply terminal V1, and the second electrode of the first transistor T1 can be connected to the first intermediate node N1.

[0092] The gate of the second transistor T2 can be connected to the input terminal IN, the first terminal of the second transistor T2 can be connected to the first power supply terminal V1, and the second terminal of the second transistor T2 can be connected to the second intermediate node N2.

[0093] The gate of the third transistor T3 can be connected to the first clock terminal CK1, the first terminal of the third transistor T3 can be connected to the second power supply terminal V2, and the second terminal of the third transistor T3 can be connected to the third intermediate node N3.

[0094] Optionally, as described above, of the type I and type II transistors, one can be N-type and the other can be P-type. That is, one transistor can be an N-type transistor (e.g., NMOS) and the other transistor can be a P-type transistor (e.g., PMOS). For example, based on the premise that the first potential is high and the second potential is low, the type I transistor can be an N-type transistor and the type II transistor can be an N-type transistor.

[0095] Optionally, referring to Figure 4, the second register circuit 012 may include a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6. Furthermore, the fifth transistor T5 may be a type I transistor (e.g., an N-type transistor), and the fourth transistor T4 and the sixth transistor T6 may be type II transistors (e.g., P-type transistors).

[0096] The gate of the fourth transistor T4 can be connected to the first clock terminal CK1, the first terminal of the fourth transistor T4 can be connected to the first intermediate node N1, and the second terminal of the fourth transistor T4 can be connected to the control node PU.

[0097] The gate of the fifth transistor T5 can be connected to the second clock terminal CK2, the first terminal of the fifth transistor T5 can be connected to the second intermediate node N2, and the second terminal of the fifth transistor T5 can be connected to the control node PU.

[0098] The gate of the sixth transistor T6 can be connected to the input terminal IN, the first terminal of the sixth transistor T6 can be connected to the third intermediate node N3, and the second terminal of the sixth transistor T6 can be connected to the control node PU.

[0099] Optionally, referring to Figure 4, the transmission circuit 02 may include a seventh transistor T7 and an eighth transistor T8. Furthermore, the seventh transistor T7 may be a type I transistor (e.g., an N-type transistor), and the eighth transistor T8 may be a type II transistor (e.g., a P-type transistor).

[0100] Among them, the gate of the seventh transistor T7 can be connected to the control node PU, the first terminal of the seventh transistor T7 can be connected to the third power supply terminal V3, and the second terminal of the seventh transistor T7 can be connected to the cascaded output terminal Next.

[0101] The gate of the eighth transistor T8 can be connected to the control node PU, the first terminal of the eighth transistor T8 can be connected to the third clock terminal CK3, and the second terminal of the eighth transistor T8 can be connected to the cascaded output terminal Next.

[0102] Optionally, referring to Figure 4, the output circuit 03 may include a ninth transistor T9 and a tenth transistor T10. Furthermore, the ninth transistor T9 may be a type I transistor (e.g., an N-type transistor), and the tenth transistor T10 may be a type II transistor (e.g., a P-type transistor).

[0103] Among them, the gate of the ninth transistor T9 can be connected to the control node PU, the first terminal of the ninth transistor T9 can be connected to the fourth power supply terminal V4, and the second terminal of the ninth transistor T9 can be connected to the scan output terminal Gate.

[0104] The gate of the tenth transistor T10 can be connected to the control node PU, the first terminal of the tenth transistor T10 can be connected to the fourth clock terminal CK4, and the second terminal of the tenth transistor T10 can be connected to the scan output terminal Gate.

[0105] It is understandable that, in conjunction with Figures 3 and 4, based on the shift register unit which also includes a signal enhancement circuit 04, the second terminals of the ninth transistor T9 and the tenth transistor T10 included in the output circuit 03 can be connected to the node PD, so as to be indirectly connected to the scan output terminal Gate through the signal enhancement circuit 04.

[0106] Optionally, referring to Figure 4, the signal enhancement circuit 04 may include an even number of cascaded inverters F. That is, the signal enhancement circuit 04 can enhance the scan signal output by the output circuit 03 an even number of times before transmitting it to the scan output terminal Gate.

[0107] Each inverter F may include an eleventh transistor T11 and a twelfth transistor T12 connected in series between the fifth power supply terminal V5 and the sixth power supply terminal V6. Furthermore, the eleventh transistor T11 may be a type I transistor (e.g., an N-type transistor), and the twelfth transistor T12 may be a type II transistor (e.g., a P-type transistor).

[0108] For example, referring to Figure 4, the signal enhancement circuit 04 shown includes two inverters F. That is, the signal enhancement circuit 04 can enhance the scan signal output by the output circuit 03 twice before transmitting it to the scan output terminal Gate. One inverter F can also be referred to as a set of buffer transistors.

[0109] To distinguish them, in Figure 4, the inverter F directly connected to the output circuit 03 (i.e., node PD) is labeled as F-1, and the eleventh transistor T11 and the twelfth transistor T12 included in the inverter F-1 are labeled as T11-1 and T12-1, respectively; and the inverter F directly connected to the scan output terminal Gate is labeled as F-2, and the eleventh transistor T11 and the twelfth transistor T12 included in the inverter F-2 are labeled as T11-2 and T12-2, respectively.

[0110] Specifically, the gates of the eleventh transistor T11-1 and the twelfth transistor T12-1 can both be connected to the output circuit 03 (i.e., node PD). The first terminal of the eleventh transistor T11-1 can be connected to the fifth power supply terminal V5, and the first terminal of the twelfth transistor T12-1 can be connected to the sixth power supply terminal V6. The second terminals of the eleventh transistor T11-1 and the twelfth transistor T12-1 can both be connected to the gates of the eleventh transistor T11-2 and the twelfth transistor T12-2, respectively. The first terminal of the eleventh transistor T11-2 can be connected to the fifth power supply terminal V5, and the first terminal of the twelfth transistor T12-2 can be connected to the sixth power supply terminal V6. The second terminals of the eleventh transistor T11-2 and the twelfth transistor T12-2 can both be connected to the scan output terminal Gate.

[0111] Optionally, referring further to Figure 4, it can be seen that the shift register unit described in this embodiment may further include a capacitor C1 connected between the second power supply terminal V2 and the control node PU. This capacitor C1 can be used to maintain the potential of the control node PU, ensuring good potential stability of the control node PU.

[0112] Optionally, referring to Figure 4, it can be seen that among the even number of inverters F, the potential of the fifth power signal provided by the fifth power supply terminal V5 connected to the last inverter F can be less than or equal to the potential of the fifth power signal provided by the fifth power supply terminal V5 connected to the other inverters F (excluding the last inverter F), and the potential of the sixth power signal provided by the sixth power supply terminal V6 connected to the last inverter F can be greater than or equal to the potential of the sixth power signal provided by the sixth power supply terminal V6 connected to the other inverters F.

[0113] It's understandable that the potential magnitude relationship here refers to the absolute value of the potential. For example, the low potential of the power signal provided by VGL2 can differ from that of the power signal provided by VGL1 by approximately 2V. For instance, the low potential Vgl2 of the power signal provided by VGL2 could be -5V, while the low potential Vgl1 of the power signal provided by VGL1 could be -7V.

[0114] In this embodiment, the output of the last inverter F is directly connected to the scan output gate. That is, for Figure 4, the last inverter F can be inverter F-2. To distinguish them, in Figure 4, the fifth power supply terminal V5 connected to the last inverter F (e.g., F-2) is labeled VGL2, and the fifth power supply terminal V5 connected to other inverters F (e.g., F-1) is labeled VGL1. Similarly, the sixth power supply terminal V6 connected to the last inverter F-2 is labeled VGH2, and the sixth power supply terminal V6 connected to other inverters F-1 is labeled VGH1. That is, in this embodiment, dual VGH (i.e., VGH1 & VGH2) and dual VGL (i.e., VGL1 & VGL2) can be used to power the shift register unit. Thus, by flexibly adjusting Vgl2 and / or Vgl1, Vgl1-Vgl2 can be made as small as possible less than the threshold voltage Vth of the eleventh transistor T11 (e.g., T11-2) in the last inverter F, thereby ensuring that the eleventh transistor T11-2 can be fully turned off when needed. The effect of using dual VGH is similar and will not be elaborated further. Of course, in some other embodiments, a single VGH and a single VGL can also be used, that is, any inverter F in the shift register unit is connected to the same VGH (e.g., VGH1) and VGL (e.g., VGL1).

[0115] Optionally, referring to Figures 1 to 4, it can also be seen that the fifth power supply terminal V5 connected to the third power supply terminal V3, the fourth power supply terminal V4, and other inverters F (such as F-1) can all be shared with the first power supply terminal V1. For example, they are all the same pull-down power supply terminal VGL1. And / or, the sixth power supply terminal V6 connected to other inverters F (such as F-1) can be shared with the second power supply terminal V2. For example, they are all the same pull-up power supply terminal VGH1. And / or, the third clock terminal CK3 can be shared with the first clock terminal CK1. For example, they are all the same clock terminal CK. The second clock terminal CK2 can be CKN. The fourth clock terminal can be CB1. In this way, the number of signal terminals that need to be set can be reduced, wiring can be simplified, and costs can be saved.

[0116] Understandably, based on the use of single VGH and single VGL power supply, the fifth power supply terminal V5 connected to the last inverter (e.g., F-2) can also be shared with the first power supply terminal V1, and the sixth power supply terminal V6 connected to the last inverter (e.g., F-2) can also be shared with the second power supply terminal V2.

[0117] As described above, the shift register unit shown in Figure 4 can include three parts: register circuit 01 (also called shift register structure), transmission circuit 02 (also called transmission unit), and output circuit 03 and signal enhancement circuit 04 (also called output unit).

[0118] The shift register structure includes 3 N-type transistors and 4 N-type transistors, belonging to a hybrid P-type + N-type TFT architecture. Combined with the clock signals provided by the first clock terminal CK1 and the second clock terminal CK2 (e.g., CK and CKN), the input signal provided by the input terminal IN can be shifted and latched, registered in the control node PU, and the stability of the latch is ensured by capacitor C1. This shift register structure is a key architecture, and it can be seen that its structure is simple and requires a relatively small number of components.

[0119] The transmission unit includes one P-type transistor and one N-type transistor, similar to a set of diodes or a buffer transistor. The transmission function of this set of diodes can be used to transmit the signal shifted and latched to the control node PU, and then transmit it to the input terminal IN of other cascaded shift register units by controlling the output of the third clock terminal CK3 (e.g., CK), thus realizing cascaded output.

[0120] The output unit includes multiple sets of P-type and N-type transistors (i.e., multiple sets of diodes) connected in series. It can shift and latch the signal to the control node PU, and through coordination with the output of the fourth clock terminal CK4 (e.g., CB1), output the node PD signal. The signal at node PD then controls subsequent diodes to achieve the scanning signal output.

[0121] That is, the shift register unit shown in Figure 4 includes 7 P-type transistors, 7 N-type transistors, and 1 capacitor, belonging to the 14T1C architecture shift register unit. Of course, it is not limited to the 14T1C architecture design. For example, in some other embodiments, the signal enhancement circuit 04 may not be included. Based on the cascaded two-stage shift register units connected to different fourth clock terminals CK4, the structure shown in Figure 4 can be considered to be driven by four sets of clock signals (CK, CKN, CB1, and CB2). CB1 is the fourth clock terminal CK4 connected to the current stage shift register unit, and CB2 is the fourth clock terminal CK4 connected to the next stage shift register unit cascaded from the current stage. Furthermore, the structure shown in Figure 4 requires two sets of power supply signals (VGH1 / VGL1 & VGH2 / VGL2) for driving. Furthermore, in the structure shown in Figure 4, the cascade output terminal Next and the scan output terminal Gate are independent of each other. The required input signals can be transmitted to the input terminals IN of other cascaded shift register units via the cascade output terminal Next, realizing cascaded driving; and the required driving signals can be transmitted to the pixel circuit via the scan output terminal Gate, realizing scan driving. The shift register unit provided in this application embodiment has a simple structure and relatively rich functionality.

[0122] In summary, this application provides a shift register unit. Because the register circuit in this shift register unit can transmit signals of different potentials to the control node at different time periods under the control of input signals and clock signals, both the transmission circuit and the output circuit can output signals of different potentials through the connected output terminals at different time periods under the potential control of the control node. Therefore, it can be seen that this shift register unit can be a hybrid circuit of P-type and N-type transistors, with a simple overall circuit structure and good output reliability.

[0123] This application also provides a method for driving a shift register unit, used to drive the shift register unit as described in the above embodiments. As shown in Figure 5, the method includes:

[0124] Step 501, First stage: The register circuit responds to the input signal provided by the input terminal, the first clock signal provided by the first clock terminal, and the second clock signal provided by the second clock terminal, to control the first power supply terminal to be connected to the control node and to control the second power supply terminal to be disconnected from the control node. The transmission circuit responds to the potential of the control node to control the third power supply terminal to be connected to the cascaded output terminal and to control the third clock terminal to be disconnected from the cascaded output terminal. The output circuit responds to the potential of the control node to control the fourth power supply terminal to be connected to the scan output terminal and to control the fourth clock terminal to be disconnected from the scan output terminal, so that the third power signal provided by the third power supply terminal is transmitted to the cascaded output terminal and the fourth power signal provided by the fourth power supply terminal is transmitted to the scan output terminal.

[0125] Step 502, Second Stage: In response to the input signals, the first clock signal, and the second clock signal, the register circuit controls the first power supply terminal to disconnect from the control node and controls the second power supply terminal to connect to the control node. In response to the potential of the control node, the transmission circuit controls the third power supply terminal to disconnect from the cascaded output terminal and controls the third clock terminal to connect to the cascaded output terminal. In response to the potential of the control node, the output circuit controls the fourth power supply terminal to disconnect from the scan output terminal and controls the fourth clock terminal to connect to the scan output terminal, so that the third clock signal provided by the third clock terminal is transmitted to the cascaded output terminal, and the fourth clock signal provided by the fourth clock terminal is transmitted to the scan output terminal.

[0126] Optionally, taking the structure shown in Figure 4, with the first potential being high and the second potential being low, as an example, Figure 6 shows a timing diagram of a shift register unit, and Figure 7 shows a simulation diagram of the timing diagram shown in Figure 6. The driving principle of the shift register unit is explained below in conjunction with Figures 6 and 7:

[0127] (1) In stage t1, the potential of the input signal provided by the input terminal IN (i.e., the turn-on signal terminal GSTV) can be high, the potential of the first clock signal provided by the first clock terminal CK1 (i.e., CK) can be low, and the potential of the second clock signal provided by the second clock terminal CK2 (i.e., CKN) can be high. Accordingly, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 can all be turned on, and the sixth transistor T6 can be turned off. In this way, the first power supply terminal V1 (i.e., VGL1) can be connected to the first intermediate node N1, the first power supply terminal V1 can be connected to the second intermediate node N2, and the second power supply terminal V2 (i.e., VGH1) can be connected to the third intermediate node N3. The first intermediate node N1 can be connected to the control node PU, the second intermediate node N2 can be connected to the control node PU, and the third intermediate node N3 can be disconnected from the control node PU. Furthermore, the low-potential first power signal provided by the first power supply terminal V1 can be transmitted first to the first intermediate node N1 and the second intermediate node N2 via the activated first transistor T1 and the activated second transistor T2, respectively, and then transmitted to the control node PU via the activated fourth transistor T4 and the fifth transistor T5. Additionally, the high-potential second power signal provided by the second power supply terminal V2 can be transmitted only to the third intermediate node N3 via the activated third transistor T3, without being transmitted to the control node PU. That is, in this stage t1, the potentials of the first intermediate node N1, the second intermediate node N2, and the control node PU can be controlled to be low, and the potential of the third intermediate node N3 can be controlled to be high.

[0128] Based on this, both the eighth transistor T8 and the tenth transistor T10 can be turned on, while both the seventh transistor T7 and the ninth transistor T9 can be turned off. This allows the third clock terminal CK3 (i.e., CK) to be connected to the cascaded output terminal Next, and the third power supply terminal V3 (i.e., VGL1) to be disconnected from the cascaded output terminal Next; and the fourth clock terminal CK4 (i.e., CB1) to be connected to node PD, and the fourth power supply terminal V4 (i.e., VGL1) to be disconnected from node PD. Furthermore, the third clock signal provided by the third clock terminal CK3 can be transmitted to the cascaded output terminal Next via the turned-on eighth transistor T8, and the fourth clock signal provided by the fourth clock terminal CK4 can be transmitted to node PD via the turned-on tenth transistor T10. In this stage t1, the potential of the third clock signal can be low, and the potential of the fourth clock signal can be low. Accordingly, in stage t1, a low-level input signal can be transmitted to the input IN of other stage shift register units via the cascaded output Next. Furthermore, a low-level fourth clock signal can first be output to node PD, and then, after passing through two inverters F-1 and F-2, this low-level fourth clock signal is amplified before being transmitted to the scan output Gate. That is, in stage t1, a low-level scan signal can be transmitted to the pixel via the scan output Gate.

[0129] (2) In stage t2, the potential of the input signal provided by the input terminal IN (i.e., the turn-on signal terminal GSTV) can be low, the potential of the first clock signal provided by the first clock terminal CK1 (i.e., CK) can be high, and the potential of the second clock signal provided by the second clock terminal CK2 (i.e., CKN) can be low. Accordingly, the sixth transistor T6 can be turned on, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 can all be turned off. In this way, the first power supply terminal V1 (i.e., VGL1) can be disconnected from the first intermediate node N1, the first power supply terminal V1 can be disconnected from the second intermediate node N2, and the second power supply terminal V2 (i.e., VGH1) can be disconnected from the third intermediate node N3. It can also be that the first intermediate node N1 is disconnected from the control node PU, the second intermediate node N2 is disconnected from the control node PU, and the third intermediate node N3 is turned on by the control node PU. Furthermore, the potentials of the first intermediate node N1, the second intermediate node N2, and the control node PU can all be maintained at the low potentials of the previous stage (i.e., stage T1), and the low potential signal of the control node PU is transmitted to the third intermediate node N3 via the turned-on sixth transistor T6, causing the potential of the third intermediate node N3 to become low. In other words, in stage t2, the potentials of the first intermediate node N1, the second intermediate node N2, the third intermediate node N3, and the control node PU can all be controlled to be low.

[0130] Based on this, in the same stage t1, both the eighth transistor T8 and the tenth transistor T10 can still be turned on, and both the seventh transistor T7 and the ninth transistor T9 can be turned off. Thus, the third clock terminal CK3 (i.e., CK) can still be turned on to the cascaded output terminal Next, and the third power supply terminal V3 (i.e., VGL1) can still be disconnected from the cascaded output terminal Next; and the fourth clock terminal CK4 (i.e., CB1) can be turned on to the node PD, and the fourth power supply terminal V4 (i.e., VGL1) can still be disconnected from the node PD. Furthermore, the third clock signal provided by the third clock terminal CK3 can still be transmitted to the cascaded output terminal Next via the turned-on eighth transistor T8, and the fourth clock signal provided by the fourth clock terminal CK4 can still be transmitted to the node PD via the turned-on tenth transistor T10. Moreover, in this stage t2, the potential of the third clock signal can be high, and the potential of the fourth clock signal can be high. Accordingly, in stage t2, a high-level input signal can be transmitted to the input IN of other stage shift register units via the cascaded output Next. Furthermore, a high-level fourth clock signal can first be output to node PD, and then, after passing through two inverters F-1 and F-2, this high-level fourth clock signal is amplified before being transmitted to the scan output Gate. In other words, in stage t2, a high-level scan signal can be transmitted to the pixel via the scan output Gate.

[0131] (3) In stage t3, the potential of the input signal provided by the input terminal IN (i.e., the turn-on signal terminal GSTV) can be low, the potential of the first clock signal provided by the first clock terminal CK1 (i.e., CK) can be low, and the potential of the second clock signal provided by the second clock terminal CK2 (i.e., CKN) can be high. Accordingly, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can all be turned on, and the first transistor T1 and the second transistor T2 can all be turned off. In this way, the first power supply terminal V1 (i.e., VGL1) can be disconnected from the first intermediate node N1, the first power supply terminal V1 can be disconnected from the second intermediate node N2, and the second power supply terminal V2 (i.e., VGH1) can be turned on to the third intermediate node N3. It can also be made that the first intermediate node N1 is turned on to the control node PU, the second intermediate node N2 is turned on to the control node PU, and the third intermediate node N3 is turned on to the control node PU. Furthermore, the high-potential second power signal provided by the second power supply terminal V2 can be transmitted first to the third intermediate node N3 via the activated third transistor T3, and then to the control node PU via the activated sixth transistor T6. Additionally, the high-potential signal transmitted to the control node PU can be transmitted to the first intermediate node N1 and the second intermediate node N2 via the activated fourth transistor T4 and fifth transistor T5, respectively. That is, in this stage t3, the potentials of the first intermediate node N1, the second intermediate node N2, the third intermediate node N3, and the control node PU can all be controlled to be high.

[0132] Based on this, both the seventh transistor T7 and the ninth transistor T9 can be turned on, while both the eighth transistor T8 and the tenth transistor T10 can be turned off. This allows the third power supply terminal V3 (i.e., VGL1) to be connected to the cascaded output terminal Next, and the third clock terminal CK3 (i.e., CK) to be disconnected from the cascaded output terminal Next; and the fourth power supply terminal V4 (i.e., VGL1) to be connected to node PD, and the fourth clock terminal CK4 (i.e., CB1) to be disconnected from node PD. Furthermore, the low-potential third power signal provided by the third power supply terminal V3 can be transmitted to the cascaded output terminal Next via the turned-on seventh transistor T7, and the low-potential fourth power signal provided by the fourth power supply terminal V4 can be transmitted to node PD via the turned-on ninth transistor T9. Accordingly, in stage t3, a low-level input signal can be transmitted to the input IN of other shift register units via the cascaded output Next. A low-level fourth power supply signal can first be output to node PD, and then, after passing through two inverters F-1 and F-2, this low-level fourth power supply signal is amplified and transmitted to the scan output Gate. That is, in stage t3, a low-level scan signal can be transmitted to the pixel via the scan output Gate. Thus, one scan output is completed.

[0133] Furthermore, it is understandable that the operation of the two inverters F-1 and F-2 is as follows:

[0134] Based on the low-potential signal output to node PD, the twelfth transistor T12-1 in inverter F-1 can be turned on, and the eleventh transistor T11-1 in inverter F-1 can be turned off. This allows the sixth power supply terminal V6 (i.e., VGH1) to conduct with inverter F-2, while disconnecting the fifth power supply terminal V5 (i.e., VGL1) from inverter F-2. Furthermore, the high-potential sixth power supply signal provided by the sixth power supply terminal V6 can be transmitted to inverter F-2 via the turned-on twelfth transistor T12-1. This further allows the eleventh transistor T11-2 in inverter F-2 to be turned on, and the twelfth transistor T12-2 in inverter F-2 to be turned off. Correspondingly, the fifth power supply terminal V5 (i.e., VGL2) can be turned on with the scan output terminal Gate, while disconnecting the sixth power supply terminal V6 (i.e., VGH2) from the scan output terminal Gate. Furthermore, the low-potential fifth power supply signal provided by the fifth power supply terminal V5 can be transmitted to the scan output terminal Gate via the turned-on eleventh transistor T11-2, thereby enabling the low-potential signal transmitted to node PD to be amplified and then output through the scan output terminal Gate.

[0135] Based on the high-potential signal output to node PD, the eleventh transistor T11-1 in inverter F-1 can be turned on, and the twelfth transistor T12-1 in inverter F-1 can be turned off. This allows the fifth power supply terminal V5 (i.e., VGL1) to conduct with inverter F-2, while the sixth power supply terminal V6 (i.e., VGH1) is disconnected from inverter F-2. Furthermore, the low-potential fifth power supply signal provided by the fifth power supply terminal V5 can be transmitted to inverter F-2 via the turned-on eleventh transistor T11-1. This further allows the twelfth transistor T12-2 in inverter F-2 to be turned on, and the eleventh transistor T11-2 in inverter F-2 to be turned off. Correspondingly, the sixth power supply terminal V6 (i.e., VGH2) can be turned on with the scan output terminal Gate, while the fifth power supply terminal V5 (i.e., VGL2) is disconnected from the scan output terminal Gate. Furthermore, the high-potential sixth power supply signal provided by the sixth power supply terminal V6 can be transmitted to the scan output terminal Gate via the turned-on twelfth transistor T12-2, thereby enabling the high-potential signal transmitted to node PD to be amplified and then output through the scan output terminal Gate.

[0136] Optionally, based on Figures 6 and 7, taking the cascading of every two adjacent shift register units, with each of the cascaded shift register units connected to different fourth clock terminals CK4 (i.e., CB1 and CB2), as an example, Figure 8 also schematically shows the timing diagram of the multi-stage shift register unit's operation. Referring to Figure 8, it can be seen that the clock signals provided by CB1 and CB2 determine the pulse width of the scan signal output through the scan output terminal Gate and the gap between the output pulses. In Figure 8, the cascaded output terminals Next of the four cascaded shift register units are labeled as Next. <1> Next <2> Next <3> and Next <4> The scan output Gate is labeled as Gate. <1> Gate <2> Gate <3> and Gate <4> .

[0137] It is understood that since the driving method of the shift register unit can have the same technical effect as the shift register unit described in the previous embodiment, the technical effect of the driving method of the shift register unit will not be described again here for the sake of brevity.

[0138] This application also provides a gate driving circuit. As shown in FIG9, the gate driving circuit includes: a plurality of cascaded shift register units (also called GOA units) as described in the above embodiments, wherein the cascaded output terminal Next of each stage shift register unit is connected to the input terminal IN of the other cascaded shift register units. The scan output terminal Gate of each stage shift register unit can be connected to a pixel.

[0139] Figure 9 schematically shows four cascaded GOA units, labeled Gate GOA1, Gate GOA2, Gate GOA3 and Gate GOA4.

[0140] Furthermore, the cascaded multiple shift register units can include multiple groups of shift register units, and each group of shift register units can include at least two cascaded shift register units.

[0141] Among them, at least two shift register units can be sequentially and alternately connected to at least two fourth clock terminals CK4 in a one-to-one correspondence, and multiple shift register units can share at least two fourth clock terminals CK4.

[0142] In other words, multiple GOA units can be divided into multiple groups. Each group of GOA units can share at least two fourth clock terminals CK4, and at least two shift register units in each group of GOA units can be alternately connected to the at least two fourth clock terminals CK4 in sequence. In other words, the gate drive circuit can be driven by a multi-phase clock.

[0143] Optionally, referring to Figure 9, each shift register unit shown includes two shift register units, and these two shift register units are alternately connected to two fourth clock terminals CK4 (labeled CB1 and CB2 respectively) in a one-to-one correspondence. For example, Gate GOA1 and Gate GOA2 can be assigned to one shift register unit, and Gate GOA1 can be connected to CB1, while Gate GOA2 can be connected to CB2; Gate GOA3 and Gate GOA4 can be assigned to one shift register unit, and Gate GOA3 can be connected to CB1, while Gate GOA4 can be connected to CB2, and so on. This is an example of using a two-phase clock. Furthermore, referring to Figure 9, it can also be seen that each GOA unit can be connected to clock terminals CK and CKN respectively, and the clock signals provided by CK and CKN can be used by the shift register architecture and transmission unit in each GOA unit. That is, each GOA unit can access three clock terminals.

[0144] It is understood that since the gate drive circuit can have essentially the same technical effect as the shift register unit described in the previous embodiments, the technical effect of the gate drive circuit will not be described again here for the sake of brevity.

[0145] This application also provides a display device. As shown in FIG10, the display device includes: a display panel 100, and a gate driving circuit 000 as described in the above embodiments.

[0146] The display panel 100 includes multiple pixels (not shown in Figure 10). Referring to Figure 9, the gate drive circuit 000 is connected to the multiple pixels via the scan output terminal Gate and is used to transmit gate drive signals to the multiple pixels to drive the multiple pixels to emit light.

[0147] Optionally, the display device described in this application embodiment can be any product or component with display function, such as an organic light-emitting diode (OLED) display device, an active-matrix organic light-emitting diode (AMOLED) display device, or a liquid crystal display device. Furthermore, the display device can be any suitable display device, including but not limited to mobile phones, tablet computers, televisions, monitors, laptops, digital photo frames, navigators, and e-books, etc., any product or component with display function.

[0148] It is understood that since the display device can have essentially the same technical effect as the shift register unit described in the previous embodiments, the technical effect of the display device will not be repeated here for the sake of brevity.

[0149] It should be noted that the terminology used in the embodiments of this application is for illustrative purposes only and is not intended to limit the application. Unless otherwise defined, the technical or scientific terms used in the implementation of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains.

[0150] For example, the words “first,” “second,” or “third,” and similar terms used in the patent application specification and claims of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0151] Similarly, words like "one" or "one" do not indicate a quantity limit, but rather that there is at least one.

[0152] The word “includes” or similar terms means that the elements or objects preceding “includes” or “include” cover the elements or objects listed after “includes” or “include” or their equivalents, and do not exclude other elements or objects.

[0153] Terms like "up," "down," "left," or "right" are used only to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly. "Connection" or "coupled" refers to an electrical connection.

[0154] The "and / or" signifies that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0155] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A shift register unit, the shift register unit comprising: A register circuit is connected to an input terminal, a first clock terminal, a second clock terminal, a first power supply terminal, a second power supply terminal, and a control node, respectively. It is used to control the connection and disconnection between the first power supply terminal and the control node in response to the input signal provided by the input terminal, the first clock signal provided by the first clock terminal, and the second clock signal provided by the second clock terminal. The first power supply terminal and the second power supply terminal are connected to the control node at different time periods. The transmission circuit is connected to the control node, the third clock terminal, the third power supply terminal, and the cascade output terminal respectively, and is used to control the on / off state of the third clock terminal and the cascade output terminal in response to the potential of the control node, and to control the on / off state of the third power supply terminal and the cascade output terminal, so as to output cascade signals to other cascaded shift register units through the cascade output terminal, and the third clock terminal and the third power supply terminal are respectively connected to the cascade output terminal in different time periods; The output circuit is connected to the control node, the fourth clock terminal, the fourth power supply terminal, and the scan output terminal respectively, and is used to control the on / off state of the fourth clock terminal and the scan output terminal in response to the potential of the control node, and to control the on / off state of the fourth power supply terminal and the scan output terminal, so as to output a scan signal to the pixels in the display panel through the scan output terminal, and the fourth clock terminal and the fourth power supply terminal are respectively connected to the scan output terminal at different time periods.

2. The shift register cell of claim 1, wherein, The register circuit includes: The first register circuit is connected to the input terminal, the first clock terminal, the first power supply terminal, the second power supply terminal, the first intermediate node, the second intermediate node, and the third intermediate node, respectively, and is used to control the on / off state of the first power supply terminal and the first intermediate node in response to the input signal, and to control the on / off state of the first power supply terminal and the second intermediate node, and to control the on / off state of the second power supply terminal and the third intermediate node in response to the first clock signal. The second register circuit is connected to the input terminal, the first clock terminal, the second clock terminal, the first intermediate node, the second intermediate node, the third intermediate node, and the control node, respectively. It is used to control the connection and disconnection between the first intermediate node and the control node in response to the first clock signal, control the connection and disconnection between the second intermediate node and the control node in response to the second clock signal, and control the connection and disconnection between the third intermediate node and the control node in response to the input signal.

3. The shift register cell of claim 2, wherein, The first register circuit includes: a first transistor, a second transistor, and a third transistor; and the first transistor and the second transistor are type I transistors, and the third transistor is a type II transistor; The gate of the first transistor is connected to the input terminal, the first electrode of the first transistor is connected to the first power supply terminal, and the second electrode of the first transistor is connected to the first intermediate node. The gate of the second transistor is connected to the input terminal, the first terminal of the second transistor is connected to the first power supply terminal, and the second terminal of the second transistor is connected to the second intermediate node; The gate of the third transistor is connected to the first clock terminal, the first terminal of the third transistor is connected to the second power supply terminal, and the second terminal of the third transistor is connected to the third intermediate node.

4. The shift register cell of claim 2 or 3, wherein, The second register circuit includes a fourth transistor, a fifth transistor, and a sixth transistor; wherein the fifth transistor is a type I transistor, and the fourth transistor and the sixth transistor are type II transistors. The gate of the fourth transistor is connected to the first clock terminal, the first electrode of the fourth transistor is connected to the first intermediate node, and the second electrode of the fourth transistor is connected to the control node. The gate of the fifth transistor is connected to the second clock terminal, the first terminal of the fifth transistor is connected to the second intermediate node, and the second terminal of the fifth transistor is connected to the control node; The gate of the sixth transistor is connected to the input terminal, the first terminal of the sixth transistor is connected to the third intermediate node, and the second terminal of the sixth transistor is connected to the control node.

5. The shift register cell of any one of claims 1 to 4, wherein, The transmission circuit includes a seventh transistor and an eighth transistor; and the seventh transistor is a type I transistor and the eighth transistor is a type II transistor. The gate of the seventh transistor is connected to the control node, the first terminal of the seventh transistor is connected to the third power supply terminal, and the second terminal of the seventh transistor is connected to the cascaded output terminal. The gate of the eighth transistor is connected to the control node, the first terminal of the eighth transistor is connected to the third clock terminal, and the second terminal of the eighth transistor is connected to the cascaded output terminal.

6. The shift register cell of any one of claims 1 to 5, wherein, The output circuit includes a ninth transistor and a tenth transistor; and the ninth transistor is a type I transistor and the tenth transistor is a type II transistor. The gate of the ninth transistor is connected to the control node, the first terminal of the ninth transistor is connected to the fourth power supply terminal, and the second terminal of the ninth transistor is connected to the scan output terminal. The gate of the tenth transistor is connected to the control node, the first terminal of the tenth transistor is connected to the fourth clock terminal, and the second terminal of the tenth transistor is connected to the scan output terminal.

7. The shift register cell of any one of claims 1 to 6, wherein, The shift register unit further includes: A signal enhancement circuit is connected between the output circuit and the scan output terminal, and is also connected to the fifth power supply terminal and the sixth power supply terminal respectively. It is used to enhance the scan signal output by the output circuit based on the fifth power supply signal provided by the fifth power supply terminal and the sixth power supply signal provided by the sixth power supply terminal, and then transmit it to the scan output terminal.

8. The shift register cell of claim 7, wherein, The signal enhancement circuit includes: an even number of cascaded inverters; Each of the inverters includes an eleventh transistor and a twelfth transistor connected in series between the fifth power supply terminal and the sixth power supply terminal; and the eleventh transistor is a type I transistor and the twelfth transistor is a type II transistor.

9. The shift register cell of claim 7 or 8, wherein, In the even number of inverters, the potential of the fifth power signal provided by the fifth power supply terminal connected to the last inverter is less than or equal to the potential of the fifth power signal provided by the fifth power supply terminal connected to the other inverters (excluding the last inverter), and the potential of the sixth power signal provided by the sixth power supply terminal connected to the last inverter is greater than or equal to the potential of the sixth power signal provided by the sixth power supply terminal connected to the other inverters. The output terminal of the last inverter is directly connected to the scan output terminal.

10. The shift register cell of claim 9, wherein, The third power supply terminal, the fourth power supply terminal, and the fifth power supply terminal connected to the other inverters are all shared with the first power supply terminal; And / or, the sixth power supply terminal connected to the other inverters is shared with the second power supply terminal; And / or, the third clock terminal is shared with the first clock terminal.

11. A shift register cell as claimed in any one of claims 3 to 10, wherein, In the shift register unit, the type I transistor is an N-type transistor, and the type II transistor is a P-type transistor.

12. The shift register cell of any one of claims 1 to 11, wherein, The shift register unit further includes a capacitor connected between the second power supply terminal and the control node.

13. A method for driving a shift register unit, used to drive a shift register unit as described in any one of claims 1 to 12; the method comprising: In the first stage, the register circuit responds to the input signal provided by the input terminal, the first clock signal provided by the first clock terminal, and the second clock signal provided by the second clock terminal, to control the first power supply terminal to be connected to the control node and to control the second power supply terminal to be disconnected from the control node. The transmission circuit responds to the potential of the control node to control the third power supply terminal to be connected to the cascaded output terminal and to control the third clock terminal to be disconnected from the cascaded output terminal. The output circuit responds to the potential of the control node to control the fourth power supply terminal to be connected to the scan output terminal and to control the fourth clock terminal to be disconnected from the scan output terminal, so that the third power signal provided by the third power supply terminal is transmitted to the cascaded output terminal and the fourth power signal provided by the fourth power supply terminal is transmitted to the scan output terminal. In the second stage, the register circuit responds to the input signal, the first clock signal, and the second clock signal by controlling the first power supply terminal to disconnect from the control node and controlling the second power supply terminal to connect to the control node. The transmission circuit responds to the potential of the control node by controlling the third power supply terminal to disconnect from the cascaded output terminal and controlling the third clock terminal to connect to the cascaded output terminal. The output circuit responds to the potential of the control node by controlling the fourth power supply terminal to disconnect from the scan output terminal and controlling the fourth clock terminal to connect to the scan output terminal, so that the third clock signal provided by the third clock terminal is transmitted to the cascaded output terminal and the fourth clock signal provided by the fourth clock terminal is transmitted to the scan output terminal.

14. A gate drive circuit, the gate drive circuit comprising: A plurality of cascaded shift register units as described in any one of claims 1 to 12, wherein the cascaded output of each stage of the shift register unit is connected to the input of the other stages of the cascaded shift register units; Furthermore, the cascaded multiple shift register units include multiple groups of shift register units, and each group of shift register units includes at least two cascaded shift register units; The at least two shift register units are sequentially and alternately connected to at least two fourth clock terminals in a one-to-one correspondence, and the multiple shift register units share the at least two fourth clock terminals.

15. The gate drive circuit of claim 14, wherein, Each group of shift register units includes two shift register units, and the two shift register units are alternately connected to two fourth clock terminals in a one-to-one correspondence.

16. A display device comprising: The display panel, and the gate driving circuit as described in claim 14 or 15; The display panel includes multiple pixels; The gate driving circuit is connected to the plurality of pixels via the scan output terminal and is used to transmit gate driving signals to the plurality of pixels to drive the plurality of pixels to emit light.

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