Driving circuit and display panel

Abstract

The present application provides a driving circuit and a display panel, wherein the driving circuit includes a display area and a driving chip located outside the display area, and the driving circuit includes at least a first fan-out trace, a second fan-out trace, and a data line. The first fan-out trace is located in the display area and is electrically connected to the driving chip, the second fan-out trace is located in the display area and is connected to the first fan-out trace, and the data line is located in the display area and is connected to the second fan-out trace. The first fan-out trace, the second fan-out trace, and the data line are arranged in different layers, and the second fan-out trace is located between the first fan-out trace and the data line. By arranging two layers of fan-out traces located on the upper layer of the data line in the display area, the driving chip can drive the data line. Since the first fan-out trace and the second fan-out trace are both located in the display area, the space originally required for wiring below the display area can be saved to achieve a narrow lower frame.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving circuit and a display panel. Background Art

[0002] Active-Matrix Organic Light Emitting Diode (AMOLED) display panels are becoming the next-generation display technology due to their high contrast, wide color gamut, and low power consumption. Compared to traditional Liquid Crystal Display (LCD) panels, OLED display panels are easier to make flexible and are a key technology for wearable and foldable products.

[0003] With the development of OLED panel technology, narrow bezel technology has become a differentiating technology that attracts a large number of users. How to achieve narrow bezels is currently a pressing issue. Summary of the Invention

[0004] The purpose of this application is to provide a driving circuit and a display panel, aiming to achieve a narrow bottom bezel.

[0005] In one aspect, the present application provides a driving circuit, comprising a display area and a driving chip located outside the display area, wherein the driving circuit comprises at least:

[0006] a first fan-out trace located in the display area and electrically connected to the driver chip;

[0007] a second fan-out line, located in the display area and connected to the first fan-out line;

[0008] a data line located in the display area and connected to the second fan-out line;

[0009] The first fan-out line, the second fan-out line and the data line are arranged in different layers, and the second fan-out line is located between the first fan-out line and the data line.

[0010] In some embodiments, the second fan-out trace is connected to the first fan-out trace through a first via, and the data line is connected to the second fan-out trace through a second via.

[0011] In some embodiments, the first fan-out trace is arranged along a first direction from the bottom of the display area, the second fan-out trace is bent relative to the first fan-out trace, and the first via is located at the bending point between the second fan-out trace and the first fan-out trace.

[0012] In some embodiments, the data line extends continuously along the first direction, the second via is located at an intersection of the data line and the second fan-out line, and one second fan-out line is connected to one data line.

[0013] In some embodiments, the first fan-out routing includes a first sub-fan-out routing and a second sub-fan-out routing symmetrical along the first direction, and the second fan-out routing includes a third sub-fan-out routing and a fourth sub-fan-out routing symmetrical along the first direction; the length of the first sub-fan-out routing gradually decreases along a second direction away from the second sub-fan-out routing, and the length of the second sub-fan-out routing gradually decreases along a third direction away from the first sub-fan-out routing; the third sub-fan-out routing bends toward the second direction, and the fourth sub-fan-out routing bends toward the third direction.

[0014] In some embodiments, the driving circuit further includes:

[0015] a first power signal line located in the display area, on the same layer as the first fan-out line and disconnected from the first fan-out line, the first power signal line extending from the first via in a direction away from the bottom of the display area;

[0016] The second power signal line is located in the display area, is on the same layer as the second fan-out line and is disconnected from the second fan-out line. The second power signal line extends between the third sub-fan-out line and the fourth sub-fan-out line.

[0017] In some embodiments, the driving circuit further includes:

[0018] a third power signal line, located in the display area, arranged on the same layer as the first fan-out line and extending continuously along the first direction;

[0019] The fourth power signal line is located in the display area, is arranged in the same layer as the data line, and extends continuously along the first direction.

[0020] In some embodiments, the first power signal line is connected to the fourth power signal line through a third via, the second power signal line is connected to the fourth power signal line through a fourth via, and the third power signal line is connected to the fourth power signal line through a fifth via.

[0021] In some embodiments, the display area includes multiple pixels, each of the pixels corresponds to three first fan-out lines and one third power signal line; each of the pixels includes two sub-pixels, one sub-pixel corresponds to two first fan-out lines, and the other sub-pixel corresponds to the remaining one first fan-out line and one third power signal line.

[0022] On the other hand, the present application provides a display panel, which includes at least the driving circuit in any one of the above embodiments.

[0023] The beneficial effects of the present application are as follows: a driving circuit and a display panel are provided, wherein the driving circuit includes a display area and a driving chip located outside the display area, and the driving circuit includes at least a first fan-out trace, a second fan-out trace, and a data line. The first fan-out trace is located in the display area and is electrically connected to the driving chip, the second fan-out trace is located in the display area and is connected to the first fan-out trace, and the data line is located in the display area and is connected to the second fan-out trace. The first fan-out trace, the second fan-out trace, and the data line are arranged in different layers, and the second fan-out trace is located between the first fan-out trace and the data line. By arranging two layers of fan-out traces located on the upper layer of the data line in the display area, the driving chip can drive the data line. Since the first fan-out trace and the second fan-out trace are both located in the display area, the space originally required for wiring below the display area can be saved to achieve a narrow lower frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0025] Figure 1 is a schematic structural diagram of a driving circuit provided in an embodiment of the present application;

[0026] Figure 2 This is a schematic diagram of the area division of the display area provided in an embodiment of the present application;

[0027] Figure 3 This embodiment of the present application provides Figure 2 Schematic diagram of the wiring distribution in the middle area C;

[0028] Figure 4 is another structural diagram of the driving circuit provided in an embodiment of the present application;

[0029] Figure 5 Schematic diagram of the structure of the display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0031] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the described features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0032] In this application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0033] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples, and such repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art will appreciate the application of other processes and / or the use of other materials.

[0034] See also Figure 1 , Figure 1 FIG1 is a schematic diagram of the structure of a driving circuit provided in an embodiment of the present application. The driving circuit 100 can be applied to various displays or display panels, such as liquid crystal displays (LCDs), organic light-emitting diode displays (OLEDs), and micro-light-emitting diode displays (Micro-LEDs).

[0035] The driving circuit 100 includes a display area AA and a driving chip 10 located outside the display area AA, that is, the driving chip 10 is located in the non-display area. The driving circuit 100 includes at least a first fan-out line 11, a second fan-out line 12 and a data line ( Figure 1(not shown). The first fan-out trace 11 is located in the display area AA and is electrically connected to the driver chip 10, the second fan-out trace 12 is located in the display area AA and is connected to the first fan-out trace 11, and the data line is located in the display area AA and is connected to the second fan-out trace 12. Among them, the first fan-out trace 11, the second fan-out trace 12 and the data line are arranged in different layers, and the second fan-out trace 12 is located between the first fan-out trace 11 and the data line. By arranging the second fan-out trace 12 located on the upper layer of the data line and the first fan-out trace 11 located on the upper layer of the second fan-out trace 12 in the display area AA, the second fan-out trace 12 is electrically connected to the data line through the first fan-out trace 11, thereby enabling the driver chip 10 to drive the data line.

[0036] In some embodiments, the driver chip 10 may be located below the display area AA, and each first fan-out trace 11 is connected to a channel in the driver chip 10. The driver circuit 100 may further include a third fan-out trace 101 located between the driver chip 10 and the display area AA, that is, the third fan-out trace 101 is located in the non-display area. The first fan-out trace 11 may be connected to the driver chip 10 via the third fan-out trace 101. It should be noted that Figure 1 Only a few third fan-out traces 101 are shown. In practice, each first fan-out trace 11 is connected to the driver chip 10 via a third fan-out trace 101 .

[0037] In some embodiments, the second fan-out trace 12 is connected to the first fan-out trace 11 through a first via 13, and the data line is connected to the first fan-out trace 11 through a second via ( Figure 1 (not shown) is connected to the second fan-out line 12. It should be noted that, Figure 1 The main display shows the wiring method and connection relationship between the first fan-out trace 11 and the second fan-out trace 12. In order to show it more clearly, the data line located below the second fan-out trace 12 is not shown. The data line will be introduced below. Figure 3 Displayed in.

[0038] In one embodiment, if Figure 1 As shown, the first fan-out trace 11 extends from the bottom of the display area AA along the first direction (Y) toward the interior of the display area AA. The second fan-out trace 12 bends relative to the first fan-out trace 11. The first via 13 is located at the bend between the second fan-out trace 12 and the first fan-out trace 11. Specifically, the first direction (Y) can be parallel to the length of the display area AA, and the direction in which the second fan-out trace 12 bends relative to the first fan-out trace 11 can be perpendicular to the first direction (Y), that is, the direction in which the second fan-out trace 12 bends can be parallel to the width of the display area AA.

[0039] The first fan-out routing 11 may include a first sub-fan-out routing 111 and a second sub-fan-out routing 112 symmetrically along the first direction (Y), and the second fan-out routing 12 may include a third sub-fan-out routing 121 and a fourth sub-fan-out routing 122 symmetrically along the first direction (Y). The third sub-fan-out routing 121 is perpendicularly bent relative to the first sub-fan-out routing 111, and is connected at the bend through a first via 13; the fourth sub-fan-out routing 122 is perpendicularly bent relative to the second sub-fan-out routing 112, and is connected at the bend through a first via 13. Specifically, the third sub-fan-out routing 121 is bent in the second direction (-X), and the fourth sub-fan-out routing 122 is bent in the third direction (X), where the second direction (-X) and the third direction (X) are two opposite directions perpendicular to the first direction (Y). Since the first fan-out trace 11 and the second fan-out trace 12 are symmetrical along the first direction (Y), the second direction (-X) can also be referred to as the direction in which the first sub-fan-out trace 111 departs from the second sub-fan-out trace 112 , and the third direction (X) can also be referred to as the direction in which the second sub-fan-out trace 112 departs from the first sub-fan-out trace 111 .

[0040] In some embodiments, the lengths of the plurality of first sub-fan-out traces 111 along the second direction (-X) gradually decrease, and the lengths of the plurality of second sub-fan-out traces 112 along the third direction (X) gradually decrease. The first vias 13 are located at the end of the first fan-out trace 11 (different from the end located at the bottom of the display area AA). Therefore, the first vias 13 connecting the third sub-fan-out trace 121 and the first sub-fan-out trace 111 are generally arranged in an oblique line, and the first vias 13 connecting the fourth sub-fan-out trace 122 and the second sub-fan-out trace 112 are generally arranged in an oblique line.

[0041] In some embodiments, the data line extends continuously along the first direction (Y) and intersects the second fan-out trace 12. The second via is located at the intersection of the data line and the second fan-out trace 12, and one second fan-out trace 12 is connected to one data line.

[0042] Specifically, the third sub-fan-out trace 121 includes a first end and a second end, and the fourth sub-fan-out trace 122 includes a third end and a fourth end. The first end is connected to the end of the first sub-fan-out trace 111 (other than the end located at the bottom of the display area AA), and the third end is connected to the end of the second sub-fan-out trace 112 (other than the end located at the bottom of the display area AA). The second end is also the intersection of the third sub-fan-out trace 121 and the data line, and the fourth end is also the intersection of the fourth sub-fan-out trace 122 and the data line. Therefore, second vias are located at the second and fourth ends to achieve the connection between the second fan-out trace 12 and the data line.

[0043] In some embodiments, the lengths of multiple third sub-fan-out traces 121 can be approximately equal, and the lengths of multiple fourth sub-fan-out traces 122 can also be approximately equal, so the second vias connecting the third sub-fan-out traces 121 and the data lines can be arranged in an oblique line, and the second vias connecting the fourth sub-fan-out traces 122 and the data lines can also be arranged in an oblique line.

[0044] See also Figure 2 , Figure 2 Schematic diagram of the area division of the display area AA provided in the embodiment of the present application. The display area AA can be divided into multiple areas, such as area A, area B, area C, area D and area E. Figure 1 As shown, the first fan-out trace 11 is distributed in area A, the second fan-out trace 12 is distributed in area D, the first via 13 is distributed in area C, and the second via is distributed in area E. Area B is an area where no fan-out traces exist. It can be seen that the first via 13 is arranged diagonally along area C, and the second via is arranged diagonally along area E.

[0045] Please combine Figure 3 , Figure 3 This embodiment of the present application provides Figure 2 Schematic diagram of the wiring distribution in area C. To be precise, Figure 3 Shown is Figure 2 The left area C, Figure 3 The trace distribution of part of area A and part of area D on both sides of area C is also shown. Figure 3 As shown, in fact, the first via hole 13 is not completely as Figure 2 Also arranged in a straight diagonal line, Figure 2 The area C in FIG. 1 only illustrates the general arrangement direction of the first via holes 13 .

[0046] In this embodiment, the position of the data line 141 coincides with the position of the first fan-out line 11, except that the data line 141 extends in the first direction (Y), while the length of the first fan-out line 11 changes gradually. Figure 3 The first fan-out trace 11 shown in the figure is a first sub-fan-out trace 111. The lengths of the first sub-fan-out traces 111 along the second direction (-X) gradually decrease. The data line 141 is located at the bottom layer, the second fan-out trace 12 is located at the middle layer, and the first fan-out trace 11 is located at the top layer.

[0047] In some embodiments, the driver circuit 100 may further include a first power signal line 113 and a second power signal line 123 located in the display area AA. The first power signal line 113 extends from the first via 13 in a direction away from the bottom of the display area AA, and the first power signal line 113 is located on the same layer as the first fan-out line 11 and is disconnected from the first fan-out line 11. In other words, the first power signal line 113 is located on an extension of the first fan-out line 11 and is disconnected from the first fan-out line 11. The second power signal line 123 extends between the third sub-fan-out line 121 and the fourth sub-fan-out line 122, and the second power signal line 123 is located on the same layer as the second fan-out line 12 and is disconnected from the second fan-out line 12. In other words, the second power signal line 123 is located on an extension of the second fan-out line 12 and is disconnected from the second fan-out line 12. The first power signal line 113 and the second power signal line 123 can increase the density uniformity of the routing pattern.

[0048] It should be noted that Figure 3 The second fan-out trace 12 shown in FIG is the third sub-fan-out trace 121. Figure 3 The fourth sub-fan-out trace 122 is not shown.

[0049] In some embodiments, the driving circuit 100 further includes a third power signal line 114 located in the display area AA. The third power signal line 114 is disposed in the same layer as the first fan-out line 11 and extends continuously along the first direction (Y).

[0050] In some embodiments, the driving circuit 100 further includes a fourth power signal line 142 located in the display area AA. The fourth power signal line 142 is disposed in the same layer as the data line 141 and extends continuously along the first direction (Y).

[0051] The first power signal line 113 is connected to the fourth power signal line 142 through a third via, the second power signal line 123 is connected to the fourth power signal line 142 through a fourth via, and the third power signal line 114 is connected to the fourth power signal line 142 through a fifth via. This application does not limit the positions of the third, fourth, and fifth vias. The first power signal line 113, the second power signal line 123, and the third power signal line 114 are respectively connected to the fourth power signal line 142, which can prevent the first power signal line 113, the second power signal line 123, and the third power signal line 114 from floating, thereby playing an anti-static role.

[0052] In some embodiments, the display area AA may include multiple pixels P, each of which may include two sub-pixels SP. The data lines 141 and the fourth power signal lines 142 may be arranged alternately, with each sub-pixel SP corresponding to one data line 141 and one fourth power signal line 142. Accordingly, one sub-pixel SP may correspond to two first fan-out lines 11, or one first fan-out line 11 and one third power signal line 114. In other words, each pixel P corresponds to three first fan-out lines 11 and one third power signal line 114. In a pixel P, if one sub-pixel SP corresponds to two first fan-out lines 11, then the other sub-pixel SP corresponds to the remaining one first fan-out line 11 and one third power signal line 114.

[0053] See also Figure 4 , Figure 4 This is another structural diagram of the driving circuit provided in an embodiment of the present application. Figure 4 It mainly displays the distribution of power signal lines. Figure 1 It can be seen that the first power signal line 113 is located on the extension line of the first fan-out line 11 and is disconnected from the first fan-out line 11. The second power signal line 123 extends between the third sub-fan-out line 121 and the fourth sub-fan-out line 122, and the second power signal line 123 and the second fan-out line 12 (including the third sub-fan-out line 121 and the fourth sub-fan-out line 122) are on the same layer and are disconnected.

[0054] In some embodiments, the driver circuit 100 may further include a fifth power signal line 115 and a sixth power signal line 124 located in the display area AA. The fifth power signal line 115 is arranged on the same layer as the first fan-out line 11 and is located on both sides of the first fan-out line 11. The fifth power signal line 115 extends continuously along the first direction (Y). The sixth power signal line 124 is arranged on the same layer as the second fan-out line 12 and is located on a side of the second power signal line 123 near the bottom of the display area AA. The sixth power signal line 124 extends continuously perpendicular to the first direction (Y). The fifth power signal line 115 and the sixth power signal line 124 can increase the density uniformity of the routing pattern.

[0055] The fifth power signal line 115 and the sixth power signal line 124 are connected to the fourth power signal line 142 through vias to prevent static electricity.

[0056] In some embodiments, the driving circuit 100 may further include a seventh power signal line 125 located in the display area AA, wherein the seventh power signal line 125 is on the same layer as the second fan-out line 12 and is disconnected from the second fan-out line 12. The seventh power signal line 125, the second fan-out line 12, and the second power signal line 123 are distributed on an extended line and are disconnected from each other. Specifically, Figure 4 The seventh power signal line 125 on the left is located at the end of the third sub-fan-out line 121 away from the second power signal line 123. Figure 4 The seventh power signal trace 125 on the right is located at the end of the fourth sub-fan-out trace 122 away from the second power signal trace 123. The seventh power signal trace 125 can increase the uniformity of the trace pattern and is also connected to the fourth power signal trace 142 through a via to prevent static electricity.

[0057] The driving circuit 100 provided in an embodiment of the present application includes a display area AA and a driver chip 10 located outside the display area AA. The driving circuit 100 includes at least a first fan-out trace 11, a second fan-out trace 12, and a data line 141. The first fan-out trace 11 is located in the display area AA and is electrically connected to the driver chip 10. The second fan-out trace 12 is located in the display area AA and is connected to the first fan-out trace 11. The data line 141 is located in the display area AA and is connected to the second fan-out trace 12. The first fan-out trace 11, the second fan-out trace 12, and the data line 141 are arranged in different layers, and the second fan-out trace 12 is located between the first fan-out trace 11 and the data line 141. By arranging two layers of fan-out traces located above the data line 141 in the display area AA, the driver chip 10 can drive the data line 141. Since the first fan-out trace 11 and the second fan-out trace 12 are both located in the display area AA, the space originally required for wiring below the display area AA can be saved, thereby achieving a narrow bottom bezel.

[0058] See also Figure 5 , Figure 5 : is a schematic diagram of the structure of the display panel provided in an embodiment of the present application. The display panel 200 may include the driving circuit of any of the above embodiments, wherein the driving circuit includes a display area and a driving chip located outside the display area, and the driving circuit includes at least: a first fan-out trace located in the display area and electrically connected to the driving chip; a second fan-out trace located in the display area and connected to the first fan-out trace; and a data line located in the display area and connected to the second fan-out trace. The first fan-out trace, the second fan-out trace, and the data line are arranged on different layers, and the second fan-out trace is located between the first fan-out trace and the data line.

[0059] The display panel 200 has the same beneficial effects as the driving circuit in any of the above embodiments, which will not be described in detail here.

[0060] The description of the above embodiments is only used to help understand the technical solutions and core ideas of this application; ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A driving circuit, characterized in that: The driving circuit includes a display area and a driving chip located outside the display area, and the driving circuit at least includes: a first fan-out trace located in the display area and electrically connected to the driver chip; a second fan-out line, located in the display area and connected to the first fan-out line; a data line located in the display area and connected to the second fan-out line; Among them, the first fan-out route, the second fan-out route and the data line are arranged in different layers, and the second fan-out route is located between the first fan-out route and the data line; the driving circuit also includes a first power signal route, the first power signal route is located in the display area, is on the same layer as the first fan-out route and is disconnected, the second fan-out route is connected to the first fan-out route through a first via, and the first power signal route extends from the first via in a direction away from the bottom of the display area.

2. The driving circuit according to claim 1, wherein: The data line is connected to the second fan-out line through a second via.

3. The driving circuit according to claim 2, wherein: The first fan-out trace is arranged along a first direction from the bottom of the display area, the second fan-out trace is bent relative to the first fan-out trace, and the first via is located at the bending point between the second fan-out trace and the first fan-out trace.

4. The driving circuit according to claim 3, wherein: The data line extends continuously along the first direction. The second via is located at an intersection of the data line and the second fan-out line. One second fan-out line is connected to one data line.

5. The driving circuit according to claim 3, wherein: The first fan-out routing includes a first sub-fan-out routing and a second sub-fan-out routing symmetrical along the first direction, and the second fan-out routing includes a third sub-fan-out routing and a fourth sub-fan-out routing symmetrical along the first direction; the length of the first sub-fan-out routing gradually decreases along a second direction away from the second sub-fan-out routing, and the length of the second sub-fan-out routing gradually decreases along a third direction away from the first sub-fan-out routing; the third sub-fan-out routing bends toward the second direction, and the fourth sub-fan-out routing bends toward the third direction.

6. The driving circuit according to claim 5, wherein: The driving circuit further includes: The second power signal line is located in the display area, is on the same layer as the second fan-out line and is disconnected from the second fan-out line. The second power signal line extends between the third sub-fan-out line and the fourth sub-fan-out line.

7. The driving circuit according to claim 6, wherein: The driving circuit further includes: a third power signal line, located in the display area, arranged on the same layer as the first fan-out line and extending continuously along the first direction; The fourth power signal line is located in the display area, is arranged in the same layer as the data line, and extends continuously along the first direction.

8. The driving circuit according to claim 7, wherein: The first power signal line is connected to the fourth power signal line through a third via, the second power signal line is connected to the fourth power signal line through a fourth via, and the third power signal line is connected to the fourth power signal line through a fifth via.

9. The driving circuit according to claim 7, wherein: The display area includes a plurality of pixels, each of which corresponds to three first fan-out lines and one third power signal line; each of the pixels includes two sub-pixels, one sub-pixel corresponds to two first fan-out lines, and the other sub-pixel corresponds to the remaining first fan-out line and one third power signal line.

10. A display panel, characterized in that: The display panel comprises at least the driving circuit according to any one of claims 1 to 9.

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