Display device

Abstract

A display device comprises: a substrate having a first pixel area and a second pixel area smaller than the first pixel area. A first pixel in the first pixel area is connected to a first scan line. A second pixel in the second pixel area is connected to a second scan line. A first scan driver provides a first scan signal to the first scan line, and a second scan driver provides a second scan signal to the second scan line. A first signal line provides a first drive signal to the first scan driver and a second scan driver. The first signal line includes: a first sub-signal line that provides the first drive signal to the first scan driver; a second sub-signal line that provides the first drive signal to the second scan driver; and a first load matching resistor connected between the first sub-signal line and the second sub-signal line.

Description

[0001] This application is a divisional application of the invention with the application date of May 18, 2017, application number 201710350850.8 and the name “Display Device”.

[0002] Citations of Related Applications

[0003] Korean Patent Application No. 10-2016-0061626, filed on May 19, 2016, and entitled “DISPLAY DEVICE,” is hereby incorporated by reference in its entirety. Technical Field

[0004] One or more embodiments described herein relate to a display device. Background Art

[0005] An organic light-emitting display device includes multiple pixels, each of which includes an organic light-emitting diode (OLED). Each diode has an organic light-emitting layer between two electrodes. Electrons injected from one electrode and holes injected from the other combine in the organic light-emitting layer to form excitons. When the excitons stabilize, light is emitted from the diode.

[0006] Organic light-emitting diodes are controlled by transistors connected to drive lines. Drive lines can have different loads depending on their location. These different loads can cause variations in pixel brightness. Summary of the Invention

[0007] According to one or more embodiments, a display device includes: a substrate including a first pixel area and a second pixel area, the second pixel area being smaller than the first pixel area; a first pixel, the first pixel being in the first pixel area and connected to a first scan line; a second pixel, the second pixel being in the second pixel area and connected to a second scan line; a first scan driver, the first scan driver providing a first scan signal to the first scan line; a second scan driver, the second scan driver providing a second scan signal to the second scan line; and a first signal line, the first signal line providing a first drive signal to the first scan driver and the second scan driver, wherein the first signal line includes: a first sub-signal line, the first sub-signal line providing a first drive signal to the first scan driver; a second sub-signal line, the second sub-signal line providing a first drive signal to the second scan driver; and a first load matching resistor, the first load matching resistor being connected between the first sub-signal line and the second sub-signal line.

[0008] The first sub-signal line may receive a first drive signal and transmit the first drive signal to the second sub-signal line via a first load matching resistor. The number of second pixels may be smaller than the number of first pixels. The second scan line may be shorter than the first scan line. The first drive signal may be a clock signal. The substrate may further include: a third pixel area, the third pixel area being smaller than the first pixel area.

[0009] The display device may include: a third pixel in a third pixel region and connected to a third scan line; a third scan driver that provides a third scan signal to the third scan line; and a second signal line that provides a second drive signal to the third scan driver. The second pixel region and the third pixel region may be located on one side of the first pixel region and spaced apart from each other.

[0010] The display device may include a fourth scan driver configured to provide a first scan signal to a first scan line. The first scan driver may be connected to a first end of the first scan line, and the fourth scan driver may be connected to a second end of the first scan line. The first scan driver and the fourth scan driver may simultaneously provide the first scan signal to the same first scan line.

[0011] The second signal line may include: a third sub-signal line that provides the second drive signal to the fourth scan driver; a fourth sub-signal line that provides the second drive signal to the second scan driver; and a second load matching resistor connected between the third sub-signal line and the fourth sub-signal line. The third sub-signal line may receive the second drive signal and may transmit the second drive signal to the fourth sub-signal line via the second load matching resistor. The number of the third pixels may be less than the number of the first pixels. The third scan line may be shorter than the first scan line. The second drive signal may be a clock signal.

[0012] The display device may include: a first emission driver that provides a first emission control signal to a first pixel through a first emission control line; a second emission driver that provides a second emission control signal to a second pixel through a second emission control line; and a third signal line that provides a third drive signal to the first emission driver and the second emission driver.

[0013] The third signal line may include: a fifth sub-signal line that provides the third driving signal to the first emission driver; a sixth sub-signal line that provides the third driving signal to the second emission driver; and a third load matching resistor connected between the fifth sub-signal line and the sixth sub-signal line.

[0014] The fifth sub-signal line may receive a third drive signal and transmit the third drive signal to the sixth sub-signal line through a third load matching resistor. The second emission control line may be shorter than the first emission control line. The third drive signal may include a clock signal.

[0015] According to one or more other embodiments, a display device includes: a substrate, the substrate including a first pixel area and a second pixel area, the second pixel area being smaller than the first pixel area; a first pixel, the first pixel being in the first pixel area and connected to a first scan line; a second pixel, the second pixel being in the second pixel area and connected to a second scan line; a first scan driver, the first scan driver providing a first scan signal to the first scan line; a second scan driver, the second scan driver providing a second scan signal to the second scan line; and a first load matching resistor, the first load matching resistor being connected between the second scan driver and the second scan line.

[0016] The number of the second pixels may be smaller than the number of the first pixels. The second scan line may be shorter than the first scan line. The substrate may further include a third pixel region that is smaller than the first pixel region. The display device may include a third pixel in the third pixel region and connected to the third scan line; and a third scan driver that provides a third scan signal to the third scan line. The second pixel region and the third pixel region may be located on one side of the first pixel region and spaced apart from each other.

[0017] The display device may include a fourth scan driver that provides a first scan signal to a first scan line. The first scan driver may be connected to a first end of the first scan line, and the fourth scan driver may be connected to a second end of the first scan line. The first scan driver and the fourth scan driver may simultaneously provide the first scan signal to the same first scan line. The display device may include a second load matching resistor connected between the third scan driver and the third scan line. The number of the third pixels may be less than the number of the first pixels. The third scan line may be shorter than the first scan line.

[0018] A display device may include: a first emission driver that provides a first emission control signal to a first pixel via a first emission control line; and a second emission driver that provides a second emission control signal to a second pixel via a second emission control line. The display device may include a third load matching resistor between the second emission driver and the second emission control line. The second emission control line may be shorter than the first emission control line. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0020] Figures 1A to 1E Various embodiments of pixel regions are shown;

[0021] Figure 2 An embodiment of a display device is shown;

[0022] Figure 3 One embodiment of a load matching resistor is shown;

[0023] Figure 4 An embodiment of a first signal line is shown;

[0024] Figure 5 An embodiment of the first signal line and the second scan driver is shown;

[0025] Figure 6 One embodiment of a load matching resistor is shown;

[0026] Figure 7 One embodiment of a scan stage circuit is shown;

[0027] Figure 8 One embodiment of a method for driving a scan stage circuit is shown;

[0028] Figure 9 An embodiment of a first pixel is shown;

[0029] Figure 10 Another embodiment of the display device is shown;

[0030] Figure 11 One embodiment of a load matching resistor is shown;

[0031] Figure 12 Another embodiment of a load matching resistor is shown;

[0032] Figure 13 Another embodiment of the display device is shown;

[0033] Figure 14 Another embodiment of a load matching resistor is shown;

[0034] Figure 15 One embodiment of a signal line and a transmit driver is shown;

[0035] Figure 16 Another embodiment of a load matching resistor is shown;

[0036] Figure 17 An embodiment of a transmitter stage circuit is shown;

[0037] Figure 18 An embodiment of a method for driving a transmitter stage circuit is shown; and

[0038] Figure 19 Another embodiment of a pixel is shown. DETAILED DESCRIPTION

[0039] Exemplary embodiments will now be described with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey exemplary implementations to those skilled in the art. The embodiments (or portions thereof) may be combined to form further embodiments.

[0040] In the accompanying drawings, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when a layer or element is referred to as being on another layer or substrate, the layer or element may be directly on the other layer or substrate, or intervening layers may be present. Furthermore, it will be understood that when a layer is referred to as being below another layer, it may be directly below the other layer, and one or more intervening layers may be present. Furthermore, it will be understood that when a layer is referred to as being between two layers, the layer may be the only layer between the two layers, or one or more intervening layers may be present. Like reference numerals refer to like elements throughout.

[0041] When an element is referred to as being “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or indirectly connected to or coupled to the other element with one or more intervening elements interposed therebetween. In addition, when an element is referred to as “including” a component, this indicates that the element may further include another component, rather than excluding the other component, unless there is a different disclosure.

[0042] Figures 1A to 1E Various embodiments of the pixel region are shown. Figure 1A The substrate 100 may include a pixel region and adjacent regions NA1, NA2, and NA3. A plurality of pixels PXL1, PXL2, and PXL3 may be located in the pixel region. Therefore, the pixel region may display a predetermined image. (The pixel region may be a display region).

[0043] Components (e.g., drivers and lines) for driving pixels PXL1, PXL2, and PXL3 may be located in adjacent areas NA1, NA2, and NA3. Pixels PXL1, PXL2, and PXL3 may not be located in adjacent areas NA1, NA2, and NA3. (Adjacent areas NA1, NA2, and NA3 may be referred to as non-display areas.) For example, adjacent areas NA1, NA2, and NA3 may be located outside the pixel area and may surround at least a portion of the pixel area.

[0044] The pixel area may include a first pixel area AA1 and a second pixel area AA2 and a third pixel area AA3 located to one side of the first pixel area AA1. The second pixel area AA2 and the third pixel area AA3 may be spaced apart from each other. The area of the first pixel area AA1 may be larger than the areas of the second pixel area AA2 and the third pixel area AA3. For example, the width W1 of the first pixel area AA1 may be larger than the widths W2 and W3 of the other pixel areas AA2 and AA3. The length L1 of the first pixel area AA1 may be larger than the lengths L2 and L3 of the other pixel areas AA2 and AA3.

[0045] The second pixel area AA2 and the third pixel area AA3 may have an area smaller than that of the first pixel area AA1 and may have the same area or different areas. For example, the width W2 of the second pixel area AA2 may be the same as or different from the width W3 of the third pixel area AA3. The length L2 of the second pixel area AA2 may be the same as or different from the length L3 of the third pixel area AA3.

[0046] The neighboring areas NA1, NA2, and NA3 may include a first neighboring area NA1, a second neighboring area NA2, and a third neighboring area NA3. The first neighboring area NA1 surrounds the first pixel area AA1 and may surround at least a portion of the first pixel area AA1. The widths of the first neighboring areas NA1 may be substantially the same. In another embodiment, for example, the widths of the first neighboring areas NA1 may vary depending on the location.

[0047] The second adjacent area NA2 is around the second pixel area AA2 and may surround at least a portion of the second pixel area AA2. The widths of the second adjacent areas NA2 may be substantially the same. In another embodiment, for example, the widths of the second adjacent areas NA2 may vary depending on the location.

[0048] The third adjacent area NA3 is around the third pixel area AA3 and may surround at least a portion of the third pixel area AA3. The widths of the third adjacent areas NA3 may be substantially the same. In another embodiment, for example, the widths of the third adjacent areas NA3 may vary depending on the location.

[0049] For example, the second neighboring area NA2 and the third neighboring area NA3 may be connected to each other or not connected to each other according to the form of the substrate 100 .

[0050] The widths of the adjacent areas NA1, NA2, and NA3 may be substantially the same. In another embodiment, for example, the widths of the adjacent areas NA1, NA2, and NA3 may be different depending on the location.

[0051] Pixels PXL1, PXL2, and PXL3 may include a first pixel PXL1, a second pixel PXL2, and a third pixel PXL3. For example, the first pixel PXL1 may be in a first pixel area AA1, the second pixel PXL2 may be in a second pixel area AA2, and the third pixel PXL3 may be in a third pixel area AA3. Pixels PXL1, PXL2, and PXL3 may emit light having a predetermined brightness according to control of a driver in adjacent areas NA1, NA2, and NA3. Pixels PXL1, PXL2, and PXL3 may include light-emitting devices (e.g., organic light-emitting diodes).

[0052] The substrate 100 may have various forms including pixel areas AA1, AA2, and AA3 and adjacent areas NA1, NA2, and NA3. For example, the substrate 100 may include a base substrate 101 having a plate shape. The first auxiliary plate 102 and the second auxiliary plate 103 may protrude from one end of the base substrate 101 in one direction. The first auxiliary plate 102 and the second auxiliary plate 103 may be formed integrally with the base substrate 101. A recess 104 may exist between the first auxiliary plate 102 and the second auxiliary plate 103. The recess 104 may be an area obtained by removing a portion of the substrate 100. Therefore, the first auxiliary plate 102 may be separated from the second auxiliary plate 103.

[0053] The first auxiliary plate 102 and the second auxiliary plate 103 may have a smaller area than the base substrate 101 and may have the same area or different areas. The first auxiliary plate 102 and the second auxiliary plate 103 may have various shapes including pixel areas AA2 and AA3 and adjacent areas NA2 and NA3. In this case, the first pixel area AA1 and the first adjacent area NA1 may be in the base substrate 101. The second pixel area AA2 and the second adjacent area NA2 may be in the first auxiliary plate 102. The third pixel area AA3 and the third adjacent area NA3 may be in the second auxiliary plate 103.

[0054] refer to Figure 1A , the second adjacent area NA2 and the third adjacent area NA3 may be connected to each other between the concave portion 104 and the first pixel area AA1.

[0055] refer to Figure 1B , for example, the second adjacent area NA2 and the third adjacent area NA3 may not be connected to each other according to the forms of the concave portion 104 and the first pixel area AA1.

[0056] In another exemplary embodiment, a different number of auxiliary plates 102 and 103 may be included. For example, more than three auxiliary plates may be formed, or one of the first auxiliary plate 102 and the second auxiliary plate 103 may be omitted. When the second auxiliary plate 103 is omitted, the third pixel area AA3 may also be omitted. The position of the first auxiliary plate 102 may be variously changed. Furthermore, the third pixel area AA3 may be omitted, and the driver and lines for driving the third pixel PXL3 may also be omitted.

[0057] The substrate 100 may be formed of an insulating material such as glass or resin. In addition, the substrate 100 may be formed of a flexible material so as to be bendable or foldable, and may have a single-layer structure or a multi-layer structure. For example, the substrate 100 may include at least one of the following: polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. In another embodiment, the material of the substrate 100 may be different, for example, formed of fiberglass reinforced plastic (FRP).

[0058] The first pixel area AA1 may have various shapes, such as a polygon or a circle. In addition, at least a portion of the first pixel area AA1 may have a curved form. For example, the first pixel area AA1 may have a Figure 1A and Figure 1B The quadrilateral shape in . Figure 1C , the corners of the first pixel area AA1 may be tilted. In one embodiment, the corners of the first pixel area AA1 may be curved. In this case, the length L1 and / or width W1 of the first pixel area AA1 may vary depending on the position. The number of first pixels PXL1 located in a line (row and column) may vary depending on the shape of the first pixel area AA1.

[0059] The base substrate 101 may also have various shapes, such as a polygon or a circle. In addition, at least a portion of the base substrate 101 may be curved. For example, the base substrate 101 may have a shape such as Figure 1A and Figure 1B The quadrilateral shape in . Figure 1C , the corners of the base substrate 101 may be inclined or curved. The base substrate 101 may have a form that is the same as or similar to the first pixel area AA1 or a form that is different from the first pixel area AA1.

[0060] Each of the second pixel area AA2 and the third pixel area AA3 may have various shapes, such as a polygon or a circle. In addition, at least a portion of each of the second pixel area AA2 and the third pixel area AA3 may be curved. For example, the second pixel area AA2 and the third pixel area AA3 may have shapes such as Figure 1A and Figure 1B The quadrilateral shape in . Figure 1C and Figure 1D , the outer corner and the inner corner of each of the second pixel area AA2 and the third pixel area AA3 may be in an inclined or curved form.

[0061] refer to Figure 1E , the corners of each of the second pixel area AA2 and the third pixel area AA3 may be stepped. In this case, the length L2 and / or width W2 of the second pixel area AA2 may vary depending on the position. In addition, the length L3 and / or width W3 of the third pixel area AA3 may vary depending on the position.

[0062] The number of second pixels PXL2 and the number of third pixels PXL3 on one line (row and column) may be different based on the positions and shapes of the second pixel area AA2 and the third pixel area AA3. Figure 1A and Figure 1B In the case of , the number of second pixels PXL2 and the number of third pixels PXL3 located on one line (row and column) can be uniformly set. Figures 1C to 1E In this case, the number of second pixels PXL2 and the number of third pixels PXL3 located on one line (row and column) may be different based on their positions.

[0063] The first auxiliary plate 102 and the second auxiliary plate 103 may have various shapes, such as a polygon or a circle. At least a portion of each of the first auxiliary plate 102 and the second auxiliary plate 103 may also have a curved shape. For example, the first auxiliary plate 102 and the second auxiliary plate 103 may have a shape such as Figure 1A and Figure 1B The quadrilateral shape in . Figure 1C and Figure 1D , the outer corner and the inner corner of each of the first auxiliary plate 102 and the second auxiliary plate 103 may be inclined. In this case, the corner of each of the first auxiliary plate 102 and the second auxiliary plate 103 may be bent.

[0064] refer to Figure 1E , a corner portion of each of the first auxiliary plate 102 and the second auxiliary plate 103 may be stepped.

[0065] Each of the first and second auxiliary plates 102 and 103 may have the same or similar form as the second and third pixel areas AA2 and AA3 , or a different form from the second and third pixel areas AA2 and AA3 .

[0066] The recess 104 may have various shapes, such as a polygonal or circular shape. At least a portion of the recess 104 may be curved.

[0067] Figure 2 Shown including Figure 1A In another embodiment, the display device 10 may include a display device 10 having pixel areas AA1, AA2, and AA3 associated with the display device 10. Figures 1B to 1E Any one of the related pixel areas AA1, AA2 and AA3.

[0068] refer to Figure 2 The display device 10 may include a substrate 100, a first pixel PXL1, a second pixel PXL2, a third pixel PXL3, a first scan driver 210, a second scan driver 220, and a third scan driver 230. The first pixel PXL1 may be in a first pixel area AA1 and may be connected to a first scan line S1 and a first data line D1.

[0069] The first scan driver 210 may provide the first scan signal to the first pixel PXL1 through the first scan line S1. For example, the first scan driver 210 may sequentially provide the first scan signal to the first scan line S1.

[0070] The first scan driver 210 may be in the first adjacent area NA1. For example, the first scan driver 210 may be on a side of the first pixel area AA1 (eg, based on the Figure 2 In the first adjacent area NA1 adjacent to the left side of the first pixel area AA1, or may be on the other side of the first pixel area AA1 (for example, based on Figure 2 The second pixel PXL2 may be in the second pixel area AA2 and may be connected to the second scan line S2 and the second data line D2.

[0071] The second scan driver 220 may provide the second scan signal to the second pixel PXL2 through the second scan line S2. For example, the second scan driver 220 may sequentially provide the second scan signal to the second scan line S2.

[0072] The second scan driver 220 may be in the second adjacent area NA2. For example, the second scan driver 220 may be on a side of the second pixel area AA2 (eg, based on the Figure 2 In the second adjacent area NA2 adjacent to the left side of the second pixel area AA2, or may be on the other side of the second pixel area AA2 (for example, based on Figure 2 In the second adjacent area NA2 adjacent to the right side of ).

[0073] The second pixel area AA2 may have an area smaller than that of the first pixel area AA1, so that the number of second pixels PXL2 may be smaller than the number of first pixels PXL1, and the length of the second scan line S2 may be smaller than the length of the first scan line S1. In addition, the number of second pixels PXL2 connected to one second scan line S2 may be smaller than the number of first pixels PXL1 connected to one first scan line S1.

[0074] The third pixels PXL3 may be in the third pixel area AA3 , and each of the third pixels PXL3 may be connected to the third scan line S3 and the third data line D3 .

[0075] The third scan driver 230 may provide the third scan signal to the third pixel PXL3 through the third scan line S3. For example, the third scan driver 230 may sequentially provide the third scan signal to the third scan line S3.

[0076] The third scan driver 230 may be in the third adjacent area NA3. For example, the third scan driver 230 may be on a side of the third pixel area AA3 (eg, based on the Figure 2 In the third adjacent area NA3 adjacent to the left side of the third pixel area AA3, or may be on the other side of the third pixel area AA3 (for example, based on Figure 2 In the third adjacent area NA3 adjacent to the right side of ).

[0077] The third pixel area AA3 may have an area smaller than that of the first pixel area AA1, so that the number of third pixels PXL3 may be smaller than the number of first pixels PXL1, and the length of the third scan line S3 may be smaller than the length of the first scan line S1. In addition, the number of third pixels PXL3 connected to one third scan line S3 may be smaller than the number of first pixels PXL1 connected to one first scan line S1.

[0078] The scan signal may be provided with a gate-on voltage (eg, a voltage having a low level) to turn on transistors in the pixels PXL1 , PXL2 , and PXL3 .

[0079] The first scan driver 210 and the second scan driver 220 may operate based on the first driving signal. To this end, the first signal line 250 may provide the first driving signal to the first scan driver 210 and the second scan driver 220. In this case, the first signal line 250 may be in the adjacent areas NA1 and NA2.

[0080] The third scan driver 230 may operate based on the second driving signal. To this end, the second signal line 260 may provide the second driving signal to the third scan driver 230. In this case, the second signal line 260 may be in the adjacent areas NA1 and NA3.

[0081] The first signal line 250 and the second signal line 260 may receive a first drive signal and a second drive signal, respectively, from a separate component (e.g., a timing controller). The first signal line 250 and the second signal line 260 may extend from the lower side of the first pixel area AA1 toward the first adjacent area NA1. In one embodiment, a plurality of first signal lines 250 and a plurality of second signal lines 260 may be included, and the first drive signal and the second drive signal may be clock signals.

[0082] The data driver 400 can provide data signals to the pixels PXL1, PXL2, and PXL3 via the data lines D1, D2, and D3. The second data line D2 can be connected to some of the first data lines D1. The third data line D3 can be connected to the other first data lines D1. For example, the second data line D2 can extend from some of the first data lines D1, and the third data line D3 can extend from the other first data lines D1.

[0083] The data driver 400 may be in the first adjacent area NA1, and, for example, may be located at a position not overlapping with the first scan driver 210 (eg, based on the Figure 2 The data driver 400 may be mounted on the substrate 100 by various methods, such as chip-on-glass, chip-on-plastic, tape carrier package, or chip-on-film. For example, the data driver 400 may be directly mounted on the substrate 100, or may be connected to the substrate 100 via a separate component (e.g., a flexible printed circuit board).

[0084] Figure 3 An embodiment of a load matching resistor installed at a signal line is shown. Figure 3 , the display device 10 may include a plurality of first signal lines 250 a and 250 b and a plurality of second signal lines 260 a and 260 b for providing driving signals CLK1 and CLK2 to the scan drivers 210 , 220 , and 230 .

[0085] The driving signals CLK1 and CLK2 may include a first clock signal CLK1 and a second clock signal CLK2. For example, the first clock signal CLK1 and the second clock signal CLK2 may have different phases.

[0086] The first signal lines 250a and 250b may provide clock signals CLK1 and CLK2 to the first scan driver 210 and the second scan driver 220. For example, the first first signal line 250a may provide the first clock signal CLK1 to the first scan driver 210 and the second scan driver 220, and the second first signal line 250b may provide the second clock signal CLK2 to the first scan driver 210 and the second scan driver 220.

[0087] The second signal lines 260a and 260b may provide clock signals CLK1 and CLK2 to the third scan driver 230. For example, the first second signal line 260a may provide the first clock signal CLK1 to the third scan driver 230, and the second second signal line 260b may provide the second clock signal CLK2 to the third scan driver 230.

[0088] The first scan driver 210 may be connected to first ends of the first scan lines S11 to S1k and may provide first scan signals to the first scan lines S11 to S1k. The first scan driver 210 may include a plurality of scan stage circuits SST11 to SST1k. The scan stage circuits SST11 to SST1k of the first scan driver 210 may be connected to one end of the first scan lines S11 to S1k, respectively, and may provide first scan signals to the first scan lines S11 to S1k, respectively. In this case, for example, the scan stage circuits SST11 to SST1k may operate based on clock signals CLK1 and CLK2 received from an external source. The scan stage circuits SST11 to SST1k may be the same circuit.

[0089] The scanning stage circuits SST11 to SST1k may receive a start pulse or an output signal (i.e., a scan signal) of a previous scanning stage circuit. For example, the first scanning stage circuit SST11 may receive a start pulse, and the remaining scanning stage circuits SST12 to SST1k may receive an output signal of a previous stage circuit.

[0090] like Figure 3 As shown, the first scan stage circuit SST11 of the first scan driver 210 may use a signal output from the last scan stage circuit SST2j of the second scan driver 220 as a start pulse. In another exemplary embodiment, the first scan stage circuit SST11 of the first scan driver 210 may not receive a signal from the last scan stage circuit SST2j of the second scan driver 220 and may receive a start pulse alone.

[0091] Each of the scanning stage circuits SST11 to SST1k can receive a first driving power supply VDD1 and a second driving power supply VSS1. The first driving power supply VDD1 can be provided with a gate-off voltage, such as a high-level voltage. In addition, the second driving power supply VSS1 can be provided with a gate-on voltage, such as a low-level voltage.

[0092] The first pixels PXL1 in the first pixel area AA1 can receive data signals from the data driver 400 via the first data lines D11 to D0. The first pixels PXL1 can receive a first pixel power source ELVDD and a second pixel power source ELVSS. When the first scan signals are supplied to the first scan lines S11 to S1k, the first pixels PXL1 can receive data signals from the first data lines D11 to D0. The first pixels PXL1 receiving the data signals can control the amount of current flowing from the first pixel power source ELVDD through the organic light emitting diode to the second pixel power source ELVSS. For example, the number of first pixels PXL1 on a line (row or column) can vary depending on the position of the first pixels PXL1.

[0093] refer to Figure 3 The second scan driver 220 may be connected to the first ends of the second scan lines S21 to S2j. The second scan driver 220 may include a plurality of scan stage circuits SST21 to SST2j. The scan stage circuits SST21 to SST2j of the second scan driver 220 may be connected to the first ends of the second scan lines S21 to S2j, respectively, and may provide second scan signals to the second scan lines S21 to S2j, respectively.

[0094] For example, the scanning stage circuits SST21 to SST2j may operate based on clock signals CLK1 and CLK2 provided from an external source.The scanning stage circuits SST21 to SST2j may be the same circuit.

[0095] The scanning stage circuits SST21 to SST2j may receive a start pulse SSP1 or an output signal (i.e., a scan signal) from a previous scanning stage circuit. For example, the first scanning stage circuit SST21 may receive a start pulse SSP1, and the remaining scanning stage circuits SST22 to SST2j may receive an output signal from a previous stage circuit. The last scanning stage circuit SST2j of the second scanning driver 220 may provide an output signal to the first scanning stage circuit SST11 of the first scanning driver 210.

[0096] Each of the scanning stage circuits SST21 to SST2j can receive a first driving power supply VDD1 and a second driving power supply VSS1. The first driving power supply VDD1 can correspond to a gate-off voltage (e.g., a high-level voltage). The second driving power supply VSS1 can correspond to a gate-on voltage (e.g., a low-level voltage).

[0097] The second pixel PXL2 in the second pixel area AA2 can receive data signals from the data driver 400 through the second data lines D21 to D2p. For example, the second data lines D21 to D2p can be connected to some of the first data lines D11 to Dm-1. The second pixel PXL2 can receive a first pixel power source ELVDD and a second pixel power source ELVSS.

[0098] When the second scan signal is supplied to the second scan lines S21 to S2j, the second pixels PXL2 may receive data signals from the second data lines D21 to D2p. The second pixels PXL2 receiving the data signals may control the amount of current flowing from the first pixel power source ELVDD through the organic light emitting diode to the second pixel power source ELVSS. The number of second pixels PXL2 in a line (row or column) may vary depending on the position of the second pixels PXL2.

[0099] refer to Figure 3 The third scan driver 230 may be connected to the first ends of the third scan lines S31 to S3j. The third scan driver 230 may include a plurality of scan stage circuits SST31 to SST3j. The scan stage circuits SST31 to SST3j of the third scan driver 230 may be connected to the first ends of the third scan lines S31 to S3j, respectively, and may provide third scan signals to the third scan lines S31 to S3j, respectively.

[0100] For example, the scanning stage circuits SST31 to SST3j may operate based on clock signals CLK1 and CLK2 provided from an external source.The scanning stage circuits SST31 to SST3j may be the same circuit.

[0101] The scanning stage circuits SST31 to SST3j may receive a start pulse SSP1 or an output signal (i.e., a scan signal) from a previous scanning stage circuit. For example, the first scanning stage circuit SST31 may receive a start pulse SSP1, and the remaining scanning stage circuits SST32 to SST3j may receive an output signal from a previous stage circuit. The last scanning stage circuit SST3j of the third scanning driver 230 may provide an output signal to the first scanning stage circuit SST11 of the first scanning driver 210.

[0102] Each of the scanning stage circuits SST31 to SST3j can receive a first driving power supply VDD1 and a second driving power supply VSS1. The first driving power supply VDD1 can correspond to a gate-off voltage (e.g., a high-level voltage). The second driving power supply VSS1 can correspond to a gate-on voltage (e.g., a low-level voltage).

[0103] The third pixel PXL3 in the third pixel area AA1 can receive data signals from the data driver 400 through the third data lines D31 to D3q. For example, the third data lines D31 to D3q can be connected to some of the first data lines Dn+1 to D0. The third pixel PXL3 can receive a first pixel power source ELVDD and a second pixel power source ELVSS.

[0104] When the third scan signal is supplied to the third scan lines S31 to S3j, the third pixels PXL3 may receive data signals from the third data lines D31 to D3q. The third pixels PXL3 receiving the data signals may control the amount of current flowing from the first pixel power source ELVDD through the organic light emitting diode to the second pixel power source ELVSS. The number of third pixels PXL3 in a line (row or column) may vary depending on the position of the third pixels PXL3.

[0105] The load of the first scan lines S11 to S1k may be different from the load of the second scan lines S21 to S2j. For example, the first scan lines S11 to S1k may be longer than the second scan lines S21 to S2j, and the number of first pixels PXL1 may be greater than the number of second pixels PXL2, so that the load of the first scan lines S11 to S1k may be greater than the load of the second scan lines S21 to S2j.

[0106] The capacitance of the first scan lines S11 to S1k may be greater than the capacitance of the second scan lines S21 to S2j. This results in a difference in time constant between the first scan signal and the second scan signal. This difference may result in a difference in brightness between the first pixel PXL1 and the second pixel PXL2.

[0107] According to the present exemplary embodiment, load matching resistors 253a and 253b may be installed in the first signal lines 250a and 250b. Therefore, the loads of the first scan lines S11 to S1k and the second scan lines S21 to S2j can be matched, and the brightness of the first pixel area AA1 and the second pixel area AA2 can be consistent.

[0108] For example, the first first signal line 250a may include a first sub-signal line 251a, a second sub-signal line 252a, and a first load matching resistor 253a. The first sub-signal line 251a may be connected to the first scan driver 210 and may provide the first clock signal CLK1 to the first scan driver 210. The second sub-signal line 252a may be connected to the second scan driver 220 and may provide the first clock signal CLK1 to the second scan driver 220.

[0109] The first load matching resistor 253a may be connected between the first sub-signal line 251a and the second sub-signal line 252a. One end of the first sub-signal line 251a may receive the first clock signal CLK1. The other end of the first sub-signal line 251a may be connected to the first load matching resistor 253a.

[0110] Therefore, the first sub-signal line 251 a may receive the first clock signal CLK1 and may transmit the first clock signal CLK1 to the second sub-signal line 252 a through the first load matching resistor 253 a .

[0111] Similar to the first first signal line 250a, the second first signal line 250b may include a first sub-signal line 251b, a second sub-signal line 252b, and a first load matching resistor 253b. The first sub-signal line 251b may be connected to the first scan driver 210 and may provide the second clock signal CLK2 to the first scan driver 210. The second sub-signal line 252b may be connected to the second scan driver 220 and may provide the second clock signal CLK2 to the second scan driver 220.

[0112] The first load matching resistor 253b may be connected between the first sub-signal line 251b and the second sub-signal line 252b. One end of the first sub-signal line 251b may receive the second clock signal CLK2. The other end of the first sub-signal line 251b may be connected to the first load matching resistor 253b.

[0113] Therefore, the first sub-signal line 251 b may receive the second clock signal CLK2 and may transmit the second clock signal CLK2 to the second sub-signal line 252 b through the first load matching resistor 253 b .

[0114] The first load matching resistors 253 a and 253 b may be connected between the first scan stage circuit SST11 of the first scan driver 210 and the last scan stage circuit SST2 j of the second scan driver 220 .

[0115] Figure 4 One embodiment of a first signal line (eg, the first first signal line 250a) is shown in cross section. Figure 4 , the first load matching resistor 253a may be on the substrate 100. The insulating layer 106 may be on the upper side of the first load matching resistor 253a. The first sub-signal line 251a and the second sub-signal line 252a may be on the upper side of the insulating layer 106. In this case, the first sub-signal line 251a and the second sub-signal line 252a may be connected to the first load matching resistor 253a through contact holes ch1 and ch2 in the insulating layer 106, respectively.

[0116] The first load matching resistor 253a may be formed of a material having a higher resistance than the resistance of the first sub-signal line 251a and the second sub-signal line 252a. For example, the first load matching resistor 253a may be formed of the same material as the gate electrode or semiconductor layer of the transistor included in the pixels PXL1, PXL2, and PXL3. In addition, the first sub-signal line 251a and the second sub-signal line 252a may be formed of the same material as the source electrode and the drain electrode of the transistor included in the pixels PXL1, PXL2, and PXL3.

[0117] For ease of description, Figure 4The first first signal line 250 a is shown, but the second first signal line 250 b may also have the same structure as that of the first first signal line 250 a .

[0118] Figure 5 An embodiment of the first signal line and the second scan driver is shown. Figure 5 , one or more additional load matching resistors 254a and 254b may be installed in the second sub-signal lines 252a and 252b in the first signal lines 250a and 250b.

[0119] The loads of the second scan lines S21 to S2j may be different from each other. For example, the lengths of the second scan lines S21 to S2j may be different from each other according to the form of the second pixel area AA2. The number of pixels PXL2 connected to each of the second scan lines S21 to S2j may be different.

[0120] In this case, load matching resistors 254a and 254b may be additionally required for matching the loads of the second scan lines S21 to S2j. To this end, each of the second sub-signal lines 252a and 252b may be divided into a plurality of signal lines, and load matching resistors 254a and 254b may be connected between the divided signal lines.

[0121] The load matching resistors 254a and 254b may be connected between two adjacent stage circuits (eg, stage circuits SST22 and SST23 and stage circuits SST2j-2 and SST2j-1). For example, the load matching resistors 254a and 254b may have a value similar to the reference voltage. Figure 4 The material and structure of the first load matching resistor 253a are the same as those described above.

[0122] The present description is based on the second sub-signal lines 252a and 252b in the first signal lines 250a and 250b, but additional load matching resistors may also be installed in the first sub-signal lines 251a and 251b in the first signal lines 250a and 250b.

[0123] Figure 6 An embodiment of load matching resistors that can be installed in scan lines is shown. To match the loads of the first scan lines S11 to S1k and the second scan lines S21 to S2j, first load matching resistors R21 to R2j can be installed in the second scan lines S21 to S2j. The first load matching resistors R21 to R2j can be connected between the second scan driver 220 and the second scan lines S21 to S2j.

[0124] The first load matching resistors R21 to R2j may have the same resistance value or different resistance values. For example, at least some of the second scan lines S21 to S2j may have different loads, so that at least some of the first load matching resistors R21 to R2j for some of the second scan lines S21 to S2j may have different resistance values. For example, the first load matching resistors R21 to R2j may be connected between the output terminals of the scan stage circuits SST21 to SST2j in the second scan driver 220 and the second scan lines S21 to S2j.

[0125] The first load matching resistors R21 to R2j may be formed of a material having a higher resistance than the resistance of the second scan lines S21 to S2j. For example, the second scan lines S21 to S2j may be formed of the same material as the source and drain electrodes of the transistors in the pixels PXL1, PXL2, and PXL3. The first load matching resistors R21 to R2j may be formed of the same material as the gate electrodes or semiconductor layers of the transistors in the pixels PXL1, PXL2, and PXL3.

[0126] In addition, the second scan lines S21 to S2j may be formed of the same material as the gate electrodes of the transistors in the pixels PXL1, PXL2, and PXL3. The first load matching resistors R21 to R2j may be formed of the same material as the semiconductor layer of the transistors in the pixels PXL1, PXL2, and PXL3.

[0127] Figure 7 Show that, for example, Figure 3 One embodiment of the corresponding scan stage circuit: The scan stage circuits SST11 and SST12 of the first scan driver 210 are taken as representative examples.

[0128] refer to Figure 7 The first scan stage circuit SST11 may include a first driving circuit 1210, a second driving circuit 1220, and an output unit 1230. The output unit 1230 may control the voltage supplied to the output terminal 1006 based on the voltages of the first node N1 and the second node N2. The output unit 1230 may include a fifth transistor M5 and a sixth transistor M6.

[0129] The fifth transistor M5 may be connected between the fourth input terminal 1004 to which the first driving power source VDD1 is input and the output terminal 1006. A gate electrode of the fifth transistor M5 may be connected to the first node N1. The fifth transistor M5 may control the connection between the fourth input terminal 1004 and the output terminal 1006 based on the voltage applied to the first node N1.

[0130] The sixth transistor M6 may be connected between the output terminal 1006 and the third input terminal 1003. A gate electrode of the sixth transistor M6 may be connected to the second node N2. The sixth transistor M6 may control the connection between the output terminal 1006 and the third input terminal 1003 based on the voltage applied to the second node N2.

[0131] The output unit 1230 may be driven as a buffer. In addition, in one embodiment, a plurality of transistors connected in parallel may replace the fifth transistor M5 and / or the sixth transistor M6.

[0132] The first driver circuit 1210 may control the voltage of the third node N3 based on the signal provided to the first input terminal 1001 to the third input terminal 1003. To this end, the first driver circuit 1210 may include second to fourth transistors M2 to M4. The second transistor M2 may be connected between the first input terminal 1001 and the third node N3, and its gate electrode may be connected to the second input terminal 1002. The second transistor M2 may control the connection between the first input terminal 1001 and the third node N3 based on the signal provided to the second input terminal 1002.

[0133] The third transistor M3 and the fourth transistor M4 may be connected in series between the third node N3 and the fourth input terminal 1004. In one embodiment, the third transistor M3 may be connected between the fourth transistor M4 and the third node N3, and its gate electrode may be connected to the third input terminal 1003. The third transistor M3 may control the connection of the fourth transistor M4 to the third node N3 based on a signal provided to the third input terminal 1003.

[0134] The fourth transistor M4 may be connected between the third transistor M3 and the fourth input terminal 1004 and its gate electrode may be connected to the first node N1. The fourth transistor M4 may control the connection of the third transistor M3 and the fourth input terminal 1004 based on the voltage applied to the first node N1.

[0135] The second driving circuit 1220 may control the voltage of the first node N1 based on the voltages of the second input terminal 1002 and the third node N3. To this end, the second driving circuit 1220 may include a first transistor M1, a seventh transistor M7, an eighth transistor M8, a first capacitor C1, and a second capacitor C2.

[0136] The first capacitor C1 may be connected between the second node N2 and the output terminal 1006. The first capacitor C1 charges a voltage corresponding to turning on and off of the sixth transistor M6.

[0137] The second capacitor C2 may be connected between the first node N1 and the fourth input terminal 1004. The second capacitor C2 may charge a voltage applied to the first node N1.

[0138] The seventh transistor M7 may be connected between the first node N1 and the second input terminal 1002 and its gate electrode may be connected to the third node N3. The seventh transistor M7 may control the connection between the first node N1 and the second input terminal 1002 based on the voltage applied to the third node N3.

[0139] The eighth transistor M8 may be between the first node N1 and the fifth input terminal 1005 to which the second driving power source VSS1 is supplied, and its gate electrode may be connected to the second input terminal 1002. The eighth transistor M8 may control the connection between the first node N1 and the fifth input terminal 1005 based on a signal supplied to the second input terminal 1002.

[0140] The first transistor M1 may be connected between the third node N3 and the second node N2, and its gate electrode may be connected to the fifth input terminal 1005. The first transistor M1 may maintain the electrical connection between the third node N3 and the second node N2 while maintaining a conductive state. In addition, the first transistor M1 may limit the width of the voltage drop at the third node N3 based on the voltage of the second node N2. For example, even if the voltage of the second node N2 drops to a voltage lower than the voltage of the second driving power supply VSS1, the voltage of the third node N3 does not drop below a voltage that can be obtained by subtracting the threshold voltage of the first transistor M1 from the second driving power supply VSS1.

[0141] The second scanning stage circuit SST12 and the remaining scanning stage circuits SST13 to SST1 k may have the same configuration as that of the first scanning stage circuit SST11 .

[0142] Furthermore, the second input terminal 1002 of the j-th (j is an odd or even number) scanning stage circuit SST1j can receive the first clock signal CLK1, and the third input terminal 1003 thereof can receive the second clock signal CLK2. The second input terminal 1002 of the j+1-th scanning stage circuit SST1j+1 can receive the second clock signal CLK2, and the third input terminal 1003 thereof can receive the first clock signal CLK1.

[0143] The first clock signal CLK1 and the second clock signal CLK2 have the same period, and their phases do not overlap with each other. For example, when the period in which the scan signal is supplied to one first scan line S1 is referred to as 1 horizontal period (1H), each of the clock signals CLK1 and CLK2 may have a period of 2H, and each of the clock signals CLK1 and CLK2 may be supplied during different horizontal periods.

[0144] refer to Figure 7The stage circuits in the first scan driver 210 will be mainly described, but the stage circuits in other scan drivers (eg, the second scan driver 220 and the third scan driver 230) except the first scan driver 210 may have the same configuration.

[0145] Figure 8 is shown for driving Figure 7 For ease of description, the waveform diagram of an embodiment of the method of scanning stage circuit in FIG. Figure 8 In the following, the operation will be described using the first scanning stage circuit SST11.

[0146] refer to Figure 8 , the first clock signal CLK1 and the second clock signal CLK2 may have a period of 2 horizontal periods (2H), and the first clock signal CLK1 and the second clock signal CLK2 may be provided during different horizontal periods. For example, the second clock signal CLK2 may be a signal shifted from the first clock signal CLK1 by half a period (i.e., 1 horizontal period). In addition, the first start pulse SSP1 provided to the first input terminal 1001 is provided synchronously with the clock signal (i.e., the first clock signal CLK1) provided to the second input terminal 1002.

[0147] In addition, when the first start pulse SSP1 is provided, the first input terminal 1002 may be provided with the voltage of the second driving power supply VSS1. When the first start pulse SSP1 is not provided, the first input terminal 1002 may receive the voltage of the first driving power supply VDD1. In addition, when the clock signals CLK1 and CLK2 are provided to the second input terminal 1002 and the third input terminal 1003, the second input terminal 1002 and the third input terminal 1003 may receive the voltage of the second driving power supply VSS1. When the clock signals CLK1 and CLK2 are not provided to the second input terminal 1002 and the third input terminal 1003, the second input terminal 1002 and the third input terminal 1003 may receive the voltage of the first driving power supply VDD1.

[0148] During operation, first, a first start pulse SSP1 is provided in synchronization with the first clock signal CLK1. When the first clock signal CLK1 is provided, the second transistor M2 and the eighth transistor M8 may be turned on. When the second transistor M2 is turned on, the first input terminal 1001 is electrically connected to the third node N3. Since the first transistor M1 is always set to the on state, the second node N2 can maintain an electrical connection with the third node N3.

[0149] When the first input terminal 1001 is electrically connected to the third node N3, the third node N3 and the second node N2 may be set to a low level voltage by the first start pulse SSP1 supplied to the first input terminal 1001. When the third node N3 and the second node N2 are set to a low level voltage, the sixth transistor M6 and the seventh transistor M7 may be turned on.

[0150] When the sixth transistor M6 is turned on, the third input terminal 1003 and the output terminal 1006 can be electrically connected. The third input terminal 1003 can be provided with a high-level voltage (i.e., the second clock signal CLK2 is not provided). Therefore, the voltage with a high level can also be output to the output terminal 1006. When the seventh transistor M7 is turned on, the second input terminal 1002 and the first node N1 can be electrically connected. Subsequently, the voltage of the first clock signal CLK1 provided to the second input terminal 1002 (i.e., the voltage with a low level) can be provided to the first node N1.

[0151] In addition, when the first clock signal CLK1 is provided, the eighth transistor M8 may be turned on. When the eighth transistor M8 is turned on, the voltage of the second driving power supply VSS1 is provided to the first node N1. The voltage of the second driving power supply VSS1 may be set to the same (or similar) voltage as the first clock signal CLK1. Therefore, the first node N1 can stably maintain a low voltage.

[0152] When the first node N1 is provided with a voltage having a low level, the fourth transistor M4 and the fifth transistor M5 may be turned on. When the fourth transistor M4 is turned on, the fourth input terminal 1004 and the third transistor M3 may be electrically connected. Since the third transistor M3 is set to an off state, even if the fourth transistor M4 is turned on, the voltage of the third node N3 may be stably maintained at a low level.

[0153] When the fifth transistor M5 is turned on, the voltage of the first driving power source VDD1 is supplied to the output terminal 1006. The voltage of the first driving power source VDD1 may be set to the same voltage as the high level voltage supplied to the third input terminal 1003. Therefore, the output terminal 1006 may stably maintain the voltage at a high level.

[0154] Subsequently, the first start pulse SSP1 and the first clock signal CLK1 may be stopped from being supplied. When the first clock signal CLK1 is stopped from being supplied, the second transistor M2 and the eighth transistor M8 may be turned off. In this case, the sixth transistor M6 and the seventh transistor M7 may remain in an on state based on the voltage stored in the first capacitor C1. For example, the second node N2 and the third node N3 may maintain a low voltage due to the voltage in the first capacitor C1.

[0155] When the sixth transistor M6 remains in the on state, the output terminal 1006 and the third input terminal 1003 may remain electrically connected. When the seventh transistor M7 remains in the on state, the first node N1 may remain electrically connected to the second input terminal 1002. The voltage of the second input terminal 1002 may be set to a high level voltage based on the cessation of the supply of the first clock signal CLK1. Therefore, the first node N1 may also be set to a high level voltage. When a low level voltage is supplied to the first node N1, the fourth transistor M4 and the fifth transistor M5 may be turned off.

[0156] Subsequently, the second clock signal CLK2 may be provided to the third input terminal 1003. Since the sixth transistor M6 is set to an on state, the second clock signal CLK2 provided to the third input terminal 1003 may be provided to the output terminal 1006. In this case, the output terminal 1006 may output the second clock signal CLK2 to the first scan line S11 as a scan signal.

[0157] When the second clock signal CLK2 is supplied to the output terminal 1006, the voltage of the second node N2 is reduced to a voltage lower than the voltage of the second driving power supply VSS1 by coupling with the first capacitor C1. Therefore, the sixth transistor M6 can stably maintain an on state. Even if the voltage of the second node N2 drops, the third node N3 maintains a voltage of approximately the second driving power supply VSS1 (actually, a voltage obtained by subtracting the threshold voltage of the first transistor M1 from the second driving power supply VSS1).

[0158] After the scan signal is output to the first scan line S11, the second clock signal CLK2 may be stopped from being provided. When the second clock signal CLK2 is stopped from being provided, the output terminal 1006 may output a high-level voltage. Subsequently, the voltage of the second node N2 may increase to the voltage of the second driving power supply VSS1 based on the high-level voltage.

[0159] Subsequently, the first clock signal CLK1 may be provided. When the first clock signal CLK1 is provided, the second transistor M2 and the eighth transistor M8 may be turned on. When the second transistor M2 is turned on, the first input terminal 1001 and the third node N3 may be electrically connected. In this case, the first start pulse SSP1 is not provided to the first input terminal 1001. Therefore, the first input terminal 1001 may be provided with a high-level voltage. Therefore, when the first transistor M1 is turned on, a high-level voltage may be provided to the third node N3 and the second node N2, and thus the sixth transistor M6 and the seventh transistor M7 may be turned off.

[0160] When the eighth transistor M8 is turned on, the second driving power source VSS1 is supplied to the first node N1. Consequently, the fourth transistor M4 and the fifth transistor M5 can be turned on. When the fifth transistor M5 is turned on, the voltage of the first driving power source VDD1 can be supplied to the output terminal 1006. Subsequently, the fourth transistor M4 and the fifth transistor M5 remain turned on based on the voltage charged in the second capacitor C2. Consequently, the output terminal 1006 can stably receive the voltage of the first driving power source VDD1.

[0161] In addition, when the second clock signal CLK2 is provided, the third transistor M3 may be turned on. In this case, since the fourth transistor M4 is set to the on state, the voltage of the first driving power supply VDD1 can be provided to the third node N3 and the second node N2. In this case, the sixth transistor M6 and the seventh transistor M7 can be stably maintained in the off state.

[0162] The second scanning stage circuit SST12 may receive an output signal (i.e., a scanning signal) from the first scanning stage circuit SST11 that is synchronized with the second clock signal CLK2. In this case, the second scanning stage circuit SST12 may output a scanning signal synchronized with the first clock signal CLK1 to a second first scanning line S12. In one embodiment, the scanning stage circuit SST may sequentially output scanning signals to the scanning lines while repeating the above process.

[0163] Regardless of the voltage of the second node N2, the first transistor M1 limits the voltage drop width of the third node N3. Therefore, it is possible to reduce manufacturing costs and ensure driving reliability.

[0164] Figure 9 Show Figure 3 For ease of description, the first pixel PXL1 connected to the m-th data line Dm and the i-th first scan line S1i is shown.

[0165] refer to Figure 9 The first pixel PXL1 may include an organic light-emitting diode (OLED), a data line Dm, and a pixel circuit PC connected to a scan line S1i to control the organic light-emitting diode (OLED). An anode electrode of the organic light-emitting diode (OLED) is connected to the pixel circuit PC. A cathode electrode is connected to a second pixel power source (ELVSS). The organic light-emitting diode (OLED) may generate light having a predetermined brightness based on a current supplied from the pixel circuit PC.

[0166] When a scan signal is supplied to the scan line S1i, the pixel circuit PC may store the data signal supplied to the data line Dm and control the amount of current supplied to the organic light emitting diode OLED based on the stored data signal. For example, the pixel circuit PC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0167] The first transistor T1 may be connected between the data line Dm and the second transistor T2. For example, in the first transistor T1, the gate electrode may be connected to the scan line S1i, the first electrode may be connected to the data line Dm, and the second electrode may be connected to the gate electrode of the second transistor T2. When a scan signal is supplied to the scan line S1i, the first transistor T1 is turned on to supply the data signal from the data line Dm to the storage capacitor Cst. In this case, the storage capacitor Cst may be charged with a voltage corresponding to the data signal.

[0168] The second transistor T2 may be connected between the first pixel power source ELVDD and the organic light emitting diode OLED. For example, in the second transistor T2, the gate electrode may be connected to the first electrode of the storage capacitor Cst and the second electrode of the first transistor T1, the first electrode may be connected to the second electrode of the storage capacitor Cst and the first pixel power source ELVDD, and the second electrode may be connected to the anode electrode of the organic light emitting diode OLED.

[0169] The second transistor T2, serving as a driving transistor, can control the amount of current flowing from the first pixel power source ELVDD to the second pixel power source ELVSS via the organic light emitting diode OLED based on the voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED can generate light corresponding to the amount of current from the second transistor T2.

[0170] The first electrodes of transistors T1 and T2 may be source electrodes or drain electrodes. The second electrodes of transistors T1 and T2 may be the other of the source electrodes or drain electrodes. For example, when the first electrode is a source electrode, the second electrode is a drain electrode.

[0171] The second pixel PXL2 and the third pixel PXL3 can be implemented using the same circuit as the first pixel PXL1. Figure 9 The described pixel structure corresponds to an example using a scan line. In one embodiment, the pixel may have a circuit structure for supplying current to the organic light emitting diode OLED.

[0172] An organic light emitting diode (OLED) can generate light of various colors (e.g., red, green, blue) based on the amount of current from a driving transistor. In one embodiment, the organic light emitting diode (OLED) can generate white light based on the amount of current from a driving transistor. In this case, a color filter can be used to realize a color image.

[0173] Figure 10 Another embodiment of a display device 10' including a fourth scan driver 240 is shown. The fourth scan driver 240 may be in the first adjacent area NA1 to provide the first scan signal to the first scan line S1. For example, the first scan driver 210 may be in the first adjacent area NA1 adjacent to one side (e.g., the left side) of the first pixel area AA1. The fourth scan driver 240 may be in the first adjacent area NA1 adjacent to the other side (e.g., the right side) of the first pixel area AA1. The first scan driver 210 and the fourth scan driver 240 may drive at least some of the first scan lines S1. One of the first scan driver 210 and the fourth scan driver 240 may be omitted. The second signal line 260 may provide the second drive signal to the third scan driver 230 and the fourth scan driver 240.

[0174] Figure 11 FIG. 1 shows one embodiment of a load matching resistor at a signal line. Figure 11 The related display device 10 may include a fourth scan driver 240 .

[0175] refer to Figure 11 The first scan driver 210 may be connected to the first ends of the first scan lines S11 to S1k. The fourth scan driver 240 may be connected to the second ends of the first scan lines S11 to S1k. For example, the first scan lines S11 to S1k may be connected between the first scan driver 210 and the fourth scan driver 240.

[0176] To prevent delay of the scan signals, the first scan driver 210 and the fourth scan driver 240 may simultaneously provide the first scan signals to the same scan lines. For example, the first first scan line S11 may simultaneously receive the first scan signals from the first scan driver 210 and the fourth scan driver 240, and then the second first scan line S12 may simultaneously receive the first scan signals from the first scan driver 210 and the fourth scan driver 240. As described above, the first scan driver 210 and the fourth scan driver 240 may sequentially provide the first scan signals to the first scan lines S11 to S1k.

[0177] The fourth scan driver 240 may include a plurality of scan stage circuits SST11 to SST1k. The scan stage circuits SST11 to SST1k of the fourth scan driver 240 may be connected to the second ends of the first scan lines S11 to S1k, respectively, and may provide first scan signals to the first scan lines S11 to S1k, respectively. The scan stage circuits SST11 to SST1k of the fourth scan driver 240 may have the same or similar configuration as that of the first scan driver 210.

[0178] The second signal lines 260a and 260b may provide the clock signals CLK1 and CLK2 to the third scan driver 230 and the fourth scan driver 240. For example, the first second signal line 260a may provide the first clock signal CLK1 to the third scan driver 230 and the fourth scan driver 240. The second second signal line 260b may provide the second clock signal CLK2 to the third scan driver 230 and the fourth scan driver 240.

[0179] The load of the first scan lines S11 to S1k can be different from the load of the third scan lines S31 to S3j. For example, the first scan lines S11 to S1k can be longer than the third scan lines S31 to S3j, and the number of first pixels PXL1 can be greater than the number of third pixels PXL3. This allows the load of the first scan lines S11 to S1k to be greater than the load of the third scan lines S31 to S3j. Therefore, as with the first signal lines 250a and 250b, second load matching resistors 263a and 263b can be installed in the second signal lines 260a and 260b. This allows the loads of the first scan lines S11 to S1k and the third scan lines S31 to S3j to be matched, and the brightness of the first pixel area AA1 and the third pixel area AA3 can be consistent.

[0180] For example, the first second signal line 260a may include a first sub-signal line 261a, a second sub-signal line 262a, and a second load matching resistor 263a. The first sub-signal line 261a may be connected to the fourth scan driver 240 and may provide the first clock signal CLK1 to the fourth scan driver 240. The second sub-signal line 262a may be connected to the third scan driver 230 and may provide the first clock signal CLK1 to the third scan driver 230. The second load matching resistor 263a may be connected between the first sub-signal line 261a and the second sub-signal line 262a.

[0181] One end of the first sub-signal line 261a can receive the first clock signal CLK1. The other end of the first sub-signal line 261a can be connected to the second load matching resistor 263a. Therefore, the first sub-signal line 261a can receive the first clock signal CLK1 and can transmit the first clock signal CLK1 to the second sub-signal line 262a through the second load matching resistor 263a.

[0182] Similar to the first second signal line 260a, the second second signal line 260b may include a first sub-signal line 261b, a second sub-signal line 262b, and a second load matching resistor 263b. The first sub-signal line 261b may be connected to the fourth scan driver 240 and may provide the second clock signal CLK2 to the fourth scan driver 240. The second sub-signal line 262b may be connected to the third scan driver 230 and may provide the second clock signal CLK2 to the third scan driver 230.

[0183] The second load matching resistor 263b may be connected between the first sub-signal line 261b and the second sub-signal line 262b. One end of the first sub-signal line 261b may receive the second clock signal CLK2. The other end of the first sub-signal line 261b may be connected to the second load matching resistor 263b. Therefore, the first sub-signal line 261b may receive the second clock signal CLK2 and may transmit the second clock signal CLK2 to the second sub-signal line 262b via the second load matching resistor 263b.

[0184] The second load matching resistors 263a and 263b may be connected between the first scan stage circuit SST11 of the fourth scan driver 240 and the last scan stage circuit SST3j of the third scan driver 230. For example, the second signal lines 260a and 260b may have a resistance equal to the reference signal. Figure 4 The material and structure of the first signal lines 250a and 250b are the same as those described above.

[0185] The first load matching resistors 253a and 253b can be as shown in FIG. Figure 3 As in Figure 5 In the embodiment, additional load matching resistors may be installed in the first sub-signal lines 261a and 261b and the second sub-signal lines 262a and 262b in the second signal lines 260a and 260b.

[0186] Figure 12An embodiment of load matching resistors installed in scan lines is shown. To match the loads of the first scan lines S11 to S1k and the third scan lines S31 to S3j, second load matching resistors R31 to R3j may be installed in the third scan lines S31 to S3j. The second load matching resistors R31 to R3j may be connected between the third scan driver 230 and the third scan lines S31 to S3j.

[0187] The second load matching resistors R31 to R3j may have the same resistance value or different resistance values. For example, at least some of the third scan lines S31 to S3j may have different loads, so that at least some of the second load matching resistors R31 to R3j associated with some of the third scan lines S31 to S3j may have different resistance values. In one embodiment, the second load matching resistors R31 to R3j may be connected between the output terminals of the scan stage circuits SST31 to SST3j in the third scan driver 230 and the third scan lines S31 to S3j.

[0188] The second load matching resistors R31 to R3j may be formed of a material having a higher resistance than the resistance of the third scan lines S31 to S3j. For example, the third scan lines S31 to S3j may be formed of the same material as the source and drain electrodes of the transistors in the pixels PXL1, PXL2, and PXL3. The second load matching resistors R31 to R3j may be formed of the same material as the gate electrodes or semiconductor layers of the transistors in the pixels PXL1, PXL2, and PXL3.

[0189] The third scan lines S31 to S3j may be formed of the same material as the gate electrodes of the transistors in the pixels PXL1, PXL2, and PXL3. The second load matching resistors R31 to R3j may be formed of the same material as the semiconductor layers of the transistors in the pixels PXL1, PXL2, and PXL3. The first load matching resistors R21 to R2j may be formed as shown in FIG. Figure 6 Operate as described.

[0190] Figure 13 Another embodiment of a display device 10 is shown, which may include a substrate 100, a first pixel PXL1, a second pixel PXL2, a third pixel PXL3, a first scan driver 210, a second scan driver 220, a third scan driver 230, a fourth scan driver 240, a first emission driver 310, a second emission driver 320, a third emission driver 330, and a fourth emission driver 340.

[0191] The first pixel PXL1 may be in the first pixel area AA1 and may be connected to the first scan line S1 , the first emission control line E1 , and the first data line D1 .

[0192] The first scan driver 210 and the fourth scan driver 240 can provide the first scan signal to the first pixel PXL1 through the first scan line S1. The first scan driver 210 and the fourth scan driver 240 may be located in the first adjacent area NA1. For example, the first scan driver 210 may be located in the first adjacent area NA1 adjacent to one side (e.g., the left side) of the first pixel area AA1, and the fourth scan driver 240 may be located in the first adjacent area NA1 adjacent to the other side (e.g., the right side) of the first pixel area AA1. The first scan driver 210 and the fourth scan driver 240 may drive at least some of the first scan lines S1. In one embodiment, one of the first scan driver 210 and the fourth scan driver 240 may be omitted.

[0193] The first emission driver 310 and the fourth emission driver 340 may provide the first emission control signal to the first pixel PXL1 through the first emission control line E1. For example, the first emission driver 310 and the fourth emission driver 340 may sequentially provide the first emission control signal to the first emission control line E1.

[0194] The first emission driver 310 and the fourth emission driver 340 may be located in the first adjacent area NA1. For example, the first emission driver 310 may be located in the first adjacent area NA1 adjacent to one side (e.g., the left side) of the first pixel area AA1. The fourth emission driver 340 may be located in the first adjacent area NA1 adjacent to the other side (e.g., the right side) of the first pixel area AA1.

[0195] The first emission driver 310 and the fourth emission driver 340 may drive at least some of the first emission control lines E1. In one embodiment, one of the first emission driver 310 and the fourth emission driver 340 may be omitted.

[0196] Figure 13 1 shows a case where the first emission driver 310 is located outside the first scan driver 210. In another embodiment, the first emission driver 310 may be located inside the first scan driver 210. Figure 13 A case is shown in which the fourth emission driver 340 is at an outer side of the fourth scan driver 240. In one embodiment, the fourth emission driver 340 may be at an inner side of the fourth scan driver 240.

[0197] The second pixel PXL2 may be located in the second pixel area AA2 and may be connected to the second scan line S2, the second emission control line E2, and the second data line D2. The second scan driver 220 may provide a second scan signal to the second pixel PXL2 via the second scan line S2. The second scan driver 220 may be located in a second adjacent area NA2 adjacent to one side (e.g., the left side) of the second pixel area AA2.

[0198] The second emission driver 320 may provide the second emission control signal to the second pixel PXL2 through the second emission control line E2. For example, the second emission driver 320 may sequentially provide the second emission control signal to the second emission control line E2. The second emission driver 320 may be in the second adjacent area NA2 adjacent to one side (e.g., the left side) of the second pixel area AA2.

[0199] In one embodiment, the second scan driver 220 and the second emission driver 320 may both be located on one side of the second pixel area AA2 (eg, based on the pixel area AA2). Figure 13 In this case, as in Figure 13 In the embodiment, the second emission driver 320 may be at an outer side of the second scan driver 220. In one embodiment, the second emission driver 320 may also be at an inner side of the second scan driver 220.

[0200] In other embodiments, the positions of the second scan driver 220 and the second emission driver 320 may be different. For example, the second scan driver 220 and the second emission driver 320 may also be located at the other side (eg, the right side) of the second pixel area AA2.

[0201] The second pixel area AA2 has an area smaller than that of the first pixel area AA1, so that the second scan line S2 and the second emission control line E2 can be shorter than the first scan line S1 and the first emission control line E1. In addition, the number of second pixels PXL2 connected to one second emission control line E2 can be smaller than the number of first pixels PXL1 connected to one first emission control line E1.

[0202] The third pixels PXL3 may be in the third pixel area AA3. Each of the third pixels PXL3 may be connected to the third scan line S3 and the third data line D3.

[0203] The third scan driver 230 may provide a third scan signal to the third pixel PXL3 through the third scan line S3. The third scan driver 230 may be in a third adjacent area NA3 adjacent to one side (eg, right side) of the third pixel area AA3.

[0204] The third emission driver 330 may provide a third emission control signal to the third pixel PXL3 through the third emission control line E3. For example, the third emission driver 330 may sequentially provide the third emission control signal to the third emission control line E3. The third emission driver 330 may be in a third adjacent area NA3 adjacent to one side (e.g., right side) of the third pixel area AA3.

[0205] In one embodiment, the third scan driver 230 and the third emission driver 330 may both be located on one side of the third pixel area AA3 (eg, based on the pixel area AA3). Figure 13 In this case, as in Figure 13 In the embodiment, the third emission driver 330 may be at an outer side of the third scan driver 230. In one embodiment, the third emission driver 330 may also be at an inner side of the third scan driver 230.

[0206] In other embodiments, the positions of the third scan driver 230 and the third emission driver 330 may be different. For example, the third scan driver 230 and the third emission driver 330 may also be located at the other side (eg, the left side) of the third pixel area AA3.

[0207] The third pixel area AA3 has an area smaller than that of the first pixel area AA1, so that the third scan line S3 and the third emission control line E3 can be shorter than the first scan line S1 and the first emission control line E1. In addition, the number of third pixels PXL3 connected to one third emission control line E3 can be smaller than the number of first pixels PXL1 connected to one first emission control line E1.

[0208] The emission control signal is used to control the emission time of the pixels PXL1, PXL2, and PXL3. To this end, the emission control signal may be set to have a width greater than that of the scan signal.

[0209] In addition, the emission control signal may be provided with a gate-off voltage (e.g., a high-level voltage) so that the transistors in the pixels PXL1, PXL2, and PXL3 may be turned off, and the scan signal may have a gate-on voltage (e.g., a low-level voltage) so that the transistors in the pixels PXL1, PXL2, and PXL3 may be turned on.

[0210] The first scan driver 210 and the second scan driver 220 may operate based on the first driving signal. To this end, the first signal line 250 may provide the first driving signal to the first scan driver 210 and the second scan driver 220. In this case, the first signal line 250 may be in the adjacent areas NA1 and NA2.

[0211] The third scan driver 230 and the fourth scan driver 240 may operate based on the second driving signal. To this end, the second signal line 260 may provide the second driving signal to the third scan driver 230 and the fourth scan driver 240. In this case, the second signal line 260 may be in the adjacent areas NA1 and NA3.

[0212] The first signal line 250 and the second signal line 260 may receive a first driving signal and a second driving signal, respectively, from separate constituent elements (eg, a timing controller) and may extend toward a lower side of the first pixel area AA1.

[0213] Furthermore, a plurality of signal lines may be used instead of each of the first signal line 250 and the second signal line 260. The first driving signal and the second driving signal may be clock signals.

[0214] The first emission driver 310 and the second emission driver 320 may operate based on the third driving signal. To this end, the third signal line 350 may provide the third driving signal to the first emission driver 310 and the second emission driver 320. In this case, the third signal line 350 may be in the adjacent areas NA1 and NA2.

[0215] The third emission driver 330 and the fourth emission driver 340 may operate based on the fourth driving signal. To this end, the fourth signal line 360 may provide the fourth driving signal to the third emission driver 330 and the fourth emission driver 340. In this case, the fourth signal line 360 may be in the adjacent areas NA1 and NA3.

[0216] The third signal line 350 and the fourth signal line 360 may receive a third drive signal and a fourth drive signal, respectively, from a separate component (e.g., a timing controller). The third signal line 350 and the fourth signal line 360 may extend toward the lower side of the first pixel area AA1. Furthermore, the number of third signal lines 350 and the number of fourth signal lines 360 may be plural. The third drive signal and the fourth drive signal may be clock signals.

[0217] Figure 14 Another embodiment of a load matching resistor installed at a signal line is shown. Figure 14 The display device 10, 10', or 10" may include a plurality of third signal lines 350a and 350b and a plurality of fourth signal lines 360a and 360b for providing driving signals CLK3 and CLK4 to the emission drivers 310, 320, 330, and 340. The driving signals CLK3 and CLK4 may include a third clock signal CLK3 and a fourth clock signal CLK4. For example, the third clock signal CLK3 and the fourth clock signal CLK4 may have different phases.

[0218] The third signal lines 350a and 350b may provide the clock signals CLK3 and CLK4 to the first emission driver 310 and the second emission driver 320. For example, the first third signal line 350a may provide the third clock signal CLK3 to the first emission driver 310 and the second emission driver 320, and the second third signal line 350b may provide the fourth clock signal CLK4 to the first emission driver 310 and the second emission driver 320.

[0219] The fourth signal lines 360a and 360b may provide the clock signals CLK3 and CLK4 to the third emission driver 330 and the fourth emission driver 340. For example, the first fourth signal line 360a may provide the third clock signal CLK3 to the third emission driver 330 and the fourth emission driver 340, and the second fourth signal line 360b may provide the fourth clock signal CLK4 to the third emission driver 330 and the fourth emission driver 340.

[0220] The first emission driver 310 may be connected to first ends of the first emission control lines E11 to E1k, and the fourth emission driver 340 may be connected to second ends of the first emission control lines E11 to E1k. For example, the first emission control lines E11 to E1k may be connected between the first emission driver 310 and the fourth emission driver 340.

[0221] To prevent delays in emission control signals, the first emission driver 310 and the fourth emission driver 340 may simultaneously provide first emission control signals to the same emission control line. For example, the first emission control line E11 may simultaneously receive first emission control signals from the first emission driver 310 and the fourth emission driver 340. Subsequently, the second emission control line E12 may simultaneously receive first emission control signals from the first emission driver 310 and the fourth emission driver 340.

[0222] As described above, the first emission driver 310 and the fourth emission driver 340 may sequentially provide the first emission control signals to the first emission control lines E11 to E1k.

[0223] The first emission driver 310 may include a plurality of emission-stage circuits EST11 to EST1k. The emission-stage circuits EST11 to EST1k of the first emission driver 310 may be connected to first ends of first emission control lines E11 to E1k, respectively, and may provide first emission control signals to the first emission control lines E11 to E1k, respectively. For example, the emission-stage circuits EST11 to EST1k may operate based on clock signals CLK3 and CLK4 provided from an external source. The emission-stage circuits EST11 to EST1k may be identical circuits.

[0224] Transmitter circuits EST11 to EST1k may receive a start pulse or an output signal (i.e., a transmission control signal) of a previous transmitter circuit. For example, the first transmitter circuit EST11 may receive a start pulse. The remaining transmitter circuits EST12 to EST1k may receive an output signal of a previous transmitter circuit.

[0225] like Figure 14 As shown, the first emission stage circuit EST11 of the first emission driver 310 may use a signal output from the last emission stage circuit EST2j of the second emission driver 320 as a start pulse. In another exemplary embodiment, the first emission stage circuit EST11 of the first emission driver 310 may not receive the signal output from the last emission stage circuit SST2j of the second emission driver 320, and may receive the start pulse alone.

[0226] Each of the transmitter circuits EST11 to EST1k can receive a third driving power supply VDD2 and a fourth driving power supply VSS2. The third driving power supply VDD2 can be a gate-off voltage, such as a high-level voltage, and the fourth driving power supply VSS2 can be a gate-on voltage, such as a low-level voltage.

[0227] In addition, the third driving power source VDD2 may have the same voltage as the first driving power source VDD1 , and the fourth driving power source VSS2 may have the same voltage as the second driving power source VSS1 .

[0228] The fourth emission driver 340 may include a plurality of emission-stage circuits EST11 through EST1k. The emission-stage circuits EST11 through EST1k of the fourth emission driver 340 may be connected to the second ends of the first emission control lines E11 through E1k, respectively, and may provide first emission control signals to the first emission control lines E11 through E1k, respectively. The emission-stage circuits EST11 through EST1k of the fourth emission driver 340 may have the same configuration as the first emission driver 310.

[0229] The first pixel PXL1 may receive a first pixel power source ELVDD, a second pixel power source ELVSS, and an initialization power source Vint. The second emission driver 320 may be connected to first ends of the second emission control lines E21 to E2j.

[0230] The second emission driver 320 may include a plurality of emission stage circuits EST21 to EST2j. The emission stage circuits EST21 to EST2j of the second emission driver 320 may be connected to first ends of the second emission control lines E21 to E2j, respectively, and may provide second emission control signals to the second emission control lines E21 to E2j, respectively.

[0231] For example, the transmitting stage circuits EST21 to EST2j may operate based on clock signals CLK3 and CLK4 provided from an external source.The transmitting stage circuits EST21 to EST2j may be the same circuit.

[0232] Transmitter circuits EST21 through EST2j may receive a start pulse or an output signal (i.e., an emission control signal) from a previous transmitter circuit. For example, the first transmitter circuit EST21 may receive a start pulse SSP2, and the remaining transmitter circuits EST22 through EST2j may receive an output signal from a previous transmitter circuit. The last transmitter circuit EST2j of the second emission driver 320 may provide an output signal to the first transmitter circuit EST11 of the first emission driver 310.

[0233] Each of the transmitter circuits EST21 to EST2j can receive a third driving power supply VDD2 and a fourth driving power supply VSS2. The third driving power supply VDD2 can be a gate-off voltage, such as a high-level voltage, and the fourth driving power supply VSS2 can be a gate-on voltage, such as a low-level voltage.

[0234] Furthermore, the second pixel PXL2 can receive a first pixel power supply ELVDD, a second pixel power supply ELVSS, and an initialization power supply Vint. The third emission driver 330 can be connected to the first ends of the third emission control lines E31 to E3j. The third emission driver 330 can include a plurality of emission stage circuits EST31 to EST3j. The emission stage circuits EST31 to EST3j of the third emission driver 330 can be connected to the first ends of the third emission control lines E31 to E3j, respectively, and can provide third emission control signals to the third emission control lines E31 to E3j, respectively.

[0235] In this case, the transmitting stage circuits EST31 to EST3j may operate based on clock signals CLK3 and CLK4 provided from the outside. The transmitting stage circuits EST31 to EST3j may be the same circuit.

[0236] Transmitter circuits EST31 through EST3j may receive a start pulse or an output signal (i.e., an emission control signal) from a previous transmitter circuit. For example, the first transmitter circuit EST31 may receive a start pulse SSP2. The remaining transmitter circuits EST32 through EST3j may receive output signals from previous transmitter circuits. The last transmitter circuit EST3j of the third emission driver 330 may provide an output signal to the first transmitter circuit EST11 of the fourth emission driver 340.

[0237] Each of the transmitter circuits EST11 to EST3j can receive a third driving power supply VDD2 and a fourth driving power supply VSS2. The third driving power supply VDD2 can be a gate-off voltage, such as a high-level voltage. The fourth driving power supply VSS2 can be a gate-on voltage, such as a low-level voltage.

[0238] The third pixel PXL3 may receive a first pixel power source ELVDD, a second pixel power source ELVSS, and an initialization power source Vint.

[0239] The loads of the first emission control lines E11 to E1k may be different from the loads of the second emission control lines E21 to E2j. The first emission control lines E11 to E1k may be longer than the second emission control lines E21 to E2j. The number of first pixels PXL1 may be greater than the number of second pixels PXL2, so that the loads of the first emission control lines E11 to E1k may be greater than the loads of the second emission control lines E21 to E2j.

[0240] The capacitance of the first emission control lines E11 to E1k may be greater than that of the second emission control lines E21 to E2j. This results in a difference in time constants between the first and second emission control signals. This difference may result in a brightness difference between the first and second pixels PXL1 and PXL2.

[0241] According to the present exemplary embodiment, load matching resistors 353a and 353b may be installed in the third signal lines 350a and 350b. Therefore, the loads of the first emission control lines E11 to E1k and the second emission control lines E21 to E2j can be matched, and the brightness of the first pixel area AA1 and the second pixel area AA2 can be consistent.

[0242] For example, the first third signal line 350a may include a first sub-signal line 351a, a second sub-signal line 352a, and a third load matching resistor 353a. The first sub-signal line 351a may be connected to the first emission driver 310 and may provide the third clock signal CLK3 to the first emission driver 310. The second sub-signal line 352a may be connected to the second emission driver 320 and may provide the third clock signal CLK3 to the second emission driver 320. The third load matching resistor 353a may be connected between the first sub-signal line 351a and the second sub-signal line 352a.

[0243] One end of the first sub-signal line 351a can receive the third clock signal CLK3. The other end of the first sub-signal line 351a can be connected to the third load matching resistor 353a. Therefore, the first sub-signal line 351a can receive the third clock signal CLK3 and transmit the third clock signal CLK3 to the second sub-signal line 352a through the third load matching resistor 353a.

[0244] Similar to the first third signal line 350a, the second third signal line 350b may include a first sub-signal line 351b, a second sub-signal line 352b, and a third load matching resistor 353b. The first sub-signal line 351b may be connected to the first emission driver 310 and may provide the fourth clock signal CLK4 to the first emission driver 310. The second sub-signal line 352b may be connected to the second emission driver 320 and may provide the fourth clock signal CLK4 to the second emission driver 320. The third load matching resistor 353b may be connected between the first sub-signal line 351b and the second sub-signal line 352b.

[0245] One end of the first sub-signal line 351b can receive the fourth clock signal CLK4. The other end of the first sub-signal line 351b can be connected to the third load matching resistor 353b. Therefore, the first sub-signal line 351b can receive the fourth clock signal CLK4 and transmit the fourth clock signal CLK4 to the second sub-signal line 352b through the third load matching resistor 353b.

[0246] The third load matching resistors 353 a and 353 b may be connected between the first emission stage circuit EST11 of the first emission driver 310 and the last emission stage circuit EST2 j of the second emission driver 320 .

[0247] The loads of the first emission control lines E11 to E1k may be different from the loads of the third emission control lines E31 to E3j. For example, the first emission control lines E11 to E1k may be longer than the third emission control lines E31 to E3j. The number of first pixels PXL1 may be greater than the number of third pixels PXL3. Therefore, the loads of the first emission control lines E11 to E1k may be greater than the loads of the third emission control lines E31 to E3j.

[0248] Like the third signal lines 350a and 350b, load matching resistors 363a and 363b may be installed in the fourth signal lines 360a and 360b. Therefore, the loads of the first emission control lines E11 to E1k and the third emission control lines E31 to E3j can be matched, and the brightness of the first pixel area AA1 and the third pixel area AA3 can be consistent.

[0249] For example, the first fourth signal line 360a may include a first sub-signal line 361a, a second sub-signal line 362a, and a fourth load matching resistor 363a. The first sub-signal line 361a may be connected to the fourth emission driver 340 and may provide the third clock signal CLK3 to the fourth emission driver 340. The second sub-signal line 362a may be connected to the third emission driver 330 and may provide the third clock signal CLK3 to the third emission driver 330. The fourth load matching resistor 363a may be connected between the first sub-signal line 361a and the second sub-signal line 362a.

[0250] One end of the first sub-signal line 361a can receive the third clock signal CLK3. The other end of the first sub-signal line 361a can be connected to the fourth load matching resistor 363a. Therefore, the first sub-signal line 361a can receive the third clock signal CLK3 and transmit the third clock signal CLK3 to the second sub-signal line 362a through the fourth load matching resistor 363a.

[0251] Similar to the first fourth signal line 360a, the second fourth signal line 360b may include a first sub-signal line 361b, a second sub-signal line 362b, and a fourth load matching resistor 363b. The first sub-signal line 361b may be connected to the fourth emission driver 340 and may provide the fourth clock signal CLK4 to the fourth emission driver 340. The second sub-signal line 362b may be connected to the third emission driver 330 and may provide the fourth clock signal CLK4 to the third emission driver 330. The fourth load matching resistor 363b may be connected between the first sub-signal line 361b and the second sub-signal line 362b.

[0252] One end of the first sub-signal line 361b can receive the fourth clock signal CLK4. The other end of the first sub-signal line 361b can be connected to the fourth load matching resistor 363b. Therefore, the first sub-signal line 361b can receive the fourth clock signal CLK4 and transmit the fourth clock signal CLK4 to the second sub-signal line 362b through the fourth load matching resistor 363b.

[0253] The fourth load matching resistors 363a and 363b may be connected between the first emission stage circuit EST11 of the fourth emission driver 340 and the last emission stage circuit EST3j of the third emission driver 330. The third signal lines 350a and 350b and the fourth signal lines 360a and 360b may have a voltage with respect to the reference voltage. Figure 4 The first signal lines 250a and 250b are described as having the same material and structure.

[0254] Figure 15 An embodiment of the third signal line and the second emission driver is shown. Figure 15 , one or more additional load matching resistors 354a and 354b may be installed in the second sub-signal lines 352a and 352b in the third signal lines 350a and 350b.

[0255] The loads of the second emission control lines E21 to E2j may be different from one another. For example, the lengths of the second emission control lines E21 to E2j may be different from one another depending on the form of the second pixel area AA2. In addition, the number of pixels PXL2 connected to each of the second emission control lines E21 to E2j may also be different.

[0256] In this case, load matching resistors 354a and 354b may be additionally used to match the loads of the second emission control lines E21 to E2j. Each of the second sub-signal lines 352a and 352b may be divided into a plurality of signal lines. Load matching resistors 354a and 354b may be connected between the separated signal lines.

[0257] Finally, the load matching resistors 354a and 354b may be connected between two adjacent stage circuits (eg, stage circuits EST22 and EST23 and stage circuits EST2j-2 and EST2j-1). The load matching resistors 354a and 354b may have a Figure 4 The first load matching resistor 253a is made of the same material and structure as described above.

[0258] The second sub-signal lines 352a and 352b in the third signal lines 350a and 350b have been described, but load matching resistors may be additionally installed in the first sub-signal lines 351a and 351b in the third signal lines 350a and 350b, and the first sub-signal lines 361a and 361b and the second sub-signal lines 362a and 362b in the fourth signal lines 360a and 360b.

[0259] Figure 16 An embodiment of load matching resistors installed in the emission control lines is shown. To match the loads of the first emission control lines E11 to E1k and the second emission control lines E21 to E2j, third load matching resistors R41 to R4j may be installed in the second emission control lines E21 to E2j. The third load matching resistors R41 to R4j may be connected between the second emission driver 320 and the second emission control lines E21 to E2j.

[0260] The third load matching resistors R41 to R4j may have the same resistance value or different resistance values. For example, at least some of the second emission control lines E21 to E2j may have different loads, so that at least some of the third load matching resistors R41 to R4j associated with some of the second emission control lines E21 to E2j may have different resistance values.

[0261] In one embodiment, the third load matching resistors R41 to R4j may be connected between the output terminals of the emitter stage circuits EST21 to EST2j and the second emission control lines E21 to E2j in the second emission driver 320. The third load matching resistors R41 to R4j may be formed of a material having a higher resistance than the resistance of the second emission control lines E21 to E2j.

[0262] For example, the second emission control lines E21 to E2j may be formed of the same material as the source and drain electrodes of the transistors in the pixels PXL1, PXL2, and PXL3. The third load matching resistors R41 to R4j may be formed of the same material as the gate electrodes or semiconductor layers of the transistors in the pixels PXL1, PXL2, and PXL3.

[0263] The second emission control lines E21 to E2j may be formed of the same material as the gate electrodes of the transistors in the pixels PXL1, PXL2, and PXL3. The third load matching resistors R41 to R4j may be formed of the same material as the semiconductor layers of the transistors in the pixels PXL1, PXL2, and PXL3.

[0264] To match the loads of the first emission control lines E11 to E1k and the third emission control lines E31 to E3j, fourth load matching resistors R51 to R5j may be installed in the third emission control lines E31 to E3j. The fourth load matching resistors R51 to R5j may be connected between the third emission driver 330 and the third emission control lines E31 to E3j.

[0265] The fourth load matching resistors R51 to R5j may have the same resistance value or different resistance values. For example, at least some of the third emission control lines E31 to E3j may have different loads, so that at least some of the fourth load matching resistors R51 to R5j associated with some of the third emission control lines E31 to E3j may have different resistance values.

[0266] In one embodiment, fourth load matching resistors R51 to R5j may be connected between output terminals of emitter stage circuits EST31 to EST3j included in the third emission driver 330 and the third emission control lines E31 to E3j. The fourth load matching resistors R51 to R5j may be formed from a material having a higher resistance than the third emission control lines E31 to E3j. For example, the third emission control lines E31 to E3j may be formed from the same material as the source and drain electrodes of the transistors in pixels PXL1, PXL2, and PXL3. The fourth load matching resistors R51 to R5j may be formed from the same material as the gate electrodes or semiconductor layers of the transistors in pixels PXL1, PXL2, and PXL3.

[0267] The third emission control lines E31 to E3j may be formed of the same material as the gate electrodes of the transistors in the pixels PXL1, PXL2, and PXL3. The fourth load matching resistors R51 to R5j may be formed of the same material as the semiconductor layers of the transistors in the pixels PXL1, PXL2, and PXL3.

[0268] For example, Figure 17 Shown with Figure 14 An embodiment of the corresponding transmitter circuit. For ease of description, Figure 17 Transmitter stage circuits EST11 and EST12 of the first transmit driver 310 are shown.

[0269] refer to Figure 17 The first emitter stage circuit EST11 may include a first driver circuit 2100, a second driver circuit 2200, a third driver circuit 2300, and an output unit 2400. The first driver circuit 2100 may control the voltages of the twenty-second node N22 and the twenty-first node N21 based on the signals provided to the first input terminal 2001 and the second input terminal 2002. To this end, the first driver circuit 2100 may include eleventh to thirteenth transistors M11 to M13.

[0270] The eleventh transistor M11 may be connected between the first input terminal 2001 and the twenty-first node N21, and a gate electrode thereof may be connected to the second input terminal 2002. When the third clock signal CLK3 is supplied to the second input terminal 2002, the eleventh transistor M11 may be turned on.

[0271] The twelfth transistor M12 may be connected between the second input terminal 2002 and the 22nd node N22, and a gate electrode thereof may be connected to the 21st node N21. The twelfth transistor M12 is turned on or off based on a voltage of the 21st node N21.

[0272] The thirteenth transistor M13 may be located between the fifth input terminal 2005 receiving the fourth driving power VSS2 and the twenty-second node N22, and its gate electrode may be connected to the second input terminal 2002. When the third clock signal CLK3 is provided to the second input terminal 2002, the thirteenth transistor M13 may be turned on.

[0273] The second driving circuit 2200 may control the voltages of the 21st node N21 and the 23rd node N23 based on the signal supplied to the third input terminal 2003 and the voltage of the 22nd node N22. To this end, the second driving circuit 2200 may include 14th to 17th transistors M14 to M17, an 11th capacitor C11, and a 12th capacitor C12.

[0274] The fourteenth transistor M14 may be connected between the fifteenth transistor M15 and the twenty-first node N21, and a gate electrode thereof may be connected to the third input terminal 2003. When the fourth clock signal CLK4 is supplied to the third input terminal 2003, the fourteenth transistor M14 may be turned on.

[0275] The fifteenth transistor M15 is connected between the fourth input terminal 2004 receiving the third driving power VDD2 and the fourteenth transistor M14, and its gate electrode is connected to the twenty-second node N22. The fifteenth transistor M15 is turned on or off based on the voltage of the twenty-second node N22.

[0276] The sixteenth transistor M16 may be connected between the first electrode of the seventeenth transistor M17 and the third input terminal 2003, and its gate electrode may be connected to the twenty-second node N22. The sixteenth transistor M16 is turned on or off based on the voltage of the twenty-second node N22.

[0277] The seventeenth transistor M17 may be connected between the first electrode of the sixteenth transistor M16 and the twenty-third node N23, and a gate electrode thereof may be connected to the third input terminal 2003. When the fourth clock signal CLK4 is supplied to the third input terminal 2003, the seventeenth transistor M17 may be turned on.

[0278] The eleventh capacitor C11 may be connected between the twenty-first node N21 and the third input terminal 2003 .

[0279] The twelfth capacitor C12 may be connected between the twenty-second node N22 and the first electrode of the seventeenth transistor M17.

[0280] The third driving circuit 2300 may control the voltage of the 23rd node N23 based on the voltage of the 21st node N21. The third driving circuit 2300 may include an 18th transistor M18 and a 13th capacitor C13.

[0281] The eighteenth transistor M18 is connected between the fourth input terminal 2004 receiving the third driving power VDD2 and the twenty-third node N23, and its gate electrode is connected to the twenty-first node N21. The eighteenth transistor M18 is turned on or off based on the voltage of the twenty-first node N21.

[0282] The thirteenth capacitor C13 may be connected between the fourth input terminal 2004 receiving the third driving power source VDD2 and the twenty-third node N23 .

[0283] The output unit 2400 may control the voltage supplied to the output terminal 2006 based on the voltages of the 21st node N21 and the 23rd node N23. To this end, the output unit 2400 may include a 19th transistor M19 and a 20th transistor M20.

[0284] The nineteenth transistor M19 may be connected between the fourth input terminal 2004 receiving the third driving power VDD2 and the output terminal 2006, and its gate electrode may be connected to the twenty-third node N23. The nineteenth transistor M19 may be turned on or off based on the voltage of the twenty-third node N23.

[0285] The twentieth transistor M20 may be located between the output terminal 2006 and the fifth input terminal 2005 receiving the fourth driving power source VSS2, and its gate electrode may be connected to the twenty-first node N21. The twentieth transistor M20 may be turned on or off based on the voltage of the twenty-first node N21. The output unit 2400 may be driven as a buffer.

[0286] In addition, the nineteenth transistor M19 and / or the twentieth transistor M20 may be formed of a plurality of transistors connected in parallel to each other.

[0287] The second transmitter stage circuit EST12 and the remaining transmitter stage circuits EST13 to EST1 k may have the same configuration as that of the first transmitter stage circuit EST11 .

[0288] The second input terminal 2002 of the j-th transmitting stage circuit EST1j can receive the third clock signal CLK3, and the third input terminal 2003 thereof can receive the fourth clock signal CLK4. The second input terminal 2002 of the j+1-th scanning stage circuit EST1j+1 can receive the fourth clock signal CLK4, and the third input terminal 2003 thereof can receive the third clock signal CLK3.

[0289] The third clock signal CLK3 and the fourth clock signal CLK4 have the same period and their phases do not overlap each other. For example, each of the clock signals CLK3 and CLK4 has a period of 2H and each of the clock signals CLK3 and CLK4 may be provided during different horizontal periods.

[0290] The stage circuit in the first emission driver 310 may be as follows Figure 17 Stage circuits in other emission drivers (eg, the second emission driver 320 , the third emission driver 330 , and the fourth emission driver 340 ) other than the first emission driver 310 may have the same configuration.

[0291] Figure 18 is shown for driving Figure 17For ease of description, the waveform diagram of an embodiment of the method of the transmitter circuit in FIG. Figure 18 , the operation will be described by using the first transmitting stage circuit EST11.

[0292] refer to Figure 18 The third clock signal CLK3 and the fourth clock signal CLK4 may have a period of 2 horizontal periods (2H), and may be provided during different horizontal periods. For example, the fourth clock signal CLK4 may be a signal shifted from the third clock signal CLK3 by half a period (i.e., 1 horizontal period (1H)).

[0293] When the second start pulse SSP2 is supplied, the first input terminal 2001 may be provided with the voltage of the third driving power supply VDD2. When the second start pulse SSP2 is not supplied, the first input terminal 2001 may have the voltage of the fourth driving power supply VSS2. In addition, when the clock signal CLK is supplied to the second input terminal 2002 and the third input terminal 2003, the second input terminal 2002 and the third input terminal 2003 may have the voltage of the fourth driving power supply VSS2. When the clock signal is not supplied to the second input terminal 2002 and the third input terminal 2003, the second input terminal 2002 and the third input terminal 2003 may have the voltage of the third driving power supply VDD2.

[0294] The second start pulse SSP2 supplied to the first input terminal 2001 is supplied synchronously with the clock signal (i.e., the third clock signal CLK3) supplied to the second input terminal 2002. Furthermore, the second start pulse SSP2 may be set to have a greater width than the third clock signal CLK3. For example, the second start pulse SSP2 may be supplied during four horizontal periods (4H).

[0295] In operation, first, the third clock signal CLK3 may be provided to the second input terminal at a first time t1. When the third clock signal CLK3 is provided to the second input terminal 2002, the eleventh transistor M11 and the thirteenth transistor M13 may be turned on.

[0296] When the eleventh transistor M11 is turned on, the first input terminal 2001 and the 21st node N21 may be electrically coupled Since the second start pulse SSP2 is not supplied to the first input terminal 2001, a voltage having a low level may be supplied to the 21st node N21.

[0297] When a voltage having a low level is supplied to the 21st node N21 , the twelfth transistor M12 , the eighteenth transistor M18 , and the twentieth transistor M20 may be turned on.

[0298] When the eighteenth transistor M18 is turned on, the third driving power source VDD2 is supplied to the twenty-third node N23. Therefore, the nineteenth transistor M19 can be turned off. In this case, the thirteenth capacitor C13 is charged with a voltage corresponding to the third driving power source VDD2. Therefore, the nineteenth transistor M19 can stably maintain the off state even after the first time t1.

[0299] When the twentieth transistor M20 is turned on, the voltage of the fourth driving power source VSS2 may be provided to the output terminal 2006. Therefore, the emission control signal is not provided to the first emission control line E11 at the first time t1.

[0300] When the twelfth transistor M12 is turned on, the third clock signal CLK3 can be provided to the twenty-second node N22. Furthermore, when the thirteenth transistor M13 is turned on, the voltage of the fourth driving power supply VSS2 can be provided to the twenty-second node N22. The third clock signal CLK3 can be the voltage of the fourth driving power supply VSS2. Therefore, the twenty-second node N22 can be stably provided with the voltage of the fourth driving power supply VSS2. At the same time, when the voltage of the twenty-second node N22 is provided with the voltage of the fourth driving power supply VSS2, the seventeenth transistor M17 can be provided in an off state. Therefore, regardless of the voltage of the twenty-second node N22, the twenty-third node N23 can maintain the voltage of the third driving power supply VDD2.

[0301] At the second time t2, the third clock signal CLK3 may be stopped from being supplied to the second input terminal 2002. When the third clock signal CLK3 is stopped, the eleventh transistor M11 and the thirteenth transistor M13 may be turned off. The voltage of the twenty-first node N21 is maintained at a low voltage level by the eleventh capacitor C11. Therefore, the twelfth transistor M12, the eighteenth transistor M18, and the twentieth transistor M20 may remain in a turned-on state.

[0302] When the twelfth transistor M12 is turned on, the second input terminal 2002 and the 22nd node N22 may be electrically connected. In this case, the 22nd node N22 may be at a high voltage.

[0303] When the eighteenth transistor M18 is turned on, the voltage of the third driving power source VDD2 is supplied to the twenty-third node N23. Therefore, the nineteenth transistor M19 may be kept in the off state.

[0304] When the twentieth transistor M20 is turned on, the voltage of the fourth driving power source VSS2 may be provided to the output terminal 2006 .

[0305] The fourth clock signal CLK4 may be provided to the third input terminal 2003 at the third time t3. When the fourth clock signal CLK4 is provided to the third input terminal 2003, the fourteenth transistor M14 and the seventeenth transistor M17 may be turned on.

[0306] When the seventeenth transistor M17 is turned on, the twelfth capacitor C12 is electrically connected to the twenty-third node N23. In this case, the twenty-third node N23 can maintain the voltage of the third driving power supply VDD2. Subsequently, when the fourteenth transistor M14 is turned on, the fifteenth transistor M15 is set to a cut-off state, so that the voltage of the twenty-first node N21 does not change even if the fourteenth transistor M14 is turned on.

[0307] When the fourth clock signal CLK4 is supplied to the third input terminal 2003, the voltage of the twenty-first node N21 may be lowered to a voltage lower than the voltage of the fourth driving power supply VSS2 by coupling of the eleventh capacitor C11. When the voltage of the twenty-first node N21 is lowered to a voltage lower than the voltage of the fourth driving power supply VSS2, the driving characteristics of the eighteenth transistor M18 and the twentieth transistor M20 may be improved (since the PMOS transistor receives a low voltage level, the PMOS transistor has good driving characteristics).

[0308] At a fourth time t4, the second start pulse SSP2 may be supplied to the first input terminal 2001, and the third clock signal CLK3 may be supplied to the second input terminal 2002. When the third clock signal CLK3 is supplied to the second input terminal 2002, the eleventh transistor M11 and the thirteenth transistor M13 may be turned on. When the eleventh transistor M11 is turned on, the first input terminal 2001 and the twenty-first node N21 may be electrically connected. In this case, since the second start pulse SSP2 is not supplied to the first input terminal 2001, a voltage having a high level may be supplied to the twenty-first node N21. When the voltage having a high level is supplied to the twenty-first node N21, the twelfth transistor M12, the eighteenth transistor M18, and the twentieth transistor M20 may be turned off.

[0309] When the thirteenth transistor M13 is turned on, the voltage of the fourth driving power source VSS2 can be supplied to the twenty-second node N22. In this case, since the fourteenth transistor M14 is set to an off state, the twenty-first node N21 can maintain a high voltage. In addition, since the seventeenth transistor M17 is set to an off state, the voltage of the twenty-third node N23 can be maintained at a high voltage through the thirteenth capacitor C13. Therefore, the nineteenth transistor M19 can maintain an off state.

[0310] The fourth clock signal CLK4 may be provided to the third input terminal 2003 at the fifth time t5. When the fourth clock signal CLK4 is provided to the third input terminal 2003, the fourteenth transistor M14 and the seventeenth transistor M17 may be turned on. In addition, since the twenty-second node N22 is provided with the voltage of the fourth driving power supply VSS2, the fifteenth transistor M15 and the sixteenth transistor M16 may be turned on.

[0311] When the sixteenth transistor M16 and the seventeenth transistor M17 are turned on, the fourth clock signal CLK4 can be provided to the twenty-third node N23. When the fourth clock signal CLK4 is provided to the twenty-third node N23, the nineteenth transistor M19 can be turned on. When the nineteenth transistor M19 is turned on, the voltage of the third driving power supply VDD2 can be provided to the output terminal 2006. The voltage of the third driving power supply VDD2 provided to the output terminal 2006 can be provided to the first emission control line E11 as an emission control signal.

[0312] At the same time, when the voltage of the fourth clock signal CLK4 is supplied to the 23rd node N23, the voltage of the 22nd node N22 is lowered to a voltage lower than the voltage of the fourth driving power supply VSS2 by coupling of the twelfth capacitor C12. Therefore, the driving characteristics of the transistor connected to the 22nd node N22 can be improved.

[0313] When the fourteenth transistor M14 and the fifteenth transistor M15 are turned on, the voltage of the third driving power source VDD2 can be supplied to the twenty-first node N21. When the voltage of the third driving power source VDD2 is supplied to the twenty-first node N21, the twentieth transistor M20 can remain in an off state. Therefore, the voltage of the third driving power source VDD2 can be stably supplied to the first emission control line E11.

[0314] The third clock signal CLK3 may be provided to the second input terminal 2002 at a sixth time t6. When the third clock signal CLK3 is provided to the second input terminal 2002, the eleventh transistor M11 and the thirteenth transistor M13 may be turned on.

[0315] When the eleventh transistor M11 is turned on, the twenty-first node N21 is electrically connected to the first input terminal 2001 and thus may be a low voltage. When the twenty-first node N21 is a low voltage, the eighteenth transistor M18 and the twentieth transistor M20 may be turned on.

[0316] When the eighteenth transistor M18 is turned on, the voltage of the third driving power supply VDD2 is supplied to the twenty-third node N23, and thus, the nineteenth transistor M19 may be turned off. When the twentieth transistor M20 is turned on, the voltage of the fourth driving power supply VSS2 is supplied to the output terminal 2006. The voltage of the fourth driving power supply VSS2 supplied to the output terminal 2006 may be supplied to the first emission control line E11. Therefore, the supply of the emission control signal may be stopped.

[0317] The transmitter stage circuit EST of this embodiment can sequentially output the emission control signals to the emission control lines while repeating the above process.

[0318] Figure 19 Show Figure 13 For ease of description, Figure 19 A first pixel PXL1 connected to an m-th data line Dm and an i-th first scan line S1i is shown.

[0319] refer to Figure 19 The first pixel PXL1 may include an organic light emitting diode OLED, first to seventh transistors T1 to T7, and a storage capacitor Cst. An anode of the organic light emitting diode OLED may be connected to the first transistor T1 via the sixth transistor T6, and a cathode thereof may be connected to the second pixel power source ELVSS. The organic light emitting diode OLED may generate light having a predetermined brightness based on a current supplied from the first transistor T1.

[0320] The first pixel power source ELVDD may be a higher voltage than the second pixel power source ELVSS so that current may flow to the organic light emitting diode OLED.

[0321] The seventh transistor T7 may be connected between an initialization power supply Vint and an anode of the organic light-emitting diode OLED. Furthermore, a gate electrode of the seventh transistor T7 may be connected to the (i+1)th first scan line Sli+1. When a scan signal is supplied to the (i+1)th first scan line Sli+1, the seventh transistor T7 may be turned on to supply the voltage of the initialization power supply Vint to the anode of the organic light-emitting diode OLED. Here, the initialization power supply Vint may be a voltage lower than the voltage of the data signal.

[0322] The sixth transistor T6 may be connected between the first transistor T1 and the organic light emitting diode OLED. Furthermore, a gate electrode of the sixth transistor T6 may be connected to the i-th first emission control line Eli. The sixth transistor T6 may be turned off when an emission control signal is supplied to the i-th first emission control line Eli, and may be turned off in other cases.

[0323] The fifth transistor T5 may be connected between the first pixel power source ELVDD and the first transistor T1. Furthermore, a gate electrode of the fifth transistor T5 may be connected to the i-th first emission control line Eli. The fifth transistor T5 may be turned off when an emission control signal is supplied to the i-th first emission control line Eli, and may be turned off in other cases.

[0324] A first electrode of the first transistor T1 (driving transistor) may be connected to the first pixel power source ELVDD via the fifth transistor T5, and a second electrode thereof may be connected to the anode of the organic light emitting diode OLED via the sixth transistor T6. Furthermore, a gate electrode of the first transistor T1 may be connected to a tenth node N10. The first transistor T1 may control the amount of current flowing from the first pixel power source ELVDD via the organic light emitting diode OLED to the second pixel power source ELVSS based on the voltage of the tenth node N10.

[0325] The third transistor T3 may be connected between the second electrode of the first transistor T1 and the tenth node N10. Furthermore, the gate electrode of the third transistor T3 may be connected to the i-th first scan line S1i. When a scan signal is supplied to the i-th first scan line S1i, the third transistor T3 may be turned on to electrically connect the second electrode of the first transistor T1 to the tenth node N10. Therefore, when the third transistor T3 is turned on, the first transistor T1 may be connected in the form of a diode.

[0326] The fourth transistor T4 may be connected between the tenth node N10 and the initialization power supply Vint. Furthermore, a gate electrode of the fourth transistor T4 may be connected to the (i-1)th first scan line Sli-1. When a scan signal is supplied to the (i-1)th first scan line Sli-1, the fourth transistor T4 may be turned on to supply the voltage of the initialization power supply Vint to the tenth node N10.

[0327] The second transistor T2 may be connected between the mth data line Dm and the first electrode of the first transistor T1. Furthermore, a gate electrode of the second transistor T2 may be connected to the i-th first scan line Sli. When a scan signal is supplied to the i-th first scan line Sli, the second transistor T2 may be turned on to electrically connect the mth data line Dm to the first electrode of the first transistor T1.

[0328] The storage capacitor Cst is connected between the first pixel power source ELVDD and the tenth node N10 and may store a data signal and a voltage corresponding to a threshold voltage of the first transistor T1.

[0329] The second pixel PXL2 and the third pixel PXL3 can be implemented using the same circuit as the first pixel PXL1. Figure 19The described pixel structure corresponds only to one example using scan lines and emission control lines. In another embodiment, the pixels PXL1, PXL2, and PXL3 may have different pixel structures.

[0330] According to one or more of the above embodiments, the organic light emitting diode (OLED) can generate light of various colors based on the amount of current supplied from the driving transistor. For example, the organic light emitting diode (OLED) can generate white light based on the amount of current supplied from the driving transistor. In this case, a color image can be achieved using separate color filters. The transistors discussed herein are P-type transistors, but in another embodiment, one or more of them can be N-type transistors.

[0331] The gate-off voltage and gate-on voltage of a transistor are at different levels depending on the type of transistor. For example, for a P-type transistor, the gate-off voltage and gate-on voltage may be a high-level voltage and a low-level voltage, respectively. For an N-type transistor, the gate-off voltage and gate-on voltage may be a low-level voltage and a high-level voltage, respectively.

[0332] Method described herein, process and / or operation can be performed by the code or instruction performed by a computer, processor, controller or other signal processing device.Computer, processor, controller or other signal processing device can be those described herein or the element except the element described herein.Owing to the algorithm of the basis of formation method (or the operation of computer, processor, controller or other signal processing device) described in detail, the code or instruction for realizing the operation of method embodiment can convert computer, processor, controller or other signal processing device into the special purpose processor for performing the method herein.

[0333] The drivers, controllers, and other processing features described herein may be implemented in logic, for example, which may include hardware, software, or both. When implemented at least partially in hardware, for example, the drivers, controllers, and other processing features may be any of a variety of integrated circuits, including but not limited to an application specific integrated circuit, a field programmable gate array, a logic gate, a system on a chip, a microprocessor, or a combination of another type of processing or control circuitry.

[0334] When implemented at least in part with software, for example, drivers, controllers, and other processing features may include a memory or other storage device for storing, for example, codes or instructions executed by a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be those described herein or elements other than those described herein. Since the algorithms forming the basis of the method (or the operation of a computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operation of the method embodiment may convert the computer, processor, controller, or other signal processing device into a dedicated processor for performing the method described herein.

[0335] Exemplary embodiments have been disclosed herein, and although specific terms are employed, these terms are used and interpreted only in a general and descriptive sense and are not intended to be limiting. In some instances, it will be apparent to those skilled in the art that, upon filing this application, unless otherwise expressly indicated, the features, characteristics, and / or elements described in conjunction with a specific embodiment may be used alone or in combination with the features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A display device comprising: a substrate comprising a first pixel region, a second pixel region, and a third pixel region, and a recessed portion, wherein the second pixel region and the third pixel region protrude from one end of the first pixel region in a first direction, and the recessed portion is formed by removing a portion of the substrate located between the second pixel region and the third pixel region; a first pixel in the first pixel region and connected to a first scan line; a second pixel in the second pixel area and connected to the second scan line; a third pixel, the third pixel being in the third pixel area and connected to the third scan line; a first scan driver including a plurality of stage circuits for respectively providing first scan signals to the first scan lines; a second scan driver including a plurality of stage circuits for respectively providing second scan signals to the second scan lines; a third scan driver including a plurality of stage circuits for respectively providing third scan signals to the third scan lines; as well as a first signal line that provides a first driving signal to the first scan driver and the second scan driver, Wherein, the first signal line includes: a first sub-signal line connected to the plurality of stage circuits of the first scan driver; a second sub-signal line connected to the plurality of stage circuits of the second scan driver; and A first load matching resistor is connected between the first sub-signal line and the second sub-signal line.

2. The display device according to claim 1, wherein The first sub-signal line is directly connected to each of the plurality of stage circuits of the first scan driver, and The second sub-signal line is directly connected to each of the plurality of stage circuits of the second scan driver.

3. The display device according to claim 1, wherein The first load matching resistor is connected between a first stage circuit among the plurality of stage circuits of the first scan driver and a last stage circuit among the plurality of stage circuits of the second scan driver.

4. The display device according to claim 1, wherein The first load matching resistor is formed of a material having a resistance higher than resistances of the first sub-signal line and the second sub-signal line.

5. The display device according to claim 1, further comprising: a second signal line, the second signal line providing a second driving signal to the third scan driver, The second signal line does not include a load matching resistor. The display device according to claim 1 , wherein: The first signal line further includes at least one additional load matching resistor connected between adjacent two stage circuits among the plurality of stage circuits of the second scan driver.

7. The display device according to claim 1, further comprising: a fourth scan driver including a plurality of stage circuits for respectively providing the first scan signals to the first scan lines; as well as a second signal line, the second signal line providing a second driving signal to the third scan driver, The second signal line includes: a third sub-signal line connected to the plurality of stage circuits of the fourth scan driver; a fourth sub-signal line connected to the plurality of stage circuits of the third scan driver; and A second load matching resistor is connected between the third sub-signal line and the fourth sub-signal line.

8. The display device according to claim 1, wherein The recess has a polygonal or circular shape in a plan view.

9. The display device according to claim 1, wherein At least a portion of the recess is curved in plan view.

10. The display device according to claim 1, wherein The number of second pixels connected to one of the second scan lines is smaller than the number of first pixels connected to one of the first scan lines.

11. The display device according to claim 1, wherein The second scan line is shorter than the first scan line.

12. The display device according to claim 1, wherein Each of the second pixel area and the third pixel area is smaller than the first pixel area.

13. The display device according to claim 1, wherein The first driving signal includes a clock signal.

14. The display device according to claim 1, further comprising: a first emission driver that provides a first emission control signal to the first pixel through a first emission control line; a second emission driver that provides a second emission control signal to the second pixel through a second emission control line; as well as a third signal line providing a third driving signal to the first emission driver and the second emission driver.

15. The display device according to claim 14, wherein The third signal line includes: a fifth sub-signal line, the fifth sub-signal line providing the third driving signal to the first emission driver; a sixth sub-signal line providing the third driving signal to the second emission driver; and A third load matching resistor is connected between the fifth sub-signal line and the sixth sub-signal line.

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