Wafer level packaging method

By setting a first and second part with spacing in the redistribution layer and connecting them with connecting lines, the problem of high cost of dielectric materials in wafer-level packaging is solved, and the packaging cost is reduced.

CN114999929BActive Publication Date: 2026-06-16NANTONG FUJITSU MICROELECTRONICS
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
NANTONG FUJITSU MICROELECTRONICS
Filing Date
2022-04-24
Publication Date
2026-06-16

AI Technical Summary

⚠Technical Problem

The high cost of dielectric materials in wafer-level packaging leads to increased packaging costs.

⚗Method used

By employing a first and second part with spacing in the redistribution layer and connecting them via connecting lines, the use of dielectric materials is reduced, forming a redistribution structure that does not require multiple interconnections.

🎯Benefits of technology

It effectively saves on the use of dielectric materials and reduces chip packaging costs.

✦ Generated by Eureka AI based on patent content.

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Abstract

The application discloses a wafer level packaging method, comprising: forming a re-distribution layer on one side of a functional surface of a chip, the re-distribution layer comprising a plurality of re-distribution lines, and one of the re-distribution lines being electrically connected to one pad on the functional surface of the chip; wherein at least one of the re-distribution lines comprises a first part and a second part arranged at intervals; forming at least one connecting line on the side of the re-distribution layer away from the chip; wherein the connecting line is arranged above the first part and the second part of the same re-distribution layer; forming a photoresist layer on the side of the re-distribution layer away from the chip, the photoresist layer covering part of the connecting line; removing the photoresist layer at the corresponding position of the connecting line to form a first groove, and arranging a baffle in the first groove. Through the above method, the application can reduce the use of dielectric materials and reduce the cost of chip packaging.
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