Transistor Structure, Display Substrate and Preparation Method Thereof, Display Device

Abstract

The present disclosure provides a transistor structure, a display substrate, a manufacturing method thereof, and a display device. The transistor structure includes: a substrate, a control electrode disposed on the substrate, a planarization layer covering at least a side surface of the control electrode, a gate insulating layer covering the control electrode and the planarization layer, an active layer disposed on a side of the gate insulating layer away from the substrate, a first electrode and a second electrode disposed on a side of the gate insulating layer away from the substrate and in electrical contact with the active layer, wherein a positive projection of the active layer on the substrate does not overlap with a positive projection of the planarization layer on the substrate. In this transistor structure, the short-circuit risk between the control electrode and the first electrode and the second electrode is reduced, and the reliability and yield of the transistor structure are improved.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technologies, and more specifically, relates to a transistor structure, a display substrate and a manufacturing method thereof, and a display device. Background Art

[0002] This section aims to provide background or context for the embodiments recited in the claims. The description herein is not admitted to be prior art merely because it is included in this section.

[0003] Display devices include, for example, liquid crystal display devices and light-emitting diode display devices. A large number of transistors are integrated in the display substrate of a display device. A short circuit defect between the gate and the source / drain of a transistor will greatly reduce the product yield. Summary of the Invention

[0004] The present disclosure provides a transistor structure, a display substrate and a manufacturing method thereof, and a display device.

[0005] The present disclosure adopts the following technical solutions: A transistor structure includes: a substrate, a control electrode disposed on the substrate, a planarization layer at least covering the side surface of the control electrode, a gate insulating layer covering the control electrode and the planarization layer, an active layer disposed on a side of the gate insulating layer away from the substrate, a first electrode and a second electrode disposed on a side of the gate insulating layer away from the substrate and in electrical contact with the active layer, wherein a positive projection of the active layer on the substrate does not overlap with a positive projection of the planarization layer on the substrate.

[0006] In some embodiments, the control electrode is light-shielding, the substrate is light-transmissive, and the material of the planarization layer includes a negative photoresist.

[0007] In some embodiments, the thickness of the planarization layer is greater than the thickness of the control electrode.

[0008] In some embodiments, the difference between the thickness of the planarization layer and the thickness of the control electrode is in the range of 0.1 μm to 2 μm.

[0009] The present disclosure adopts the following technical solutions: A display substrate includes the foregoing transistor structure.

[0010] In some embodiments, the display substrate further includes: a first trace disposed on the same layer as the control electrode, the planarization layer further at least covering the side surface of the first trace, and the planarization layer is provided with a vacancy at least in a partial area of the top surface of the first trace.

[0011] In some embodiments, the display substrate includes: a liquid crystal display substrate, a light-emitting diode display substrate or an electronic paper display substrate.

[0012] The present disclosure adopts the following technical solutions: A method for manufacturing a display substrate, comprising:

[0013] Forming a control electrode on a substrate;

[0014] Forming a planarization layer;

[0015] Patterning the planarization layer to remove at least a part of the planarization layer at a partial region on the top surface of the control electrode, and retaining at least a part of the planarization layer on the side surface of the control electrode;

[0016] Forming a gate insulating layer covering the planarization layer and the control electrode;

[0017] Forming an active layer on the gate insulating layer, wherein a positive projection of the active layer on the substrate does not overlap with a positive projection of the planarization layer on the substrate;

[0018] Forming a first electrode and a second electrode electrically connected to the active layer.

[0019] In some embodiments, the control electrode is light-shielding, the substrate is light-transmissive, the material of the planarization layer includes a negative photoresist, and in the step of patterning the planarization layer, the control electrode is used as a mask, and exposure is performed from one side of the substrate towards the planarization layer.

[0020] In some embodiments,

[0021] In the step of forming the control electrode on the substrate, a first trace arranged in the same layer as the control electrode is further formed on the substrate;

[0022] When performing exposure from one side of the substrate towards the planarization layer, the first trace is further used as a mask.

[0023] The present disclosure adopts the following technical solutions: A display device, comprising: the aforementioned display substrate or a display substrate obtained according to the aforementioned manufacturing method. Description of the Drawings

[0024] Figure 1 is a schematic structural diagram of a transistor structure provided by an embodiment of the present disclosure.

[0025] Figure 2 is a schematic structural diagram of a partial trace of a display substrate provided by an embodiment of the present disclosure.

[0026] Figure 3 is a schematic flow diagram of a method for manufacturing a display substrate provided by an embodiment of the present disclosure.

[0027] Figure 4a and Figure 4bThey are respectively schematic structural diagrams of a wiring region and a transistor region of a display substrate provided by an embodiment of the present disclosure in a first stage of preparation.

[0028] Figure 5a and Figure 5b They are respectively schematic structural diagrams of a wiring region and a transistor region of a display substrate provided by an embodiment of the present disclosure in a second stage of preparation.

[0029] Figure 6a and Figure 6b They are respectively schematic structural diagrams of a wiring region and a transistor region of a display substrate provided by an embodiment of the present disclosure in a third stage of preparation.

[0030] Figure 7a and Figure 7b They are respectively schematic structural diagrams of a wiring region and a transistor region of a display substrate provided by an embodiment of the present disclosure in a fourth stage of preparation.

[0031] Figure 8a and Figure 8b They are respectively schematic structural diagrams of a wiring region and a transistor region of a display substrate provided by an embodiment of the present disclosure in a fifth stage of preparation.

[0032] Wherein the reference numerals are as follows: 1, substrate; 21, control electrode; 22, first wiring; 3, planarization layer; 4, gate insulating layer; 5, active layer; 61, first electrode; 62, second electrode; 63, second wiring. Detailed Embodiments

[0033] The present disclosure will be further described below in conjunction with the embodiments shown in the drawings.

[0034] In a transistor structure in the related art, a gate insulating layer is provided on a gate, and an active layer and source-drain electrodes are provided on the gate insulating layer. The side surface of the gate is an inclined surface relative to the substrate where the transistor is located, and the thickness of the gate insulating layer on the side surface of the gate is relatively thin. The pattern of the gate is formed by an etching process, which results in the side surface of the gate being uneven and prone to generating tips. In a high-temperature and high-humidity environment, the tips on the side surface of the gate are easily oxidized and grown to penetrate the relatively thin gate insulating layer, thereby causing a short circuit between the gate and the source-drain electrodes.

[0035] For a display substrate with a high pixel density and a high refresh rate, in order to reduce the resistance of the electrodes and the wiring, the electrodes and the wiring adopt a relatively thick metal layer (the material is, for example, copper). The side surfaces of the electrodes and the wiring are higher and occupy a larger area of the substrate, and it is easier to generate the defect of a short circuit between the gate and the source-drain electrodes.

[0036] In the present disclosure, the gate is referred to as a control electrode, one of the source-drain electrodes is referred to as a first electrode, and the other of the source-drain electrodes is referred to as a second electrode.

[0037] ReferenceFigure 1 , embodiments of the present disclosure provide a transistor structure, including: a substrate 1, a control electrode 21 disposed on the substrate 1, a planarization layer 3 covering at least the side surface of the control electrode 21, a gate insulating layer 4 covering the control electrode 21 and the planarization layer 3, an active layer 5 disposed on the side of the gate insulating layer 4 away from the substrate 1, a first electrode 61 and a second electrode 62 disposed on the side of the gate insulating layer 4 away from the substrate 1 and in electrical contact with the active layer 5, wherein the orthographic projection of the active layer 5 on the substrate 1 does not overlap with the orthographic projection of the planarization layer 3 on the substrate 1.

[0038] The top surface of the control electrode 21 refers to the surface on the side of the control electrode 21 away from the substrate 1. The surface of the control electrode 21 close to the substrate 1 is called the bottom surface of the control electrode 21. The surface connecting the top surface and the bottom surface of the control electrode 21 is called the side surface of the control electrode 21.

[0039] The planarization layer 3 makes the gate insulating layer 4 parallel or approximately parallel to the substrate 1, the thickness of the gate insulating layer 4 is relatively uniform, the distance between the first electrode 61 of the transistor and the side surface of the control electrode 21 is larger, and the distance between the second electrode 62 of the transistor and the side surface of the control electrode 21 is larger. The tip on the side surface of the control electrode 21 is difficult to penetrate the planarization layer 3 and the gate insulating layer 4, thereby effectively reducing the short - circuit risk between the control electrode 21 and the first electrode 61 and the second electrode 62, and improving the yield and reliability of the product.

[0040] In some embodiments, the control electrode 21 blocks light, the substrate 1 is light - transmissive, and the material of the planarization layer 3 includes negative photoresist. After exposure of the negative photoresist, the unexposed part of the negative photoresist is removed in the subsequent development process, and the exposed part of the negative photoresist is retained in the subsequent development process. Since the control electrode 21 blocks light, the control electrode 21 can be used as a mask for exposure. Due to the diffraction of light in the negative photoresist and the continuous distribution of the intensity of the chemical reaction in the negative photoresist, by controlling the light intensity and exposure time of the exposure process, the negative photoresist above the side surface of the control electrode 21 can be retained in the subsequent development process. Thus, patterning of the planarization layer 3 can be achieved without increasing the number of mask plates.

[0041] In some other embodiments, the material of the planarization layer 3 includes positive photoresist. Then, an additional mask plate is required to pattern the planarization layer 3.

[0042] In some embodiments, refer to Figure 1 , the orthographic projection of the active layer 5 on the substrate 1 does not overlap with the orthographic projection of the planarization layer 3 on the substrate 1. This makes the surface of the active layer 5 (the area on the top surface of the control electrode 21 not covered by the planarization layer 3) a relatively flat surface.

[0043] In some embodiments, refer to Figure 1, the thickness of the planarization layer 3 is greater than the thickness of the control electrode 21. This can ensure that the planarization layer 3 completely covers the side surface of the control electrode 21.

[0044] In some embodiments, the difference between the thickness of the planarization layer 3 and the thickness of the control electrode 21 is in the range of 0.1 um to 2 um. In other embodiments, the difference between the thickness of the planarization layer 3 and the thickness of the control electrode 21 is in the range of 0.1 um to 1 um.

[0045] If the thickness of the planarization layer 3 is very close to the thickness of the control electrode 21, it cannot be guaranteed that the planarization layer 3 completely covers the side surface of the control electrode 21 after patterning. If the thickness of the planarization layer 3 exceeds the thickness of the control electrode 21 too much, it will increase the process difficulty and material consumption and increase the product thickness.

[0046] In some embodiments, the material of the planarization layer 3 includes: epoxy resin or polyimide. These materials can all be used as the materials of negative photoresist.

[0047] In some embodiments, the material of the substrate 1 includes: glass.

[0048] In other embodiments, the material of the substrate 1 includes: polyimide, polycarbonate, polyethersulfone, polyethylene terephthalate, polyethylene naphthalate or polyaryl compound. In these embodiments, the substrate 1 is flexible.

[0049] In some embodiments, the material of the gate insulating layer 4 includes: oxide of silicon or nitride of silicon.

[0050] In some embodiments, the material of the active layer 5 includes: polysilicon, amorphous silicon or transparent semiconductor oxide such as indium zinc oxide (IGZO).

[0051] In some embodiments, the material of the control electrode 21 includes: metal elements such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), chromium (Cr) and tungsten (W) or metal alloys composed of these metal elements.

[0052] In some embodiments, the material of the first electrode 61 and the second electrode 62 includes: metal elements such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), chromium (Cr) and tungsten (W) or metal alloys composed of these metal elements.

[0053] Based on the same inventive concept as the foregoing embodiments, the embodiments of the present disclosure further provide a display substrate, including the foregoing transistor structure.

[0054] In some embodiments, in combination Figure 1 and Figure 2, the display substrate further includes: a first trace 22 disposed on the same layer as the control electrode 21, and the planarization layer 3 at least covers the side surface of the first trace 22, and the planarization layer 3 is provided with a vacancy at least in a partial area of the top surface of the first trace 22.

[0055] When the substrate 1 is light-transmissive and the first trace 22 is light-shielding, and the material of the planarization layer 3 includes a negative photoresist, the vacancy area of the planarization layer 3 on the top surface of the first trace 22 can be formed synchronously with the vacancy area of the planarization layer 3 on the top surface of the control electrode 21.

[0056] Specifically, when exposing the planarization layer 3 from one side of the substrate 1, the first trace 22 can be used as a mask, so that in the subsequent development step, the material of the planarization layer 3 on the top surface of the first trace 22 can be removed. By controlling the exposure time and intensity, the size of the area of the planarization layer 3 remaining on the top surface of the first trace 22 can be controlled.

[0057] In some embodiments, the first electrode 61 and the second electrode 62 are disposed on the same layer, and the display substrate further includes a second trace 63 disposed on the same layer as the first electrode 61 and the second electrode 62. If the second trace 63 has an overlapping area with the side surface of the first trace 22, then the risk of short circuit between the second trace 63 and the first trace 22 can also be reduced.

[0058] In the present disclosure, it is said that two structures are disposed on the same layer, which means that the two are formed by the same material layer, and it is not limited that the distances of the two from the substrate 1 are equal.

[0059] In some embodiments, the display substrate includes: a liquid crystal display substrate or a light-emitting diode display substrate. The light-emitting diode display substrate is, for example, an organic light-emitting diode (OLED) display substrate or a micro-light-emitting diode (Micro-LED or Mini-LED) display substrate. The chip size of the Mini-LED is between 100 μm and 200 μm. The size of the Micro-LED is smaller than that of the Mini-LED, usually between 1 μm and 100 μm. The present disclosure collectively refers to the above two types of light-emitting diodes as micro-light-emitting diodes.

[0060] Based on the same inventive concept as the foregoing embodiments, referring to Figure 3 , an embodiment of the present disclosure further provides a method for manufacturing a display substrate, including the following steps.

[0061] Step 101, referring to Figure 4b Form a control electrode 21 on the substrate 1;

[0062] In some embodiments, synchronously, referring to Figure 4a , form a first trace 22 on the substrate 1. The first trace 22 is disposed on the same layer as the control electrode 21.

[0063] Step 102: Form a planarization layer 3. For example, the planarization layer 3 is formed by a coating process.

[0064] Reference Figure 5b , the planarization layer 3 covers the control electrode 21. Also referring to Figure 5a , the planarization layer 3 covers the first trace 22.

[0065] Step 103: Pattern the planarization layer 3 to remove at least a part of the planarization layer 3 located at a partial area on the top surface of the control electrode 21, and retain at least a part of the planarization layer 3 located on the side surface of the control electrode 21.

[0066] The patterning process described in the present disclosure may include one or several of the processes such as coating photoresist, exposure, development, baking, etching, etc.

[0067] In some embodiments, referring to Figure 5a and Figure 5b , the first trace 22 and the control electrode 21 are light-shielding, the substrate 1 is light-transmissive, and the material of the planarization layer 3 includes negative photoresist. Figure 5a and Figure 5b The direction of the arrow in is the propagation direction of the light for exposure. Using the first trace 22 and the control electrode 21 as a mask, the planarization layer 3 is exposed from one side of the substrate 1. After development and baking treatments, referring to Figure 6a and Figure 6b , not only the negative photoresist material at a partial area on the top surface of the control electrode 21 is removed, but also the negative photoresist at a partial area on the top surface of the first trace 22 is removed.

[0068] Step 104: Referring to Figure 7b , form a gate insulating layer 4 covering the planarization layer 3 and the control electrode 21.

[0069] Referring to Figure 7a , in some embodiments, the gate insulating layer 4 also covers the top surface of the first trace 22.

[0070] Step 105: Referring to Figure 8b , form an active layer 5 on the gate insulating layer 4, wherein the orthographic projection of the active layer 5 on the substrate 1 does not overlap with the orthographic projection of the planarization layer 3 on the substrate 1.

[0071] Referring to Figure 8a , the material of the active layer 5 is removed at the wiring area, and no active layer 5 is provided on the second trace 63.

[0072] Step 106: Referring to Figure 1 , form a first electrode 61 and a second electrode 62 electrically connected to the active layer 5.

[0073] In some embodiments, in combination with Figure 1and Figure 2 The first electrode 61, the second electrode 62, and the second trace 63 are formed by one photolithography process on the same material layer.

[0074] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, including: the foregoing display substrate or the display substrate obtained by the foregoing manufacturing method.

[0075] A display device refers to any product or component having a display function. For example, the display device is a display panel, a display module, a mobile phone, a tablet computer, a monitor, a television, an in-vehicle display screen, a navigator, a ground display screen, an electronic billboard, etc.

[0076] The display type of the display device is, for example, liquid crystal display, light-emitting diode display, electronic paper display, etc. The present disclosure does not limit the display type of the display device.

[0077] Each embodiment in the present disclosure is described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments.

[0078] The protection scope of the present disclosure is not limited to the above embodiments. Obviously, those skilled in the art can make various changes and deformations to the present disclosure without departing from the scope and spirit of the present disclosure. If these changes and deformations belong to the scope of the claims of the present disclosure and their equivalent technologies, the intention of the present disclosure also includes these changes and deformations.

Claims

1. A transistor structure, characterized in that, Comprising: a substrate (1), a control electrode (21) disposed on the substrate (1), a planarization layer (3) covering at least the side surface of the control electrode (21), a gate insulating layer (4) covering the control electrode (21) and the planarization layer (3), an active layer (5) disposed on a side of the gate insulating layer (4) away from the substrate (1), a first electrode (61) and a second electrode (62) disposed on a side of the gate insulating layer (4) away from the substrate (1) and in electrical contact with the active layer (5), wherein a positive projection of the active layer (5) on the substrate (1) does not overlap with a positive projection of the planarization layer (3) on the substrate (1); the planarization layer (3) extends from the side surface of the control electrode (21) to a part of the surface of the control electrode (21) on the side away from the substrate (1); the thickness of the planarization layer (3) is greater than the thickness of the control electrode (21), and the difference between the thickness of the planarization layer (3) and the thickness of the control electrode (21) is in the range of 0.1 um to 2 um.

2. The transistor structure according to claim 1, wherein, The control electrode (21) shields light, the substrate (1) is light-transmissive, and the material of the planarization layer (3) includes a negative photoresist.

3. The transistor structure according to claim 1, wherein, A positive projection of the active layer (5) on the substrate (1) does not overlap with a positive projection of the planarization layer (3) on the substrate (1).

4. A display substrate, characterized in that, Comprising the transistor structure according to any one of claims 1 to 3.

5. The display substrate according to claim 4, characterized in that The display substrate further includes: a first trace (22) disposed on the same layer as the control electrode (21), the planarization layer (3) further covering at least the side surface of the first trace (22), and the planarization layer (3) is provided with a vacancy at least in a partial area of the top surface of the first trace (22).

6. The display substrate according to claim 4, wherein The display substrate includes: a liquid crystal display substrate, a light-emitting diode display substrate, or an electronic paper display substrate.

7. A method for preparing a display substrate, characterized in that, Comprising: forming a control electrode (21) on a substrate (1); forming a planarization layer (3); patterning the planarization layer (3) to remove at least a part of the planarization layer (3) in a partial area on the top surface of the control electrode (21) and retain at least a part of the planarization layer (3) on the side surface of the control electrode (21); the planarization layer (3) extends from the side surface of the control electrode (21) to a part of the surface of the control electrode (21) on the side away from the substrate (1); the thickness of the planarization layer (3) is greater than the thickness of the control electrode (21), and the difference between the thickness of the planarization layer (3) and the thickness of the control electrode (21) is in the range of 0.1 um to 2 um; forming a gate insulating layer (4) covering the planarization layer (3) and the control electrode (21); forming an active layer (5) on the gate insulating layer (4), wherein a positive projection of the active layer (5) on the substrate (1) does not overlap with a positive projection of the planarization layer (3) on the substrate (1); forming a first electrode (61) and a second electrode (62) electrically connected to the active layer (5).

8. The preparation method according to claim 7, characterized in that, The gate electrode (21) is light-shielding, the substrate (1) is light-transmissive, the planarizing material includes a negative photoresist, and in the step of patterning the planarization layer (3), the gate electrode (21) is used as a mask, and exposure is performed from one side of the substrate (1) toward the planarization layer (3).

9. The manufacturing method according to claim 8, wherein in the step of forming the gate electrode (21) on the substrate (1), a first trace (22) arranged on the same layer as the gate electrode (21) is further formed on the substrate (1); when performing exposure from one side of the substrate (1) toward the planarization layer (3), the first trace (22) is further used as a mask.

10. A display device, characterized in that, including: a display substrate according to any one of claims 4 to 6 or a display substrate obtained by the manufacturing method according to any one of claims 7 to 9.

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