Image sensor with dielectric relaxation correction circuit

Abstract

This application relates to image sensors with dielectric relaxation correction circuitry. Some image sensors include pixels with capacitors. The capacitors can be used to store charge in the imaging pixels prior to readout. The capacitors can be metal-insulator-metal (MIM) capacitors that are susceptible to dielectric relaxation. Dielectric relaxation can cause a lag in the signal on the capacitor, which affects the signal on the capacitor during sampling. The image sensor can include dielectric relaxation correction circuitry that corrects for dielectric relaxation using a linear relationship between voltage stress and lagged signal. The image sensor can include a shield pixel that operates using a similar timing scheme as the imaging pixels in the active array. Measured lagged signals from the shield pixel can be used to correct the imaging data.

Description

Technical Field

[0001] The present invention relates generally to imaging devices, and more specifically, to imaging sensors comprising pixels having capacitors. Background Technology

[0002] Image sensors are commonly used in electronic devices such as mobile phones, cameras, and computers to capture images. In a typical arrangement, an image sensor comprises an array of image pixels arranged in rows and columns. Circuitry can be coupled to each pixel column to read out image signals from the image pixels.

[0003] Each image pixel in the array includes a photodiode coupled to a floating diffusion region via a transfer gate. Each pixel receives incident photons (light) and converts them into an electrical signal. Column circuitry is coupled to each pixel column for reading out the pixel signal from the image pixel. Sometimes, image sensors are designed to provide images to electronic devices using the Joint Image Experts Group (JPEG) format.

[0004] Some image sensors include imaging pixels with capacitors. Capacitors can be susceptible to dielectric relaxation (hysteresis). Dielectric relaxation experienced by a capacitor can result in some charge remaining on the capacitor after discharge (e.g., a hysteresis signal). Hysteresis signals on capacitors can negatively impact the image quality of the image sensor.

[0005] Therefore, it is desirable to have an improved image sensor that can provide reduced artifacts from hysteresis signals. Summary of the Invention

[0006] According to one aspect of this application, an image sensor is provided, the image sensor comprising: an imaging pixel array exposed to incident light in a plurality of frames; and a shielding pixel shielding the incident light, wherein each of the imaging pixel and the shielding pixel includes a capacitor, and wherein the shielding pixel is configured to: obtain a hysteresis signal measurement by applying a first voltage stress of a first magnitude to the capacitor before a first integration time of a first frame; and obtain a reference measurement by applying a second voltage stress of the first magnitude to the capacitor after a first integration time of a second frame and before readout of the second frame.

[0007] According to another aspect of this application, an image sensor is provided, the image sensor comprising: an imaging pixel array exposed to incident light, wherein each imaging pixel includes a capacitor; a shielding pixel shielding the incident light and configured to generate a test signal; and a dielectric relaxation correction circuit configured to use the test signal to correct for hysteresis in raw pixel data from the imaging pixels caused by dielectric relaxation in the capacitors of the imaging pixels.

[0008] According to another aspect of this application, an image sensor is provided, the image sensor comprising: an imaging pixel array exposed to incident light, wherein the imaging pixel array generates raw pixel data; a shielding pixel shielding the incident light; a frame buffer configured to store the raw pixel data from the imaging pixel array; and a dielectric relaxation correction circuit configured to compensate for hysteresis caused by dielectric relaxation of the raw pixel data from the imaging pixel using the raw pixel data from the frame buffer and measurements from the shielding pixel. Attached Figure Description

[0009] Figure 1 This is a diagram of an illustrative electronic device with an image sensor according to one embodiment.

[0010] Figure 2 This is a diagram of an exemplary pixel array and associated readout circuitry for reading out image signals from an image sensor, according to one embodiment.

[0011] Figure 3 This is a circuit diagram of an exemplary imaging pixel with a storage capacitor according to one embodiment.

[0012] Figure 4A This is a graph showing the change of capacitor voltage over time according to one embodiment, illustrating how dielectric relaxation can result in a hysteresis signal on the capacitor after discharge.

[0013] Figure 4B It is based on an implementation plan. Figure 4A The RC model of a capacitor undergoing dielectric relaxation is described in the figure.

[0014] Figure 5A This is a graph illustrating the relationship between hysteresis signal and stress time in a capacitor, according to one embodiment.

[0015] Figure 5B This is a graph illustrating the relationship between hysteresis signal and voltage stress in a capacitor, according to one embodiment.

[0016] Figure 6 It is an illustration of imaging pixels (such as...) according to an implementation scheme Figure 3 How can the imaging pixels be used to measure the timing diagram of the hysteresis signal?

[0017] Figure 7 This is a timing diagram illustrating how steady-state hysteresis signals can be compensated in a frame with one exposure period, according to one implementation scheme.

[0018] Figure 8 This is a timing diagram illustrating how steady-state hysteresis signals can be compensated in frames with multiple exposure cycles, according to one implementation scheme.

[0019] Figure 9 This is a timing diagram illustrating how transient hysteresis signals can be compensated in frames with multiple exposure cycles, according to one implementation scheme.

[0020] Figure 10 This is a diagram of an exemplary image sensor according to one embodiment, the image sensor including an active pixel array, shielded pixels and dielectric relaxation correction circuitry.

[0021] Figure 11 This is a timing diagram illustrating exemplary operation for an active imaging pixel according to one embodiment.

[0022] Figure 12 This is a timing diagram illustrating exemplary operation of a masked pixel for measuring a hysteresis signal, according to one embodiment.

[0023] Figure 13 This is a timing diagram illustrating exemplary operation of a shielded pixel for measuring a reference signal, according to one embodiment.

[0024] Figure 14 This is an exemplary timing scheme shown according to one embodiment for pixels in normal operation, for obtaining hysteresis signal measurements, and for obtaining reference measurements.

[0025] Figure 15 This is a flowchart of exemplary method steps for operating an image sensor with dielectric relaxation compensation circuitry according to one embodiment. Detailed Implementation

[0026] Embodiments of the present invention relate to image sensors. Those skilled in the art will understand that exemplary embodiments of the invention can be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail to avoid unnecessarily obscuring embodiments of the invention.

[0027] Electronic devices such as digital cameras, computers, cellular phones, and other electronic devices may include image sensors that collect incoming light to capture images. Image sensors may include pixel arrays. Pixels in an image sensor may include photosensitive elements, such as photodiodes, that convert incoming light into image signals. Image sensors may have any number (e.g., hundreds or thousands or more) of pixels. Typical image sensors may, for example, have hundreds of thousands or millions of pixels (e.g., megapixels). Image sensors may include control circuitry (such as circuitry for manipulating the pixels) and readout circuitry for reading out image signals corresponding to the charges generated by the photosensitive elements.

[0028] Figure 1 This is a diagram illustrating an imaging and response system, which includes an imaging system that captures images using an image sensor. Figure 1 The system 100 may be an electronic device, such as a camera, cellular phone, video camera or other electronic device that captures digital image data, may be a vehicle safety system (e.g., an active braking system or other vehicle safety system), or may be a surveillance system.

[0029] like Figure 1 As shown, system 100 may include an imaging system (such as imaging system 10) and a host subsystem (such as host subsystem 20). Imaging system 10 may include camera module 12. Camera module 12 may include one or more image sensors 14 and one or more lenses.

[0030] Each image sensor in camera module 12 may be identical, or different types of image sensors may exist within a given image sensor array integrated circuit. During image capture operation, each lens can focus light onto its associated image sensor 14. Image sensor 14 may include photosensitive elements (i.e., pixels) that convert light into digital data. Image sensors may have any number (e.g., hundreds, thousands, millions, or more) of pixels. A typical image sensor may, for example, have millions of pixels (e.g., megapixels). For example, image sensor 14 may include bias circuitry (e.g., source follower load circuitry), sample-and-hold circuitry, correlated double sampling (CDS) circuitry, amplifier circuitry, analog-to-digital converter circuitry, data output circuitry, memory (e.g., buffer circuitry), addressing circuitry, etc.

[0031] Still image data and video image data from camera sensor 14 can be provided to image processing and data formatting circuitry 16 via path 28. Image processing and data formatting circuitry 16 can be used to perform image processing functions such as data formatting, adjusting white balance and exposure, implementing video image stabilization, face detection, etc. Image processing and data formatting circuitry 16 can also be used to compress raw camera image files as needed (e.g., compressing them to Joint Image Experts Group format, or JPEG for short). In a typical arrangement (sometimes referred to as a system-on-a-chip (SOC) arrangement), camera sensor 14 and image processing and data formatting circuitry 16 are implemented on a common semiconductor substrate (e.g., a common silicon image sensor integrated circuit die). If desired, camera sensor 14 and image processing circuitry 16 can be formed on separate semiconductor substrates. For example, camera sensor 14 and image processing circuitry 16 can be formed on separate, stacked substrates.

[0032] Imaging system 10 (e.g., image processing and data formatting circuitry 16) can transmit acquired image data to host subsystem 20 via path 18. Host subsystem 20 may include processing software for detecting objects in the image, detecting motion of objects between image frames, determining distances to objects in the image, filtering, or otherwise processing the images provided by imaging system 10.

[0033] If needed, system 100 can provide users with many advanced functions. For example, in a computer or advanced mobile phone, it can provide users with the ability to run user applications. To achieve these functions, the host subsystem 20 of system 100 may have input-output devices 22 (such as a keypad, input-output ports, joystick, and display) and storage and processing circuitry 24. Storage and processing circuitry 24 may include volatile and non-volatile memory (e.g., random access memory, flash memory, hard disk drive, solid-state drive, etc.). Storage and processing circuitry 24 may also include microprocessors, microcontrollers, digital signal processors, application-specific integrated circuits, etc.

[0034] Figure 2 It shows Figure 1 An example of the arrangement of camera module 12. For example... Figure 2 As shown, the camera module 12 includes an image sensor 14 and a control and processing circuit 44. The control and processing circuit 44 may correspond to... Figure 1The image sensor 14 includes image processing and data formatting circuitry 16. The image sensor 14 may include a pixel array, such as an array 32 of pixels 34 (sometimes referred to herein as image sensor pixels, imaging pixels, or image pixels 34), and may also include control circuitry 40 and 42. Control and processing circuitry 44 may be coupled to row control circuitry 40 and may be coupled to column control and readout circuitry 42 via data and control path 26. Row control circuitry 40 may receive row addresses from control and processing circuitry 44 and may supply corresponding row control signals (e.g., dual-conversion gain control signals, pixel reset control signals, charge transfer control signals, halo control signals, row selection control signals, or any other desired pixel control signals) to image pixels 34 via control path 36. Column control and readout circuitry 42 may be coupled to columns of pixel array 32 via one or more wires (e.g., column lines 38). Column lines 38 may be coupled to each column of image pixels 34 in image pixel array 32 (e.g., each column of pixels may be coupled to a corresponding column line 38). Column line 38 can be used to read image signals from image pixels 34 and to supply bias signals (e.g., bias current or bias voltage) to image pixels 34. During image pixel readout operation, row control circuitry 40 can be used to select pixel rows in image pixel array 32, and image data associated with image pixels 34 in that pixel row can be read on column line 38 by column control and readout circuitry 42.

[0035] The column control and readout circuit 42 may include column circuitry, such as a column amplifier for amplifying the signal read from array 32, a sample-and-hold circuit for sampling and storing the signal read from array 32, an analog-to-digital converter circuit for converting the read analog signal into a corresponding digital signal, and a column memory for storing the read signal and any other desired data. The column control and readout circuit 42 can output digital pixel values ​​to the control and processing circuit 44 via line 26.

[0036] Array 32 may have any number of rows and columns. Generally speaking, the size of array 32 and the number of rows and columns in array 32 will depend on the specific implementation of image sensor 14. Although rows and columns are generally described herein as horizontal and vertical respectively, rows and columns may refer to any grid-like structure (e.g., features described herein as rows may be arranged vertically, and features described herein as columns may be arranged horizontally).

[0037] Pixel array 32 may include a color filter array with multiple color filter elements, which allows a single image sensor to sample different colors of light. For example, image sensor pixels (such as image pixels in array 32) may include a color filter array that allows a single image sensor to sample red, green, and blue light (RGB) using corresponding red, green, and blue image sensor pixels arranged in a Bayer mosaic pattern. The Bayer mosaic pattern consists of repeating cells of 2×2 image pixels, where two green image pixels are diagonally opposite each other and adjacent to a red image pixel diagonally opposite a blue image pixel. In another suitable example, the green pixels in the Bayer pattern are replaced with broadband image pixels having broadband color filter elements (e.g., transparent color filter elements, yellow color filter elements, etc.). These examples are merely illustrative, and in general, color filter elements of any desired color and any desired pattern can be formed over any desired number of image pixels 34.

[0038] If desired, array 32 may be part of a stacked die arrangement in which pixels 34 of array 32 are partitioned between two or more stacked substrates. In such an arrangement, each pixel 34 in array 32 may be partitioned between two dies at any desired node within the pixel. For example, nodes (such as floating diffusion nodes) may be formed on both dies. Pixel circuitry, including a photodiode and circuitry coupled between the photodiode and the desired node (such as a floating diffusion node in this example), may be formed on the first die, and the remaining pixel circuitry may be formed on the second die. The desired node may be formed on (i.e., as part of) a coupling structure (such as a conductive pad, micropad, conductive interconnect, or conductive via) connecting the two dies. The coupling structure may have a first portion on the first die and a second portion on the second die before the two dies are bonded. The first and second dies may be bonded to each other such that the first portion and the second portion of the coupling structure are bonded together and electrically coupled. If desired, the first and second portions of the coupling structure may be compressed together. However, this is merely illustrative. If desired, any metal-to-metal bonding technique (such as soldering or welding) can be used to join the first and second portions of the coupling structure formed on the respective first and second dies together.

[0039] As described above, the desired node in the pixel circuit that is partitioned across the two dies can be a floating diffusion node. Alternatively, the desired node in the pixel circuit that is partitioned across the two dies can be a node between the floating diffusion region and the gate of the source follower transistor (i.e., the floating diffusion node can be formed on the first die on which a photodiode is formed, while the coupling structure can connect the floating diffusion node to the source follower transistor on the second die), a node between the floating diffusion region and the source-drain node of the transfer transistor (i.e., the floating diffusion node can be formed on the second die on which the photodiode is not located), a node between the source-drain node of the source follower transistor and the row select transistor, or any other desired node in the pixel circuit.

[0040] Generally, array 32, row control circuitry 40, column control and readout circuitry 42, and control and processing circuitry 44 can be partitioned between two or more stacked substrates. In one example, array 32 can be formed in a first substrate, and row control circuitry 40, column control and readout circuitry 42, and control and processing circuitry 44 can be formed in a second substrate. In another example, array 32 can be partitioned between a first substrate and a second substrate (using one of the pixel partitioning schemes described above), and row control circuitry 40, column control and readout circuitry 42, and control and processing circuitry 44 can be formed in a third substrate.

[0041] In some image sensors, one or more pixels 34 may include capacitors. For example, capacitors can be used to store charge in the imaging pixel before readout. Capacitors can be used to implement dual-conversion gain modes for the imaging pixel, increasing the dynamic range of the imaging pixel, etc.

[0042] There are many types of pixels that can contain capacitors. Figure 3 An exemplary example of a pixel with a capacitor is shown in the figure.

[0043] like Figure 3As shown, image pixel 34 includes a photosensitive element 102 (e.g., a photodiode). The photosensitive element 102 has a first terminal coupled to ground. A second terminal of the photosensitive element 102 is coupled to a transfer transistor 104. The transfer transistor 104 is coupled to a floating diffusion (FD) region 118. A reset transistor 106 may be coupled between the floating diffusion region 118 and a voltage source 124. The floating diffusion region 118 may be a doped semiconductor region (e.g., a region in a silicon substrate doped by ion implantation, impurity diffusion, or other doping processes). The floating diffusion region 118 has an associated capacitance. A gain selection transistor 108 has a first terminal coupled to the floating diffusion region 118 and a second terminal coupled to a dual-conversion gain capacitor 110 (sometimes referred to as a storage capacitor 110). The dual-conversion gain capacitor 110 may have a first plate 110-1 (sometimes referred to as an upper plate or top plate) coupled to the second terminal of the gain selection transistor. The dual-conversion gain capacitor 110 may have a second plate 110-2 (sometimes referred to as the lower plate or base plate) that receives the capacitor plate signal (DCG_BOT_PLATE) from the driver 122.

[0044] The source follower transistor 112 has a gate terminal coupled to a first terminal of the floating diffusion region 118 and the gain selection transistor 108. The source follower transistor 112 also has a first source-drain terminal coupled to a voltage source 120. Both voltage sources 120 and 124 can provide a supply voltage (V). AAPIX The power supply voltages at power supplies 120 and 124 may be the same or different. In this application, each transistor is illustrated as having three terminals: source, drain, and gate. The source and drain terminals of each transistor may vary depending on how the transistor is biased and the type of transistor used. For simplicity, the source and drain terminals are referred to herein as source-drain terminals or simply terminals. The second source-drain terminal of the source follower transistor 112 is coupled to the column output line 116 via the row select transistor 114.

[0045] The gate terminal of transfer transistor 104 receives the control signal TX. The gate terminal of gain selection transistor 108 receives the control signal DCG. The gate terminal of reset transistor 106 receives the control signal RST. The gate terminal of row selection transistor 114 receives the control signal RS. This can be controlled by a row control circuit (e.g., Figure 2 The line control circuit 40 in the middle controls the path (e.g., Figure 2 The control path 36 in the middle provides control signals TX, DCG, RST, RS. The driver 122 that provides the signal DCG_BOT_PLATE can be a row control circuit (e.g., Figure 2 This is part of the row control circuit 40. For example, each row may have a driver 122. The driver 122 can be controlled via a control path (such as... Figure 2 The control path 36) provides the signal DCG_BOT_PLATE.

[0046] Gain selection transistor 108 and dual conversion gain capacitor 110 can be used by pixel 34 to implement dual conversion gain modes. Specifically, pixel 34 can operate in both high and low conversion gain modes. If gain selection transistor 108 is disabled, pixel 34 will be placed in high conversion gain mode. If gain selection transistor 108 is enabled, pixel 34 will be placed in low conversion gain mode. When gain selection transistor 108 is on, dual conversion gain capacitor 110 can be switched to active mode to provide additional capacitance to floating diffusion region 118. This results in a lower conversion gain for pixel 34. When gain selection transistor 108 is off, the additional load on the capacitor is removed and the pixel returns to a relatively higher pixel conversion gain configuration.

[0047] Capacitors used in imaging pixels can be susceptible to dielectric relaxation. Imaging pixels may use metal-insulator-metal (MIM) capacitors. MIM capacitors are formed by two conductive (metal) plates separated by a dielectric material. These MIM capacitors can be susceptible to dielectric relaxation.

[0048] Figure 4A This is a graph showing the voltage versus time, illustrating the effect of dielectric relaxation on the capacitor. As shown, the capacitor can be stressed at voltage v0 during the stress time. The capacitor can then be discharged during the discharge time. During the discharge time, the capacitor can be reset to its reset voltage.

[0049] It can be used with such Figure 4B The first and second capacitors shown in parallel coupling (e.g., C) ∞ and C0-C ∞ The RC model is used to model dielectric relaxation. A resistor (R) can be coupled between the first and second capacitors in the RC model. When the stress time is long enough, C ∞ and C0-C ∞ All are fully charged to V0. When the capacitor discharges rapidly (e.g., as shown in Figure 4), C ∞ Can be fully discharged while C0-C ∞ No. During the float time, C0-C ∞ The remaining charge is redistributed across the two parts of the capacitor, and the voltage (V) f The signal reappears on the capacitor. The hysteresis signal opposes change. Therefore, the signal change at the capacitor is not as large as expected.

[0050] The magnitude of the hysteresis signal at the pixel output at any given time point depends on several variables. For example, the frame stress time (e.g., the length of the integration time), the frame float time (e.g., the duration the capacitor is in a floating state), the frame reset time (e.g., the duration the storage capacitor discharges during a reset operation), and voltage stress (e.g., the magnitude of the voltage difference across the capacitor plates) can all affect the magnitude of the hysteresis signal in the capacitor. Stress time, float time, reset time, and voltage stress are all independent variables affecting the hysteresis signal.

[0051] Due to the number of variables affecting the hysteresis signal, it can be difficult to universally correct the hysteresis signal during different operating conditions of the image sensor. In addition to having multiple independent variables affecting the hysteresis signal, some of these independent variables exhibit nonlinear responses. Figure 5A This is a graph of hysteresis signal versus stress-time (assuming float time, reset time, and voltage stress remain constant). As shown, the hysteresis signal (e.g., the amount of charge on a capacitor due to dielectric relaxation) has a logarithmic relationship with stress-time. The hysteresis signal can also have a nonlinear relationship with float time and reset time.

[0052] Figure 5B This is a graph showing the relationship between hysteresis and voltage stress. As shown, there is a linear relationship between the hysteresis and voltage stress. This linear relationship makes voltage stress a more readily available variable for determining the magnitude of the hysteresis.

[0053] Figure 6 This shows how it can be imaged pixels (e.g., Figure 3 A time-series diagram of the measurement of hysteresis signals in the imaging pixels. For example... Figure 6 As shown, between t1 and t2, stress can be applied to capacitor 110 by reducing DCG_BOT (sometimes called DCG_BOT_PLATE). Simultaneously, RST and DCG are high, causing transistors 106 and 108 to activate. The supply voltage V... AAPIX Therefore, it is applied to plate 110-1 of capacitor 110. This difference applies voltage stress to the capacitor.

[0054] When DCG_BOT increases (e.g., to V), AAPIXAt the same voltage, the stress time can end at t2. Therefore, the capacitor is discharged. At t3, the discharge time ends and RST decreases to disable the reset transistor 106. This disconnects capacitor plate 110-1 from the supply voltage, meaning capacitor 110 remains floating during the float time. At the end of the float time, a double-sample readout can be performed to read the charge held on the capacitor due to dielectric relaxation hysteresis. A hysteresis signal sample is read out at t4. Subsequently, the float diffusion region is reset, and the reset signal is also sampled. The difference between the hysteresis signal sample and the reset signal can be equal to the magnitude of the hysteresis signal on the capacitor.

[0055] It should be noted that in this example, the TX signal is low throughout the hysteresis measurement (to prevent charge from photodiode 102 from being included in the measurement). An optional anti-corona transistor controlled by signal AB (e.g., directly coupled to the power supply voltage of the photodiode) can be active throughout the hysteresis measurement to prevent charge buildup and overflow from photodiode 102.

[0056] Hysteresis compensation can be used to compensate for steady-state and / or transient effects. In the steady-state case, it is assumed that the current image is equal to the previous image. In other words, it is assumed that the image does not change from frame to frame. Under this assumption, hysteresis compensation can be performed without any additional memory. However, the assumption that the image does not change between frames may not always be correct.

[0057] To compensate for transient effects (where consecutive image frames are not necessarily identical), memory (e.g., a frame buffer) can be included in the image sensor to store previous frames. When correcting a given frame, information about previous frames can be accessed from the frame buffer to compensate for hysteresis in the given frame.

[0058] Figure 7 This is a timing diagram illustrating examples of how hysteresis signals can be corrected under steady-state and single-exposure conditions. (Example) Figure 7 As shown, the first frame occurs between t1 and t3, the second frame occurs between t3 and t5, and the third frame occurs between t5 and t7. Each frame may include an integration time T. int1 (For example, in) Figure 7 The integration time (between t1 and t2) and non-integration time (e.g., between t2 and t3) during which the pixel can remain in a reset (discharge) state. During the integration time, charge accumulates in the photodiode. Charge can overflow from the photodiode to the capacitor in the pixel (e.g., ...). Figure 3 On 110), thus generating the stress time T of the capacitor. STRESS The pixel is read out at the end of the integration time. Subsequently, the capacitor can be discharged during non-integration periods (e.g., between t2 and t3 for frame 1, between t4 and t5 for frame 2, etc.).

[0059] Therefore, each integration time is used as the stress time for all subsequent integration times and the float time for all previous integration times. The hysteresis signal can be mainly caused by a single previous frame, but multiple previous frames can be considered during compensation if needed.

[0060] Therefore, the stress induced during the integration time of frame 1 can cause a hysteresis signal in the frame 1 readout and the frame 2 integration period (which will affect the frame 2 readout).

[0061] Because between the two integration times (e.g., in) Figure 7 Between t2 and t3, there exists a discharge time (during which charge is released), and the amount of charge absorbed in one integration time is greater than the amount of charge released again in the next integration time. This results in T INT1 The gain decreases.

[0062] In some cases, imaging pixels can use multiple exposures (integration time) per frame. Figure 8 This is a timing diagram illustrating an example of how hysteresis signals can be corrected under steady-state and multiple-exposure conditions. (Example) Figure 8 As shown, the first frame occurs between t1 and t2, the second frame occurs between t2 and t3, and the third frame occurs between t3 and t4. During each frame, there is a first integration time Tint1 and a second integration time Tint2. A first readout for the first integration time may occur between the first integration time and the second integration time. A second readout for the second integration time may occur after the second integration time.

[0063] like Figure 8 As shown, the integration time of frame 1 is used as the stress time. The subsequent non-integration time is used as the first discharge time T. DISCHARGE1 The second integral time is used as the first floating time T. FLOAT1 The subsequent non-integral time is used as the second discharge time T. DISCHARGE2 And the integration time of frame 2 is used as the second floating time T. FLOAT2 Therefore, T from frame 1 INT1 The resulting hysteresis signal will cause frame 1 to be read out and the second frame 1 integration period T to be interrupted. INT2 (This will affect the second frame 1 readout) and the first frame 2 integration period T. INT1 (This will affect the hysteresis signal in the first frame 2 readout).

[0064] Because between two integration times (e.g., at T) INT1 With T INT2 There exists a discharge time (during which charge is released) between these two integral times, and the amount of charge that can be absorbed in one integral time is greater than the amount of charge released again in the next integral time. This results in T INT1The gain decreases. Meanwhile, at T... INT2 The charge released in a medium is usually greater than the charge absorbed, therefore T INT2 The gain increases.

[0065] Figure 9 This is a timing diagram illustrating an example of how hysteresis signals can be corrected in transient and multiple exposure conditions. As shown in the figure, the first integration time T... INT1 The stress time can cause a hysteresis signal in all future integration times. The transient effects of the hysteresis signal can be compensated for by storing data about the image frame in memory (e.g., a frame buffer).

[0066] Compensating for transient effects can mitigate ghosting from image sensors. An example of ghosting occurring when a brightly lit frame is followed by a dark frame. In the dark frame, remnants of the previous brightly lit frame (e.g., the ghosting) are visible.

[0067] Figure 10 This is a diagram of an exemplary image sensor including a dielectric relaxation correction circuit. The dielectric relaxation correction circuit can correct dielectric relaxation using the linear relationship between voltage stress and hysteresis signal. Specifically, the image sensor may include a shielded pixel that shields incident light. The DCG_BOT_PLATE signal can be used to apply a known voltage stress to the capacitor of the shielded pixel. Importantly, the shielded pixel can operate using the same (or similar) timing scheme as the imaging pixels in the active array. Therefore, the time-based variables affecting the hysteresis signal (stress time, reset time, float time) are the same for both the active imaging pixels and the shielded pixel. The only remaining variable is the voltage stress. By applying at least one known voltage stress to the shielded pixel and measuring the corresponding hysteresis signal, the linear relationship between the hysteresis signal and voltage stress can be determined by the dielectric relaxation correction circuit (for the current timing scheme). Since the timing schemes of the shielded pixel and the imaging pixel are the same, the identified (identified using the shielded pixel) hysteresis signal function can be applied to the active imaging pixels in the array. The hysteresis signal function can be used to correct the signal from the active imaging pixels used for dielectric relaxation. If it is necessary to update the pixel timing scheme, a new hysteresis signal function can be determined (using masked pixels that operate with the new timing scheme) and applied to the imaging pixels.

[0068] like Figure 10 As shown, in addition to the active pixel array 32, the image sensor 14 may also include shielded pixels 200. The shielded pixels 200 may have the same circuit design and structure as the active imaging pixels in array 32. For example, each shielded pixel and imaging pixel may have, for example, Figure 3The design is shown. However, the shielding pixel 200 (sometimes referred to as the optical black pixel) is covered with an opaque material that blocks the photodiode from receiving incident light. Any opaque material can be used to cover the shielding pixel (e.g., metal, black ink, etc.). The opaque material may have a transparency of less than 5%, less than 1%, less than 0.1%, less than 0.01%, etc.

[0069] During the test operation (sometimes referred to as the calibration operation or hysteresis measurement operation), the shielded pixel 200 can be operated using a timing scheme similar to that of the imaging pixels in array 32. Specifically, the stress time, float time, and reset time of pixel 200 and pixel 32 can be the same or similar (e.g., within 3 times, within 2 times, within 50%, within 20%, within 10%, within 5%, within 1%, etc.).

[0070] For pixel 32, during the stress time (integration time), the charge generated by the photodiode in the pixel in response to incident light can be stored on the storage capacitor. For shielded pixel 200, during the stress time, DCG_BOT_PLATE can be adjusted to intentionally apply a known voltage stress to the storage capacitor. Since the pixel is shielded, the incident light level does not affect the test signal from shielded pixel 200. Therefore, the sampled test signal serves as an independent measure of the hysteresis signal associated with the current operating conditions of the image sensor (e.g., voltage stress, stress time, float time, and reset time).

[0071] The dielectric relaxation correction circuit 204 (sometimes referred to as correction circuit 204, hysteresis correction circuit 204, processing circuit 204, etc.) can receive test signals from the shielded pixel 200. A linear relationship exists between the hysteresis signal and the voltage stress, while the stress time, float time, and reset time are constant. The test signal can be used to determine a representative hysteresis signal for a given applied voltage stress value. The magnitude of the hysteresis signal and the voltage stress value can be used as data points in the voltage stress versus hysteresis signal function (slope). Since it is assumed that the relationship between voltage stress and hysteresis signal is linear, and that the hysteresis signal is approximately 0 in the absence of applied voltage stress, the obtained data points (combined with (0,0) data points) can be used to determine the hysteresis signal versus voltage stress function.

[0072] This example is merely illustrative. If needed, multiple hysteresis signal and voltage stress data points can be obtained using masked pixels (e.g., using the same one or more pixels sequentially, using different groups of one or more pixels simultaneously for different conditions, etc.). Even if the hysteresis signal and voltage stress relationship is linear, multiple data points can be used to compensate for any offset. In the case of a nonlinear hysteresis signal and voltage stress relationship, multiple data points can be used to approximate the hysteresis signal and voltage stress function. Samples from one or more masked pixels can be averaged to obtain any given hysteresis signal and voltage stress data points.

[0073] Simultaneously, pixel data from the active pixel array 32 is acquired (e.g., stress time, float time, and reset / discharge time conditions used to generate test signals using shielded pixels 200). The pixel data is provided to the dielectric relaxation (DR) correction circuit 204. The DR correction circuit 204 can correct the dielectric relaxation of the original pixel data using the hysteresis signal identified by the test signal and the voltage stress function, and outputs the corrected pixel data.

[0074] The dielectric relaxation correction circuit may optionally include a frame buffer 206. If the frame buffer is not included, the dielectric relaxation correction circuit can correct for steady-state effects of dielectric relaxation. If the frame buffer is included, the dielectric relaxation correction circuit can correct for transient effects of dielectric relaxation.

[0075] Without a frame buffer, the dielectric relaxation correction circuit 204 assumes that the amount of sampled charge from a given integration period is the same as the charge from the previous frame. The assumed value of the charge from the previous frame is then used to determine the amount of hysteresis present in the pixel signal.

[0076] With a frame buffer, dielectric relaxation correction circuit 204 uses the actual amount of charge from the previous frame to determine the amount of hysteresis present in the pixel signal.

[0077] Figures 11 to 13 It is shown Figure 10 The timing diagram shows the operations of active pixels and masked pixels. Specifically, Figure 11 The operation of active pixels in an image sensor is illustrated. Figure 12 The operation of masking pixels during the measurement of hysteresis signals is shown. Figure 13 The operation of masking pixels during reference measurement is shown.

[0078] Figure 11 An exemplary method is shown that uses active pixels in a multi-exposure operation (e.g., a first integration time T1 and a second integration time T2, similar to...). Figure 8 and Figure 9(As shown). During T1 and T2, the TX and DCG signals can be kept at intermediate levels to allow charge to overflow from the photodiode into the floating diffusion region and storage capacitor 110. Figure 11 An example with two readouts is shown. First, there is a high conversion gain correlated double sampling (e.g., PD 4T HCG readout). Next, there is a low conversion gain double sampling (e.g., overflow + PD 3T LCG readout). After the second integration time T2, there is an additional low conversion gain double sampling (e.g., overflow + PD 3T LCG readout). The signal on the capacitor (sampled during overflow + PD 3T LCG readout) will experience hysteresis.

[0079] Figure 12 An example of measuring hysteresis signals by masking pixels is shown. As illustrated, DCG_BOT can be modulated to... Figure 12 Charge injection at point 210 injects charge onto the capacitor. Charge injection can occur during the shutter phase of the frame (e.g., at the falling edge of the reset signal RST). The signal prompted by this charge injection can remain on the capacitor during the integration time until it is read out (e.g., at the moment of induction). Figure 12 During the readout period (214), the signal on the capacitor experiences a lag. The equivalent integration time T1 can be approximately equal to (duration). Figure 11 The T1 integration time is shown. The equivalent T1 integration time can be within 20%, 10%, 5%, or 1% of the T1 integration time, etc. The impact of lag on the T2 integration period can be determined based on the T2 reading. For transient cases, it can also be determined by... Figure 12 The effect of hysteresis on the T1 integration time of the next frame is determined by the subsequent frames with normal operation after the frame with charge injection.

[0080] Figure 13 An example of measuring a reference signal by masking pixels is shown. As shown, DCG_BOT can be modulated to... Figure 13 Charge injection at point 212 injects charge onto the capacitor. This charge injection can occur precisely before readout at point 214 to minimize hysteresis in the sampled signal. It can be assumed that the signal originates from... Figure 13 The samples are 'hysteresis-free' data points used for the charge injection values ​​employed. This can be obtained from using... Figure 12 The measurement of the "no hysteresis" data point is subtracted from the hysteresis signal identified by the operation. The difference between these two values ​​can be a measurement of the contribution of the hysteresis signal (which is associated with the magnitude of the voltage stress caused by charge injection 210 / 212). Charge injection 210 / 212 can have the same magnitude (e.g., causing the same magnitude of voltage stress) to ensure comparison under the same operating conditions.

[0081] Figure 14 This is a summary of the operation of active and masked pixels in an image sensor. As shown in the figure, during normal operation (e.g., active pixels), each given frame (N) has a shutter speed of T1 (first integration time), an integration time of T1, and a readout of T1. Then, there is a shutter speed of T2 (second integration time), an integration time of T2, and a readout of T2.

[0082] To obtain a measurement of the hysteresis signal, a signal charge is injected during shutter speed T1. Then there is an equivalent integration time T1, followed by a readout T1. Then there is a shutter speed T2 (second integration time), an integration time T2, and a readout T2, similar to normal operation. This measurement operation allows for the hysteresis caused by the signal charge injected during the shutter speed T1 to be measured.

[0083] If necessary, charge injection at the N T1 shutter speed during measurement ( Figure 14 As shown in the diagram, additional frames (N+1) may be included in the case of the impact on the N+1T1 readout and T2 readout. This can be used to correct transient hysteresis when a frame buffer is included in the sensor.

[0084] To obtain a reference measurement for the hysteresis signal, a signal charge is injected before the T1 readout. Then, there is a T2 (second integration time) shutter, a T2 integration time, and a T2 readout, similar to normal operation. This reference measurement operation allows for a hysteresis-free signal associated with the injected signal charge of the same magnitude as the measurand.

[0085] Figure 15 A flowchart is shown illustrating an exemplary method of operating an image sensor using shielded pixels and dielectric relaxation compensation circuitry. First, at step 302, the shielded pixels (e.g., Figure 10 Pixel 200 in the image can be used to obtain one or more hysteresis measurements and one or more reference measurements. One or more hysteresis measurements (such as...) can be obtained by injecting a signal onto a capacitor before the first integration time. Figure 12 As shown). One or more reference measurements (such as) can be obtained by injecting a signal onto a capacitor before reading. Figure 13 (As shown).

[0086] The stress signal applied during the measurement in step 302 can be a fixed charge sampled on the capacitor, a constant voltage on the capacitor, a variable voltage on the capacitor, or a constant current in the capacitor.

[0087] Next, at step 304, the difference between the hysteresis measurement and the reference measurement can be used to quantify the effect of the hysteresis signal from the first integration cycle on subsequent integration cycles. The measurement obtained from the masked pixel in step 302 can be used to determine the voltage stress versus hysteresis signal function (e.g., a linear function).

[0088] At step 306, the active imaging pixels in pixel array 32 can be used to acquire pixel data (e.g., a frame of pixel data for a given scene). Optionally, the pixel data may be stored in memory (e.g., a frame buffer) at step 308. Including additional memory allows for more accurate hysteresis correction (e.g., considering not only steady-state effects but also transient effects).

[0089] Finally, at step 310, the dielectric relaxation compensation circuit 204 can compensate for the hysteresis of the original pixel data. Different options exist for compensating for the hysteresis of the original pixel data. In one example, individual readouts (e.g., readouts associated with each integration time) can be compensated based on the hysteresis signal identified by the determined hysteresis signal and the voltage stress function (e.g., compensating a given frame using only pixel data from a given frame). In another example (e.g., in the case of including a frame buffer), the T1 signal from a previous image can be used as the basis for hysteresis signal compensation (e.g., compensating a given frame using pixel data from one or more previous frames).

[0090] It should be understood that the examples of pixel structures and timing diagrams shown in this article are merely illustrative. Generally, the aforementioned techniques for measuring hysteresis signals using masked pixels, determining the relationship between hysteresis signals and voltage stress, and correcting pixel data for hysteresis signals can be applied to any pixel that has capacitors and is therefore susceptible to hysteresis signals.

[0091] For example, Figure 3 The source of the reset transistor in the circuit can be connected to a different node than FD.

[0092] Some imaging pixels can use multiple integration times and readout operations within a single frame. For example, after a first integration time and corresponding readout, an imaging pixel can have a second, shorter integration time and corresponding readout (similar to...). Figures 11 to 13 (As shown). Having multiple integration times and / or readouts in this manner can increase the dynamic range in the imaging pixels. In these types of pixels, each readout may have a corresponding hysteresis signal. The techniques described herein can be used to determine the relationship between the hysteresis signal of any (or all) readouts and voltage stress and to correct the pixel data accordingly.

[0093] Implementation schemes for compensating for hysteresis in image sensors can be applied to either rolling shutter image sensors or global shutter image sensors, and are applicable to both overflow capacitors and storage capacitors.

[0094] According to one embodiment, the image sensor may include an array of imaging pixels exposed to incident light in multiple frames and shielding pixels shielding the incident light. Each of the imaging pixels and the shielding pixels may include a capacitor, and the shielding pixels may be configured to obtain a hysteresis signal measurement by applying a first voltage stress of a first magnitude to the capacitor before a first integration time in a first frame, and to obtain a reference measurement by applying a second voltage stress of the first magnitude to the capacitor after a first integration time in a second frame and before readout of the second frame.

[0095] According to another embodiment, the image sensor may also include a dielectric relaxation correction circuit configured to compensate for raw pixel data from the imaging pixel array using hysteresis signal measurements and reference measurements.

[0096] According to another embodiment, the image sensor may also include a memory. Raw pixel data may be configured to be stored in the memory.

[0097] According to another embodiment, the dielectric relaxation correction circuit can be configured to compensate for the original pixel data of a given frame using hysteresis signal measurements, reference measurements, and original pixel data of previous frames stored in memory.

[0098] According to another embodiment, the image sensor may also include a frame buffer. The dielectric relaxation correction circuitry may be configured to use raw pixel data from at least one previous frame when compensating for the raw pixel data of a given frame.

[0099] According to another embodiment, applying the first voltage stress may include applying the first voltage stress during the shutter cycle.

[0100] According to another embodiment, each capacitor may have a first capacitor plate, and applying a first voltage stress to the capacitor may include adjusting the voltage supplied to the first capacitor plate.

[0101] According to another implementation, the readout of the second frame can be the readout of the charge on the capacitor.

[0102] According to one embodiment, the image sensor may include an array of imaging pixels exposed to incident light, each imaging pixel including a capacitor; a shielding pixel that shields the incident light and is configured to generate a test signal; and a dielectric relaxation correction circuit configured to use the test signal to correct for hysteresis in the raw pixel data from the imaging pixels caused by dielectric relaxation in the capacitor of the imaging pixels.

[0103] According to another implementation, the dielectric relaxation correction circuit can be configured to use a test signal to determine the relationship between hysteresis and voltage stress.

[0104] According to another implementation, each of the shielded pixels may have a corresponding capacitor, wherein the corresponding base plate is coupled to the driver.

[0105] According to another embodiment, the imaging pixel array can be operated using a first timing scheme that includes stress time, float time, and reset time, and the shielding pixels can be operated using a second timing scheme that also includes stress time, float time, and reset time.

[0106] According to another embodiment, the imaging pixel array can operate during the integral time of the first duration, the shielded pixel can generate a test signal, and voltage stress is applied to the capacitor in each shielded pixel during the stress time, and the stress time can have a second duration.

[0107] According to another implementation, the second duration may be the same as the first duration.

[0108] According to another implementation, the second duration can be up to three times the first duration.

[0109] According to another implementation, each shielded pixel may have the same component arrangement as the imaging pixel array.

[0110] According to one embodiment, the image sensor may include an imaging pixel array exposed to incident light and generating raw pixel data, a shielding pixel shielding the incident light, a frame buffer configured to store the raw pixel data from the imaging pixel array, and a dielectric relaxation correction circuit configured to compensate for hysteresis caused by dielectric relaxation of the raw pixel data from the imaging pixel using the raw pixel data from the frame buffer and measurements from the shielding pixel.

[0111] According to another implementation, the dielectric relaxation correction circuit can be configured to use measurements from the shielded pixel to determine the linear relationship between hysteresis and voltage stress.

[0112] According to another implementation, each of the shielded pixels may have the same component arrangement as the imaging pixel array.

[0113] According to another implementation, each imaging pixel and each shielding pixel may include a capacitor.

[0114] The foregoing description is merely an illustrative illustration of the principles of the present invention, and those skilled in the art can make various modifications. The above embodiments can be implemented individually or in any combination.

Claims

1. An image sensor, the image sensor comprising: An imaging pixel array, which is exposed to incident light in multiple frames; A shielding pixel that shields the incident light, wherein each of the imaging pixel and the shielding pixel includes a capacitor, and wherein the shielding pixel is configured to: The hysteresis signal measurement value is obtained by applying a first voltage stress of a first magnitude to the capacitor before the first integration time of the first frame. as well as A reference measurement value is obtained by applying a second voltage stress of the first magnitude to the capacitor after the first integration time of the second frame and before the readout of the second frame.

2. The image sensor according to claim 1, further comprising: A dielectric relaxation correction circuit is configured to use the hysteresis signal measurement and the reference measurement to compensate for the raw pixel data from the imaging pixel array.

3. The image sensor according to claim 2, further comprising: The memory, wherein the original pixel data is configured to be stored in the memory, and wherein the dielectric relaxation correction circuit is configured to compensate the original pixel data of a given frame using the hysteresis signal measurement, the reference measurement, and the original pixel data of a previous frame stored in the memory.

4. The image sensor according to claim 2, further comprising: A frame buffer, wherein the dielectric relaxation correction circuit is configured to use the original pixel data of at least one previous frame when compensating for the original pixel data of a given frame.

5. The image sensor of claim 1, wherein applying the first voltage stress comprises applying the first voltage stress during the shutter cycle.

6. The image sensor of claim 1, wherein each capacitor has a first capacitor plate, and wherein applying the first voltage stress to the capacitor includes adjusting the voltage supplied to the first capacitor plate.

7. The image sensor of claim 1, wherein the readout of the second frame is a readout of the charge on the capacitor.

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