Modular inversion hardware circuit and control method

Abstract

The application discloses a modulo inverse operation hardware circuit and a control method, relates to the field of information security, and is applied to modulo inverse operation and negative modulo inverse operation. The hardware circuit comprises an algorithm control module, which is used for acquiring an algorithm control signal, generating a calling instruction based on the algorithm control signal, and calling a basic operation module to perform corresponding modulo inverse operation and / or negative modulo inverse operation; and the basic operation module is used for performing corresponding basic operation according to the calling instruction. The application is a hardware circuit. The algorithm control module generates a calling instruction according to an algorithm control signal, the basic operation module performs corresponding operation according to the calling instruction, the operation speed of the hardware circuit is higher, the security is higher, and the security level and the operation speed of the modulo inverse operation and the negative modulo inverse operation are improved.

Description

Technical Field

[0001] This invention relates to the field of information security, and in particular to a hardware circuit and control method for modular inverse operation. Background Technology

[0002] Currently, with the rapid development of information security, public-key cryptography based on mathematical problems has been widely used. Elliptic Curve Cryptography (ECC) is widely used in mobile communications, e-commerce, and other fields due to its advantages such as short keys, high speed, high security, and resource saving.

[0003] Modular inverse operation of large numbers, as a type of modular arithmetic, is an indispensable operation in elliptic curve cryptography (ECC) of prime number fields. In ECC systems, point addition and doubling operations both require inversion operations. With the industrial upgrading of bank IC cards, contactless financial IC cards will gradually increase, and the application of high-security cryptographic systems is becoming increasingly urgent. Therefore, modular inverse algorithms for large numbers, which are simple to operate, small in size, and low in power consumption, have significant research significance and application value.

[0004] Meanwhile, elliptic curve cryptography algorithms using the Montgomery algorithm require pre-computing the negative modulus inverse N' of the modulus N with respect to the bit weights R. However, the SM2 asymmetric commercial cryptographic algorithm, due to its relatively low security requirements, uses a fixed modulus N, meaning the parameter N' is also a fixed value. Therefore, the parameter N' only needs to be calculated once. To avoid increasing hardware resource consumption, the parameter N' is generally calculated in software. This method is time-consuming, inefficient, and has low security.

[0005] Therefore, how to provide a solution to the above-mentioned technical problems is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0006] In view of this, the purpose of this invention is to provide a hardware circuit and control method for modular inverse operation, so as to ensure operation speed with low resource consumption. The specific solution is as follows:

[0007] A hardware circuit for modular inverse operation, comprising:

[0008] The algorithm control module is used to acquire algorithm control signals and, based on the algorithm control signals, generate a call instruction to call the basic operation module to perform corresponding modular inverse operations and / or negative modular inverse operations.

[0009] The basic operation module is used to perform corresponding basic operations according to the calling instruction.

[0010] Preferably, the algorithm control module includes:

[0011] The operation scheduling unit is used to acquire the algorithm control signal and send the algorithm control signal to the operation control unit;

[0012] The computation control unit is used to determine the computation control instruction according to the algorithm control signal and send the computation control instruction to the computation scheduling unit;

[0013] The operation scheduling unit is further configured to generate the call instruction according to the operation control instruction, so as to call the basic operation module to perform corresponding basic operations.

[0014] Preferably, the operation control unit is a state machine control unit, and the state machine control unit stores preset operation logic, which includes multiple operation states and the transition relationships between the operation states;

[0015] The state machine control unit is used to determine the operation control instruction based on the current operation state.

[0016] Preferably, the hardware circuit further includes:

[0017] A preset number of registers are used to store operation parameter values, which include operation input values, intermediate variable coefficients, and operation result values.

[0018] Preferably, the basic arithmetic module includes an addition circuit, a subtraction circuit, a left shift circuit, and a right shift circuit.

[0019] Accordingly, this application also discloses a modular inverse operation control method, which is applied to the modular inverse operation hardware circuit as described in any of the above claims, and the control method includes:

[0020] The algorithm control module acquires the algorithm control signal and generates a call instruction based on the algorithm control signal to call the basic operation module to perform the corresponding modular inverse operation and / or negative modular inverse operation; the algorithm control signal is a modular inverse operation signal or a negative modular inverse operation signal.

[0021] The basic operation module performs corresponding basic operations according to the calling instruction.

[0022] Preferably, the process of obtaining the algorithm control signal through the algorithm control module and generating a calling instruction based on the algorithm control signal includes:

[0023] The algorithm control signal is obtained by the operation scheduling unit and sent to the operation control unit;

[0024] The computation control unit determines the computation control instruction based on the algorithm control signal and sends the computation control instruction to the computation scheduling unit.

[0025] The operation scheduling unit generates a call instruction based on the operation control instruction to call the basic operation module to perform the corresponding basic operations.

[0026] Preferably, the process of determining the operation control instruction based on the algorithm control signal includes:

[0027] The operation control instructions are determined based on the current operation status and the preset operation logic;

[0028] The preset operation logic includes multiple operation states and the transition relationships between the multiple operation states.

[0029] Preferably, the modular inverse operation control method further includes:

[0030] When an operation instruction is received, the operation scheduling unit initializes and assigns values ​​to a preset number of registers.

[0031] Preferably, the plurality of operation states of the preset operation logic include S1 to S8, and the transition relationship between the plurality of operation states includes:

[0032] S1: Idle state; When the operation instruction is received, the preset number of registers are initialized; When the operation mode flag corresponds to the modulo inverse operation mode, jump to S2; When the operation mode flag corresponds to the negative modulo inverse operation mode, jump to S7.

[0033] S2: Determine whether the first operand is 1, an even number, or an odd number other than 1; if the first operand is 1, jump to S8; if the first operand is even, jump to S6; if the first operand is an odd number other than 1, jump to S3.

[0034] S3: Determine if the second operand is even; if the second operand is even, jump to S4; if the second operand is not even, jump to S5.

[0035] S4: Trigger the right shift circuit to control the second operand to shift right by one bit, and determine whether the intermediate variable is even. If not, trigger the addition circuit to sum the intermediate variable with a preset constant, and assign the current result of the addition circuit to the intermediate variable. Then trigger the right shift circuit to control the intermediate variable to shift right by one bit. If yes, trigger the right shift circuit to control the intermediate variable to shift right by one bit; jump to S3.

[0036] S5: Determine whether the first operand is greater than the second operand, determine whether the modular inverse result is greater than the intermediate variable, and determine whether the intermediate variable is greater than the modular inverse result;

[0037] If the first operand is greater than the second operand, and the modular inverse result is greater than the intermediate variable, then the subtraction circuit is triggered to calculate the difference between the first operand and the second operand, and the current result of the subtraction circuit is assigned to the first operand; the subtraction circuit is triggered to calculate the difference between the modular inverse result and the intermediate variable, and the current result of the subtraction circuit is assigned to the modular inverse result.

[0038] If the first operand is greater than the second operand, and the modular inverse result is not greater than the intermediate variable, then the subtraction circuit is triggered to calculate the difference between the first operand and the second operand, and the current result of the subtraction circuit is assigned to the first operand; the subtraction circuit is triggered to calculate the difference between the modular inverse result and the intermediate variable; the addition circuit is triggered to sum the preset constant and the current result of the subtraction circuit, and the current result of the addition circuit is assigned to the modular inverse result.

[0039] If the first operand is not greater than the second operand, and the intermediate variable is greater than the modular inverse result, then the subtraction circuit is triggered to calculate the difference between the second operand and the first operand, and the current result of the subtraction circuit is assigned to the second operand. The subtraction circuit is also triggered to calculate the difference between the intermediate variable and the modular inverse result, and the current result magnitude of the subtraction circuit is assigned to the intermediate variable.

[0040] If the first operand is not greater than the second operand, and the intermediate variable is not greater than the modular inverse result, then the subtraction circuit is triggered to calculate the difference between the second operand and the first operand, and the current result of the subtraction circuit is assigned to the second operand. The subtraction circuit is then triggered to calculate the difference between the intermediate variable and the modular inverse result. The addition circuit is then triggered to sum the current result of the subtraction circuit with the preset constant, and the current result of the addition circuit is assigned to the intermediate variable.

[0041] Jump to S2;

[0042] S6: Trigger the right shift circuit to control the first operand to shift right by one bit, and when the operation mode flag corresponds to the negative modulus inverse operation mode, trigger the left shift circuit to control the intermediate variable to shift left by one bit; jump to S7;

[0043] S7: Determine whether the modulo inverse result is even. If so, trigger the right shift circuit to shift the modulo inverse result one position to the right. If not, trigger the addition circuit to sum the modulo inverse result with the preset constant, and assign the current result of the addition circuit to the modulo inverse result. Then trigger the right shift circuit to shift the modulo inverse result one position to the right. When the operation mode flag corresponds to the negative modulo inverse operation mode, trigger the addition circuit to sum the negative modulo inverse result with the intermediate variable, and assign the current result of the addition circuit to the negative modulo inverse result. Jump to S2.

[0044] S8: The operation is complete. Output the corresponding modulo inverse result or the negative modulo inverse result according to the operation mode flag; jump to S1.

[0045] This application discloses a hardware circuit for modular inverse operation, comprising: an algorithm control module for acquiring algorithm control signals and generating a call instruction based on the algorithm control signals to call a basic operation module to perform corresponding modular inverse operations and / or negative modular inverse operations; and a basic operation module for performing corresponding basic operations according to the call instruction. This application is a hardware circuit, wherein the algorithm control module generates call instructions based on the algorithm control signals, and the basic operation module performs corresponding operations according to the call instructions. The hardware circuit offers faster operation speed and higher security, while simultaneously improving the security level and operation speed of modular inverse and negative modular inverse operations. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0047] Figure 1 This is a structural distribution diagram of a modular inverse operation hardware circuit in an embodiment of the present invention;

[0048] Figure 2 This is a flowchart illustrating the steps of a modular inverse operation control method in an embodiment of the present invention;

[0049] Figure 3 This is a diagram showing the transition relationships of the operation states in an embodiment of the present invention;

[0050] Figure 4 This is a diagram showing the transition relationships between sub-operation states in operation state S2 in this embodiment of the invention.

[0051] Figure 5 This is a diagram showing the transition relationships between sub-operation states in operation state S4 of this embodiment of the invention;

[0052] Figure 6 This is a diagram showing the transition relationships between sub-operation states in operation state S5 of this embodiment of the invention;

[0053] Figure 7 This is a diagram showing the transition relationships between sub-operation states in operation state S7 of this embodiment of the invention. Detailed Implementation

[0054] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0055] In the general SM2 cryptographic algorithm, the negative modulus inverse parameter N' only needs to be calculated once. To avoid increasing the consumption of hardware resources, the parameter N' is usually calculated in software. This method is time-consuming, inefficient, and has low security.

[0056] To address the aforementioned problems, this invention discloses a hardware circuit for modular inverse operation, see [link to relevant documentation]. Figure 1 As shown, it includes:

[0057] Algorithm control module 1 is used to acquire algorithm control signals and, based on the algorithm control signals, generate calling instructions to call basic operation module 2 to perform corresponding modular inverse operations and / or negative modular inverse operations;

[0058] Basic operation module 2 is used to perform corresponding basic operations according to the call instructions.

[0059] Specifically, to realize the multiplexing circuit for modular inverse and negative modular inverse, the modular inverse operation hardware circuit of this embodiment of the invention includes an algorithm control module 1. The algorithm control module 1 receives an algorithm control signal, which is either a modular inverse operation signal or a negative modular inverse operation signal. Based on the algorithm control signal, it generates a call instruction and calls the basic operation module 2 to perform the corresponding modular inverse operation and / or negative modular inverse operation according to the call instruction. The basic operation module 2 includes an addition circuit, a subtraction circuit, a left shift circuit, and a right shift circuit.

[0060] In some specific embodiments, the algorithm control module 1 includes:

[0061] The operation scheduling unit 11 is used to acquire the algorithm control signal and send the algorithm control signal to the operation control unit 12;

[0062] The arithmetic control unit 12 is used to determine the arithmetic control command based on the algorithm control signal and send the arithmetic control command to the arithmetic scheduling unit 11;

[0063] The operation scheduling unit 11 is also used to generate a call instruction based on the operation control instruction to call the basic operation module 2 to perform the corresponding basic operation.

[0064] It is understandable that the algorithm control module 1 includes an operation scheduling unit 11 and an operation control unit 12. Specifically, the algorithm control signal includes a modulo inverse operation signal or a negative modulo inverse operation signal. The operation control instruction is determined according to the algorithm control signal, including the specific operation process when implementing the corresponding modulo inverse operation or negative modulo inverse operation. The call instruction is generated according to the operation control instruction, thereby realizing the basic call to the basic operation module 2. The call instruction is the simplest and most basic circuit command, such as triggering the addition circuit to realize the summation of two parameters, or triggering the left shift circuit to realize the left shift of a parameter by one bit, etc.

[0065] The process from operation control instructions to call instructions includes instruction fragmentation and changes in instruction form. Specifically, operation control instructions include specific operation processes, mainly algorithms, and are program instructions that the operation scheduling unit 11 can understand. The logic and language of the program instructions can be relatively complex, while the object of the call instructions is any basic operation module. The call instructions decompose the complex specific operation processes into basic call elements, and the instruction form is simple and direct so that any basic operation module 2 can be directly called to perform basic operations.

[0066] Taking modular inverse operation as an example, the operation scheduling unit 11 receives the algorithm control signal as the modular inverse control signal. The operation control unit 12 generates the corresponding operation control instruction for the modular inverse operation based on the modular inverse control signal to determine the specific operation process, including several operation steps of the modular inverse operation. The operation control unit 12 sends the operation control instruction to the operation scheduling unit 11, so that the operation scheduling unit 11 generates a call instruction that can call the basic operation module 2.

[0067] In some specific embodiments, the arithmetic control unit 12 is a state machine control unit. The state machine control unit stores preset arithmetic logic, which includes multiple arithmetic states and transition relationships between these states. The state machine control unit is used to determine arithmetic control instructions based on the current arithmetic state. It is understood that the state machine control unit is the physical implementation of the state machine. A state machine is a mathematical model representing multiple arithmetic states and the transition behavior between them. In this embodiment, the state machine control unit includes a programmable logic device, and / or a programmable logic controller, and / or a trigger, and / or a relay. Furthermore, the hardware implementation requires registers to store state variables and the preset arithmetic logic. Therefore, in some specific embodiments, the hardware circuit also includes:

[0068] A preset number of registers (3) are used to store the operation parameter values, which include the operation input values, intermediate variable coefficients, and operation result values.

[0069] It is understandable that the operation parameter values ​​here are also the state variables. The operation input values ​​include the first operand q, the second operand r, and the operation mode flag, which corresponds to the algorithm control signal. The intermediate variable coefficients include the intermediate variable t and the preset constant n. The operation result values ​​include the modular inverse result s and the negative modular inverse result n'. The theoretical formula for the modular inverse operation is s = q mod n, where the first operand q is any integer. The theoretical formula for the negative modular inverse operation is n' = -n mod q, where the first operand is the bit weight 2. k Taking the modular inverse operation as an example, to calculate 7 mod 4, when using this embodiment for calculation, the first operand q = 7, the preset constant n = 4, and the second operand r and the intermediate variable t are continuously assigned values ​​and changed during the process, finally obtaining the modular inverse result s = 3.

[0070] It is understood that this embodiment can be applied to the Internet of Things (IoT) field. The basic operation module 2 is reused in the modular inverse operation and the negative modular inverse operation, which can not only meet the requirement of low resource consumption, but also improve the security level and operation speed of the security encryption chip.

[0071] The modular inverse operation hardware circuit provided in this application includes an algorithm control module that generates a call instruction based on an algorithm control signal, and a basic operation module that performs corresponding modular inverse operations and / or negative modular inverse operations based on the call instruction. This hardware circuit can realize the reuse of modular inverse operations and negative modular inverse operations, and the hardware circuit has a faster operation speed and higher security. At the same time, it improves the security level and operation speed of modular inverse operations and negative modular inverse operations.

[0072] Accordingly, this application also discloses a modular inverse operation control method, which is applied to the modular inverse operation hardware circuit provided in the above embodiments. See [link to relevant documentation]. Figure 2 As shown, the control methods include:

[0073] S01: Obtain the algorithm control signal through the algorithm control module, and generate a call instruction based on the algorithm control signal to call the basic operation module to perform the corresponding modular inverse operation and / or negative modular inverse operation; the algorithm control signal is the modular inverse operation signal or the negative modular inverse operation signal;

[0074] S02: Perform corresponding basic operations through the basic operation module according to the call instructions.

[0075] Step S02, which involves obtaining algorithm control signals through the algorithm control module and generating a call instruction based on those signals, includes:

[0076] The algorithm control signal is obtained through the operation scheduling unit and then sent to the operation control unit.

[0077] The arithmetic control unit determines the arithmetic control instructions based on the algorithm control signals and sends the arithmetic control instructions to the arithmetic scheduling unit.

[0078] The arithmetic scheduling unit generates a call instruction based on the arithmetic control instruction to call the basic arithmetic module to perform the corresponding basic arithmetic operations.

[0079] The process of determining the operation control instructions based on the algorithm control signals includes:

[0080] The operation control instructions are determined based on the current operation status and the preset operation logic;

[0081] The preset operation logic includes multiple operation states and the jump relationships between these operation states.

[0082] Furthermore, the modular inverse operation control method also includes:

[0083] When an operation instruction is received, the operation scheduling unit initializes and assigns values ​​to a preset number of registers.

[0084] Specifically, a predetermined number of registers are used to store the operation parameter values, which include the operation input values, intermediate variable coefficients, and operation result values. The operation input values ​​include the first operand q, the second operand r, and the operation mode flag; the intermediate variable coefficients include the intermediate variable t and the predetermined constant n; and the operation result values ​​include the modular inverse result s and the negative modular inverse result n'.

[0085] Specifically, the operation mode flag corresponds to two operation modes: modular inverse operation mode and negative modular inverse operation mode, each corresponding to a different algorithm control signal. It can be understood that since the operation mode flag only corresponds to these two operation modes, a binary code of 0 or 1 can be used to establish the relationship between the operation mode flag and the two operation modes. In this embodiment, the operation mode flag corresponding to the modular inverse operation mode can be set to 1, and the operation mode flag corresponding to the negative modular inverse operation mode can be set to 0; of course, the opposite values ​​can also be set.

[0086] The modulo inverse operation is expressed as s = q mod n, where the first operand q is any integer; the negative modulo inverse operation is expressed as n' = -n mod q, where the first operand is the place value 2. k During initialization, the second operand r takes the value of a preset constant n.

[0087] Furthermore, the initialization assignment includes:

[0088] Assign the first operand q, the second operand r, the preset constant n, and the operation mode flag the values ​​of the corresponding operation instructions, and assign the modulo inverse result s to 1;

[0089] When the operation mode flag corresponds to the modular inverse operation mode, the intermediate variable t is assigned the value 0;

[0090] When the operation mode flag corresponds to the negative modulus inverse operation mode, the intermediate variable t is assigned the value 1, and the negative modulus inverse result n' is assigned the value 0.

[0091] Since the negative modular inverse operation mode does not involve the negative modular inverse result n', there is no need to assign a value to the negative modular inverse result n'. For reliable calculation, it can be assigned the value 0.

[0092] It is understandable that the initialization assignment here refers to writing the corresponding values ​​to each storage bit in a preset number of registers corresponding to the first operand q, the second operand r, the modulo inverse result s, the intermediate variable t, the negative modulo inverse result n', the preset constant n, and the operation mode flag. The processing of each value in the following text is to read the value of its corresponding storage bit from the register, then input it into one or more circuits in the basic operation module for operation, and finally write the operation result back to the corresponding storage bit in the register.

[0093] This embodiment utilizes hardware circuits for computation, resulting in faster computation speed and higher security. It also improves the security level and computation speed of modular inverse and negative modular inverse operations.

[0094] This invention discloses a specific modular inverse operation control method. Compared with the previous embodiment, this embodiment further explains and optimizes the technical solution. Specifically:

[0095] See Figure 3 As shown, the preset operation logic includes multiple operation states S1 to S8, and the transition relationships between these operation states are as follows:

[0096] S1: Idle state; when an operation instruction is received, initialize and assign values ​​to a preset number of registers; when the operation mode flag corresponds to the modulo inverse operation mode, jump to S2; when the operation mode flag corresponds to the negative modulo inverse operation mode, jump to S7.

[0097] S2: Determine if the first operand q is 1, an even number, or an odd number other than 1; if the first operand q is 1, jump to S8; if the first operand q is even, jump to S6; if the first operand q is an odd number other than 1, jump to S3.

[0098] S3: Determine if the second operand r is even; if the second operand r is even, jump to S4; if the second operand r is not even, jump to S5.

[0099] S4: Trigger the right shift circuit to shift the second operand r one bit to the right, and determine whether the intermediate variable t is even. If not, trigger the addition circuit to sum the intermediate variable t with the preset constant n, and assign the current result of the addition circuit to the intermediate variable t. Then trigger the right shift circuit to shift the intermediate variable t one bit to the right. If it is even, trigger the right shift circuit to shift the intermediate variable t one bit to the right; jump to S3.

[0100] S5: Determine if the first operand q is greater than the second operand r, determine if the modular inverse result s is greater than the intermediate variable t, and determine if the intermediate variable t is greater than the modular inverse result s;

[0101] If the first operand q is greater than the second operand r, and the modulo inverse result s is greater than the intermediate variable t, then the subtraction circuit is triggered to calculate the difference between the first operand q and the second operand r, and the current result of the subtraction circuit is assigned to the first operand q. The subtraction circuit is then triggered to calculate the difference between the modulo inverse result s and the intermediate variable t, and the current result of the subtraction circuit is assigned to the modulo inverse result s.

[0102] If the first operand q is greater than the second operand r, and the modular inverse result s is not greater than the intermediate variable t, then the subtraction circuit is triggered to calculate the difference between the first operand q and the second operand r, and the current result of the subtraction circuit is assigned to the first operand q. The subtraction circuit is also triggered to calculate the difference between the modular inverse result s and the intermediate variable t. The addition circuit is triggered to sum the preset constant n with the current result of the subtraction circuit, and the current result of the addition circuit is assigned to the modular inverse result s.

[0103] If the first operand q is not greater than the second operand r, and the intermediate variable t is greater than the modulo inverse result s, then the subtraction circuit is triggered to calculate the difference between the second operand r and the first operand q, and the current result of the subtraction circuit is assigned to the second operand r. The subtraction circuit is also triggered to calculate the difference between the intermediate variable t and the modulo inverse result s, and the magnitude of the current result of the subtraction circuit is assigned to the intermediate variable t.

[0104] If the first operand q is not greater than the second operand r, and the intermediate variable t is not greater than the modular inverse result s, then the subtraction circuit is triggered to calculate the difference between the second operand r and the first operand q, and the current result of the subtraction circuit is assigned to the second operand r. The subtraction circuit is then triggered to calculate the difference between the intermediate variable t and the modular inverse result s. The addition circuit is then triggered to sum the current result of the subtraction circuit with the preset constant n, and the current result of the addition circuit is assigned to the intermediate variable t.

[0105] Jump to S2;

[0106] S6: Trigger the right shift circuit to shift the first operand q one bit to the right, and when the operation mode flag corresponds to the negative modulus inverse operation mode, trigger the left shift circuit to shift the intermediate variable t one bit to the left; jump to S7;

[0107] S7: Determine if the modulo inverse result s is even. If it is, trigger the right shift circuit to shift the modulo inverse result s one position to the right. If not, trigger the addition circuit to sum the modulo inverse result s with the preset constant n, and assign the current result of the addition circuit to the modulo inverse result s. Then trigger the right shift circuit to shift the modulo inverse result s one position to the right. When the operation mode flag corresponds to the negative modulo inverse operation mode, trigger the addition circuit to sum the negative modulo inverse result n' with the intermediate variable t, and assign the current result of the addition circuit to the negative modulo inverse result n'. Jump to S2.

[0108] S8: Operation complete. Output the corresponding modular inverse result s or negative modular inverse result n' according to the operation mode flag; jump to S1.

[0109] It is understandable that the operation scheduling unit processes each value by reading the value of the corresponding storage bit from the register, inputting it into one or more circuits in the basic operation module for operation, and finally writing the operation result back into the corresponding storage bit in the register.

[0110] Furthermore, each state can be divided into multiple sub-states. If there is no variable association between sub-states, there is no necessary order relationship, and they can be combined in any order, as specified below:

[0111] See Figure 4 As shown, operation state S2 specifically includes sub-operation states S2.1 and S2.2 executed sequentially, wherein:

[0112] S2.1: Determine if the first operand q is 1. If yes, jump to S8; otherwise, jump to S2.2.

[0113] S2.2: Determine if the first operand q is even. If it is, jump to S6; otherwise, jump to S3.

[0114] See Figure 5 As shown, operation state S4 specifically includes sub-operation states S4.1-S4.4, where:

[0115] S4.1: Trigger the right shift circuit to shift the second operand r one bit to the right;

[0116] S4.2: Determine whether the intermediate variable t is even;

[0117] S4.3: Trigger the adder circuit to sum the intermediate variable t with the preset constant n, and assign the current result of the adder circuit to the intermediate variable t;

[0118] S4.4: Trigger the right shift circuit to shift the intermediate variable t one bit to the right;

[0119] In this process, S4.1 can be placed before or after S4.2, S4.3, or S4.4; S4.2 can be placed before S4.3 and S4.4; and S4.3 can be placed before S4.4. If the result of S4.2 is yes, then S4.3 is ignored. In other words, S4.1 and S4.2-S4.4 are logically two parallel and unrelated threads. Therefore, step S4.1 can be located anywhere in the operation state S4. If the hardware computing power allows, these two unrelated threads can also be executed in parallel. Figure 5 This refers to the execution order of the scheme; however, S4.2, S4.3, and S4.4 have explicit triggering conditions, and therefore have a specific order.

[0120] See Figure 6 As shown, operation state S5 specifically includes sub-operation states S5.1-S5.9, where:

[0121] S5.1: Determine if the first operand q is greater than the second operand r;

[0122] S5.2: Determine whether the modular inverse result s is greater than the intermediate variable t;

[0123] S5.3: Determine whether the intermediate variable t is greater than the modular inverse result s;

[0124] S5.4: Trigger the subtraction circuit to calculate the difference between the first operand q and the second operand r, and assign the current result of the subtraction circuit to the first operand q;

[0125] S5.5: Trigger the adder circuit to sum the modular inverse result s with the preset constant n, and assign the current result of the adder circuit to the modular inverse result s;

[0126] S5.6: Trigger the subtraction circuit to calculate the difference between the modular inverse result s and the intermediate variable t, and assign the current result of the subtraction circuit to the modular inverse result s;

[0127] S5.7: Trigger the subtraction circuit to calculate the difference between the second operand r and the first operand q, and assign the current result of the subtraction circuit to the second operand r;

[0128] S5.8: Trigger the adder circuit to sum the intermediate variable t with the preset constant n, and assign the current result of the adder circuit to the intermediate variable t;

[0129] S5.9: Trigger the subtraction circuit to calculate the difference between the intermediate variable t and the inverse modulo result s, and assign the current result of the subtraction circuit to the intermediate variable t;

[0130] If the result of S5.1 is yes, then execute S5.2 and S5.4; otherwise, execute S5.3 and S5.7.

[0131] If the result of S5.2 is negative, then execute S5.5 and S5.6; if it is positive, then execute S5.6.

[0132] If the result of S5.3 is negative, then execute S5.8 and S5.9; if it is positive, then execute S5.9.

[0133] It is understandable that actions mentioned in the same context but without a clear order, such as S5.2 and S5.4, or S5.3 and S5.7, can be executed in any order or in parallel.

[0134] Similarly, operation state S6 specifically includes sub-operation states S6.1 and S6.2, wherein:

[0135] S6.1: Trigger the right shift circuit to shift the first operand q one bit to the right;

[0136] S6.2: When the operation mode flag corresponds to the negative modulus inverse operation mode, the left shift circuit is triggered to control the intermediate variable t to shift left by one bit;

[0137] S6.1 is located before S6.2 or after S6.2.

[0138] It is understandable that S6.1 and S6.2 are logically unrelated, so there is no order requirement for their execution. If executed in a single thread, S6.1 can be executed before or after S6.2. If the hardware computing power allows, S6.1 and S6.2 can also be executed simultaneously.

[0139] See Figure 7 As shown, operation state S7 specifically includes sub-operation states S7.1-S7.4, where:

[0140] S7.1: Determine if the modular inverse result s is even;

[0141] S7.2: Trigger the right shift circuit to shift the modulo inverse result s one bit to the right;

[0142] S7.3: Trigger the adder circuit to sum the modulo inverse result s with the preset constant n, and assign the current result of the adder circuit to the modulo inverse result s;

[0143] S7.4: When the operation mode flag corresponds to the negative modulus inverse operation mode, the addition circuit is triggered to sum the negative modulus inverse result n' with the intermediate variable t, and the current result of the addition circuit is assigned to the negative modulus inverse result n'.

[0144] S7.1 is located before S7.2 and S7.3, S7.3 is located before S7.2, if the result of S7.1 is yes, then S7.3 is ignored, and S7.4 is located before or after S7.1, S7.2 or S7.3.

[0145] It is understandable that S7.1-S7.3 have a clear sequential logic, while S7.4 belongs to two unrelated logical threads from S7.1-S7.3. Therefore, S7.4 can be located at any position in the operation state S7. If the hardware computing power allows, these two logical threads can also be executed simultaneously. Figure 7 This is a diagram illustrating simultaneous execution.

[0146] Furthermore, operation state S1 also includes setting the operation completion flag to 0 when an operation instruction is received; operation state S8 also includes setting the operation completion flag to 1 when the operation is completed.

[0147] It is understandable that operation states S1 and S8 set the operation completion flag at the start and end of the operation to improve the operation program of the entire modular inverse operation hardware circuit and enhance the reliability and integrity of the hardware program.

[0148] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0149] The hardware circuit and control method for modular inverse operation provided by the present invention have been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A hardware circuit for modular inverse operation, characterized in that, include: The algorithm control module is used to acquire algorithm control signals and, based on the algorithm control signals, generate a call instruction to call the basic operation module to perform corresponding modular inverse operations and / or negative modular inverse operations. The basic operation module is used to perform corresponding basic operations according to the calling instruction; The algorithm control module includes: The operation scheduling unit is used to acquire the algorithm control signal and send the algorithm control signal to the operation control unit; The computation control unit is used to determine the computation control instruction according to the algorithm control signal and send the computation control instruction to the computation scheduling unit; wherein, the algorithm control signal includes a modular inverse operation signal or a negative modular inverse operation signal; The operation scheduling unit is also used to generate the call instruction according to the operation control instruction, so as to call the basic operation module to perform the corresponding basic operation; the process from operation control instruction to call instruction includes instruction fragmentation and instruction form change; The computation control unit is a state machine control unit. The state machine control unit stores preset computation logic, which includes multiple computation states and the transition relationships between the computation states. The state machine control unit is used to determine the operation control instruction based on the current operation state; the transition relationships between the operation states include: When the operation mode flag corresponds to the modular inverse operation mode, determine whether the first operand is 1; When the operation mode flag corresponds to the negative modulo inverse operation mode, determine whether the modulo inverse result is even. If it is, trigger the right shift circuit to shift the modulo inverse result one bit to the right. If not, trigger the addition circuit to sum the modulo inverse result with a preset constant, and assign the current result of the addition circuit to the modulo inverse result. Then trigger the right shift circuit to shift the modulo inverse result one bit to the right. When the operation mode flag corresponds to the negative modulo inverse operation mode, trigger the addition circuit to sum the negative modulo inverse result with an intermediate variable, and assign the current result of the addition circuit to the negative modulo inverse result. Determine whether the first operand is 1. When the first operand is determined to be 1, the operation is complete, and the corresponding modular inverse result or negative modular inverse result is output according to the operation mode flag.

2. The modular inverse operation hardware circuit according to claim 1, characterized in that, The hardware circuit also includes: A preset number of registers are used to store operation parameter values, which include operation input values, intermediate variable coefficients, and operation result values.

3. The modular inverse operation hardware circuit according to claim 1, characterized in that, The basic arithmetic module includes an addition circuit, a subtraction circuit, a left shift circuit, and a right shift circuit.

4. A modular inverse operation control method, characterized in that, The control method is applied to the modular inverse operation hardware circuit as described in any one of claims 1 to 3, and the control method includes: The algorithm control module acquires the algorithm control signal and generates a call instruction based on the algorithm control signal to call the basic operation module to perform the corresponding modular inverse operation and / or negative modular inverse operation; the algorithm control signal is a modular inverse operation signal or a negative modular inverse operation signal. The basic operation module performs corresponding basic operations according to the calling instruction. The process of acquiring algorithm control signals through the algorithm control module and generating calling instructions based on the algorithm control signals includes: The algorithm control signal is obtained by the operation scheduling unit and sent to the operation control unit; The computation control unit determines the computation control instruction based on the algorithm control signal and sends the computation control instruction to the computation scheduling unit; wherein, the algorithm control signal includes a modular inverse operation signal or a negative modular inverse operation signal; The operation scheduling unit generates a call instruction based on the operation control instruction to call the basic operation module to perform the corresponding basic operation; the process from operation control instruction to call instruction includes instruction fragmentation and change of instruction form. The process of determining the operation control instruction based on the algorithm control signal includes: The operation control instructions are determined based on the current operation status and the preset operation logic; The preset operation logic includes multiple operation states and the transition relationships between the multiple operation states.

5. The modular inverse operation control method according to claim 4, characterized in that, Also includes: When an operation instruction is received, the operation scheduling unit initializes and assigns values ​​to a preset number of registers.

6. The modular inverse operation control method according to claim 4, characterized in that, The plurality of operation states of the preset operation logic include S1 to S8, and the transition relationship between the plurality of operation states includes: S1: Idle state; when an operation instruction is received, initialize and assign values ​​to a preset number of registers; when the operation mode flag corresponds to the modulo inverse operation mode, jump to S2; when the operation mode flag corresponds to the negative modulo inverse operation mode, jump to S7. S2: Determine whether the first operand is 1, an even number, or an odd number other than 1; if the first operand is 1, jump to S8; if the first operand is even, jump to S6; if the first operand is an odd number other than 1, jump to S3. S3: Determine if the second operand is even; if the second operand is even, jump to S4; if the second operand is not even, jump to S5. S4: Trigger the right shift circuit to control the second operand to shift right by one bit, and determine whether the intermediate variable is even. If not, trigger the addition circuit to sum the intermediate variable with a preset constant, and assign the current result of the addition circuit to the intermediate variable. Then trigger the right shift circuit to control the intermediate variable to shift right by one bit. If yes, trigger the right shift circuit to control the intermediate variable to shift right by one bit; jump to S3. S5: Determine whether the first operand is greater than the second operand, determine whether the modular inverse result is greater than the intermediate variable, and determine whether the intermediate variable is greater than the modular inverse result; If the first operand is greater than the second operand, and the modular inverse result is greater than the intermediate variable, then the subtraction circuit is triggered to calculate the difference between the first operand and the second operand, and the current result of the subtraction circuit is assigned to the first operand; the subtraction circuit is triggered to calculate the difference between the modular inverse result and the intermediate variable, and the current result of the subtraction circuit is assigned to the modular inverse result. If the first operand is greater than the second operand, and the modular inverse result is not greater than the intermediate variable, then the subtraction circuit is triggered to calculate the difference between the first operand and the second operand, and the current result of the subtraction circuit is assigned to the first operand; the subtraction circuit is triggered to calculate the difference between the modular inverse result and the intermediate variable; the addition circuit is triggered to sum the preset constant and the current result of the subtraction circuit, and the current result of the addition circuit is assigned to the modular inverse result. If the first operand is not greater than the second operand, and the intermediate variable is greater than the modular inverse result, then the subtraction circuit is triggered to calculate the difference between the second operand and the first operand, and the current result of the subtraction circuit is assigned to the second operand. The subtraction circuit is also triggered to calculate the difference between the intermediate variable and the modular inverse result, and the current result magnitude of the subtraction circuit is assigned to the intermediate variable. If the first operand is not greater than the second operand, and the intermediate variable is not greater than the modular inverse result, then the subtraction circuit is triggered to calculate the difference between the second operand and the first operand, and the current result of the subtraction circuit is assigned to the second operand. The subtraction circuit is then triggered to calculate the difference between the intermediate variable and the modular inverse result. The addition circuit is then triggered to sum the current result of the subtraction circuit with the preset constant, and the current result of the addition circuit is assigned to the intermediate variable. Jump to S2; S6: Trigger the right shift circuit to control the first operand to shift right by one bit, and when the operation mode flag corresponds to the negative modulus inverse operation mode, trigger the left shift circuit to control the intermediate variable to shift left by one bit; jump to S7; S7: Determine whether the modulo inverse result is even. If so, trigger the right shift circuit to shift the modulo inverse result one position to the right. If not, trigger the addition circuit to sum the modulo inverse result with the preset constant, and assign the current result of the addition circuit to the modulo inverse result. Then trigger the right shift circuit to shift the modulo inverse result one position to the right. When the operation mode flag corresponds to the negative modulo inverse operation mode, trigger the addition circuit to sum the negative modulo inverse result with the intermediate variable, and assign the current result of the addition circuit to the negative modulo inverse result. Jump to S2. S8: The operation is complete. Output the corresponding modulo inverse result or the negative modulo inverse result according to the operation mode flag; jump to S1.

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