FPGA code rule detection method, device and equipment
By generating syntax trees and design classes, combined with call hierarchy graphs, effective detection of FPGA code is achieved, solving the problem of insufficient Chinese interface and rule detection of existing tools. It is particularly suitable for the detection of defense and military FPGA code.
Patent Information
- Application Number
- CN202210374810.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-04-11
- Publication Date
- 2025-09-16
- Estimated Expiration
- 2042-04-11
AI Technical Summary
Existing FPGA code detection tools lack support for Chinese interfaces and detection of certain standard coding rules in my country, resulting in the inability to guarantee the code quality of FPGA products in the aerospace field.
This paper provides an FPGA code rule detection method. By generating syntax trees, design classes and call hierarchy diagrams, it uses modules as units to perform rule scanning and detection. It supports Chinese interfaces and multiple coding rules, including national military standards and STARC.
It realizes effective detection of FPGA code, especially general detection of VHDL and Verilog code in defense and military industry, improves detection efficiency and applicability, has fast response speed, and is suitable for mixed code detection.
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Figure CN115017032B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of coding detection, and in particular relates to a method, device and equipment for detecting FPGA code rules. Background Art
[0002] As FPGA (Field Programmable Gate Array) devices grow in size, the number of resources and complexity of their logic also increase, making the FPGA code that implements FPGA software functions more complex. To ensure the quality of software development, software developers or testers can write unit tests and integration tests during the development phase to verify the correctness of the code logic.
[0003] In the existing technology, the widely used HDL (High-Speed Integrated Circuit Hardware Description Language) code rule checking tools mainly include: HDLdesigner, LEDA, Nlint and Alint, etc. However, the software interfaces of the above HDL code rule checking tools do not support Chinese, the rule descriptions are difficult to understand, and there is a lack of detection methods for certain standard coding rules in my country. For example, in the aerospace field, in order to improve the code quality of aerospace-type FPGA products, the Second Academy of China Aerospace Science and Industry Corporation formulated the "Q / WE1117-2014 Second Academy Model FPGA Hardware Description Language Programming Guidelines" to standardize the design of FPGA code. However, there is currently no FPGA code checking tool that is compatible with the above coding rules, resulting in the inability to guarantee the code quality of FPGA products in the aerospace field. Summary of the Invention
[0004] The object of the present invention is to provide an FPGA code rule detection method, device and equipment for solving at least one technical problem existing in the prior art.
[0005] In order to achieve the above object, the present invention adopts the following technical solutions:
[0006] In a first aspect, the present invention provides an FPGA code rule detection method, comprising:
[0007] Selecting a corresponding coding rule set according to multiple FPGA code files to be tested;
[0008] Perform syntax parsing on each FPGA code file in file units, generate a syntax tree, and load the syntax tree into a data structure in module units;
[0009] Creating a design class based on a project, and storing modules and module information in each FPGA code file in the design class, wherein the project includes multiple FPGA code files, and the module information includes at least a modular syntax tree;
[0010] Setting a top-level file and a top-level module, and automatically matching submodules called by the top-level module based on the design class to generate a call hierarchy graph;
[0011] The coding rule set is used to perform rule scanning and detection on the codes in the design class in modules according to the calling logic of the calling hierarchy graph.
[0012] In one possible design, the method further includes:
[0013] If there is any violation information, the violation information will be saved, exported in the form of a file and fed back to the user interface, where the user interface is a Chinese interface.
[0014] In one possible design, the FPGA code file includes a Verilog file and / or a VHDL file.
[0015] In one possible design, the modules and module information in each FPGA code file are stored in the design class, including:
[0016] For a Verilog file, each module node is regarded as a Verilog module, and each Verilog module and its syntax tree, file path, module name and / or calling submodule information are stored in the design class.
[0017] In one possible design, the modules and module information in each FPGA code file are stored in the design class, including:
[0018] For a vhdl file, search for each entity in the vhdl file, match each entity with a corresponding structure, and combine each entity with the corresponding structure to generate a vhdl module;
[0019] The vhdl module and the module's syntax tree, file path, module name and / or calling submodule information are stored in the design class.
[0020] In one possible design, after automatically matching the called submodules for the top-level module based on the design class, the method further includes:
[0021] Identify whether the submodule called by the top-level module is a valid submodule. If it is a valid submodule, perform white box testing on the current submodule; if it is an invalid submodule, perform black box testing on the current submodule.
[0022] In one possible design, the coding rules include at least the National Military Standard 9765-2020 VHDL coding rules, the National Military Standard 10157-2021 Verilog coding rules, the STARC coding rules, the RMM coding rules and / or the DO-254 coding rules.
[0023] In a possible design, each of the encoding rules is provided with an encoding example and several modification suggestions.
[0024] In a second aspect, the present invention provides an FPGA code rule detection device, comprising:
[0025] The module selects a rule set, which is used to select a corresponding coding rule set according to multiple FPGA code files to be detected;
[0026] The parsing module generates a syntax tree, which is used to perform syntax parsing on each FPGA code file in units of files, generate a syntax tree, and load the syntax tree into a data structure in units of modules;
[0027] a design class creation module for creating a design class based on a project, and storing modules and module information in each FPGA code file into the design class, wherein the project includes multiple FPGA code files and the module information includes at least a modular syntax tree;
[0028] A hierarchy diagram generation module is used to set the top-level file and the top-level module, and automatically match the submodules called by the top-level module based on the design class to generate a call hierarchy diagram;
[0029] A rule detection module is used to use the coding rule set to perform rule scanning and detection on the code in the design class in modules according to the calling logic of the call hierarchy diagram.
[0030] In one possible design, the device further includes:
[0031] The violation information feedback module is used to save the violation information if there is any, export it in the form of a file and feed it back to the user interface, wherein the user interface is a Chinese interface.
[0032] In one possible design, the FPGA code file includes a Verilog file and / or a VHDL file.
[0033] In one possible design, when storing the modules and module information in each FPGA code file into the design class, the design class creation module is specifically configured to:
[0034] For a Verilog file, each module node is regarded as a Verilog module, and each Verilog module and its syntax tree, file path, module name and / or calling submodule information are stored in the design class.
[0035] In one possible design, when storing the modules and module information in each FPGA code file into the design class, the design class creation module is specifically configured to:
[0036] For a vhdl file, search for each entity in the vhdl file, match each entity with a corresponding structure, and combine each entity with the corresponding structure to generate a vhdl module;
[0037] The vhdl module and the module's syntax tree, file path, module name and / or calling submodule information are stored in the design class.
[0038] In a possible design, after automatically matching the called submodules for the top-level module based on the design class, the hierarchical graph generation module is further configured to:
[0039] Identify whether the submodule called by the top-level module is a valid submodule. If it is a valid submodule, perform white box testing on the current submodule; if it is an invalid submodule, perform black box testing on the current submodule.
[0040] In one possible design, the coding rules include at least the National Military Standard 9765-2020 VHDL coding rules, the National Military Standard 10157-2021 Verilog coding rules, the STARC coding rules, the RMM coding rules and / or the DO-254 coding rules.
[0041] In a possible design, each of the encoding rules is provided with an encoding example and several modification suggestions.
[0042] In a third aspect, the present invention provides a computer device, characterized in that it includes a memory, a processor and a transceiver that are communicatively connected in sequence, wherein the memory is used to store computer programs, the transceiver is used to send and receive messages, and the processor is used to read the computer program and execute the FPGA code rule detection method described in any possible design of the first aspect.
[0043] In a fourth aspect, the present invention provides a computer-readable storage medium having instructions stored thereon. When the instructions are run on a computer, the FPGA code rule detection method as described in any possible design of the first aspect is executed.
[0044] In a fifth aspect, the present invention provides a computer program product comprising instructions, which, when executed on a computer, causes the computer to execute the FPGA code rule detection method as described in any possible design of the first aspect.
[0045] Beneficial effects:
[0046] The present invention selects corresponding encoding rules based on multiple FPGA code files to be tested and generates an encoding rule set. Then, each FPGA code file is parsed on a file-by-file basis to generate a syntax tree, which is then loaded into a data structure based on a module. Then, a design class is created on a project-by-project basis to store all Verilog modules and VHDL modules. A call hierarchy graph is generated by setting top-level files and top-level modules and automatically matching submodules called by the top-level modules based on the design class. The encoding rule set is used to perform rule scanning and detection on the design class code on a module-by-module basis according to the call logic of the call hierarchy graph. The present invention selects several preset encoding rules based on different FPGA code files, and after processing the files, uses the encoding rule set to perform rule scanning and detection on the code on a module-by-module basis, thereby achieving effective detection of FPGA code. The method is particularly applicable to universal detection of VHDL and Verilog code in defense and military FPGAs, overcoming the shortcomings of the prior art. Furthermore, by setting a unified module class and storing the modules of all files in the design class, mixed code detection can be achieved, improving the applicability of the method. BRIEF DESCRIPTION OF THE DRAWINGS
[0047] Figure 1 Flowchart of the FPGA code rule detection method in this embodiment. DETAILED DESCRIPTION
[0048] To make the objectives, technical solutions, and advantages of the embodiments of this specification more clear, the technical solutions in the embodiments of this specification will be clearly and completely described below in conjunction with the drawings in the embodiments of this specification. Obviously, the embodiments described are part of the embodiments of this specification, not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this invention.
[0049] Example
[0050] To address technical issues in existing HDL code rule detection tools, such as the software interface not supporting Chinese, difficult-to-understand rule descriptions, and a lack of detection methods for certain standard coding rules in my country, this embodiment proposes an FPGA code rule detection method. This method selects a number of preset coding rules based on different FPGA code files. After processing the files, it uses the coding rule set to scan and detect the code rules on a module basis, thereby achieving effective detection of FPGA code. The method is particularly applicable to the universal detection of VHDL and Verilog codes in defense and military FPGAs, overcoming the shortcomings of the existing technology. Furthermore, by setting a unified module class and storing the modules of all files in the module class, mixed code detection can be achieved, improving the applicability of the method. The embodiment is described in detail below.
[0051] like Figure 1 As shown, in the first aspect, this embodiment provides an FPGA code rule detection method, including but not limited to steps S101 to S105, specifically including:
[0052] Step S101. Select a corresponding encoding rule set based on multiple FPGA code files to be detected;
[0053] In step S101, the FPGA code files include but are not limited to Verilog files and VHDL (Very-High-Speed Integrated Circuit Hardware Description Language) files, wherein the Verilog file refers to a code file written in the hardware description language Verilog HDL (a language that describes the structure and behavior of digital system hardware in text form, which can be used to represent logic circuit diagrams, logic expressions, and logical functions performed by digital logic systems); the VHDL file refers to a code file written in the VHDL language.
[0054] In step S101, the encoding rules are several encoding rules preset in the system, including but not limited to Chinese encoding rules and English encoding rules, such as: National Military Standard 9765-2020 VHDL encoding rules, National Military Standard 10157-2021 Verilog encoding rules, STARC encoding rules, RMM encoding rules and / or DO-254 encoding rules. Preferably, the Chinese encoding rules are "Q / WE1117-2014 Second Academy Model FPGA Hardware Description Language Programming Guidelines".
[0055] It should be noted that this embodiment detects multiple FPGA code files in units of projects. Different FPGA code files may correspond to different encoding rules. Therefore, it is necessary to select corresponding encoding rules to form an encoding rule set for subsequent calls.
[0056] In step S101, preferably, each of the coding rules is provided with a corresponding coding example and a number of modification suggestions, thereby guiding coding personnel in writing and modifying the code, thereby improving the efficiency of subsequent code writing or rewriting.
[0057] Step S102: Perform syntax parsing on each FPGA code file in units of files, generate a syntax tree, and load the syntax tree into a data structure in units of modules;
[0058] In step S102, since FPGA code is based on modules, after generating a syntax tree, the code file needs to load the syntax tree into a module-based data structure to adapt to the module. Preferably, after generating the syntax tree, the syntax tree is optimized or simplified to generate an abstract syntax tree, which is then loaded into the module-based data structure.
[0059] It should be noted that the principle of syntax parsing is to convert a label expression into a syntax tree using specific syntax rules. Preferably, each FPGA code file can also be subjected to lexical parsing. The parsing principle is to use regular expressions to complete lexical matching of strings in the input stream and return the matched lexical expression in the form of labels, thereby parsing the source code into a label expression. Of course, semantic parsing can also be performed, which is not limited here.
[0060] Step S103. Create a design class based on the project, and store the modules and module information in each FPGA code file into the design class, wherein the project includes multiple FPGA code files, and the module information includes at least a modular syntax tree;
[0061] It should be noted that, since each FPGA code file may contain multiple entities or modules, in order to achieve orderly detection of all modules, as a specific implementation of step S103, the modules and module information in each FPGA code file are stored in the design class, including:
[0062] For a Verilog file, each module node is regarded as a Verilog module, and each Verilog module and its syntax tree, file path, module name and / or calling submodule information are stored in the module class.
[0063] As a specific implementation of step S103, storing the modules and module information in each FPGA code file into the design class includes:
[0064] For a vhdl file, search for each entity in the vhdl file, match each entity with a corresponding structure, and combine each entity with the corresponding structure to generate a vhdl module;
[0065] The vhdl module and the module's syntax tree, file path, module name and / or calling submodule information are stored in the module class.
[0066] Based on the above disclosed content, by storing both Verilog modules and VHDL modules in a unified design class, when there is a mutual calling relationship between the Verilog modules and the VHDL modules, mixed code detection can be implemented based on the calling relationship between the two, thereby eliminating the need to detect each code file separately, thereby improving the code detection efficiency and applicability of the method.
[0067] Step S104: Setting the top-level file and the top-level module, and automatically matching the sub-modules called by the top-level module based on the design class to generate a call hierarchy graph;
[0068] It should be noted that after the design classes of all modules are constructed through step S103, it is necessary to set the top-level file and the top-level module to set the running starting point for the program call. Therefore, by using one of the FPGA code files as the top-level file and a module of the top-level file as the top-level module, the starting point of the program operation can be established, and based on the functions of each code in the design class, the sub-modules called by the top-level module are automatically matched, thereby generating a call hierarchy diagram and realizing subsequent sequential detection.
[0069] In step S104, after automatically matching the called submodules for the top-level module based on the design class, the method further includes:
[0070] Identify whether the submodule called by the top-level module is a valid submodule. If it is a valid submodule, it is considered that the module has source code, and the current submodule can be subjected to white box testing. If it is an invalid submodule, it is considered that the module has no source code, and the current submodule can be subjected to black box testing.
[0071] Step S105: Using the coding rule set, according to the calling logic of the call hierarchy graph, the code rules of the design class are scanned and tested in modules.
[0072] In step S105, specifically, through the calling logic between modules, the code is scanned and detected in modules to identify violation information, where the violation information includes but is not limited to rule number, violation description, file path, line number, violation level, comments, etc.
[0073] In a specific embodiment, the method further comprises:
[0074] If there is any violation information, the violation information will be saved, exported in the form of a file and fed back to the user interface, where the user interface is a Chinese interface.
[0075] Based on the above disclosure, this embodiment selects several preset coding rules based on different FPGA code files. After processing the files, the coding rule set is used to perform rule scanning and detection on the code in module units, thereby achieving effective detection of FPGA code. In particular, it is applicable to the general detection of VHDL code and Verilog code in defense and military FPGAs, overcoming the shortcomings of the existing technology. Among them, by setting a unified module class and storing the modules of all files in the design class, mixed code detection can be achieved, improving the applicability of the method.
[0076] Furthermore, through application of this embodiment, it is found that this embodiment responds very quickly to code violation detection, and can achieve a rate of less than 5 minutes to check 10,000 lines of code violations, and the code detection efficiency is very high.
[0077] Based on the above disclosure, this embodiment selects corresponding encoding rules based on multiple FPGA code files to be tested and generates an encoding rule set. Then, each FPGA code file is parsed on a file-by-file basis to generate a syntax tree, which is then loaded into a module-by-module data structure. Then, a design class is created on a project-by-project basis to store all Verilog and VHDL modules. By setting top-level files and top-level modules, and automatically matching submodules called by the top-level modules based on the design class, a call hierarchy graph is generated. Using the encoding rule set, the code of the design class is subjected to rule scanning and detection on a module-by-module basis according to the call logic of the call hierarchy graph. The present invention selects several preset encoding rules based on different FPGA code files, and then, after processing the files, uses the encoding rule set to perform rule scanning and detection on the code on a module-by-module basis, thereby achieving effective detection of FPGA code, particularly applicable to universal detection of VHDL and Verilog code in defense and military FPGAs, overcoming the shortcomings of the prior art. Furthermore, by setting a unified module class and storing the modules of all files in the design class, mixed code detection can be achieved, improving the applicability of the method.
[0078] In a second aspect, the present invention provides an FPGA code rule detection device, comprising:
[0079] The module selects a rule set, which is used to select a corresponding coding rule set according to multiple FPGA code files to be detected;
[0080] The parsing module generates a syntax tree, which is used to perform syntax parsing on each FPGA code file in units of files, generate a syntax tree, and load the syntax tree into a data structure in units of modules;
[0081] a design class creation module for creating a design class based on a project, and storing modules and module information in each FPGA code file into the design class, wherein the project includes multiple FPGA code files and the module information includes at least a modular syntax tree;
[0082] A hierarchy diagram generation module is used to set the top-level file and the top-level module, and automatically match the submodules called by the top-level module based on the design class to generate a call hierarchy diagram;
[0083] A rule detection module is used to use the coding rule set to perform rule scanning and detection on the code in the design class in modules according to the calling logic of the call hierarchy diagram.
[0084] In one possible design, the device further includes:
[0085] The violation information feedback module is used to save the violation information if there is any, export it in the form of a file and feed it back to the user interface, wherein the user interface is a Chinese interface.
[0086] In one possible design, the FPGA code file includes a Verilog file and / or a VHDL file.
[0087] In one possible design, when storing the modules and module information in each FPGA code file into the design class, the design class creation module is specifically configured to:
[0088] For a Verilog file, each module node is regarded as a Verilog module, and each Verilog module and its syntax tree, file path, module name and / or calling submodule information are stored in the design class.
[0089] In one possible design, when storing the modules and module information in each FPGA code file into the design class, the design class creation module is specifically configured to:
[0090] For a vhdl file, search for each entity in the vhdl file, match each entity with a corresponding structure, and combine each entity with the corresponding structure to generate a vhdl module;
[0091] The vhdl module and the module's syntax tree, file path, module name and / or calling submodule information are stored in the design class.
[0092] In a possible design, after automatically matching the called submodules for the top-level module based on the design class, the hierarchical graph generation module is further configured to:
[0093] Identify whether the submodule called by the top-level module is a valid submodule.
[0094] In one possible design, the coding rules include at least the National Military Standard 9765-2020 VHDL coding rules, the National Military Standard 10157-2021 Verilog coding rules, the STARC coding rules, the RMM coding rules and / or the DO-254 coding rules.
[0095] In a possible design, each of the encoding rules is provided with an encoding example and several modification suggestions.
[0096] In a third aspect, the present invention provides a computer device, characterized in that it includes a memory, a processor and a transceiver that are communicatively connected in sequence, wherein the memory is used to store computer programs, the transceiver is used to send and receive messages, and the processor is used to read the computer program and execute the FPGA code rule detection method described in any possible design of the first aspect.
[0097] In a fourth aspect, the present invention provides a computer-readable storage medium having instructions stored thereon. When the instructions are run on a computer, the FPGA code rule detection method as described in any possible design of the first aspect is executed.
[0098] In a fifth aspect, the present invention provides a computer program product comprising instructions, which, when executed on a computer, causes the computer to execute the FPGA code rule detection method as described in any possible design of the first aspect.
[0099] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included in the scope of protection of the present invention.
Claims
1. A method for detecting FPGA code rules, characterized in that: include: Selecting a corresponding coding rule set according to multiple FPGA code files to be tested; Perform syntax parsing on each FPGA code file in file units, generate a syntax tree, and load the syntax tree into a data structure in module units; Creating a design class based on a project, and storing modules and module information in each FPGA code file in the design class, wherein the project includes multiple FPGA code files, and the module information includes at least a modular syntax tree; Setting a top-level file and a top-level module for establishing a program running starting point, and automatically matching submodules called by the top-level module based on the design class to generate a call hierarchy graph, wherein the top-level module is a module in the top-level file; The coding rule set is used to perform rule scanning and detection on the codes in the design class in modules according to the calling logic of the calling hierarchy graph.
2. The FPGA code rule detection method according to claim 1, wherein: The method further comprises: If there is any violation information, the violation information will be saved, exported in the form of a file and fed back to the user interface, where the user interface is a Chinese interface.
3. The FPGA code rule detection method according to claim 1, wherein: The FPGA code file includes a Verilog file and / or a VHDL file.
4. The FPGA code rule detection method according to claim 3, wherein: Storing the modules and module information in each FPGA code file into the design class includes: For a Verilog file, each module node is regarded as a Verilog module, and each Verilog module and its syntax tree, file path, module name and / or calling submodule information are stored in the design class.
5. The FPGA code rule detection method according to claim 3, wherein: Storing the modules and module information in each FPGA code file into the design class includes: For a vhdl file, search for each entity in the vhdl file, match each entity with a corresponding structure, and combine each entity with the corresponding structure to generate a vhdl module; The vhdl module and the module's syntax tree, file path, module name and / or calling submodule information are stored in the design class.
6. The FPGA code rule detection method according to claim 1, wherein: After automatically matching the called submodules for the top-level module based on the design class, the method further includes: Identify whether the submodule called by the top-level module is a valid submodule. If it is a valid submodule, perform white box testing on the current submodule; if it is an invalid submodule, perform black box testing on the current submodule.
7. The FPGA code rule detection method according to claim 1, wherein: The coding rules include at least the National Military Standard 9765-2020 VHDL coding rules, the National Military Standard 10157-2021 Verilog coding rules, the STARC coding rules, the RMM coding rules and / or the DO-254 coding rules.
8. The FPGA code rule detection method according to claim 1, wherein: Each of the coding rules is provided with a coding example and several modification suggestions.
9. An FPGA code rule detection device, characterized in that: include: The module selects a rule set, which is used to select a corresponding coding rule set according to multiple FPGA code files to be detected; The parsing module generates a syntax tree, which is used to perform syntax parsing on each FPGA code file in units of files, generate a syntax tree, and load the syntax tree into a data structure in units of modules; a design class creation module for creating a design class based on a project, and storing modules and module information in each FPGA code file into the design class, wherein the project includes multiple FPGA code files and the module information includes at least a modular syntax tree; a hierarchy diagram generation module, configured to set a top-level file and a top-level module for establishing a program running starting point, and automatically match submodules called by the top-level module based on the design class to generate a call hierarchy diagram, wherein the top-level module is a module in the top-level file; A rule detection module is used to use the coding rule set to perform rule scanning and detection on the code in the design class in modules according to the calling logic of the call hierarchy diagram.
10. A computer device, characterized in that: The invention comprises a memory, a processor and a transceiver which are communicatively connected in sequence, wherein the memory is used to store a computer program, the transceiver is used to send and receive messages, and the processor is used to read the computer program and execute the FPGA code rule detection method according to any one of claims 1 to 8.
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