Tone management using tone gain functions for high dynamic range imaging applications

Abstract

Tone management using tone gain functions for high dynamic range imaging applications is disclosed. Apparatus, systems, and techniques for performing effective tone management of image data. In embodiments, a set of contrast gain curves corresponding to a set of tone ranges of an input image are generated. An output image can then be generated by applying at least the corresponding contrast gain curves to the tone ranges of the input image.

Description

Background Art

[0001] High dynamic range imaging (HDRI) includes techniques for generating image data with a high dynamic range (HDR). Specifically, HDRI provides an increased ratio of the maximum possible pixel value (e.g., the maximum possible luminance value) to the minimum possible pixel value (e.g., the minimum possible luminance value). Pixels with smaller luminance values ​​appear as darker (e.g., blacker) areas of the encoded image, while pixels with larger luminance values ​​appear as brighter (e.g., whiter) areas of the image. Due to this enhanced ratio of maximum to minimum luminance values, and when displayed on a device capable of rendering the increased dynamic range (DR), HDR images can provide greater detail and contrast, and therefore appear more realistic and natural to human viewers. Furthermore, the increased contrast and detail of these HDR images can improve the results of various image processing tasks, such as identifying entities or objects in an image. For example, when rendered appropriately, an image of a scene encoded with HDR image data can have greater detail and contrast, enabling more accurate object detection in the scene by image processing software.

[0002] Conventional methods for tone mapping HDR image data may result in saturation and / or clipping of the image due to improper tone and contrast processing, which may lead to data loss and / or detection failure. Moreover, in controlling the brightness of an HDR image and / or an image encoded by tone-mapped HDR image data, various image processing techniques may reduce many of the visual benefits associated with HDRI, for example, causing the HDR image and / or tone-mapped HDR image to appear "washed out," less realistic, or less detailed. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The various techniques will be described with reference to the accompanying drawings, in which:

[0004] Figure 1 An example method for applying separate tonal gain functions to discrete tonal regions of an input image in accordance with at least one embodiment is shown;

[0005] Figure 2 An example method for applying separate tonal gain functions to discrete tonal regions of an input image in accordance with at least one embodiment is shown;

[0006] Figure 3 shows an example histogram generated at least in part based on an input image in accordance with at least one embodiment;

[0007] Figure 4 An example method for calculating contrast values ​​using different scales according to at least one embodiment is shown;

[0008] Figure 5 shows an example contrast image according to at least one embodiment;

[0009] Figure 6 An example method for determining contrast gain curves for discrete tonal regions of an input image according to at least one embodiment is shown;

[0010] Figure 7 shows example contrast gain curves for discrete tonal regions of an input image in accordance with at least one embodiment;

[0011] Figure 8 An example method for contrast mapping according to at least one embodiment is shown;

[0012] Figure 9 shows an example global tone mapping curve in accordance with at least one embodiment;

[0013] Figure 10 An example method for generating an output image according to at least one embodiment is shown;

[0014] Figure 11 An example data center is shown in accordance with at least one embodiment;

[0015] Figure 12 A processing system according to at least one embodiment is shown;

[0016] Figure 13 A computer system according to at least one embodiment is shown;

[0017] Figure 14 A system according to at least one embodiment is shown;

[0018] Figure 15 An example integrated circuit according to at least one embodiment is shown;

[0019] Figure 16 A computing system according to at least one embodiment is shown;

[0020] Figure 17 An APU is shown according to at least one embodiment;

[0021] Figure 18 A CPU according to at least one embodiment is shown;

[0022] Figure 19 An example accelerator integrated slice is shown in accordance with at least one embodiment;

[0023] Figures 20A-20B An example graphics processor is shown in accordance with at least one embodiment;

[0024] Figure 21AA graphics core according to at least one embodiment is shown;

[0025] Figure 21B GPGPU according to at least one embodiment is shown;

[0026] Figure 22A A parallel processor according to at least one embodiment is shown;

[0027] Figure 22B illustrates a processing cluster according to at least one embodiment;

[0028] Figure 22C A graphics multiprocessor is shown in accordance with at least one embodiment;

[0029] Figure 23 A graphics processor according to at least one embodiment is shown;

[0030] Figure 24 A processor according to at least one embodiment is shown;

[0031] Figure 25 A processor according to at least one embodiment is shown;

[0032] Figure 26 illustrates a graphics processor core according to at least one embodiment;

[0033] Figure 27 illustrates a PPU according to at least one embodiment;

[0034] Figure 28 shows a GPC according to at least one embodiment;

[0035] Figure 29 A streaming multiprocessor is shown in accordance with at least one embodiment;

[0036] Figure 30 illustrates a software stack for a programming platform according to at least one embodiment;

[0037] Figure 31 According to at least one embodiment, Figure 30 CUDA implementation of the software stack;

[0038] Figure 32 According to at least one embodiment, Figure 30 ROCm implementation of the software stack;

[0039] Figure 33 According to at least one embodiment, Figure 30 OpenCL implementation of the software stack;

[0040] Figure 34illustrates software supported by a programming platform according to at least one embodiment;

[0041] Figure 35 According to at least one embodiment, Figures 30-33 Compiled code executed on the programming platform;

[0042] Figure 36 According to at least one embodiment, Figures 30-33 More detailed compiled code executed on the programming platform;

[0043] Figure 37 Transforming source code before compiling it according to at least one embodiment is shown;

[0044] Figure 38A A system configured to compile and execute CUDA source code using different types of processing units is shown in accordance with at least one embodiment;

[0045] Figure 38B A method configured to compile and execute a program using a CPU and a CUDA-enabled GPU according to at least one embodiment is shown. Figure 38A CUDA source code system;

[0046] Figure 38C A method configured to compile and execute using a CPU and a non-CUDA enabled GPU according to at least one embodiment is shown. Figure 38A CUDA source code system;

[0047] Figure 39 According to at least one embodiment, Figure 38C The CUDA to HIP conversion tool converts the sample kernel;

[0048] Figure 40 More details are shown according to at least one embodiment. Figure 38C A non-CUDA-enabled GPU;

[0049] Figure 41 shows how threads of an example CUDA grid are mapped to Figure 40 different computational units; and

[0050] Figure 42 It shows how to migrate existing CUDA code to data-parallel C++ code according to at least one embodiment. DETAILED DESCRIPTION

[0051] Embodiments of the present disclosure relate to efficient tone management with multiple tone gain functions. Systems and methods are disclosed for determining a set of regions within HDR image data, wherein separate tone gain functions are applied to specific regions within the set of regions.

[0052] Compared to conventional systems (such as those described above), applying separate tonal gain functions to discrete tonal regions of HDR image data minimizes the negative effects of tonal and contrast enhancement, such as saturation, clipping, and / or lack of contrast. In various embodiments, optimal tonal gain functions are determined for multiple tonal keys representing tonal ranges within the HDR image data. In one example, these tonal ranges include shadow, mid-tone, and highlight ranges. These tonal ranges can represent localized regions within an image, and specific tonal gain functions can be applied to these localized regions.

[0053] In various embodiments, an HDR image processing pipeline includes a statistical analyzer, a contrast calculator, a contrast gain curve generator, contrast mapping, and global tone mapping. As described in more detail below, the operations of the HDR image processing pipeline can be performed in parallel, serially, or a combination thereof. For example, local contrast processing including the statistical analyzer, contrast calculator, contrast gain curve generator, and local contrast mapping can be performed before or after performing global tone mapping.

[0054] A statistical analyzer, described in more detail below, can process the HDR image data to determine various statistics of the HDR image data. In an embodiment, the statistical analyzer processes a histogram representing the HDR image data to generate a plurality of tonal ranges, a mean for each tonal range, and a variance for each tonal range. In one example, the HDR image data is divided into three tonal ranges: a shadow range, a mid-tone range, and a highlight range, where the shadow range represents the lower ten percent (e.g., the number of pixels represented in the histogram), the highlight range represents the upper ten percent, and the mid-tone range represents the portion of the HDR image data between the shadow range and the highlight range. In various embodiments, the plurality of ranges and / or the associated means are provided as input to a contrast gain curve generator, as described in more detail below.

[0055] In one embodiment, a contrast calculator determines a tonal difference between an input image and a reference tonal image, where the tonal difference is scaled by a smoothing factor in a Gaussian scale space. Furthermore, multiple contrast images may be generated based at least in part on different scales. In various embodiments, luminance values ​​of pixels of the input image are determined, and then the luminance values ​​are smoothed using a Gaussian kernel to generate smoothed luminance values. A contrast image may then be generated by comparing at least the luminance values ​​to the smoothed luminance values. In one example, the contrast image includes positive and negative values.

[0056] In various embodiments, a contrast gain curve generator generates a set of contrast gain curves for the tonal range generated by the statistical analyzer. Furthermore, various control parameters can be applied to contrast gain curves in the set of contrast gain curves as well as to a global contrast gain curve, which can be a combination of contrast gain curves in the set of contrast gain curves. Furthermore, in various embodiments, these control factors are adjusted based on scene conditions (e.g., nighttime or low-light images). Returning to the example above, three gain curves are generated: a shadow contrast gain curve, a highlight contrast gain curve, and a mid-tone contrast gain curve. In various embodiments, the contrast gain curve is determined based, at least in part, on a mean value for the tonal range and a sigma representing a Gaussian curve generated by the statistical analyzer based on the distribution of the tonal range. Typically, the contrast gain curve is a function of an input tonal value to generate a corresponding gain for that tonal value.

[0057] In various embodiments, contrast mapping applies a contrast gain curve to a contrast image generated by a contrast calculator to generate an adjusted contrast image. In one example, these adjusted contrast images are combined to create a final contrast image. In some embodiments, the final contrast image is merged with the output of global tone mapping. In other embodiments, a global tone mapping is applied to the input image before performing local tone mapping. The output image (e.g., the final contrast image or the final contrast image merged with the global tone mapped image) can be used as input to an object detection algorithm or other image processing algorithm. In other embodiments, the output image is simply generated to create a more appealing image for human users.

[0058] Figure 1 A method 100 is shown in which separate tonal gain functions are applied to discrete tonal regions of an HDR image and / or HDR image data to generate an output image. Figure 1In the example shown, an input image 102 is processed using several functions including, but not limited to, a statistical analyzer 106, a contrast gain curve generator 108, a contrast calculator 110, a contrast map 112, and a global tone map 104 to produce an output image 120. The input image 102 may be data representing something to be displayed, such as a scene captured by an image capture device (e.g., a digital camera), something generated by an automated process (e.g., for display in a video game or animated film), and / or other data to be displayed. In an embodiment, the input image 102 is formatted as a bitmap file, although the techniques of the present disclosure may be applicable to input images in other formats, such as Joint Photographic Experts Group (JPEG), and Graphics Interchange Format (GIF), Portable Network Graphics (PNG). The methods and operations described in the present disclosure are applicable to two-dimensional images as well as three-dimensional images (e.g., animation, film, video game, and other image data). In addition, as Figure 1 As shown in , a global tone map 104 is applied to an input image 102 in parallel with applying separate tone gain functions to discrete tonal regions of the input image 102, and the two resulting images (e.g., the global tone map 104 and the results of the local tone mapping) are combined (in Figure 1 denoted by a plus sign in the image) to generate an output image 120. As described in this disclosure, combining images includes various operations such as merging images, applying mathematical transformations to pixel values ​​(e.g., luminance values ​​and / or RGB values) of images, adding, subtracting, or otherwise modifying pixel values, or other methods of combining two or more images. Alternatively, as described below, Figure 2 In more detail, before performing local tone mapping, a global tone map 104 is applied to the input image 102. As described in this disclosure, local tone mapping may refer to the process of applying separate tone gain functions to discrete tonal regions of the input image 102.

[0059] The methods described in this disclosure (including Figure 1 、 Figure 2 、 Figure 4 、 Figure 6 、 Figure 8 and Figure 10) include computing processes that can be performed using any combination of hardware, firmware and / or software. For example, various functions can be implemented by a processor executing instructions stored in a memory. In various embodiments, the elements of these figures include source code or other executable instructions stored in a memory that, when executed by a processor of a computing device, cause the computing device to perform the operations described below. Each of these methods may also be embodied as computer-usable instructions stored on a computer storage medium. To name a few, the methods may be provided by a stand-alone application, a service or a hosted service (standalone or in combination with other hosted services), or a plug-in to another product. However, these methods may additionally or alternatively be performed by any one system or any combination of systems, including but not limited to those described herein. Furthermore, the operations of the above methods may be omitted, performed in a different order, performed in parallel, or a combination of serial and parallel.

[0060] return Figure 1 , the statistical analyzer 106 determines the statistics and key values ​​used during the contrast gain curve generation 108 and the global tone mapping 104. Figure 3 As described in more detail, in an embodiment, the statistical analyzer 106 generates a histogram based at least in part on the input image 102. The contrast calculator 110 determines a contrast image comprising a set of local contrast values, wherein a local contrast value in the set of local contrast values ​​corresponds to a particular pixel position within the input image 102. In one example, the contrast calculator 110 assigns a local contrast value to each pixel position of the input image based at least in part on image data obtained from the input image. Figure 4 Various operations of the contrast calculator 110 are described in more detail.

[0061] In an embodiment, contrast gain curve generation 108 generates a contrast gain transfer function that is applied to a contrast image obtained from contrast calculator 110. In addition, data obtained from statistical analyzer 106 (e.g., a histogram of input image 102) may be used to determine the contrast gain curve generated during contrast gain curve generation 108. In an embodiment, during contrast mapping 112, a discrete contrast gain curve is applied to a contrast image (e.g., the output of contrast calculator 110). As described below in conjunction with Figure 8 As described in more detail, in various embodiments, during contrast mapping 112 , discrete tone functions may be applied to different tonal regions based at least in part on representative local pixels.

[0062] In an embodiment, the statistical analyzer 106 includes a process for statistical data analysis of the input image 102. In one example, the statistics of the input image 102 are estimated and presented in a histogram. In another example, the statistics are calculated directly from the input image 102 or other statistical representation. In various embodiments, the statistical data and / or key statistics include midtone mean, highlight mean, shadow mean, and variance. In one example, these values ​​are defined by the following equations:

[0063]

[0064]

[0065]

[0066]

[0067] In the above equation, R is a set of indices of the edges of the histogram. For example, R S Defines the range of shadow tones. In addition, the variables m, h, and s correspond to the midtone average, highlight average, and shadow average, respectively. Although the above equation includes three separate ranges (e.g., midtones, highlights, and shadows), the statistical analyzer 106 can subdivide the input image 102 into any number of ranges and generate corresponding key statistics. Returning to the above example equation, e[n] and k[n] represent the edge value at index n and the number of pixels on the edge of the histogram of e[n]. As shown below in combination Figure 3 As described in more detail, in various embodiments, this key statistic generated by the statistical analyzer 106 is depicted in a graph where the base curve is a representative Gaussian function with a standard deviation (std) of 3 times sigma and a mean of midtones (m). Figure 6 As described in more detail, during contrast gain curve generation 108, key statistics having different sigmas and means may be used.

[0068] Figure 2 A method 200 is shown in which separate tonal gain functions are applied to discrete tonal regions of an HDR image and / or HDR image data to generate an output image. Figure 2 In the example shown, the input image 202 is processed using several functions including, but not limited to, a statistical analyzer 206, a contrast gain curve generator 208, a contrast calculator 210, a contrast map 212, and a global tone map 204 to produce an output image 220. Figure 2 As shown, the global tone map 204 is applied before applying individual tone gain functions to discrete tonal regions of the result (or output) of the global tone map 204 .

[0069] In various embodiments, after applying the global tone mapping 204 to the input image 202, the resulting image is provided as input to the statistical analyzer 206, the contrast calculator 210, and contrast mapping 212 is performed. In addition, the resulting image (e.g., after performing the global tone mapping 204 on the input image 202) is similar to applying a separate tone gain function (e.g., in combination with Figure 6 In other words, a contrast gain curve is determined and applied to a first result of the global tone mapping 204 to generate a second result (e.g., an image to which the local tone mapping is applied), and an output image 220 is generated by combining at least the first and second results. Figure 2 Indicated by a plus sign.

[0070] Figure 3 300 is an example graph illustrating statistical data and / or key statistics generated by a statistical analyzer based at least in part on an input image according to one embodiment. In an embodiment, curve 302 represents a histogram of the input image, curve 306 represents a cumulative histogram of the input image, curve 304 represents a Gaussian function, an area 308 below curve 302 represents the lower ten percent of the input image (e.g., based on the brightness values ​​of the pixels of the input image), and an area 310 below curve 302 represents the upper ten percent of the input image (e.g., based on the brightness values ​​of the pixels of the input image). Additionally, between 308 and 310 (e.g., at a value e[N s ] and e[N h ] represents the remainder of the input image. Although, as depicted, chart 300 uses ten percent values ​​for the upper and lower ranges, such values ​​may be modified in accordance with the present disclosure. For example, various lighting conditions (e.g., nighttime images, low-light images, brightly lit images, reflective objects within the image, moving objects within the image, etc.), applications, sensitivities, or other factors may require adjustment of these values ​​(e.g., a more uniform distribution of the ranges). Furthermore, the input image may be divided into more than three regions.

[0071] As shown in the graph 300, s represents the shadow tone average, m represents the mid-tone average, and h represents the highlight average. In various embodiments, these values ​​(e.g., the x-axis) represent the luminance values ​​of the pixels of the input image. In various embodiments, these luminance values ​​are determined based at least in part on the color values ​​(e.g., RGB) of the pixels of the input image. Figure 3 In the example of , zero represents a darker portion of the input image and one represents a lighter portion of the input image. As described in more detail below, the s, m, and h values ​​comprise key statistics determined by a statistical analyzer based at least in part on the input image.

[0072] Figure 4 A method 400 is shown in which a contrast calculator is applied to an input image to generate a hue image according to one embodiment. Contrast is defined as the hue difference between the input and reference hue images, scaled by a smoothing factor in a Gaussian scale space. Figure 4 As shown, an input image 402 is provided as input to a contrast calculator. The input image 402 may include an HDR image as described above. Furthermore, in various embodiments, a hue image 404 is generated based at least in part on the input image 402. For example, the luminance values ​​of the pixels of the input image 402 are determined based at least in part on an equation, such as a BT.709 color encoding of the RGB values ​​of the input image represented by the following equation:

[0073] Y(x,y)=0.2126×RGB(x,y,1)+0.7152×RGB(x,y,D+0.0722×RGB(x,y,3).

[0074] However, various other representations of image brightness may be used in conjunction with the present disclosure. Figure 5 As shown, in various embodiments, the reference tone image is transformed into scale space representations 406A and 406B based at least in part on different t values. In an embodiment, the equations for scale space representations 406A and 406B are described as:

[0075] Y t (x,y)=Y(x,y,t)=Y(x,y)*g(x,y,t)

[0076] In the above equation, Y t is a scale-space representation (e.g., 406A and 406B) defined by convolution of Y(x,y) with a Gaussian kernel g(x,y,t) having a standard deviation (t). In various embodiments, the scale-space representations 406A and 406B smooth the luminance values, such as Figure 5 In this manner, multiple contrast images are generated at different scales to regenerate multiple scale space representations 406A and 406B. In various embodiments, these scale space representations 406A and 406B are compared (e.g., the brightness values ​​are subtracted, as shown in FIG. Figure 4 ) to generate a set of contrast maps 408A and 408B.

[0077] Figure 5An embodiment 500 is shown in which a contrast image is generated based at least in part on the method 400 described above, according to one embodiment. In an embodiment, an input tone image 502 is used to generate a scale-space representation 504. For example, the scale-space representation 504 is generated by applying at least the above equation to the input tone image 502, defined by convolution of Y(x,y) with a Gaussian kernel g(x,y,t) having a standard deviation (t), where t=32. Additionally, as described above, the input tone image 502 may be converted or otherwise modified to include luminance value pixels of the input image, or a subset thereof.

[0078] In various embodiments, multiple scale-space representations are generated with various t values. For example, a computing device for generating an HDR image described in the present disclosure generates multiple scale-space representations by applying at least the above equation to an input hue image 502 having multiple different t values. In an embodiment, the input hue image 502 is compared with the scale-space representation 504 to generate a contrast image 506. In an example, the contrast image 506 includes positive and negative contrast values ​​for particular pixels of the image. In one example, grayscale is used to represent positive and / or negative contrast in the contrast image 506. Furthermore, in this example, the magnitude of the contrast is proportional to the saturation, where white represents zero contrast.

[0079] Figure 6 A method 600 is shown in which a set of contrast curves is generated based at least in part on statistical data according to an embodiment. Figure 6 As shown, three contrast gain curves are generated. In one example, the three contrast gain curves are then modified by a set of control parameters 616, merged together, and the final control parameter in the set of control parameters 616 is then used to modify the merged curve. In various embodiments, an input image 602 (e.g., the input image 102 described above) is provided to a statistical analyzer 606 (e.g., the statistical analyzer 106 described above). Furthermore, as described above, the statistical analyzer 606 determines statistical data, such as a shadow average, a highlight average, and a mid-tone average, based at least in part on the input image 602. Although Figure 6 Only three contrast gain curves are shown in FIG, but any number of contrast gain curves may be determined based at least in part on discrete portions of the input image. For example, to accommodate different contrast levels, the number of contrast gain curves may be varied based at least in part on the purpose of the application.

[0080] Back to Figure 6 , each contrast gain curve representing a tonal region is defined by a corresponding equation. For example, the mid-tone contrast gain curve generation 608, the shadow contrast gain curve generation 610, and the highlight contrast gain curve generation 612 are defined by the following equations:

[0081] Mid-tone contrast gain curve: m curve (y) = m gain ×Gaussian(m,S m )

[0082] Highlight contrast gain curve generation: h curve (y) = h gain ×Gaussian(h,S h )

[0083] Shadow contrast gain curve: s curve (y)=s gain ×Gaussian(S, S s )

[0084] In the above equation, m, h, and s comprise the key statistics described above, where these values ​​represent the average values ​​of discrete tonal regions of the input image 602 (e.g., shadow average, highlight average, and mid-tone average). Additionally, S m 、S h and S s Included are sigma values ​​representing a Gaussian curve, which has been adjusted by the statistical analyzer 606 based on the standard deviation (std as defined above) according to the distribution of values ​​within the discrete tonal regions.

[0085] like Figure 6 As shown, a set of control parameters 616 includes midtone gain 618, shadow gain 620, highlight gain 622, and intensity 624. In various embodiments, these control parameters include a set of values ​​for modifying the contrast gain curve. For example, a user may define the set of control parameters 616 based at least in part on a particular application, such as photography, object / person detection, low-light imaging, or other application. Returning to the above equation, m gain 、h gain , and s gain 6. The control parameters 616 represent midtone gain 618, highlight gain 622, and shadow gain 620. In various embodiments, these values ​​are scaling factors used to define the maximum magnitude of the corresponding contrast gain curves (e.g., midtone contrast gain curve generation 608, shadow contrast gain curve generation 610, and highlight contrast gain curve generation 612). In one example, the control parameters 616 are determined based at least in part on scene conditions from the input image 602.

[0086] In an embodiment, the maximum magnitude of the contrast gain curve can be defined by the ratio of the amount of contrast space that can be expanded to the fully expanded intrinsic contrast of a particular tonal region, where the fully expanded intrinsic contrast can be expressed as a weighted combination (w) of the possible maximum contrast of the image and the limited contrast between adjacent tonal regions. In addition, in some embodiments, the weight value w is adaptively adjusted based at least in part on the statistical characteristics of the input image 602 (e.g., the mode and skewness of the histogram of the input image 602). For example, an image that shows a single tonal distribution and a higher skewness in that histogram has a higher probability of both low tones and high tones coexisting in the same local area. In this example, w needs to be set lower so that the estimate of contrast becomes closer to the full range of contrast (e.g., highlight areas to shadow areas). In another example, if the image has multiple modes shown in its histogram, w can be set higher than for a single tonal to improve separation in the tonal distribution and reduce the chance of different tones crossing over. In various embodiments, a set of control parameters 616 adapts to the maximum contrast within a limited range, as described below in conjunction with Figure 7 Shown as h_to_max and s_to_min. In an embodiment, w can be formalized with the constraint of w∝(mode×1 / skewness).

[0087] In yet other embodiments, the contrast gain curve is not limited to these equations, and any other method of determining a gain curve may be employed. For example, according to the present disclosure, a method for generating a gain curve that includes a sufficient number of representative tonal regions and ensures that one tonal region is distinct from at least one other tonal region with a smooth transition at the boundary may be used. In various embodiments, after applying the corresponding control parameters (e.g., midtone gain 618, shadow gain 620, highlight gain 622), the midtone contrast gain curve generation 608, shadow contrast gain curve generation 610, and highlight contrast gain curve generation 612 are merged together (in Figure 6 The combined contrast gain curve 614 generates Figure 7 Contrast gain curve of the combination shown in .

[0088] Figure 7 An example graph 700 of a set of contrast gain curves determined at least in part based on an input image according to one embodiment is shown. Graph 700 shows a histogram 708 of an image, a shadow contrast gain curve 702, a mid-tone contrast gain curve 704, a highlight contrast gain curve 706, and a combined contrast gain curve 710. In various embodiments, as described above in conjunction with Figure 6The shadow contrast gain curve 702, the mid-tone contrast gain curve 704, and the highlight contrast gain curve 706 are described as being determined. In an embodiment, a combined contrast gain curve 710 is determined based at least in part on the following equation:

[0089] G(y)=P o (P1×S curve (y)+P2×m curve (y)+P3×S curve (y))

[0090] In the above equation, P0, P1, P2 and P3 define control parameters, such as the above combination Figure 6 In one example, P1 is a shadow gain parameter, P2 is a mid-tone gain parameter, P3 is a highlight gain parameter, and P0 is an intensity parameter, as described above. As described above, in various embodiments, although in combination Figure 7 Four contrast gain curves are described, but the input image may be divided into any number of discrete regions with corresponding contrast gain curves.

[0091] Figure 8 A method 800 is shown in which a set of contrast curves is applied to scale a spatial representation of an input image to generate a contrast image, according to one embodiment. In various embodiments, the contrast gain curve is a function of the input tonal value to produce a corresponding gain defined by the contrast gain curve. Figure 8 As shown, in an embodiment, contrast gain curves 802A and 802B are applied to scale-space representations 804A and 804B to generate contrast gain maps 810A and 810B. In one example, contrast gain curves 802A and 802B are generated using method 600 as described above. Additionally, in various embodiments, scale-space representations 804A and 804B are generated, at least in part, based on convolution of Y(x, y) with a Gaussian kernel g(x, y, t) having a standard deviation (t), as described above.

[0092] In an embodiment, contrast gain maps 810A and 810B define tonal values ​​based at least in part on input tonal values ​​and corresponding gains defined by contrast gain curves 802A and 802B, which are defined by the following equations:

[0093] G M (x, y, t) = G(Y(x, y, t))

[0094] exist Figure 8 In the example shown, contrast gain maps 810A and 810B are then applied (in Figure 8In various embodiments, the contrast images 806A and 806B are generated using the method 400 described above. For example, the contrast gain map G M (x, y, t) is applied to the contrast image C(x, y, t) pixel of the contrast image. In various embodiments, as a result of applying the contrast gain maps 810A and 810B to the contrast images 806A and 806B, adjusted contrast images 812A and 812B are generated. As described above, the adjusted contrast images 812A and 812B indicate the tonal values ​​produced by applying the contrast gain curves 802A and 802B to the input tonal values ​​(e.g., the tonal values ​​indicated in the scale-space representations 804A and 804B).

[0095] In an embodiment, Figure 8 As shown in , multiple contrast images (e.g., adjusted contrast images 812A and 812B) are added together, indicated by a "+". In one example, adding the adjusted contrast images 812A and 812B is defined by the following equation:

[0096]

[0097] In the above equation, C F A final contrast image 814 is defined that is generated by adding at least a set of adjusted contrast images (eg, adjusted contrast images 812A and 812B) for a set of t-values.

[0098] Figure 9 An example graph 900 of a global tone map applied to an image, according to one embodiment, is shown. Graph 900 illustrates a global tone mapping curve 902, which, in various embodiments, is applied to the values ​​of an input image. In one example, the global tone mapping curve is applied to the luminance values ​​of the input image. The process of determining and applying a global tone mapping to an input image is defined in U.S. Patent Application No. 16 / 526,902, filed on July 30, 2019, entitled “ENHANCED HIGH-DYNAMIC-RANGE IMAGING AND TONE MAPPING,” which is incorporated by reference as if fully set forth.

[0099] Figure 10 A method 1000 is shown in which an output image 1020 is generated by combining at least a final contrast image 1014 with a global tone map 1004, according to one embodiment. For example, as described above, the contrast image C F(x, y) (e.g., final contrast image 814) is merged with the result of applying the global tone mapping to the input image (in Figure 10 In one example, the input image includes the above combined Figure 1 Depicted input image 102. In various embodiments, output image 1020 indicates the result of applying separate tonal gain functions to discrete tonal regions of the HDR image.

[0100] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one skilled in the art that the present invention can be practiced without one or more of these specific details.

[0101] Data Center

[0102] Figure 11 An example data center 1100 is shown in accordance with at least one embodiment. In at least one embodiment, the data center 1100 includes, but is not limited to, a data center infrastructure layer 1110, a framework layer 1120, a software layer 1130, and an application layer 1140.

[0103] In at least one embodiment, Figure 11 As shown, the data center infrastructure layer 1110 may include a resource coordinator 1112, grouped computing resources 1114, and node computing resources ("node CRs") 1116(1)-1116(N), where "N" represents any complete positive integer. In at least one embodiment, the node CRs 1116(1)-1116(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays ("FPGAs"), graphics processors, etc.), memory devices (e.g., dynamic read-only memories), storage devices (e.g., solid-state drives or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules, and cooling modules, etc. In at least one embodiment, one or more of the node CRs 1116(1)-1116(N) may be servers having one or more of the above-mentioned computing resources.

[0104] In at least one embodiment, the grouped computing resources 1114 may include separate groups of node CRs housed in one or more racks (not shown), or many racks (also not shown) housed in data centers at various geographic locations. The separate groups of node CRs within the grouped computing resources 1114 may include computing, network, memory, or storage resources that can be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including CPUs or processors may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0105] In at least one embodiment, resource coordinator 1112 may configure or otherwise control one or more nodes CR 1116(1)-1116(N) and / or grouped computing resources 1114. In at least one embodiment, resource coordinator 1112 may comprise a software design infrastructure ("SDI") management entity for data center 1100. In at least one embodiment, resource coordinator 1112 may comprise hardware, software, or some combination thereof.

[0106] In at least one embodiment, Figure 11As shown, framework layer 1120 includes, but is not limited to, a job scheduler 1132, a configuration manager 1134, a resource manager 1136, and a distributed file system 1138. In at least one embodiment, framework layer 1120 may include a framework that supports software 1152 of software layer 1130 and / or one or more applications 1142 of application layer 1140. In at least one embodiment, software 1152 or applications 1142 may respectively include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1120 may include, but is not limited to, a free and open source software web application framework, such as Apache Spark™ (hereinafter referred to as "Spark"), which may utilize distributed file system 1138 for large-scale data processing (e.g., "big data"). In at least one embodiment, job scheduler 1132 may include a Spark driver to facilitate scheduling of workloads supported by various layers of data center 1100. In at least one embodiment, a configuration manager 1134 can be capable of configuring different layers, such as a software layer 1130 and a framework layer 1120 including Spark and a distributed file system 1138 for supporting large-scale data processing. In at least one embodiment, a resource manager 1136 can manage clustered or grouped computing resources mapped to or allocated to support the distributed file system 1138 and the job scheduler 1132. In at least one embodiment, the clustered or grouped computing resources can include grouped computing resources 1114 on the data center infrastructure layer 1110. In at least one embodiment, the resource manager 1136 can coordinate with a resource coordinator 1112 to manage these mapped or allocated computing resources.

[0107] In at least one embodiment, the software 1152 included in the software layer 1130 may include software used by at least a portion of the node CRs 1116(1)-1116(N), the grouped computing resources 1114, and / or the distributed file system 1138 of the framework layer 1120. The one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0108] In at least one embodiment, the one or more applications 1142 included in the application layer 1140 may include one or more types of applications used by at least a portion of the node CRs 1116(1)-1116(N), the grouped computing resources 1114, and / or the distributed file system 1138 of the framework layer 1120. The one or more types of applications may include, but are not limited to, CUDA applications.

[0109] In at least one embodiment, any of configuration manager 1134, resource manager 1136, and resource coordinator 1112 can implement any number and type of self-modification actions based on any number and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of data center 1100 from making potentially poor configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0110] Computer-based systems

[0111] The following figures set forth, but are not limiting of, exemplary computer-based systems that may be used to implement at least one embodiment.

[0112] Figure 12 A processing system 1200 is shown in accordance with at least one embodiment. In at least one embodiment, system 1200 includes one or more processors 1202 and one or more graphics processors 1208, and can be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 1202 or processor cores 1207. In at least one embodiment, processing system 1200 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device.

[0113] In at least one embodiment, the processing system 1200 may include or be incorporated into a server-based gaming platform, including a gaming console, a mobile gaming console, a handheld gaming console, or an online gaming console. In at least one embodiment, the processing system 1200 is a mobile phone, a smartphone, a tablet computing device, or a mobile internet device. In at least one embodiment, the processing system 1200 may also include a device coupled to or integrated into a wearable device, such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 1200 is a television or set-top box device having one or more processors 1202 and a graphical interface generated by one or more graphics processors 1208.

[0114] In at least one embodiment, one or more processors 1202 each include one or more processor cores 1207 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 1207 is configured to process a specific instruction set 1209. In at least one embodiment, the instruction set 1209 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). In at least one embodiment, multiple processor cores 1207 can each process a different instruction set 1209, which can include instructions that facilitate emulating other instruction sets. In at least one embodiment, the processor cores 1207 can also include other processing devices, such as a digital signal processor (DSP).

[0115] In at least one embodiment, processor 1202 includes cache memory 1204. In at least one embodiment, processor 1202 can have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among various components of processor 1202. In at least one embodiment, processor 1202 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which can share this logic among processor cores 1207 using known cache coherence techniques. In at least one embodiment, processor 1202 also includes a register file 1206. Processor 1202 can include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 1206 can include general purpose registers or other registers.

[0116] In at least one embodiment, one or more processors 1202 are coupled to one or more interface buses 1210 to transmit communication signals, such as address, data, or control signals, between the processors 1202 and other components in the system 1200. In at least one embodiment, the interface bus 1210 can be a processor bus, such as a version of a Direct Media Interface (DMI) bus. In at least one embodiment, the interface bus 1210 is not limited to a DMI bus and can include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the processor 1202 includes an integrated memory controller 1216 and a platform controller hub 1230. In at least one embodiment, the memory controller 1216 facilitates communication between storage devices and other components of the processing system 1200, while the platform controller hub (PCH) 1230 provides connections to input / output (I / O) devices via a local I / O bus.

[0117] In at least one embodiment, the storage device 1220 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or other suitable memory device for use as processor memory. In at least one embodiment, the storage device 1220 can be used as system memory for the processing system 1200 to store data 1222 and instructions 1221 for use when one or more processors 1202 execute applications or processes. In at least one embodiment, the memory controller 1216 is also coupled to an optional external graphics processor 1212, which can communicate with one or more graphics processors 1208 in the processor 1202 to perform graphics and media operations. In at least one embodiment, a display device 1211 can be connected to the processor 1202. In at least one embodiment, the display device 1211 can include one or more internal display devices, such as in a mobile electronic device or portable computer device, or an external display device connected via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, the display device 1211 may include a head-mounted display (HMD), such as a stereoscopic display device used in virtual reality (VR) applications or augmented reality (AR) applications.

[0118] In at least one embodiment, the platform controller hub 1230 enables peripheral devices to connect to the storage device 1220 and the processor 1202 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 1246, a network controller 1234, a firmware interface 1228, a wireless transceiver 1226, a touch sensor 1225, and a data storage device 1224 (e.g., a hard drive, flash memory, etc.). In at least one embodiment, the data storage device 1224 can be connected via a memory interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 1225 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 1226 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, the firmware interface 1228 enables communication with the system firmware and can be, for example, a unified extensible firmware interface (UEFI). In at least one embodiment, a network controller 1234 can enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 1210. In at least one embodiment, the audio controller 1246 is a multi-channel high-definition audio controller. In at least one embodiment, the processing system 1200 includes an optional legacy I / O controller 1240 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the processing system 1200. In at least one embodiment, the platform controller hub 1230 can also be connected to one or more universal serial bus (USB) controllers 1242, which connect input devices such as a keyboard and mouse 1243 combination, a camera 1244, or other USB input devices.

[0119] In at least one embodiment, instances of the memory controller 1216 and the platform controller hub 1230 may be integrated into a discrete external graphics processor, such as the external graphics processor 1212. In at least one embodiment, the platform controller hub 1230 and / or the memory controller 1216 may be external to one or more processors 1202. For example, in at least one embodiment, the processing system 1200 may include the external memory controller 1216 and the platform controller hub 1230, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with the processor 1202.

[0120] Figure 13A computer system 1300 is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 1300 can be a system of interconnected devices and components, a SOC, or some combination thereof. In at least one embodiment, the computer system 1300 is formed by a processor 1302, which can include an execution unit for executing instructions. In at least one embodiment, the computer system 1300 can include, but is not limited to, components such as the processor 1302, which employs an execution unit including logic to execute algorithms for processing data. In at least one embodiment, the computer system 1300 can include a processor such as the Intel® processor available from Intel Corporation of Santa Clara, California. Processor family, XeonTM, XScaleTM and / or StrongARMTM, Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1300 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0121] In at least one embodiment, computer system 1300 can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, embedded applications can include microcontrollers, digital signal processors ("DSPs"), SoCs, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system that can execute one or more instructions according to at least one embodiment.

[0122] In at least one embodiment, computer system 1300 may include, but is not limited to, a processor 1302, which may include, but is not limited to, one or more execution units 1308, which may be configured to execute Compute Unified Device Architecture ("CUDA") ( Developed by NVIDIA Corporation of Santa Clara, California) program. In at least one embodiment, a CUDA program is at least a portion of a software application written in the CUDA programming language. In at least one embodiment, computer system 1300 is a single-processor desktop or server system. In at least one embodiment, computer system 1300 may be a multi-processor system. In at least one embodiment, processor 1302 may include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1302 may be coupled to a processor bus 1310 that may transmit data signals between processor 1302 and other components in computer system 1300.

[0123] In at least one embodiment, processor 1302 may include, but is not limited to, level 1 ("L1") internal cache memory ("cache") 1304. In at least one embodiment, processor 1302 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor 1302. In at least one embodiment, processor 1302 may include a combination of internal and external caches. In at least one embodiment, register file 1306 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and an instruction pointer register.

[0124] In at least one embodiment, an execution unit 1308, including but not limited to logic for performing integer and floating-point operations, is also located in the processor 1302. The processor 1302 may also include a microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, the execution unit 1308 may include logic for processing a packed instruction set 1309. In at least one embodiment, by including the packed instruction set 1309 in the instruction set of the general-purpose processor 1302, along with associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in the general-purpose processor 1302. In at least one embodiment, many multimedia applications may be executed faster and more efficiently by using the full width of the processor's data bus to perform operations on the packed data, which may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations on one data element at a time.

[0125] In at least one embodiment, execution unit 1308 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, or other types of logic circuits. In at least one embodiment, computer system 1300 may include, but is not limited to, memory 1320. In at least one embodiment, memory 1320 may be implemented as a DRAM device, an SRAM device, a flash memory device, or other storage device. Memory 1320 may store instructions 1319 and / or data 1321 represented by data signals that may be executed by processor 1302.

[0126] In at least one embodiment, the system logic chip can be coupled to the processor bus 1310 and the memory 1320. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 1316, and the processor 1302 can communicate with the MCH 1316 via the processor bus 1310. In at least one embodiment, the MCH 1316 can provide a high-bandwidth memory path 1318 to the memory 1320 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1316 can initiate data signals between the processor 1302, the memory 1320, and other components in the computer system 1300, and bridge data signals between the processor bus 1310, the memory 1320, and the system I / O 1322. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1316 may be coupled to the memory 1320 via a high-bandwidth memory path 1318 , and the graphics / video card 1312 may be coupled to the MCH 1316 via an Accelerated Graphics Port (“AGP”) interconnect 1314 .

[0127] In at least one embodiment, computer system 1300 may use system I / O 1322 as a proprietary hub interface bus to couple MCH 1316 to I / O controller hub ("ICH") 1330. In at least one embodiment, ICH 1330 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, a local I / O bus may include, but is not limited to, a high-speed I / O bus used to connect peripheral devices to memory 1320, chipset, and processor 1302. Examples may include, but are not limited to, an audio controller 1329, a firmware hub ("Flash BIOS") 1328, a wireless transceiver 1326, a data store 1324, a legacy I / O controller 1323 including user input 1325 and a keyboard interface, a serial expansion port 1327 (e.g., USB), and a network controller 1334. Data store 1324 may include a hard drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0128] In at least one embodiment, Figure 13 A system comprising interconnected hardware devices or "chips" is shown. In at least one embodiment, Figure 13 An example SoC may be shown. In at least one embodiment, Figure 13 The devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 1300 are interconnected using a Compute Express Link (CXL) interconnect.

[0129] Figure 14 A system 1400 is shown in accordance with at least one embodiment. In at least one embodiment, the system 1400 is an electronic device that utilizes a processor 1410. In at least one embodiment, the system 1400 can be, for example, but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0130] In at least one embodiment, system 1400 may include, but is not limited to, a processor 1410 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 1410 is coupled using a bus or interface, such as an I 2 C bus, System Management Bus ("SMBus"), Low Pin Count (LPC) bus, Serial Peripheral Interface ("SPI"), High Definition Audio ("HDA") bus, Serial Advanced Technology Attachment ("SATA") bus, USB (Revisions 1, 2, 3), or Universal Asynchronous Receiver / Transmitter ("UART") bus. In at least one embodiment, Figure 14 A system is shown that includes interconnected hardware devices or "chips". In at least one embodiment, Figure 14 An example SoC may be shown. In at least one embodiment, Figure 14 The devices shown in can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 14 One or more components of the system are interconnected using Compute Express Link (CXL) interconnect lines.

[0131] In at least one embodiment, Figure 14 The components may include a display 1424, a touch screen 1425, a touchpad 1430, a near field communication unit ("NFC") 1445, a sensor hub 1440, a thermal sensor 1446, a fast chipset ("EC") 1435, a trusted platform module ("TPM") 1438, a BIOS / firmware / flash memory ("BIOS, FW Flash") 1422, a DSP 1460, a solid-state disk ("SSD") or a hard disk drive ("HDD") 1420, a wireless local area network unit ("WLAN") 1450, a Bluetooth unit 1452, a wireless wide area network unit ("WWAN") 1456, a global positioning system (GPS) 1455, a camera ("USB 3.0 camera") 1454 (e.g., a USB 3.0 camera), or a low-power double data rate ("LPDDR") memory unit ("LPDDR3") 1415 implemented in, for example, the LPDDR3 standard. Each of these components may be implemented in any suitable manner.

[0132] In at least one embodiment, other components may be communicatively coupled to processor 1410 through the components discussed above. In at least one embodiment, accelerometer 1441, ambient light sensor (“ALS”) 1442, compass 1443, and gyroscope 1444 may be communicatively coupled to sensor hub 1440. In at least one embodiment, thermal sensor 1439, fan 1437, keyboard 1446, and touchpad 1430 may be communicatively coupled to EC 1435. In at least one embodiment, speaker 1463, earphone 1464, and microphone (“mic”) 1465 may be communicatively coupled to audio unit (“audio codec and class D amplifier”) 1464, which in turn may be communicatively coupled to DSP 1460. In at least one embodiment, audio unit 1464 may include, for example, but not limited to, an audio codec / decoder (“codec”) and a class D amplifier. In at least one embodiment, SIM card (“SIM”) 1457 may be communicatively coupled to WWAN unit 1456. In at least one embodiment, components such as the WLAN unit 1450 and the Bluetooth unit 1452 and the WWAN unit 1456 may be implemented as a next generation form factor (NGFF).

[0133] Figure 15 An example integrated circuit 1500 is shown in accordance with at least one embodiment. In at least one embodiment, the example integrated circuit 1500 is a SoC, which may be manufactured using one or more IP cores. In at least one embodiment, the integrated circuit 1500 includes one or more application processors 1505 (e.g., CPUs), at least one graphics processor 1510, and may additionally include an image processor 1515 and / or a video processor 1520, any of which may be modular IP cores. In at least one embodiment, the integrated circuit 1500 includes peripheral or bus logic including a USB controller 1525, a UART controller 1530, an SPI / SDIO controller 1535, and an I / O controller. 2 S / I 2 IC controller 1540. In at least one embodiment, integrated circuit 1500 may include a display device 1545 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 1550 and a Mobile Industry Processor Interface (MIPI) display interface 1555. In at least one embodiment, storage may be provided by a flash memory subsystem 1560, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1565 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1570.

[0134] Figure 16A computing system 1600 is shown in accordance with at least one embodiment. In at least one embodiment, computing system 1600 includes a processing subsystem 1601 having one or more processors 1602 and system memory 1604 communicating via an interconnect path that may include a memory hub 1605. In at least one embodiment, memory hub 1605 may be a separate component within a chipset assembly or integrated within one or more processors 1602. In at least one embodiment, memory hub 1605 is coupled to an I / O subsystem 1611 via a communication link 1606. In at least one embodiment, I / O subsystem 1611 includes an I / O hub 1607, which enables computing system 1600 to receive input from one or more input devices 1608. In at least one embodiment, I / O hub 1607 may enable a display controller, included in one or more processors 1602, to provide output to one or more display devices 1610A. In at least one embodiment, the one or more display devices 1610A coupled to I / O hub 1607 may include local, internal, or embedded display devices.

[0135] In at least one embodiment, the processing subsystem 1601 includes one or more parallel processors 1612 coupled to the memory hub 1605 via a bus or other communication link 1613. In at least one embodiment, the communication link 1613 can be one of many standard-based communication link technologies or protocols, such as, but not limited to, PCIe, or can be a vendor-specific communication interface or communication structure. In at least one embodiment, the one or more parallel processors 1612 form a computationally focused parallel or vector processing system that can include a large number of processing cores and / or processing clusters, such as a multi-integrated core (MIC) processor. In at least one embodiment, the one or more parallel processors 1612 form a graphics processing subsystem that can output pixels to one of one or more display devices 1610A coupled via the I / O hub 1607. In at least one embodiment, the one or more parallel processors 1612 can also include a display controller and display interface (not shown) to enable direct connection to the one or more display devices 1610B.

[0136] In at least one embodiment, system storage unit 1614 can be connected to I / O hub 1607 to provide a storage mechanism for computing system 1600. In at least one embodiment, I / O switch 1616 can be used to provide an interface mechanism to enable connections between I / O hub 1607 and other components, such as network adapter 1618 and / or wireless network adapter 1619 that can be integrated into the platform, as well as various other devices that can be added via one or more add-on devices 1620. In at least one embodiment, network adapter 1618 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1619 can include one or more of Wi-Fi, Bluetooth, NFC, or other network devices including one or more radios.

[0137] In at least one embodiment, computing system 1600 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 1607. Figure 16 The communication paths that interconnect the various components in the system can be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCIe), or other bus or point-to-point communication interfaces and / or protocols (e.g., NVLink high-speed interconnect or interconnect protocol).

[0138] In at least one embodiment, one or more parallel processors 1612 include circuitry optimized for graphics and video processing (including, for example, video output circuitry) and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 1612 include circuitry optimized for general-purpose processing. In at least one embodiment, the components of computing system 1600 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1612, memory hub 1605, processor 1602, and I / O hub 1607 may be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of computing system 1600 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 1600 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules into a modular computing system. In at least one embodiment, I / O subsystem 1611 and display device 1610B are omitted from computing system 1600.

[0139] Processing system

[0140] The following figures illustrate, but are not limited to, example processing systems that can be used to implement at least one embodiment.

[0141] Figure 17 An accelerated processing unit ("APU") 1700 is shown in accordance with at least one embodiment. In at least one embodiment, the APU 1700 was developed by Advanced Micro Devices, Inc. of Santa Clara, California. In at least one embodiment, the APU 1700 can be configured to execute application programs, such as CUDA programs. In at least one embodiment, the APU 1700 includes, but is not limited to, a core complex 1710, a graphics complex 1740, a fabric 1760, an I / O interface 1770, a memory controller 1780, a display controller 1792, and a multimedia engine 1794. In at least one embodiment, the APU 1700 can include, but is not limited to, any combination of any number of core complexes 1710, any number of graphics complexes 1740, any number of display controllers 1792, and any number of multimedia engines 1794. For purposes of illustration, multiple instances of similar objects are denoted herein by reference numerals, where the reference numeral identifies the object and a number in parentheses identifies the desired instance.

[0142] In at least one embodiment, core complex 1710 is a CPU, graphics complex 1740 is a GPU, and APU 1700 is a processing unit that is not limited to integrating 1710 and 1740 onto a single chip. In at least one embodiment, some tasks may be assigned to core complex 1710, while other tasks may be assigned to graphics complex 1740. In at least one embodiment, core complex 1710 is configured to execute primary control software associated with APU 1700, such as an operating system. In at least one embodiment, core complex 1710 is the main processor of APU 1700, controlling and coordinating the operations of the other processors. In at least one embodiment, core complex 1710 issues commands that control the operations of graphics complex 1740. In at least one embodiment, core complex 1710 may be configured to execute host executable code derived from CUDA source code, and graphics complex 1740 may be configured to execute device executable code derived from CUDA source code.

[0143] In at least one embodiment, core complex 1710 includes, but is not limited to, cores 1720(1)-1720(4) and L3 cache 1730. In at least one embodiment, core complex 1710 may include, but is not limited to, any number of cores 1720 and any combination of any number and type of caches. In at least one embodiment, cores 1720 are configured to execute instructions of a particular instruction set architecture ("ISA"). In at least one embodiment, each core 1720 is a CPU core.

[0144] In at least one embodiment, each core 1720 includes, but is not limited to, a fetch / decode unit 1722, an integer execution engine 1724, a floating-point execution engine 1726, and an L2 cache 1728. In at least one embodiment, the fetch / decode unit 1722 fetches instructions, decodes these instructions, generates micro-ops, and dispatches individual micro-ops to the integer execution engine 1724 and the floating-point execution engine 1726. In at least one embodiment, the fetch / decode unit 1722 can simultaneously dispatch one micro-op to the integer execution engine 1724 and another micro-op to the floating-point execution engine 1726. In at least one embodiment, the integer execution engine 1724 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating-point engine 1726 performs, but is not limited to, floating-point and vector operations. In at least one embodiment, the fetch-decode unit 1722 dispatches micro-ops to a single execution engine that replaces both the integer execution engine 1724 and the floating-point execution engine 1726.

[0145] In at least one embodiment, each core 1720(i) can access an L2 cache 1728(i) included in the core 1720(i), where i is an integer representing a specific instance of the core 1720. In at least one embodiment, each core 1720 included in a core complex 1710(j) is connected to the other cores 1720 included in the core complex 1710(j) via an L3 cache 1730(j) included in the core complex 1710(j), where j is an integer representing a specific instance of the core complex 1710. In at least one embodiment, a core 1720 included in a core complex 1710(j) can access all L3 caches 1730(j) included in the core complex 1710(j), where j is an integer representing a specific instance of the core complex 1710. In at least one embodiment, the L3 cache 1730 can include, but is not limited to, any number of slices.

[0146] In at least one embodiment, graphics complex 1740 can be configured to perform computational operations in a highly parallel manner. In at least one embodiment, graphics complex 1740 is configured to perform graphics pipeline operations, such as draw commands, pixel operations, geometry calculations, and other operations associated with rendering an image to a display. In at least one embodiment, graphics complex 1740 is configured to perform operations that are not graphics-related. In at least one embodiment, graphics complex 1740 is configured to perform both graphics-related operations and graphics-independent operations.

[0147] In at least one embodiment, graphics complex 1740 includes, but is not limited to, any number of compute units 1750 and L2 cache 1742. In at least one embodiment, compute units 1750 share L2 cache 1742. In at least one embodiment, L2 cache 1742 is partitioned. In at least one embodiment, graphics complex 1740 includes, but is not limited to, any number of compute units 1750 and any number (including zero) and type of cache. In at least one embodiment, graphics complex 1740 includes, but is not limited to, any amount of dedicated graphics hardware.

[0148] In at least one embodiment, each compute unit 1750 includes, but is not limited to, any number of SIMD units 1752 and shared memory 1754. In at least one embodiment, each SIMD unit 1752 implements a SIMD architecture and is configured to execute operations in parallel. In at least one embodiment, each compute unit 1750 can execute any number of thread blocks, but each thread block executes on a single compute unit 1750. In at least one embodiment, a thread block includes, but is not limited to, any number of threads of execution. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit 1752 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in a warp belongs to a single thread block and is configured to process different data sets based on a single instruction set. In at least one embodiment, predication can be used to disable one or more threads in a warp. In at least one embodiment, a channel is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block can be synchronized and communicated via shared memory 1754.

[0149] In at least one embodiment, fabric 1760 is a system interconnect that facilitates data and control transfers across core complex 1710, graphics complex 1740, I / O interface 1770, memory controller 1780, display controller 1792, and multimedia engine 1794. In at least one embodiment, APU 1700 may include, in addition to or in lieu of fabric 1760, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of directly or indirectly linked components that may be internal or external to APU 1700. In at least one embodiment, I / O interface 1770 represents any number and type of I / O interfaces (e.g., PCI, PCI-Extended ("PCI-X"), PCIe, Gigabit Ethernet ("GBE"), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1770. In at least one embodiment, peripheral devices coupled to I / O interface 1770 may include, but are not limited to, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, etc.

[0150] In at least one embodiment, display controller AMD92 displays images on one or more display devices, such as liquid crystal display (LCD) devices. In at least one embodiment, multimedia engine 240 includes, but is not limited to, any number and type of multimedia-related circuits, such as video decoders, video encoders, image signal processors, and the like. In at least one embodiment, memory controller 1780 facilitates data transfer between APU 1700 and unified system memory 1790. In at least one embodiment, core complex 1710 and graphics complex 1740 share unified system memory 1790.

[0151] In at least one embodiment, the APU 1700 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers 1780 and memory devices (e.g., shared memory 1754) that can be dedicated to a component or shared among multiple components. In at least one embodiment, the APU 1700 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 1828, L3 cache 1730, and L2 cache 1742), each of which can be private to a component or shared among any number of components (e.g., core 1720, core complex 1710, SIMD units 1752, compute units 1750, and graphics complex 1740).

[0152] Figure 18A CPU 1800 according to at least one embodiment is shown. In at least one embodiment, the CPU 1800 is developed by Advanced Micro Devices, Inc. of Santa Clara, California. In at least one embodiment, the CPU 1800 can be configured to execute application programs. In at least one embodiment, the CPU 1800 is configured to execute host control software, such as an operating system. In at least one embodiment, the CPU 1800 issues commands to control the operation of an external GPU (not shown). In at least one embodiment, the CPU 1800 can be configured to execute host executable code derived from CUDA source code, and the external GPU can be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, the CPU 1800 includes, but is not limited to, any number of core complexes 1810, structures 1860, I / O interfaces 1870, and memory controllers AMAD80.

[0153] In at least one embodiment, core complex 1810 includes, but is not limited to, cores 1820(1)-1820(4) and L3 cache 1830. In at least one embodiment, core complex 1810 may include, but is not limited to, any number of cores 1820 and any combination of any number and type of caches. In at least one embodiment, cores 1820 are configured to execute instructions of a specific ISA. In at least one embodiment, each core 1820 is a CPU core.

[0154] In at least one embodiment, each core 1820 includes, but is not limited to, a fetch / decode unit 1822, an integer execution engine 1824, a floating-point execution engine 1826, and an L2 cache 1828. In at least one embodiment, the fetch / decode unit 1822 fetches instructions, decodes these instructions, generates micro-ops, and dispatches individual micro-ops to the integer execution engine 1824 and the floating-point execution engine 1826. In at least one embodiment, the fetch / decode unit 1822 can simultaneously dispatch one micro-op to the integer execution engine 1824 and another micro-op to the floating-point execution engine 1826. In at least one embodiment, the integer execution engine 1824 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating-point engine 1826 performs, but is not limited to, floating-point and vector operations. In at least one embodiment, the fetch-decode unit 1822 dispatches micro-ops to a single execution engine that replaces both the integer execution engine 1824 and the floating-point execution engine 1826.

[0155] In at least one embodiment, each core 1820(i) can access an L2 cache 1828(i) included in the core 1820(i), where i is an integer representing a specific instance of the core 1820. In at least one embodiment, each core 1820 included in a core complex 1810(j) is connected to the other cores 1820 in the core complex 1810(j) via an L3 cache 1830(j) included in the core complex 1810(j), where j is an integer representing a specific instance of the core complex 1810. In at least one embodiment, a core 1820 included in a core complex 1810(j) can access all L3 caches 1830(j) included in the core complex 1810(j), where j is an integer representing a specific instance of the core complex 1810. In at least one embodiment, the L3 cache 1830 can include, but is not limited to, any number of slices.

[0156] In at least one embodiment, fabric 1860 is a system interconnect that facilitates data and control transfers across core complexes 1810(1)-1810(N) (where N is an integer greater than zero), I / O interface 1870, and memory controller 1880. In at least one embodiment, CPU 1800 may include, in addition to or in lieu of fabric 1860, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of directly or indirectly linked components that may be internal or external to CPU 1800. In at least one embodiment, I / O interface 1870 represents any number and type of I / O interfaces (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1870. In at least one embodiment, peripheral devices coupled to I / O interface 1870 may include, but are not limited to, a display, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, and the like.

[0157] In at least one embodiment, memory controller 1880 facilitates data transfers between CPU 1800 and system memory 1890. In at least one embodiment, core complex 1810 and graphics complex 1840 share system memory 1890. In at least one embodiment, CPU 1800 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers 1880 and memory devices that can be dedicated to a component or shared among multiple components. In at least one embodiment, CPU 1800 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 1828 and L3 cache 1830), each of which can be private to a component or shared among any number of components (e.g., core 1820 and core complex 1810).

[0158] Figure 19 An example accelerator integrated slice 1990 is shown according to at least one embodiment. As used herein, a "slice" includes a specified portion of the processing resources of an accelerator integrated circuit. In at least one embodiment, the accelerator integrated circuit provides cache management, memory access, environment management, and interrupt management services on behalf of multiple graphics processing engines in multiple graphics acceleration modules. The graphics processing engines may each include a separate GPU. Optionally, the graphics processing engines may include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module may be a GPU having multiple graphics processing engines. In at least one embodiment, the graphics processing engines may be individual GPUs integrated on a common package, line card, or chip.

[0159] The application effective address space 1982 within system memory 1914 stores a process element 1983. In one embodiment, the process element 1983 is stored in response to a GPU call 1981 from an application 1980 executing on processor 1907. The process element 1983 contains the processing state of the corresponding application 1980. The work descriptor (WD) 1984 contained in the process element 1983 can be a single job requested by the application or can contain a pointer to a job queue. In at least one embodiment, the WD 1984 is a pointer to a job request queue in the application effective address space 1982.

[0160] Graphics acceleration module 1946 and / or each graphics processing engine can be shared by all or part of the processes in the system.In at least one embodiment, an infrastructure for establishing a processing state and sending WD 1984 to graphics acceleration module 1946 to start a job in a virtualized environment can be included.

[0161] In at least one embodiment, a dedicated process programming model is implemented. In this model, a single process owns the graphics acceleration module 1946 or individual graphics processing engine. Because the graphics acceleration module 1946 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owning partition, and the operating system initializes the accelerator integrated circuit for the owning partition when the graphics acceleration module 1946 is allocated.

[0162] In operation, a WD fetch unit 1991 in the accelerator integrated slice 1990 fetches the next WD 1984, which includes an indication of work to be performed by one or more graphics processing engines in the graphics acceleration module 1946. Data from WD 1984 can be stored in registers 1945 for use by the memory management unit (MMU) 1939, interrupt management circuitry 1947, and / or context management circuitry 1948, as shown. For example, one embodiment of the MMU 1939 includes segment / page roaming circuitry for accessing segment / page tables 1986 within the OS virtual address space 1985. The interrupt management circuitry 1947 can process interrupt events (INTs) 1992 received from the graphics acceleration module 1946. When executing graph operations, effective addresses 1993 generated by the graphics processing engines are converted to real addresses by the MMU 1939.

[0163] In one embodiment, the same register set 1945 is replicated for each graphics processing engine and / or graphics acceleration module 1946 and can be initialized by the hypervisor or operating system. Each of these replicated registers can be included in the accelerator integration slice 1990. Table 1 shows example registers that can be initialized by the hypervisor.

[0164] Table 1 – Registers initialized by the hypervisor

[0165] 1 Slice Control Register 2 Real address (RA) plan processing area pointer 3 Authorization Mask Override Register 4 Interrupt vector table input offset 5 Interrupt vector table entry restriction 6 Status Register 7 Logical partition ID 8 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 9 Storage Description Register

[0166] Example registers that may be initialized by the operating system are shown in Table 2.

[0167] Table 2 – Operating System Initialization Registers

[0168] 1 Process and thread identification 2 Effective Address (EA) environment save / restore pointer 3 Virtual Address (VA) Accelerator Utilization Record Pointer 4 Virtual Address (VA) stores the segment table pointer 5 Mask of Authority 6 Job Descriptor

[0169] In one embodiment, each WD 1984 is specific to a particular graphics acceleration module 1946 and / or a particular graphics processing engine. It contains all the information the graphics processing engine needs to do its work or work, or it can be a pointer to a memory location where the application has set up a command queue for work to be done.

[0170] Figure 20A and 20B An example graphics processor according to at least one embodiment of the present disclosure is shown. In at least one embodiment, any example graphics processor can be manufactured using one or more IP cores. In addition to the illustrations, in at least one embodiment, other logic and circuitry can be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores. In at least one embodiment, the example graphics processor is used within a SoC.

[0171] Figure 20A An example graphics processor 2010 of a SoC integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Figure 20B An additional example graphics processor 2040 of a SoC integrated circuit is shown, which may be manufactured using one or more IP cores, according to at least one embodiment. In at least one embodiment, Figure 20A The graphics processor 2010 is a low power graphics processor core. In at least one embodiment, Figure 20B The graphics processor 2040 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 2010, 2040 can be Figure 15 A variant of the graphics processor 1510.

[0172] In at least one embodiment, the graphics processor 2010 includes a vertex processor 2005 and one or more fragment processors 2015A-2015N (e.g., 2015A, 2015B, 2015C, 2015D through 2015N-1 and 2015N). In at least one embodiment, the graphics processor 2010 can execute different shader programs via separate logic, such that the vertex processor 2005 is optimized to perform operations for the vertex shader program, while one or more fragment processors 2015A-2015N perform fragment (e.g., pixel) shading operations for the fragment or pixel or shader program. In at least one embodiment, the vertex processor 2005 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the fragment processors 2015A-2015N use the primitives and vertex data generated by the vertex processor 2005 to generate a frame buffer for display on a display device. In at least one embodiment, fragment processors 2015A-2015N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0173] In at least one embodiment, graphics processor 2010 additionally includes one or more MMUs 2020A-2020B, caches 2025A-2025B, and circuit interconnects 2030A-2030B. In at least one embodiment, one or more MMUs 2020A-2020B provide virtual-to-physical address mapping for graphics processor 2010, including for vertex processor 2005 and / or fragment processors 2015A-2015N, which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more caches 2025A-2025B. In at least one embodiment, one or more MMUs 2020A-2020B may synchronize with other MMUs within the system, including with other MMUs. Figure 15 One or more MMUs associated with one or more application processors 1505, graphics processor 1515, and / or video processor 1520 enable each processor 1505-1520 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 2030A-2030B enable graphics processor 2010 to connect to other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0174] In at least one embodiment, graphics processor 2040 includes Figure 20A One or more MMUs 2020A-2020B, caches 2025A-2025B, and circuit interconnects 2030A-2030B of the graphics processor 2010. In at least one embodiment, the graphics processor 2040 includes one or more shader cores 2055A-2055N (e.g., 2055A, 2055B, 2055C, 2055D, 2055E, 2055F, through 2055N-1 and 2055N), which provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 2040 includes an inter-core task manager 2045 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 2055A-2055N and a tiling unit 2058 to accelerate tile-based rendering operations in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize the use of internal caches.

[0175] Figure 21AFIG2 shows a graphics core 2100 according to at least one embodiment. In at least one embodiment, the graphics core 2100 may include Figure 15 In at least one embodiment, the graphics core 2100 may be Figure 20B 2055N. In at least one embodiment, the graphics core 2100 includes a shared instruction cache 2102, texture units 2118, and cache / shared memory 2120, which are common to execution resources within the graphics core 2100. In at least one embodiment, the graphics core 2100 may include multiple slices 2101A-2101N or partitions of each core, and the graphics processor may include multiple instances of the graphics core 2100. The slices 2101A-2101N may include support logic including local instruction caches 2104A-2104N, thread schedulers 2106A-2106N, thread dispatchers 2108A-2108N, and a set of registers 2110A-2110N. In at least one embodiment, the slices 2101A-2101N may include a set of additional function units (AFUs) 2112A-2112N, floating point units (FPUs) 2114A-2114N, integer arithmetic logic units (ALUs) 2116A-2116N, address calculation units (ACUs) 2113A-2113N, double precision floating point units (DPFPUs) 2115A-2115N, and matrix processing units (MPUs) 2117A-2117N.

[0176] In one embodiment, the FPUs 2114A-2114N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 2115A-2115N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 2116A-2116N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 2117A-2117N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPUs 2117A-2117N can perform various matrix operations to accelerate CUDA programs, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFUs 2112A-2112N can perform additional logical operations not supported by the floating-point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

[0177] Figure 21BA general purpose graphics processing unit (GPGPU) 2130 is shown in at least one embodiment. In at least one embodiment, GPGPU 2130 is highly parallel and suitable for deployment on a multi-chip module. In at least one embodiment, GPGPU 2130 can be configured to enable highly parallel computational operations to be performed by an array of GPUs. In at least one embodiment, GPGPU 2130 can be directly linked to other instances of GPGPU 2130 to create a multi-GPU cluster to improve execution time for CUDA programs. In at least one embodiment, GPGPU 2130 includes a host interface 2132 to enable connection to a host processor. In at least one embodiment, host interface 2132 is a PCIe interface. In at least one embodiment, host interface 2132 can be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU 2130 receives commands from the host processor and dispatches execution threads associated with those commands to a set of compute clusters 2136A-2136H using a global scheduler 2134. In at least one embodiment, the compute clusters 2136A-2136H share a cache memory 2138. In at least one embodiment, the cache memory 2138 can serve as a higher level cache for the cache memories within the compute clusters 2136A-2136H.

[0178] In at least one embodiment, GPGPU 2130 includes memory 2144A-2144B coupled to compute clusters 2136A-2136H via a set of memory controllers 2142A-2142B. In at least one embodiment, memory 2144A-2144B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0179] In at least one embodiment, computing clusters 2136A-2136H each include a set of graphics cores, such as Figure 21A The graphics core 2100, which may include multiple types of integer and floating-point logic units, may perform computational operations at various precisions, including computations suitable for use with CUDA programs. For example, in at least one embodiment, at least a subset of the floating-point units in each compute cluster 2136A-2136H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0180] In at least one embodiment, multiple instances of GPGPU 2130 can be configured to operate as a compute cluster. Compute clusters 2136A-2136H can implement any technically feasible communication technology for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU 2130 communicate via host interface 2132. In at least one embodiment, GPGPU 2130 includes an I / O hub 2139 that couples GPGPU 2130 to GPU link 2140, enabling direct connection to other instances of GPGPU 2130. In at least one embodiment, GPU link 2140 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 2130. In at least one embodiment, GPU link 2140 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2130 are located in separate data processing systems and communicate via a network device accessible via host interface 2132. In at least one embodiment, GPU link 2140 may be configured to connect to a host processor, in addition to or in place of host interface 2132. In at least one embodiment, GPGPU 2130 may be configured to execute CUDA programs.

[0181] Figure 22A A parallel processor 2200 in accordance with at least one embodiment is shown. In at least one embodiment, the various components of the parallel processor 2200 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or an FPGA.

[0182] In at least one embodiment, parallel processor 2200 includes a parallel processing unit (PPU) 2202. In at least one embodiment, PPU 2202 includes an I / O unit 2204 that enables communication with other devices, including other instances of PPU 2202. In at least one embodiment, I / O unit 2204 can be directly connected to other devices. In at least one embodiment, I / O unit 2204 connects to other devices using a hub or switch interface (e.g., memory hub 2205). In at least one embodiment, the connection between memory hub 2205 and I / O unit 2204 forms a communication link. In at least one embodiment, I / O unit 2204 is connected to a host interface 2206 and a memory crossbar switch 2216, where host interface 2206 receives commands for performing processing operations and memory crossbar switch 2216 receives commands for performing memory operations.

[0183] In at least one embodiment, when host interface 2206 receives command buffers via I / O unit 2204, host interface 2206 can direct work operations to execute those commands to front end 2208. In at least one embodiment, front end 2208 is coupled to scheduler 2210, which is configured to dispatch commands or other work items to processing array 2212. In at least one embodiment, scheduler 2210 ensures that processing array 2212 is properly configured and in a valid state before dispatching tasks to a processing array 2212. In at least one embodiment, scheduler 2210 is implemented by firmware logic executing on a microcontroller. In at least one embodiment, a microcontroller-implemented scheduler 2210 can be configured to perform complex scheduling and work dispatch operations at both coarse and fine granularity, thereby enabling fast preemption and context switching of threads executing on processing array 2212. In at least one embodiment, host software can authenticate workloads for scheduling on processing array 2212 through one of multiple graphics processing doorbells. In at least one embodiment, the workload may then be automatically distributed across the processing array 2212 by scheduler 2210 logic within a microcontroller that includes scheduler 2210 .

[0184] In at least one embodiment, the processing array 2212 can include up to "N" processing clusters (e.g., cluster 2214A, cluster 2214B, through cluster 2214N). In at least one embodiment, each cluster 2214A-2214N of the processing array 2212 can execute a large number of concurrent threads. In at least one embodiment, the scheduler 2210 can allocate work to the clusters 2214A-2214N of the processing array 2212 using various scheduling and / or work distribution algorithms, which can vary depending on the workload generated by each program or computation type. In at least one embodiment, scheduling can be handled dynamically by the scheduler 2210 or can be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing array 2212. In at least one embodiment, different clusters 2214A-2214N of the processing array 2212 can be assigned to process different types of programs or to perform different types of computations.

[0185] In at least one embodiment, the processing array 2212 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing array 2212 can be configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing array 2212 can include logic to perform processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0186] In at least one embodiment, the processing array 2212 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing array 2212 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing array 2212 may be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing units 2202 may transfer data from system memory via the I / O units 2204 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2222) during processing and then written back to the system memory.

[0187] In at least one embodiment, when parallel processing units 2202 are used to perform graph processing, scheduler 2210 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations to multiple clusters 2214A-2214N of processing array 2212. In at least one embodiment, portions of processing array 2212 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 2214A-2214N can be stored in a buffer to allow the intermediate data to be transferred between clusters 2214A-2214N for further processing.

[0188] In at least one embodiment, the processing array 2212 can receive processing tasks to be executed via the scheduler 2210, which receives commands defining the processing tasks from the front end 2208. In at least one embodiment, the processing tasks can include an index of data to be processed, which can include surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 2210 can be configured to obtain the index corresponding to the task, or can receive the index from the front end 2208. In at least one embodiment, the front end 2208 can be configured to ensure that the processing array 2212 is configured in a valid state before starting the workload specified by the incoming command buffer (e.g., batch buffer, push buffer, etc.).

[0189] In at least one embodiment, each of one or more instances of parallel processing unit 2202 can be coupled to parallel processor memory 2222. In at least one embodiment, parallel processor memory 2222 can be accessed via memory crossbar 2216, which can receive memory requests from processing array 2212 and I / O unit 2204. In at least one embodiment, memory crossbar 2216 can access parallel processor memory 2222 via memory interface 2218. In at least one embodiment, memory interface 2218 can include multiple partition units (e.g., partition unit 2220A, partition unit 2220B, through partition unit 2220N), which can each be coupled to a portion of parallel processor memory 2222 (e.g., a memory unit). In at least one embodiment, the plurality of partition units 2220A-2220N are configured to be equal to the number of memory cells, such that the first partition unit 2220A has a corresponding first memory cell 2224A, the second partition unit 2220B has a corresponding memory cell 2224B, and the Nth partition unit 2220N has a corresponding Nth memory cell 2224N. In at least one embodiment, the number of partition units 2220A-2220N may not be equal to the number of memory devices.

[0190] In at least one embodiment, memory units 2224A-2224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 2224A-2224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, render targets such as frame buffers or texture maps may be stored across memory units 2224A-2224N, allowing partition units 2220A-2220N to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 2222. In at least one embodiment, local instances of parallel processor memory 2222 may be eliminated in favor of a unified memory design utilizing system memory in combination with local cache memory.

[0191] In at least one embodiment, any of the clusters 2214A-2214N of the processing array 2212 can process data to be written to any memory unit 2224A-2224N within the parallel processor memory 2222. In at least one embodiment, the memory crossbar 2216 can be configured to transmit the output of each cluster 2214A-2214N to any partition unit 2220A-2220N or another cluster 2214A-2214N, which can perform other processing operations on the output. In at least one embodiment, each cluster 2214A-2214N can communicate with a memory interface 2218 via the memory crossbar 2216 to read from or write to various external storage devices. In at least one embodiment, memory crossbar switch 2216 has connections to memory interface 2218 for communicating with I / O unit 2204, as well as connections to local instances of parallel processor memory 2222, thereby enabling processing units within different processing clusters 2214A-2214N to communicate with system memory or other memory that is not local to parallel processing unit 2202. In at least one embodiment, memory crossbar switch 2216 can use virtual channels to separate traffic flows between clusters 2214A-2214N and partition units 2220A-2220N.

[0192] In at least one embodiment, multiple instances of parallel processing unit 2202 can be provided on a single plug-in card, or multiple plug-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 2202 can be configured to interoperate with each other, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 2202 can include higher precision floating point units relative to other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 2202 or parallel processor 2200 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0193] Figure 22BShown is a processing cluster 2294 according to at least one embodiment. In at least one embodiment, processing cluster 2294 is included in a parallel processing unit. In at least one embodiment, processing cluster 2294 is an instance of one of the processing clusters 2214A-2214N of Figure 22. In at least one embodiment, processing cluster 2294 can be configured to execute many threads in parallel, where the term "thread" refers to an instance of a specific program executed on a specific set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads, which uses a public instruction unit that is configured to issue instructions to a group of processing engines in each processing cluster 2294.

[0194] In at least one embodiment, the operation of the processing cluster 2294 can be controlled by a pipeline manager 2232 that distributes processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 2232 receives instructions from the scheduler 2210 of FIG. 22 and manages the execution of these instructions by the graphics multiprocessor 2234 and / or the texture unit 2236. In at least one embodiment, the graphics multiprocessor 2234 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures can be included within the processing cluster 2294. In at least one embodiment, one or more instances of the graphics multiprocessor 2234 can be included within the processing cluster 2294. In at least one embodiment, the graphics multiprocessor 2234 can process data, and the data crossbar 2240 can be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2232 can facilitate the distribution of the processed data by specifying the destination of the processed data to be distributed via the data crossbar 2240.

[0195] In at least one embodiment, each graphics multiprocessor 2234 within a processing cluster 2294 may include the same set of function execution logic (e.g., arithmetic logic unit, load store unit (LSU), etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, where new instructions may be issued before previous instructions have completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating point arithmetic, comparison operations, Boolean operations, shifts, and calculations of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0196] In at least one embodiment, instructions transmitted to the processing cluster 2294 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 2234. In at least one embodiment, a thread group can include fewer threads than the number of processing engines within the graphics multiprocessor 2234. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more processing engines may be idle during the processing of a loop of the thread group. In at least one embodiment, a thread group can also include more threads than the number of processing engines within the graphics multiprocessor 2234. In at least one embodiment, when a thread group includes more threads than the number of processing engines within the graphics multiprocessor 2234, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 2234.

[0197] In at least one embodiment, the graphics multiprocessor 2234 includes internal cache memory to perform load and store operations. In at least one embodiment, the graphics multiprocessor 2234 can abandon the internal cache and use cache memory within the processing cluster 2294 (e.g., L1 cache 2248). In at least one embodiment, each graphics multiprocessor 2234 can also access a partition unit (e.g., Figure 22A L2 cache within partition units 2220A-2220N) of the graphics multiprocessor 2202 is shared across all processing clusters 2294 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 2234 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 2202 can be used as global memory. In at least one embodiment, processing cluster 2294 includes multiple instances of graphics multiprocessor 2234, which can share common instructions and data, which can be stored in L1 cache 2248.

[0198] In at least one embodiment, each processing cluster 2294 may include an MMU 2245 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 2245 may reside within memory interface 2218 of FIG. 22 . In at least one embodiment, MMU 2245 includes a set of page table entries (PTEs) that map virtual addresses to physical addresses of tiles (more on tiles below) and, optionally, cache line indices. In at least one embodiment, MMU 2245 may include a translation lookaside buffer (TLB) or a cache that may reside within graphics multiprocessor 2234 or L1 cache 2248 or within processing cluster 2294. In at least one embodiment, physical addresses are processed to distribute surface data access locality for efficient request interleaving between partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0199] In at least one embodiment, the processing clusters 2294 can be configured such that each graphics multiprocessor 2234 is coupled to a texture unit 2236 to perform texture mapping operations, which may involve, for example, determining texture sample locations, reading texture data, and filtering the texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2234, and texture data is retrieved from an L2 cache, local parallel processor memory, or system memory as needed. In at least one embodiment, each graphics multiprocessor 2234 outputs processed tasks to a data crossbar 2240 to provide the processed tasks to another processing cluster 2294 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 2216. In at least one embodiment, a pre-raster operations unit (preROP) 2242 is configured to receive data from the graphics multiprocessor 2234 and direct the data to a ROP unit, which may be located with a partition unit as described herein (e.g., partition units 2220A-2220N of FIG. 22 ). In at least one embodiment, the PreROP 2242 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0200] Figure 22C A graphics multiprocessor 2296 is shown in accordance with at least one embodiment. In at least one embodiment, the graphics multiprocessor 2296 is Figure 22B2266 . The graphics multiprocessor 2296 is coupled to the pipeline manager 2232 of the processing cluster 2294. In at least one embodiment, the graphics multiprocessor 2296 has an execution pipeline that includes, but is not limited to, an instruction cache 2252, an instruction unit 2254, an address mapping unit 2256, a register file 2258, one or more GPGPU cores 2262, and one or more LSUs 2266. The GPGPU cores 2262 and the LSUs 2266 are coupled to the cache memory 2272 and the shared memory 2270 via a memory and cache interconnect 2268.

[0201] In at least one embodiment, the instruction cache 2252 receives a stream of instructions to be executed from the pipeline manager 2232. In at least one embodiment, the instructions are cached in the instruction cache 2252 and dispatched for execution by the instruction unit 2254. In one embodiment, the instruction unit 2254 can dispatch instructions as thread groups (e.g., warps), assigning each thread of the thread group to a different execution unit within the GPGPU core 2262. In at least one embodiment, the instructions can access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 2256 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the LSU 2266.

[0202] In at least one embodiment, register file 2258 provides a set of registers for the functional units of graphics multiprocessor 2296. In at least one embodiment, register file 2258 provides temporary storage for operands for the data paths of the functional units (e.g., GPGPU core 2262, LSU 2266) connected to graphics multiprocessor 2296. In at least one embodiment, register file 2258 is divided between each functional unit such that a dedicated portion of register file 2258 is allocated to each functional unit. In at least one embodiment, register file 2258 is divided between the different thread groups being executed by graphics multiprocessor 2296.

[0203] In at least one embodiment, the GPGPU cores 2262 may each include an FPU and / or ALU for executing instructions of the graphics multiprocessor 2296. The GPGPU cores 2262 may be architecturally similar or the architectures may differ. In at least one embodiment, a first portion of the GPGPU core 2262 includes a single-precision FPU and integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2208 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 2296 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 2262 may also include fixed-function or special-function logic.

[0204] In at least one embodiment, the GPGPU core 2262 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, the GPGPU core 2262 can physically execute SIMD4, SIMD8, and SIMD9 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed by a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel by a single SIMD8 logic unit.

[0205] In at least one embodiment, the memory and cache interconnect 2268 is an interconnect network that connects each functional unit of the graphics multiprocessor 2296 to the register file 2258 and the shared memory 2270. In at least one embodiment, the memory and cache interconnect 2268 is a crossbar interconnect that allows the LSU 2266 to implement load and store operations between the shared memory 2270 and the register file 2258. In at least one embodiment, the register file 2258 can operate at the same frequency as the GPGPU core 2262, resulting in very low latency for data transfers between the GPGPU core 2262 and the register file 2258. In at least one embodiment, the shared memory 2270 can be used to enable communication between threads executing on the functional units within the graphics multiprocessor 2296. In at least one embodiment, the cache memory 2272 can be used, for example, as a data cache to cache texture data communicated between the functional units and the texture unit 2236. In at least one embodiment, the shared memory 2270 can also be used as a program-managed cache. In at least one embodiment, in addition to automatically cached data stored in cache memory 2272, threads executing on GPGPU core 2262 may programmatically store data in shared memory.

[0206] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., internal to the package or chip). In at least one embodiment, regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in the WD. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0207] Figure 23A graphics processor 2300 is shown in accordance with at least one embodiment. In at least one embodiment, graphics processor 2300 includes a ring interconnect 2302, a pipeline front end 2304, a media engine 2337, and graphics cores 2380A-2380N. In at least one embodiment, ring interconnect 2302 couples graphics processor 2300 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2300 is one of many processors integrated within a multi-core processing system.

[0208] In at least one embodiment, the graphics processor 2300 receives batches of commands via a ring interconnect 2302. In at least one embodiment, the input commands are interpreted by a command streamer 2303 in a pipeline front end 2304. In at least one embodiment, the graphics processor 2300 includes scalable execution logic to perform 3D geometry processing and media processing via graphics cores 2380A-2380N. In at least one embodiment, for 3D geometry processing commands, the command streamer 2303 provides the commands to a geometry pipeline 2336. In at least one embodiment, for at least some media processing commands, the command streamer 2303 provides the commands to a video front end 2334, which is coupled to a media engine 2337. In at least one embodiment, the media engine 2337 includes a video quality engine (VQE) 2330 for video and image post-processing, and a multi-format encoding / decoding (MFX) 2333 engine for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2336 and the media engine 2337 each generate execution threads for thread execution resources provided by at least one graphics core 2380A.

[0209] In at least one embodiment, the graphics processor 2300 includes scalable thread execution resources featuring modular graphics cores 2380A-2380N (sometimes referred to as core slices), each of which has multiple sub-cores 2350A-2350N, 2360A-2360N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2300 can have any number of graphics cores 2380A-2380N. In at least one embodiment, the graphics processor 2300 includes a graphics core 2380A having at least a first sub-core 2350A and a second sub-core 2360A. In at least one embodiment, the graphics processor 2300 is a low-power processor having a single sub-core (e.g., 2350A). In at least one embodiment, the graphics processor 2300 includes multiple graphics cores 2380A-2380N, each of which includes a set of first sub-cores 2350A-2350N and a set of second sub-cores 2360A-2360N. In at least one embodiment, each of the first sub-cores 2350A-2350N includes at least a first set of execution units (EUs) 2352A-2352N and media / texture samplers 2354A-2354N. In at least one embodiment, each of the second sub-cores 2360A-2360N includes at least a second set of execution units 2362A-2362N and samplers 2364A-2364N. In at least one embodiment, each of the sub-cores 2350A-2350N, 2360A-2360N shares a set of shared resources 2370A-2370N. In at least one embodiment, the shared resources include a shared cache and pixel operation logic.

[0210] Figure 24 A processor 2400 is shown for use in accordance with at least one embodiment. In at least one embodiment, the processor 2400 may include, but is not limited to, logic circuitry for executing instructions. In at least one embodiment, the processor 2400 may execute instructions including x86 instructions, ARM instructions, specialized instructions for ASICs, and the like. In at least one embodiment, the processor 2410 may include registers for storing packed data, such as the 64-bit wide MMX™ registers in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, California. In at least one embodiment, the MMX registers, available in integer and floating-point form, may operate with packed data elements associated with SIMD and Streaming SIMD Extensions ("SSE") instructions. In at least one embodiment, the 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or later (generally referred to as "SSEx") technology may store such packed data operands. In at least one embodiment, the processor 2410 may execute instructions to accelerate CUAD programs.

[0211] In at least one embodiment, processor 2400 includes an in-order front end ("Front End") 2401 to fetch instructions for execution and prepare them for later use in the processor pipeline. In at least one embodiment, Front End 2401 may include several units. In at least one embodiment, instruction prefetcher 2426 retrieves instructions from memory and provides them to instruction decoder 2428, which in turn decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2428 decodes received instructions into one or more operations, called "microinstructions" or "micro-operations" (also referred to as "micro-ops" or "micro-instructions"), for execution. In at least one embodiment, instruction decoder 2428 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform the operations. In at least one embodiment, trace cache 2430 can assemble the decoded microinstructions into a program-ordered sequence or trace in microinstruction queue 2434 for execution. In at least one embodiment, when trace cache 2430 encounters a complex instruction, microcode ROM 2432 provides the microinstructions necessary to complete the operation.

[0212] In at least one embodiment, some instructions may be converted into a single micro-op, while other instructions may require several micro-ops to complete the entire operation. In at least one embodiment, if more than four micro-ops are required to complete an instruction, the instruction decoder 2428 may access the microcode ROM 2432 to execute the instruction. In at least one embodiment, an instruction may be decoded into a smaller number of micro-ops for processing at the instruction decoder 2428. In at least one embodiment, if multiple micro-ops are required to complete the operation, the instruction may be stored in the microcode ROM 2432. In at least one embodiment, the trace cache 2430 references the entry point programmable logic array ("PLA") to determine the correct micro-op pointer for reading the microcode sequence from the microcode ROM 2432 to complete one or more instructions according to at least one embodiment. In at least one embodiment, after the microcode ROM 2432 completes the micro-op sequencing for the instruction, the front end 2401 of the machine may resume fetching micro-ops from the trace cache 2430.

[0213] In at least one embodiment, an out-of-order execution engine ("OOO engine") 2403 can prepare instructions for execution. In at least one embodiment, the OOO logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions flow down the pipeline and are scheduled for execution. The OOO engine 2403 includes, but is not limited to, an allocator / register renamer 2440, a memory microinstruction queue 2442, an integer / floating-point microinstruction queue 2444, a memory scheduler 2446, a fast scheduler 2402, a slow / general floating-point scheduler ("slow / general FP scheduler") 2404, and a simple floating-point scheduler ("simple FP scheduler") 2406. In at least one embodiment, the fast scheduler 2402, the slow / general floating-point scheduler 2404, and the simple floating-point scheduler 2406 are also collectively referred to as "microinstruction schedulers 2402, 2404, 2406." The allocator / register renamer 2440 allocates the machine buffers and resources required for each microinstruction to execute in order. In at least one embodiment, the allocator / register renamer 2440 renames logical registers into entries in the register file. In at least one embodiment, the allocator / register renamer 2440 also allocates an entry for each microinstruction in one of two microinstruction queues: a memory microinstruction queue 2442 for memory operations and an integer / floating point microinstruction queue 2444 for non-memory operations, preceding the memory scheduler 2446 and the microinstruction schedulers 2402, 2404, 2406. In at least one embodiment, the microinstruction schedulers 2402, 2404, 2406 determine when a microinstruction is ready to execute based on the readiness of their dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. In at least one embodiment, the fast scheduler 2402 of at least one embodiment can schedule on every half of the main clock cycle, while the slow / general floating point scheduler 2404 and the simple floating point scheduler 2406 can schedule once per main processor clock cycle. In at least one embodiment, microinstruction schedulers 2402, 2404, 2406 arbitrate dispatch ports to schedule microinstructions for execution.

[0214] In at least one embodiment, execution block 2411 includes, but is not limited to, integer register file / branch network 2408, floating point register file / branch network ("FP register file / branch network") 2410, address generation units ("AGUs") 2412 and 2414, fast arithmetic logic units ("fast ALUs") 2416 and 2418, slow ALU 2420, floating point ALU ("FP") 2422, and floating point move unit ("FP move") 2424. In at least one embodiment, integer register file / branch network 2408 and floating point register file / bypass network 2410 are also referred to herein as "register files 2408, 2410." In at least one embodiment, AGUS 2412 and 2414, fast ALUs 2416 and 2418, slow ALU 2420, floating-point ALU 2422, and floating-point move unit 2424 are also referred to herein as "execution units 2412, 2414, 2416, 2418, 2420, 2422, and 2424." In at least one embodiment, an execution block may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0215] In at least one embodiment, register files 2408 and 2410 may be arranged between microinstruction schedulers 2402, 2404, and 2406 and execution units 2412, 2414, 2416, 2418, 2420, 2422, and 2424. In at least one embodiment, integer register file / branch network 2408 performs integer operations. In at least one embodiment, floating-point register file / branch network 2410 performs floating-point operations. In at least one embodiment, each of register files 2408 and 2410 may include, but is not limited to, a branch network that can bypass or forward recently completed results that have not yet been written to the register file to new dependent objects. In at least one embodiment, register files 2408 and 2410 can communicate data with each other. In at least one embodiment, integer register file / branch network 2408 may include, but is not limited to, two separate register files, one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, floating point register file / branch network 2410 may include, but is not limited to, 128-bit wide entries, as floating point instructions typically have operands that are 64 to 128 bits wide.

[0216] In at least one embodiment, execution units 2412, 2414, 2416, 2418, 2420, 2422, and 2424 can execute instructions. In at least one embodiment, register files 2408 and 2410 store integer and floating-point data operand values ​​required for microinstructions to execute. In at least one embodiment, processor 2400 can include, but is not limited to, any number of execution units 2412, 2414, 2416, 2418, 2420, 2422, and 2424, and combinations thereof. In at least one embodiment, floating-point ALU 2422 and floating-point move unit 2424 can execute floating-point, MMX, SIMD, AVX, SSE, or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2422 can include, but is not limited to, a 64-bit by 64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to fast ALUs 2416 and 2418. In at least one embodiment, fast ALUs 2416 and 2418 can perform fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to slow ALU 2420, as slow ALU 2420 may include, but is not limited to, integer execution hardware for long-latency operations, such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations can be performed by ALUs 2412 and 2414. In at least one embodiment, fast ALU 2416, fast ALU 2418, and slow ALU 2420 can perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2416, fast ALU 2418, and slow ALU 2420 can be implemented to support various data bit sizes, including 16, 32, 128, 256, and the like. In at least one embodiment, the floating point ALU 2422 and floating point shift unit 2424 can be implemented to support a range of operands having bits of various widths. In at least one embodiment, the floating point ALU 2422 and floating point shift unit 2424 can operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0217] In at least one embodiment, the microinstruction schedulers 2402, 2404, and 2406 schedule dependent operations before the parent load completes execution. In at least one embodiment, because microinstructions can be speculatively scheduled and executed in processor 2400, processor 2400 can also include logic for handling memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations running in the pipeline that temporarily prevent the scheduler from having the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and allow independent operations to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor can also be designed to capture instruction sequences for text string comparison operations.

[0218] In at least one embodiment, the term "register" may refer to an on-board processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, registers may be those that can be used from outside the processor (from a programmer's perspective). In at least one embodiment, registers may not be limited to a particular type of circuit. Instead, in at least one embodiment, registers can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented by circuitry within the processor using a variety of different techniques, such as dedicated physical registers, physical registers dynamically allocated using register renaming, a combination of dedicated and dynamically allocated physical registers, and the like. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packing data.

[0219] Figure 25 A processor 2500 is shown in accordance with at least one embodiment. In at least one embodiment, the processor 2500 includes, but is not limited to, one or more processor cores (cores) 2502A-2502N, an integrated memory controller 2514, and an integrated graphics processor 2508. In at least one embodiment, the processor 2500 may include additional cores, up to and including the additional processor core 2502N represented by the dashed box. In at least one embodiment, each processor core 2502A-2502N includes one or more internal cache units 2504A-2504N. In at least one embodiment, each processor core may also have access to one or more shared cache units 2506.

[0220] In at least one embodiment, the internal cache units 2504A-2504N and the shared cache unit 2506 represent a cache memory hierarchy within the processor 2500. In at least one embodiment, the cache memory units 2504A-2504N may include at least one level of instruction and data within each processor core and one or more levels of cache in a shared mid-level cache, such as an L2, L3, level 4 (L4), or other level of cache, with the highest level of cache being categorized as LLC before external memory. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 2506 and 2504A-2504N.

[0221] In at least one embodiment, the processor 2500 may also include a set of one or more bus controller units 2516 and a system agent core 2510. In at least one embodiment, the one or more bus controller units 2516 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, the system agent core 2510 provides management functions for various processor components. In at least one embodiment, the system agent core 2510 includes one or more integrated memory controllers 2514 to manage access to various external memory devices (not shown).

[0222] In at least one embodiment, one or more processor cores 2502A-2502N include support for simultaneous multithreading. In at least one embodiment, system agent core 2510 includes components for coordinating and operating processor cores 2502A-2502N during multithreaded processing. In at least one embodiment, system agent core 2510 may additionally include a power control unit (PCU) that includes logic and components to regulate one or more power states of processor cores 2502A-2502N and graphics processor 2508.

[0223] In at least one embodiment, the processor 2500 further includes a graphics processor 2508 to perform graphics processing operations. In at least one embodiment, the graphics processor 2508 is coupled to a shared cache unit 2506 and a system agent core 2510 including one or more integrated memory controllers 2514. In at least one embodiment, the system agent core 2510 also includes a display controller 2511 for driving the graphics processor output to one or more coupled displays. In at least one embodiment, the display controller 2511 may also be a separate module coupled to the graphics processor 2508 via at least one interconnect, or may be integrated within the graphics processor 2508.

[0224] In at least one embodiment, a ring-based interconnect 2512 is used to couple the internal components of the processor 2500. In at least one embodiment, alternative interconnects may be used, such as point-to-point interconnects, switched interconnects, or other technologies. In at least one embodiment, the graphics processor 2508 is coupled to the ring interconnect 2512 via I / O links 2513.

[0225] In at least one embodiment, I / O link 2513 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 2518 (e.g., an eDRAM module). In at least one embodiment, each of the processor cores 2502A-2502N and the graphics processor 2508 uses the embedded memory module 2518 as a shared LLC.

[0226] In at least one embodiment, the processor cores 2502A-2502N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 2502A-2502N are heterogeneous in terms of ISA, where one or more processor cores 2502A-2502N execute a common instruction set, while one or more other processor cores 2502A-2502N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, the processor cores 2502A-2502N are heterogeneous in terms of microarchitecture, where one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In at least one embodiment, the processor 2500 can be implemented on one or more chips or as a SoC integrated circuit.

[0227] Figure 26 A graphics processor core 2600 is shown in accordance with at least one described embodiment. In at least one embodiment, graphics processor core 2600 is included within a graphics core array. In at least one embodiment, graphics processor core 2600 (sometimes referred to as a core slice) can be one or more graphics cores within a modular graphics processor. In at least one embodiment, graphics processor core 2600 is an example of one graphics core slice, and the graphics processors described herein can include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core 2600 can include a fixed function block 2630 coupled to multiple sub-cores 2601A-2601F, also referred to as sub-slices, which include modules of general purpose and fixed function logic.

[0228] In at least one embodiment, fixed function block 2630 includes a geometry / fixed function pipeline 2636, which, for example, in lower performance and / or lower power graphics processor implementations, may be shared by all sub-cores in graphics processor 2600. In at least one embodiment, geometry / fixed function pipeline 2636 includes a 3D fixed function pipeline, a video front end unit, a thread spawner and thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0229] In at least one embodiment, fixed function block 2630 also includes a graphics SoC interface 2637, a graphics microcontroller 2638, and a media pipeline 2639. Graphics SoC interface 2637 provides an interface between graphics core 2600 and other processor cores in the SoC integrated circuit system. In at least one embodiment, graphics microcontroller 2638 is a programmable subprocessor that can be configured to manage various functions of graphics processor 2600, including thread dispatching, scheduling, and preemption. In at least one embodiment, media pipeline 2639 includes logic that facilitates decoding, encoding, pre-processing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, media pipeline 2639 implements media operations via requests to computational or sampling logic within sub-cores 2601-2601F.

[0230] In at least one embodiment, the SoC interface 2637 enables the graphics core 2600 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared LLC memory, system RAM, and / or embedded on-chip or packaged DRAM. In at least one embodiment, the SoC interface 2637 may also enable communication with fixed-function devices within the SoC (e.g., a camera imaging pipeline) and enable the use and / or implementation of global memory atomics that can be shared between the graphics core 2600 and the CPU within the SoC. In at least one embodiment, the SoC interface 2637 may also implement power management controls for the graphics core 2600 and enable interfaces between the clock domain of the graphics core 2600 and other clock domains within the SoC. In at least one embodiment, the SoC interface 2637 enables the reception of command buffers from a command stream converter and a global thread dispatcher, which are configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, commands and instructions may be dispatched to the media pipeline 2639 when media operations are to be performed, or may be assigned to the geometry and fixed function pipelines (e.g., geometry and fixed function pipeline 2636, geometry and fixed function pipeline 2614) when graph processing operations are to be performed.

[0231] In at least one embodiment, the graphics microcontroller 2638 can be configured to perform various scheduling and management tasks for the graphics core 2600. In at least one embodiment, the graphics microcontroller 2638 can perform graph and / or compute workload scheduling on the various graphics parallel engines within the execution unit (EU) arrays 2602A-2602F, 2604A-2604F in the sub-cores 2601A-2601F. In at least one embodiment, host software executing on a CPU core of a SoC including the graphics core 2600 can submit a workload to one of multiple graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operations include determining which workload to run next, submitting the workload to the command stream converter, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is complete. In at least one embodiment, the graphics microcontroller 2638 may also facilitate a low power or idle state for the graphics core 2600, thereby providing the graphics core 2600 with the ability to save and restore registers across low power state transitions within the graphics core 2600 independent of the operating system and / or graphics driver software on the system.

[0232] In at least one embodiment, graphics core 2600 may have more or fewer sub-cores than the sub-cores 2601A-2601F shown, up to N modular sub-cores. For each set of N sub-cores, in at least one embodiment, graphics core 2600 may also include shared function logic 2610, shared and / or cache memory 2612, geometry / fixed function pipelines 2614, and additional fixed function logic 2616 to accelerate various graphics and compute processing operations. In at least one embodiment, shared function logic 2610 may include logic units (e.g., samplers, math, and / or inter-thread communication logic) that may be shared by each of the N sub-cores within graphics core 2600. Shared and / or cache memory 2612 may be LLC for the N sub-cores 2601A-2601F within graphics core 2600 and may also serve as shared memory accessible by multiple sub-cores. In at least one embodiment, geometry / fixed function pipeline 2614 may be included in place of geometry / fixed function pipeline 2636 within fixed function block 2630 and may include the same or similar logic units.

[0233] In at least one embodiment, graphics core 2600 includes additional fixed-function logic 2616, which may include various fixed-function acceleration logic for use by graphics core 2600. In at least one embodiment, additional fixed-function logic 2616 includes an additional geometry pipeline for use in position-only shading. In position-only shading, there are at least two geometry pipelines, a full geometry pipeline and a culling pipeline within geometry / fixed-function pipelines 2616, 2636, which are additional geometry pipelines that may be included in additional fixed-function logic 2616. In at least one embodiment, the culling pipeline is a modified version of the full geometry pipeline. In at least one embodiment, the full pipeline and the culling pipeline can execute different instances of an application, each with a separate context. In at least one embodiment, position-only shading can hide long culling runs for discarded triangles, allowing shading to complete earlier in some cases. For example, in at least one embodiment, the culling pipeline logic in the additional fixed function logic 2616 can execute position shaders in parallel with the main application and generally generate critical results faster than the full pipeline because the culling pipeline obtains and masks the position attributes of the vertices without having to perform rasterization and render the pixels to the frame buffer. In at least one embodiment, the culling pipeline can use the generated critical results to calculate visibility information for all triangles, regardless of whether those triangles are culled. In at least one embodiment, the full pipeline (which in this case may be called a replay pipeline) can consume visibility information to skip culled triangles to mask only visible triangles that are ultimately passed to the rasterization stage.

[0234] In at least one embodiment, the additional fixed function logic 2616 may also include general purpose processing acceleration logic, such as fixed function matrix multiplication logic, for implementing slowed down CUAD routines.

[0235] In at least one embodiment, a set of execution resources is included within each graphics sub-core 2601A-2601F that can be used to execute graphics, media, and compute operations in response to requests from the graphics pipeline, media pipeline, or shader programs. In at least one embodiment, the graphics sub-core 2601A-2601F includes multiple EU arrays 2602A-2602F, 2604A-2604F, thread dispatch and inter-thread communication (TD / IC) logic 2603A-2603F, 3D (e.g., texture) samplers 2605A-2605F, media samplers 2606A-2606F, shader processors 2607A-2607F, and shared local memory (SLM) 2608A-2608F. Each EU array 2602A-2602F, 2604A-2604F includes multiple execution units, which are GU GPUs capable of servicing graphics, media, or compute operations, executing floating-point and integer / fixed-point logic operations, including graphics, media, or compute shader programs. In at least one embodiment, TD / IC logic 2603A-2603F performs local thread dispatch and thread control operations for the execution units within the sub-core and facilitates communication between threads executing on the execution units of the sub-core. In at least one embodiment, 3D samplers 2605A-2605F can read texture or other 3D graphics-related data into memory. In at least one embodiment, 3D samplers can read texture data differently based on the configured sampling state and texture format associated with a given texture. In at least one embodiment, media samplers 2606A-2606F can perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics sub-core 2601A-2601F may alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each sub-core 2601A-2601F may utilize shared local memory 2608A-2608F within each sub-core, enabling threads executing within a thread group to execute using a common pool of on-chip memory.

[0236] Figure 27A parallel processing unit ("PPU") 2700 is shown in accordance with at least one embodiment. In at least one embodiment, PPU 2700 is configured with machine-readable code that, if executed by PPU 2700, causes PPU 2700 to perform some or all of the processes and techniques described herein. In at least one embodiment, PPU 2700 is a multi-threaded processor implemented on one or more integrated circuit devices and utilizes multithreading as a latency hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) executed in parallel on multiple threads. In at least one embodiment, a thread refers to an execution thread and is an instance of a group of instructions configured to be executed by PPU 2700. In at least one embodiment, PPU 2700 is a graphics processing unit ("GPU") configured to implement a graphics rendering pipeline for processing three-dimensional ("3D") graphics data to generate two-dimensional ("2D") image data for display on a display device, such as an LCD device. In at least one embodiment, PPU 2700 is configured to perform computations, such as linear algebra operations and machine learning operations. Figure 27 The example parallel processor is shown for illustrative purposes only and should be construed as a non-limiting example of a processor architecture implemented in at least one embodiment.

[0237] In at least one embodiment, one or more PPUs 2700 are configured to accelerate high-performance computing ("HPC"), data center, and machine learning applications. In at least one embodiment, one or more PPUs 2700 are configured to accelerate CUDA programs. In at least one embodiment, a PPU 2700 includes, but is not limited to, an I / O unit 2706, a front-end unit 2710, a scheduler unit 2712, a work distribution unit 2714, a hub 2716, a crossbar ("Xbar") 2720, one or more general processing clusters ("GPCs") 2718, and one or more partitioning units ("memory partitioning units") 2722. In at least one embodiment, a PPU 2700 is connected to a host processor or other PPUs 2700 via one or more high-speed GPU interconnects ("GPU interconnects") 2708. In at least one embodiment, a PPU 2700 is connected to a host processor or other peripheral devices via an interconnect 2702. In one embodiment, a PPU 2700 is connected to local memory including one or more memory devices ("memory") 2704. In at least one embodiment, memory device 2704 includes, but is not limited to, one or more dynamic random access memory ("DRAM") devices. In at least one embodiment, one or more DRAM devices are configured and / or configurable as a high bandwidth memory ("HBM") subsystem with multiple DRAM dies stacked within each device.

[0238] In at least one embodiment, the high-speed GPU interconnect 2708 may refer to a wire-based, multi-lane communication link that a system uses to scale and includes one or more PPUs 2700 ("CPUs") in conjunction with one or more CPUs, supporting cache coherency between the PPU 2700 and the CPUs and CPU mastering. In at least one embodiment, the high-speed GPU interconnect 2708 transmits data and / or commands to other units of the PPU 2700, such as one or more copy engines, video encoders, video decoders, power management units, and / or other processors, via a hub 2716. Figure 27 Other components that may not be explicitly shown.

[0239] In at least one embodiment, the I / O unit 2706 is configured to receive data from the host processor ( Figure 27 2706). In at least one embodiment, the I / O unit 2706 communicates with the host processor directly via the system bus 2702 or through one or more intermediate devices (e.g., a memory bridge). In at least one embodiment, the I / O unit 2706 can communicate with one or more other processors (e.g., one or more PPUs 2700) via the system bus 2702. In at least one embodiment, the I / O unit 2706 implements a PCIe interface for communicating over the PCIe bus. In at least one embodiment, the I / O unit 2706 implements an interface for communicating with external devices.

[0240] In at least one embodiment, the I / O unit 2706 decodes packets received via the system bus 2702. In at least one embodiment, at least some of the packets represent commands configured to cause the PPU 2700 to perform various operations. In at least one embodiment, the I / O unit 2706 sends the decoded commands to various other units of the PPU 2700 as specified by the commands. In at least one embodiment, the commands are sent to the front end unit 2710 and / or to the hub 2716 or other units of the PPU 2700, such as one or more copy engines, video encoders, video decoders, power management units, etc. ( Figure 27 In at least one embodiment, I / O unit 2706 is configured to route communications between the various logical units of PPU 2700.

[0241] In at least one embodiment, a program executed by a host processor encodes a command stream in a buffer that provides a workload to the PPU 2700 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is an area in memory that is accessible (e.g., read / write) by both the host processor and the PPU 2700—the host interface unit can be configured to access the buffer in system memory connected to the system bus 2702 via memory requests transmitted via the I / O unit 2706 over the system bus 2702. In at least one embodiment, the host processor writes a command stream into the buffer and then sends a pointer indicating the beginning of the command stream to the PPU 2700, so that the front end unit 2710 receives pointers to one or more command streams and manages the one or more command streams, reading commands from the command streams and forwarding the commands to the various units of the PPU 2700.

[0242] In at least one embodiment, the front end unit 2710 is coupled to a scheduler unit 2712, which configures the various GPCs 2718 to process tasks defined by one or more command streams. In at least one embodiment, the scheduler unit 2712 is configured to track state information related to the various tasks managed by the scheduler unit 2712, where the state information may indicate which GPC 2718 the task is assigned to, whether the task is active or inactive, a priority associated with the task, and the like. In at least one embodiment, the scheduler unit 2712 manages multiple tasks that execute on one or more GPCs 2718.

[0243] In at least one embodiment, the scheduler unit 2712 is coupled to a work distribution unit 2714, which is configured to dispatch tasks for execution on the GPCs 2718. In at least one embodiment, the work distribution unit 2714 tracks a plurality of scheduled tasks received from the scheduler unit 2712 and manages a pending task pool and an active task pool for each GPC 2718. In at least one embodiment, the pending task pool includes a plurality of time slots (e.g., 32 time slots) containing tasks assigned to be processed by a particular GPC 2718; the active task pool may include a plurality of time slots (e.g., 4 time slots) for tasks actively being processed by the GPC 2718, such that as a task in a GPC 2718 completes execution, the task is evicted from the active task pool of the GPC 2718, and one of the other tasks is selected from the pending task pool and scheduled for execution on the GPC 2718. In at least one embodiment, if an active task is idle on a GPC 2718, such as while waiting for data dependencies to be resolved, the active task is evicted from the GPC 2718 and returned to the pending task pool, while another task in the pending task pool is selected and scheduled for execution on the GPC 2718.

[0244] In at least one embodiment, work distribution unit 2714 communicates with one or more GPCs 2718 via XBar 2720. In at least one embodiment, XBar 2720 is an interconnect network that couples many units of PPU 2700 to other units of PPU 2700 and can be configured to couple work distribution unit 2714 to a specific GPC 2718. In at least one embodiment, one or more other units of PPU 2700 can also be connected to XBar 2720 through hub 2716.

[0245] In at least one embodiment, tasks are managed by a scheduler unit 2712 and assigned to one of the GPCs 2718 by a work distribution unit 2714. The GPC 2718 is configured to process tasks and produce results. In at least one embodiment, the results can be consumed by other tasks in the GPC 2718, routed to a different GPC 2718 via an XBar 2720, or stored in memory 2704. In at least one embodiment, the results can be written to memory 2704 via a partition unit 2722, which implements a memory interface for writing data to or reading data from memory 2704. In at least one embodiment, the results can be transferred to another PPU 2700 or CPU via a high-speed GPU interconnect 2708. In at least one embodiment, the PPU 2700 includes, but is not limited to, U partition units 2722, which equal the number of separate and distinct memory devices 2704 coupled to the PPU 2700.

[0246] In at least one embodiment, the host processor executes a driver core that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU 2700. In one embodiment, multiple computing applications are executed simultaneously by the PPU 2700, and the PPU 2700 provides isolation, quality of service ("QoS"), and independent address spaces for the multiple computing applications. In at least one embodiment, the application generates instructions (e.g., in the form of API calls) that cause the driver core to generate one or more tasks for execution by the PPU 2700, and the driver core outputs the tasks to one or more streams processed by the PPU 2700. In at least one embodiment, each task includes one or more related thread groups, which may be referred to as warps. In at least one embodiment, a warp includes multiple related threads (e.g., 32 threads) that can execute in parallel. In at least one embodiment, a cooperative thread may refer to multiple threads that include instructions for executing tasks and exchanging data through shared memory.

[0247] Figure 28 FIG2 shows a GPC 2800 according to at least one embodiment. In at least one embodiment, the GPC 2800 is Figure 272718. In at least one embodiment, each GPC 2800 includes, but is not limited to, multiple hardware units for processing tasks, and each GPC 2800 includes, but is not limited to, a pipeline manager 2802, a pre-raster operations unit ("PROP") 2804, a raster engine 2808, a work distribution crossbar ("WDX") 2816, a memory management unit ("MMU") 2818, one or more data processing clusters ("DPCs") 2806, and any suitable combination of components.

[0248] In at least one embodiment, the operation of the GPC 2800 is controlled by a pipeline manager 2802. In at least one embodiment, the pipeline manager 2802 manages the configuration of one or more DPCs 2806 to process tasks assigned to the GPC 2800. In at least one embodiment, the pipeline manager 2802 configures at least one of the one or more DPCs 2806 to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, a DPC 2806 is configured to execute vertex shader programs on a programmable streaming multiprocessor ("SM") 2814. In at least one embodiment, the pipeline manager 2802 is configured to route packets received from a work distribution unit to appropriate logic within the GPC 2800, and in at least one embodiment, some packets may be routed to fixed-function hardware units in the PROP 2804 and / or raster engine 2808, while other packets may be routed to a DPC 2806 for processing by a primitive engine 2812 or an SM 2814. In at least one embodiment, pipeline manager 2802 configures at least one of DPCs 2806 to implement a neural network model and / or a computational pipeline. In at least one embodiment, pipeline manager 2802 configures at least one of DPCs 2806 to execute at least a portion of a CUDA program.

[0249] In at least one embodiment, PROP unit 2804 is configured to route data generated by raster engine 2808 and DPC 2806 to a raster operations ("ROP") unit in a partition unit, such as described above in conjunction with Figure 27Memory partitioning unit 2722, etc., described in more detail. In at least one embodiment, PROP unit 2804 is configured to perform optimizations for color blending, organize pixel data, perform address translation, and the like. In at least one embodiment, raster engine 2808 includes, but is not limited to, a plurality of fixed-function hardware units configured to perform various raster operations, and in at least one embodiment, raster engine 2808 includes, but is not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile aggregation engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices; the plane equations are passed to the coarse raster engine to generate coverage information for the primitives (e.g., an x, y coverage mask for the tile); the output of the coarse raster engine is passed to the culling engine, where fragments associated with primitives that fail the z test are culled, and to the clipping engine, where fragments outside the viewing frustum are clipped. In at least one embodiment, the clipped and culled fragments are passed to a fine raster engine to generate properties for the pixel fragments based on a plane equation generated by the setup engine. In at least one embodiment, the output of the raster engine 2808 includes fragments to be processed by any appropriate entity (e.g., by a fragment shader implemented within the DPC 2806).

[0250] In at least one embodiment, each DPC 2806 included in a GPC 2800 includes, but is not limited to, an M-pipeline controller ("MPC") 2810; a primitive engine 2812; one or more SMs 2814; and any suitable combination thereof. In at least one embodiment, the MPC 2810 controls the operation of the DPC 2806, routing packets received from the pipeline manager 2802 to appropriate units within the DPC 2806. In at least one embodiment, packets associated with vertices are routed to the primitive engine 2812, which is configured to fetch vertex attributes associated with the vertices from memory; conversely, packets associated with shader programs may be sent to the SM 2814.

[0251] In at least one embodiment, SM 2814 includes, but is not limited to, a programmable streaming processor configured to process tasks represented by multiple threads. In at least one embodiment, SM 2814 is multithreaded and configured to simultaneously execute multiple threads (e.g., 32 threads) from a particular thread group and implements a single instruction, multiple data ("SIMD") architecture, in which each thread in a group of threads (e.g., a warp) is configured to process a different set of data based on the same instruction set. In at least one embodiment, all threads in a thread group execute the same instructions. In at least one embodiment, SM 2814 implements a single instruction, multiple thread ("SIMT") architecture, in which each thread in a group of threads is configured to process a different set of data based on the same instruction set, but in which individual threads in a thread group are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each warp, thereby enabling concurrency between warps and serial execution within a warp when threads in the warp diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread, thereby enabling equal concurrency between all threads within a warp and between warps. In at least one embodiment, execution state is maintained for each individual thread, and threads executing the same instruction can be converged and executed in parallel to improve efficiency. Figure 29 At least one embodiment of SM 2814 is described in more detail.

[0252] In at least one embodiment, the MMU 2818 provides a communication channel between the GPC 2800 and the memory partition unit (e.g., Figure 27 The MMU 2818 provides an interface between the memory and the partition unit 2722, and provides virtual to physical address translation, memory protection, and arbitration of memory requests. In at least one embodiment, the MMU 2818 provides one or more translation lookaside buffers ("TLBs") for performing translation of virtual addresses to physical addresses in memory.

[0253] Figure 29 Streaming Multiprocessor ("SM") 2900 is shown in accordance with at least one embodiment. In at least one embodiment, SM 2900 is Figure 28SM 2814. In at least one embodiment, SM 2900 includes, but is not limited to, an instruction cache 2902; one or more scheduler units 2904; a register file 2908; one or more processing cores ("cores") 2910; one or more special function units ("SFUs") 2912; one or more load / store units ("LSUs") 2914; an interconnect network 2916; a shared memory / level 1 ("L1") cache 2918; and any suitable combination thereof. In at least one embodiment, a work distribution unit schedules tasks for execution on a general processing cluster ("GPC") of a parallel processing unit ("PPU"), with each task being assigned to a specific data processing cluster ("DPC") within the GPC, and if the task is associated with a shader program, the task is assigned to one of SMs 2900. In at least one embodiment, scheduler unit 2904 receives tasks from the work distribution unit and manages instruction scheduling for one or more thread blocks assigned to SM 2900. In at least one embodiment, the scheduler unit 2904 schedules thread blocks for execution as warps of parallel threads, where each thread block is assigned at least one warp. In at least one embodiment, each warp executes a thread. In at least one embodiment, the scheduler unit 2904 manages a plurality of different thread blocks, assigns warps to different thread blocks, and then dispatches instructions from a plurality of different cooperating groups to various functional units (e.g., processing cores 2910, SFUs 2912, and LSUs 2914) during each clock cycle.

[0254] In at least one embodiment, "cooperative groups" may refer to a programming model for organizing groups of communicating threads, allowing developers to express the granularity at which threads are communicating, thereby enabling the expression of richer, more efficient decompositions of parallelism. In at least one embodiment, a cooperative launch API supports synchronization between thread blocks to execute parallel algorithms. In at least one embodiment, conventional programming model APIs provide a single, simple construct for synchronizing cooperating threads: a barrier across all threads of a thread block (e.g., the syncthreads() function). However, in at least one embodiment, programmers can define thread groups at a granularity smaller than a thread block and synchronize within the defined group to achieve higher performance, design flexibility, and software reuse in the form of a collective group-wide function interface. In at least one embodiment, cooperative groups enable programmers to explicitly define thread groups at sub-block and multi-block granularity and perform collective operations, such as synchronizing threads within a cooperative group. In at least one embodiment, the sub-block granularity is as small as a single thread. In at least one embodiment, the programming model supports clean composition across software boundaries, allowing libraries and utility functions to safely synchronize within their local environment without making assumptions about convergence. In at least one embodiment, the cooperation group primitive enables new patterns of cooperative parallelism, including but not limited to producer-consumer parallelism, opportunistic parallelism, and global synchronization across an entire grid of thread blocks.

[0255] In at least one embodiment, the dispatch unit 2906 is configured to send instructions to one or more of the functional units, and the scheduler unit 2904 includes, but is not limited to, two dispatch units 2906 that enable two different instructions from the same warp to be dispatched per clock cycle. In at least one embodiment, each scheduler unit 2904 includes a single dispatch unit 2906 or additional dispatch units 2906.

[0256] In at least one embodiment, each SM 2900 includes, but is not limited to, a register file 2908 that provides a set of registers for the functional units of SM 2900. In at least one embodiment, register file 2908 is partitioned between each functional unit, allocating a dedicated portion of register file 2908 to each functional unit. In at least one embodiment, register file 2908 is partitioned between the different warps executed by SM 2900, and register file 2908 provides temporary storage for operands connected to the data paths of the functional units. In at least one embodiment, each SM 2900 includes, but is not limited to, a plurality of L processing cores 2910. In at least one embodiment, SM 2900 includes, but is not limited to, a large number (e.g., 128 or more) of different processing cores 2910. In at least one embodiment, each processing core 2910 includes, but is not limited to, a fully pipelined, single-precision, double-precision, and / or mixed-precision processing unit, including, but not limited to, a floating-point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, the floating-point arithmetic logic unit implements the IEEE 754-2008 standard for floating-point arithmetic. In at least one embodiment, processing core 2910 includes, but is not limited to, 64 single-precision (32-bit) floating point cores, 64 integer cores, 32 double-precision (64-bit) floating point cores, and 8 tensor cores.

[0257] In at least one embodiment, the tensor cores are configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in processing core 2910. In at least one embodiment, the tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inference. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiplication and accumulation operation D=A×B+C, where A, B, C, and D are 4×4 matrices.

[0258] In at least one embodiment, the matrix multiplication inputs A and B are 16-bit floating-point matrices, and the accumulation matrices C and D are 16-bit floating-point or 32-bit floating-point matrices. In at least one embodiment, the tensor core performs a 32-bit floating-point accumulation operation on the 16-bit floating-point input data. In at least one embodiment, the 16-bit floating-point multiplication uses 64 operations and obtains a full-precision product, which is then accumulated with other intermediate products using 32-bit floating-point addition to perform a 4x4x4 matrix multiplication. In at least one embodiment, the tensor core is used to perform larger two-dimensional or higher-dimensional matrix operations composed of these smaller elements. In at least one embodiment, an API (such as the CUDA-C++ API) exposes specialized matrix load, matrix multiplication and accumulation, and matrix store operations to efficiently use the tensor cores from a CUDA-C++ program. In at least one embodiment, at the CUDA level, the warp-level interface assumes a 16×16 matrix size across all 32 warp threads.

[0259] In at least one embodiment, each SM 2900 includes, but is not limited to, M SFUs 2912 that perform specialized functions (e.g., attribute evaluation, reciprocal square root, etc.). In at least one embodiment, the SFUs 2912 include, but are not limited to, tree traversal units configured to traverse a hierarchical tree data structure. In at least one embodiment, the SFUs 2912 include, but are not limited to, texture units configured to perform texture map filtering operations. In at least one embodiment, the texture units are configured to load texture maps (e.g., 2D arrays of texels) from memory and sample the texture maps to generate sampled texture values ​​for use by shader programs executed by the SM 2900. In at least one embodiment, the texture maps are stored in shared memory / L1 cache 2918. In at least one embodiment, the texture units implement texture operations (such as filtering operations) using mip-maps (e.g., texture maps with different levels of detail). In at least one embodiment, each SM 2900 includes, but is not limited to, two texture units.

[0260] In at least one embodiment, each SM 2900 includes, but is not limited to, N LSUs 2914 that implement load and store operations between the shared memory / L1 cache 2918 and the register file 2908. In at least one embodiment, each SM 2900 includes, but is not limited to, an interconnection network 2916 that connects each functional unit to the register file 2908, and the LSUs 2914 connect to the register file 2908 and the shared memory / L1 cache 2918. In at least one embodiment, the interconnection network 2916 is a crossbar switch that can be configured to connect any functional unit to any register in the register file 2908, and to connect the LSUs 2914 to memory locations in the register file 2908 and the shared memory / L1 cache 2918.

[0261] In at least one embodiment, shared memory / L1 cache 2918 is an array of on-chip memory that, in at least one embodiment, allows for data storage and communication between the SM 2900 and the primitive engines, as well as between threads within the SM 2900. In at least one embodiment, shared memory / L1 cache 2918 includes, but is not limited to, 128KB of storage capacity and is located in the path from the SM 2900 to the partition unit. In at least one embodiment, shared memory / L1 cache 2918 is used, in at least one embodiment, to cache reads and writes. In at least one embodiment, one or more of shared memory / L1 cache 2918, L2 cache, and memory is a backing store.

[0262] In at least one embodiment, combining data cache and shared memory functionality into a single memory block provides improved performance for both types of memory accesses. In at least one embodiment, capacity is used by programs that do not utilize the shared memory or as a cache. For example, if the shared memory is configured to use half of its capacity, texture and load / store operations can use the remaining capacity. According to at least one embodiment, integration within the shared memory / L1 cache 2918 enables the shared memory / L1 cache 2918 to function as a high-throughput pipeline for streaming data, while providing high-bandwidth and low-latency access to frequently reused data. In at least one embodiment, when configured for general-purpose parallel computing, a simpler configuration can be used compared to graphics processing. In at least one embodiment, the fixed-function GPU is bypassed, creating a simpler programming model. In at least one embodiment, in a general-purpose parallel computing configuration, the work distribution unit directly allocates and distributes blocks of threads to DPCs. In at least one embodiment, threads in a block execute the same program, use unique thread IDs in computations to ensure each thread generates unique results, use SM 2900 to execute the program and perform computations, use shared memory / L1 cache 2918 to communicate between threads, and use LSU 2914 to read and write global memory through shared memory / L1 cache 2918 and a memory partitioning unit. In at least one embodiment, when configured for general-purpose parallel computation, SM 2900 writes commands to scheduler unit 2904 that can be used to start new work on a DPC.

[0263] In at least one embodiment, the PPU is included in or coupled to a desktop computer, laptop computer, tablet computer, server, supercomputer, smartphone (e.g., wireless, handheld device), PDA, digital camera, vehicle, head-mounted display, handheld electronic device, etc. In at least one embodiment, the PPU is implemented on a single semiconductor substrate. In at least one embodiment, the PPU is included in a system-on-chip ("SoC") along with one or more other devices (e.g., additional PPUs, memory, a RISC CPU, an MMU, a digital-to-analog converter ("DAC"), etc.).

[0264] In at least one embodiment, the PPU can be included on a graphics card that includes one or more storage devices. The graphics card can be configured to connect to a PCIe slot on a desktop computer motherboard. In at least one embodiment, the PPU can be an integrated GPU ("iGPU") included in a chipset on the motherboard.

[0265] Software Construction for General Computing

[0266] The following figures illustrate, but are not limited to, example software architectures for implementing at least one embodiment.

[0267] Figure 30 A software stack for a programming platform according to at least one embodiment is shown. In at least one embodiment, a programming platform is a platform for utilizing hardware on a computing system to accelerate computing tasks. In at least one embodiment, a software developer can access the programming platform through libraries, compiler directives, and / or extensions to a programming language. In at least one embodiment, the programming platform can be, but is not limited to, CUDA, Radeon Open Compute Platform ("ROCm"), OpenCL (OpenCL developed by Khronos group), TM ), SYCL, or Intel One API.

[0268] In at least one embodiment, the programming platform's software stack 3000 provides an execution environment for an application 3001. In at least one embodiment, the application 3001 may include any computer software capable of being launched on the software stack 3000. In at least one embodiment, the application 3001 may include, but is not limited to, artificial intelligence ("AI") / machine learning ("ML") applications, high performance computing ("HPC") applications, virtual desktop infrastructure ("VDI"), or data center workloads.

[0269] In at least one embodiment, the application 3001 and the software stack 3000 run on hardware 3007. In at least one embodiment, the hardware 3007 may include one or more GPUs, CPUs, FPGAs, AI engines, and / or other types of computing devices that support a programming platform. In at least one embodiment, for example, using CUDA, the software stack 3000 may be vendor-specific and only compatible with devices from a specific vendor. In at least one embodiment, for example, using OpenCL, the software stack 3000 can be used with devices from different vendors. In at least one embodiment, the hardware 3007 includes a host connected to one or more devices that can be accessed via application programming interface (API) calls to perform computing tasks. In at least one embodiment, compared to the host within the hardware 3007, which may include but is not limited to a CPU (but may also include a computing device) and its memory, the devices within the hardware 3007 may include but are not limited to a GPU, FPGA, AI engine, or other computing device (but may also include a CPU) and its memory.

[0270] In at least one embodiment, the programming platform's software stack 3000 includes, but is not limited to, a plurality of libraries 3003, a runtime 3005, and device kernel drivers 3006. In at least one embodiment, each of the libraries 3003 may include data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, the libraries 3003 may include, but are not limited to, pre-written code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. In at least one embodiment, the libraries 3003 include functions optimized for execution on one or more types of devices. In at least one embodiment, the libraries 3003 may include, but are not limited to, functions for performing mathematical, deep learning, and / or other types of operations on the devices. In at least one embodiment, the libraries 3003 are associated with corresponding APIs 3002, which may include one or more APIs that expose the functions implemented in the libraries 2903.

[0271] In at least one embodiment, the application 3001 is written as source code that is compiled into executable code as follows: Figures 35-37 3001 can be run at least in part on an execution environment provided by software stack 3000. In at least one embodiment, during the execution of application 3001, code that needs to be run on a device (as opposed to a host) can be obtained. In this case, in at least one embodiment, runtime 3005 can be called to load and start the necessary code on the device. In at least one embodiment, runtime 3005 can include any technically feasible runtime system capable of supporting the execution of application 3001.

[0272] In at least one embodiment, runtime 3005 is implemented as one or more runtime libraries associated with a corresponding API (shown as API 3004). In at least one embodiment, one or more such runtime libraries may include, but are not limited to, functions for memory management, execution control, device management, error handling, and / or synchronization, among others. In at least one embodiment, memory management functions may include, but are not limited to, functions for allocating, deallocating, and copying device memory, and for transferring data between host memory and device memory. In at least one embodiment, execution control functions may include, but are not limited to, functions for launching functions on the device (sometimes referred to as "kernels" when the function is a global function callable from the host), and functions for setting property values ​​in buffers maintained by the runtime library for a given function to be executed on the device.

[0273] In at least one embodiment, the runtime library and corresponding API 3004 can be implemented in any technically feasible manner. In at least one embodiment, one (or any number of) APIs can expose a low-level set of functions for fine-grained control of a device, while another (or any number of) APIs can expose such a higher-level set of functions. In at least one embodiment, a high-level runtime API can be built on top of the low-level APIs. In at least one embodiment, one or more runtime APIs can be language-specific APIs layered on top of a language-independent runtime API.

[0274] In at least one embodiment, the device kernel driver 3006 is configured to facilitate communication with the underlying device. In at least one embodiment, the device kernel driver 3006 can provide APIs such as API 3004 and / or low-level functions that other software relies on. In at least one embodiment, the device kernel driver 3006 can be configured to compile intermediate representation ("IR") code into binary code at runtime. In at least one embodiment, for CUDA, the device kernel driver 3006 can compile non-hardware-specific parallel thread execution ("PTX") IR code into binary code for a specific target device at runtime (caching the compiled binary code), which is sometimes also referred to as "final" code. In at least one embodiment, doing so can allow the final code to run on a target device that may not have existed when the source code was originally compiled into PTX code. Alternatively, in at least one embodiment, the device source code can be compiled into binary code offline without the need for the device kernel driver 3006 to compile the IR code at runtime.

[0275] Figure 31 According to at least one embodiment, Figure 30 3100. In at least one embodiment, the CUDA software stack 3100, on which the application 3101 can be launched, includes a CUDA library 3103, a CUDA runtime 3105, a CUDA driver 3107, and a device kernel driver 3108. In at least one embodiment, the CUDA software stack 3100 executes on hardware 3109, which may include a CUDA-enabled GPU developed by NVIDIA Corporation of Santa Clara, California.

[0276] In at least one embodiment, the application 3101, the CUDA runtime 3105, and the device kernel driver 3108 can perform functions similar to the application 3001, the runtime 3005, and the device kernel driver 3006, respectively. Figure 303106 . In at least one embodiment, the CUDA driver 3107 includes a library (libcuda.so) that implements the CUDA driver API 3106. In at least one embodiment, similar to the CUDA runtime API 3104 implemented by the CUDA runtime library (cudart), the CUDA driver API 3106 may expose, but is not limited to, functions for memory management, execution control, device management, error handling, synchronization, and / or graphics interoperability. In at least one embodiment, the CUDA driver API 3106 differs from the CUDA runtime API 3104 in that the CUDA runtime API 3104 simplifies device code management by providing implicit initialization, context (similar to process) management, and module (similar to dynamically loaded libraries) management. In contrast to the high-level CUDA runtime API 3104, in at least one embodiment, the CUDA driver API 3106 is a low-level API that provides finer-grained control over the device, particularly with respect to context and module loading. In at least one embodiment, the CUDA driver API 3106 may expose functions for context management that are not exposed by the CUDA runtime API 3104. In at least one embodiment, the CUDA driver API 3106 is also language-independent and supports, for example, OpenCL in addition to the CUDA runtime API 3104. Furthermore, in at least one embodiment, the development libraries, including the CUDA runtime 3105, can be considered separate from the driver components, including the user-mode CUDA driver 3107 and the kernel-mode device driver 3108 (sometimes also referred to as a "display" driver).

[0277] In at least one embodiment, the CUDA libraries 3103 may include, but are not limited to, mathematical libraries, deep learning libraries, parallel algorithm libraries, and / or signal / image / video processing libraries, which can be utilized by parallel computing applications (e.g., application 3101). In at least one embodiment, the CUDA libraries 3103 may include mathematical libraries, such as the cuBLAS library, which is an implementation of the Basic Linear Algebra Subroutines ("BLAS") for performing linear algebra operations; the cuFFT library for computing fast Fourier transforms ("FFTs"), and the cuRAND library for generating random numbers. In at least one embodiment, the CUDA libraries 3103 may include deep learning libraries, such as the cuDNN library for primitives for deep neural networks and the TensorRT platform for high-performance deep learning inference.

[0278] Figure 32 According to at least one embodiment, Figure 303200 . In at least one embodiment, the ROCm software stack 3200 , on which an application 3201 can be launched, includes a language runtime 3203 , a system runtime 3205 , thunks 3207 , and a ROCm kernel driver 3208 . In at least one embodiment, the ROCm software stack 3200 executes on hardware 3209 , which may include a ROCm-enabled GPU developed by AMD, Inc. of Santa Clara, California.

[0279] In at least one embodiment, application 3201 may execute a combination of the above Figure 30 In addition, in at least one embodiment, the language runtime 3203 and the system runtime 3205 can perform functions similar to those described above in conjunction with the application 3001. Figure 30 3205. In at least one embodiment, the language runtime 3203 differs from the system runtime 3205 in that the system runtime 3205 is a language-agnostic runtime that implements the ROCr system runtime API 3204 and leverages the Heterogeneous System Architecture ("HSA") runtime API. In at least one embodiment, the HSA runtime API is a thin user-mode API that exposes interfaces for accessing and interacting with the AMD GPU, including functions for memory management, execution control of kernels dispatched by the architecture, error handling, system and agent information, and runtime initialization and shutdown. In at least one embodiment, compared to the system runtime 3205, the language runtime 3203 is an implementation of a language-specific runtime API 3202 layered on top of the ROCr system runtime API 3204. In at least one embodiment, the language runtime API may include, but is not limited to, a portable heterogeneous compute interface ("HIP") language runtime API, a heterogeneous compute compiler ("HCC") language runtime API, or an OpenCL API, among others. In particular, the HIP language is an extension of the C++ programming language with a functionally similar version of the CUDA mechanism, and in at least one embodiment, the HIP language runtime API includes a Figure 31 Similar functions to the CUDA runtime API 3104 are discussed, such as those used for memory management, execution control, device management, error handling, and synchronization.

[0280] In at least one embodiment, thunk (ROCt) 3207 is an interface that can be used to interact with the underlying ROCm driver 3208. In at least one embodiment, the ROCm driver 3208 is a ROCk driver, which is a combination of the AMDGPU driver and the HSA kernel driver (amdkfd). In at least one embodiment, the AMDGPU driver is a device kernel driver for GPUs developed by AMD that performs the above combined Figure 30 The HSA kernel driver 3006 may function similarly to the discussed device kernel driver 3006. In at least one embodiment, the HSA kernel driver is a driver that allows different types of processors to more efficiently share system resources via hardware features.

[0281] In at least one embodiment, various libraries (not shown) may be included in the ROCm software stack 3200 above the language runtime 3203 and provide Figure 31 The various libraries may include, but are not limited to, math, deep learning, and / or other libraries, such as a hipBLAS library that implements functions similar to CUDA cuBLAS, a rocFFT library similar to CUDA cuFFT for computing FFTs, and the like.

[0282] Figure 33 According to at least one embodiment, Figure 30 3300. In at least one embodiment, the OpenCL software stack 3300, on which an application 3301 can be launched, includes an OpenCL framework 3305, an OpenCL runtime 3306, and a driver 3307. In at least one embodiment, the OpenCL software stack 3300 executes on hardware 3109 that is not vendor-specific. In at least one embodiment, because devices developed by different vendors support OpenCL, specific OpenCL drivers may be required to interoperate with hardware from such vendors.

[0283] In at least one embodiment, the application 3301, the OpenCL runtime 3306, the device kernel driver 3307 and the hardware 3308 can each execute in conjunction with the above Figure 30 Similar functionality is discussed for application 3001, runtime 3005, device kernel driver 3006, and hardware 3007. In at least one embodiment, application 3301 also includes an OpenCL kernel 3302 having code to be executed on the device.

[0284] In at least one embodiment, OpenCL defines a "platform" that allows a host to control devices connected to the host. In at least one embodiment, the OpenCL framework provides a platform layer API and a runtime API, shown as platform API 3303 and runtime API 3305. In at least one embodiment, runtime API 3305 uses contexts to manage the execution of kernels on devices. In at least one embodiment, each identified device can be associated with a respective context, which runtime API 3305 can use to manage the device's command queue, program and kernel objects, shared memory objects, and the like. In at least one embodiment, platform API 3303 exposes functions that allow device contexts to be used to select and initialize devices, submit work to devices via command queues, and enable data transfer to and from devices. Additionally, in at least one embodiment, the OpenCL framework provides various built-in functions (not shown), including mathematical functions, relational functions, image processing functions, and the like.

[0285] In at least one embodiment, compiler 3304 is also included in OpenCL framework 3305. In at least one embodiment, source code can be compiled offline before executing the application or compiled online during execution of the application. In contrast to CUDA and ROCm, OpenCL applications in at least one embodiment can be compiled online by compiler 3304, which is included to represent any number of compilers that can be used to compile source code and / or IR code (e.g., Standard Portable Intermediate Representation ("SPIR-V") code) into binary code. Alternatively, in at least one embodiment, OpenCL applications can be compiled offline before executing such applications.

[0286] Figure 34 Software supported by a programming platform according to at least one embodiment is shown. In at least one embodiment, programming platform 3404 is configured to support various programming models 3403, middleware and / or libraries 3402, and frameworks 3401 that applications 3400 can rely on. In at least one embodiment, application 3400 can be an AI / ML application implemented using, for example, a deep learning framework (e.g., MXNet, PyTorch, or TensorFlow), which can rely on libraries such as cuDNN, NVIDIA Collective Communications Library ("NCCL"), and / or NVIDIA Developer Data Loading Library ("DALI") CUDA libraries to provide accelerated computation on the underlying hardware.

[0287] In at least one embodiment, the programming platform 3404 can be a combination of the above Figure 31 、 Figure 32 and Figure 33 In at least one embodiment, the programming platform 3404 supports one of the CUDA, ROCm, or OpenCL platforms described herein. In at least one embodiment, the programming platform 3404 supports multiple programming models 3403, which are abstractions of the underlying computing system that allow the expression of algorithms and data structures. In at least one embodiment, the programming model 3403 can expose features of the underlying hardware to improve performance. In at least one embodiment, the programming model 3403 can include, but is not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism ("C++AMP"), Open Multiprocessing ("OpenMP"), Open Accelerators ("OpenACC"), and / or Vulcan Compute.

[0288] In at least one embodiment, the library and / or middleware 3402 provides an abstract implementation of the programming model 3404. In at least one embodiment, such a library includes data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, in addition to those that can be obtained from the programming platform 3404, such middleware also includes software that provides services to the application. In at least one embodiment, the library and / or middleware 3402 may include but is not limited to cuBLAS, cuFFT, cuRAND and other CUDA libraries, or rocBLAS, rocFFT, rocRAND and other ROCm libraries. In addition, in at least one embodiment, the library and / or middleware 3402 may include NCCL and ROCm communication collection libraries ("RCCL") libraries that provide communication routines for GPUs, MIOpen libraries for deep learning acceleration and / or intrinsic libraries for linear algebra, matrix and vector operations, geometric transformations, numerical solvers, and related algorithms.

[0289] In at least one embodiment, application framework 3401 relies on libraries and / or middleware 3402. In at least one embodiment, each application framework 3401 is a software framework for implementing a standard structure for application software. Returning to the AI / ML example discussed above, in at least one embodiment, AI / ML applications can be implemented using a framework such as Caffe, Caffe2, TensorFlow, Keras, PyTorch, or MxNet deep learning framework.

[0290] Figure 35 Compiled code is shown in accordance with at least one embodiment to Figures 30-33In at least one embodiment, compiler 3501 receives source code 3500, which includes both host code and device code. In at least one embodiment, compiler 3501 is configured to convert source code 3500 into host executable code 3502 for execution on the host and device executable code 3503 for execution on the device. In at least one embodiment, source code 3500 can be compiled offline before executing the application, or compiled online during execution of the application.

[0291] In at least one embodiment, source code 3500 may include code in any programming language supported by compiler 3501, such as C++, C, Fortran, etc. In at least one embodiment, source code 3500 may be included in a single-source file having a mixture of host code and device code, with the location of the device code indicated therein. In at least one embodiment, the single-source file may be a .cu file including CUDA code or a .hip.cpp file including HIP code. Alternatively, in at least one embodiment, source code 3500 may include multiple source code files, rather than a single source file, in which host code and device code are separated.

[0292] In at least one embodiment, compiler 3501 is configured to compile source code 3500 into host executable code 3502 for execution on a host and device executable code 3503 for execution on a device. In at least one embodiment, compiler 3501 performs operations including parsing source code 3500 into an abstract system tree (AST), performing optimizations, and generating executable code. In at least one embodiment where source code 3500 comprises a single source file, compiler 3501 may separate device code from host code in such a single source file, compile the device code and host code into device executable code 3503 and host executable code 3502, respectively, and link device executable code 3503 and host executable code 3502 together in a single file, as described below with respect to Figure 36 discussed in more detail.

[0293] In at least one embodiment, host executable code 3502 and device executable code 3503 may be in any suitable format, such as binary code and / or IR code. In the case of CUDA, in at least one embodiment, host executable code 3502 may include native object code, while device executable code 3503 may include code in a PTX intermediate representation. In at least one embodiment, in the case of ROCm, both host executable code 3502 and device executable code 3503 may include target binary code.

[0294] Figure 36 is compiled code according to at least one embodiment to Figures 30-33 36. In at least one embodiment, compiler 3601 is configured to receive source code 3600, compile source code 3600, and output executable file 3608. In at least one embodiment, source code 3600 is a single source file, such as a .cu file, a .hip.cpp file, or a file in another format, that includes both host code and device code. In at least one embodiment, compiler 3601 can be, but is not limited to, the NVIDIA CUDA compiler ("NVCC") for compiling CUDA code in .cu files, or the HCC compiler for compiling HIP code in .hip.cpp files.

[0295] In at least one embodiment, compiler 3601 includes a compiler front end 3602, a host compiler 3605, a device compiler 3606, and a linker 3609. In at least one embodiment, compiler front end 3602 is configured to separate device code 3604 from host code 3603 in source code 3600. In at least one embodiment, device code 3604 is compiled by device compiler 3606 into device executable code 3608, which, as described, may include binary code or IR code. In at least one embodiment, host code 3603 is separately compiled by host compiler 3605 into host executable code 3607. In at least one embodiment, for NVCC, host compiler 3605 may be, but is not limited to, a general-purpose C / C++ compiler that outputs native object code, while device compiler 3606 may be, but is not limited to, a Low-Level Virtual Machine ("LLVM")-based compiler that forks the LLVM compiler infrastructure and outputs PTX code or binary code. In at least one embodiment, for HCC, both host compiler 3605 and device compiler 3606 can be, but are not limited to, LLVM-based compilers that output target binary code.

[0296] In at least one embodiment, after source code 3600 is compiled into host executable code 3607 and device executable code 3608, linker 3609 links host and device executable code 3607 and 3608 together in executable file 3610. In at least one embodiment, native object code for the host and PTX or binary code for the device may be linked together in an Executable and Linkable Format ("ELF") file, which is a container format for storing object code.

[0297] Figure 373702. Figure 35 discussed.

[0298] In at least one embodiment, the conversion performed by the conversion tool 3701 is used to port the source code 3700 for execution in an environment different from that on which it was originally intended to run. In at least one embodiment, the conversion tool 3701 may include, but is not limited to, a HIP converter for "hipifying" CUDA code for a CUDA platform into HIP code that can be compiled and executed on a ROCm platform. In at least one embodiment, the conversion of the source code 3700 may include parsing the source code 3700 and converting calls to APIs provided by one programming model (e.g., CUDA) to corresponding calls to APIs provided by another programming model (e.g., HIP), as described below in conjunction with Figures 38A-39 Returning to the example of porting CUDA code, in at least one embodiment, calls to the CUDA runtime API, the CUDA driver API, and / or the CUDA library can be converted to corresponding HIP API calls. In at least one embodiment, the automatic conversion performed by the conversion tool 3701 may sometimes be incomplete, requiring additional manual effort to fully port the source code 3700.

[0299] Configuring GPUs for general computing

[0300] The following figures illustrate, but are not limited to, example architectures for compiling and executing computing source code in accordance with at least one embodiment.

[0301] Figure 38AA system 3800 is shown configured to compile and execute CUDA source code 3810 using different types of processing units in accordance with at least one embodiment. In at least one embodiment, the system 3800 includes, but is not limited to, CUDA source code 3810, a CUDA compiler 3850, a host executable 3870(1), a host executable 3870(2), a CUDA device executable 3884, a CPU 3890, a CUDA-enabled GPU 3894, a GPU 3892, a CUDA to HIP conversion tool 3820, HIP source code 3830, a HIP compiler driver 3840, an HCC 3860, and an HCC device executable 3882.

[0302] In at least one embodiment, CUDA source code 3810 is a collection of human-readable code in the CUDA programming language. In at least one embodiment, CUDA code is human-readable code in the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension of the C++ programming language that includes, but is not limited to, mechanisms for defining device code and distinguishing between device code and host code. In at least one embodiment, device code is source code that can be executed in parallel on a device after compilation. In at least one embodiment, the device can be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU 3890, GPU 3892, or another GPGPU. In at least one embodiment, host code is source code that can be executed on a host after compilation. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as a CPU 3890.

[0303] In at least one embodiment, CUDA source code 3810 includes, but is not limited to, any number (including zero) of global functions 3812, any number (including zero) of device functions 3814, any number (including zero) of host functions 3816, and any number (including zero) of host / device functions 3818. In at least one embodiment, global functions 3812, device functions 3814, host functions 3816, and host / device functions 3818 can be intermixed within CUDA source code 3810. In at least one embodiment, each global function 3812 is executable on the device and callable from the host. Thus, in at least one embodiment, one or more of the global functions 3812 can serve as an entry point for the device. In at least one embodiment, each global function 3812 is a kernel. In at least one embodiment, and in a technique known as dynamic parallelism, one or more global functions 3812 define a kernel that is executable on and callable from a device. In at least one embodiment, the kernel is executed N times (where N is any positive integer) in parallel by N different threads on the device during execution.

[0304] In at least one embodiment, each device function 3814 executes on a device and can only be called from such a device. In at least one embodiment, each host function 3816 executes on a host and can only be called from such a host. In at least one embodiment, each host / device function 3816 defines both a host version of the function that is executable on the host and can only be called from such a host, and a device version of the function that is executable on a device and can only be called from such a device.

[0305] In at least one embodiment, CUDA source code 3810 may also include, but is not limited to, any number of calls to any number of functions defined by the CUDA runtime API 3802. In at least one embodiment, the CUDA runtime API 3802 may include, but is not limited to, any number of functions executed on the host for allocating and deallocating device memory, transferring data between host and device memory, managing systems with multiple devices, and the like. In at least one embodiment, CUDA source code 3810 may also include, but is not limited to, any number of calls to any number of functions specified in any number of other CUDA APIs. In at least one embodiment, a CUDA API may be any API designed for use by CUDA code. In at least one embodiment, CUDA APIs include, but are not limited to, the CUDA runtime API 3802, the CUDA driver API, APIs for any number of CUDA libraries, and the like. In at least one embodiment, and relative to the CUDA runtime API 3802, the CUDA driver API is a lower-level API that provides finer-grained control over the device. In at least one embodiment, examples of CUDA libraries include, but are not limited to, cuBLAS, cuFFT, cuRAND, cuDNN, and the like.

[0306] In at least one embodiment, the CUDA compiler 3850 compiles input CUDA code (e.g., CUDA source code 3810) to generate host executable code 3870(1) and CUDA device executable code 3884. In at least one embodiment, the CUDA compiler 3850 is NVCC. In at least one embodiment, the host executable code 3870(1) is a compiled version of the host code included in the input source code that is executable on the CPU 3890. In at least one embodiment, the CPU 3890 can be any processor optimized for sequential instruction processing.

[0307] In at least one embodiment, the CUDA device executable code 3884 is a compiled version of the device code included in the input source code that is executable on the CUDA-enabled GPU 3894. In at least one embodiment, the CUDA device executable code 3884 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3884 includes, but is not limited to, IR code, such as PTX code, which is further compiled by a device driver at runtime into binary code for a specific target device (e.g., a CUDA-enabled GPU 3894). In at least one embodiment, the CUDA-enabled GPU 3894 can be any processor optimized for parallel instruction processing and that supports CUDA. In at least one embodiment, the CUDA-enabled GPU 3894 was developed by NVIDIA Corporation of Santa Clara, California.

[0308] In at least one embodiment, the CUDA to HIP conversion tool 3820 is configured to convert CUDA source code 3810 into functionally similar HIP source code 3830. In at least one embodiment, the HIP source code 3830 is a collection of human-readable code in the HIP programming language. In at least one embodiment, the HIP code is human-readable code in the HIP programming language. In at least one embodiment, the HIP programming language is an extension of the C++ programming language and includes, but is not limited to, a functionally similar version of the CUDA mechanisms for defining device code and distinguishing between device code and host code. In at least one embodiment, the HIP programming language may include a subset of the functionality of the CUDA programming language. In at least one embodiment, for example, the HIP programming language includes, but is not limited to, mechanisms for defining global functions 3812. However, such a HIP programming language may lack support for dynamic parallelism, and therefore, global functions 3812 defined in the HIP code are only callable from the host.

[0309] In at least one embodiment, HIP source code 3830 includes, but is not limited to, any number (including zero) of global functions 3812, any number (including zero) of device functions 3814, any number (including zero) of host functions 3816, and any number (including zero) of host / device functions 3818. In at least one embodiment, HIP source code 3830 may also include any number of calls to any number of functions specified in HIP runtime API 3832. In one embodiment, HIP runtime API 3832 includes, but is not limited to, functionally similar versions of a subset of functions included in CUDA runtime API 3802. In at least one embodiment, HIP source code 3830 may also include any number of calls to any number of functions specified in any number of other HIP APIs. In at least one embodiment, a HIP API may be any API designed for use by HIP code and / or ROCm. In at least one embodiment, HIP APIs include, but are not limited to, HIP runtime API 3832, HIP driver APIs, APIs for any number of HIP libraries, APIs for any number of ROCm libraries, and the like.

[0310] In at least one embodiment, the CUDA to HIP conversion tool 3820 converts each kernel call in the CUDA code from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the CUDA code to any number of other functionally similar HIP calls. In at least one embodiment, a CUDA call is a call to a function specified in the CUDA API, and a HIP call is a call to a function specified in the HIP API. In at least one embodiment, the CUDA to HIP conversion tool 3820 converts any number of calls to functions specified in the CUDA runtime API 3802 to any number of calls to functions specified in the HIP runtime API 3832.

[0311] In at least one embodiment, the CUDA to HIP conversion tool 3820 is a tool called hipify-perl, which performs a text-based conversion process. In at least one embodiment, the CUDA to HIP conversion tool 3820 is a tool called hipify-clang, which performs a more complex and robust conversion process than hipify-perl, which involves parsing the CUDA code using clang (a compiler front end) and then converting the resulting symbols. In at least one embodiment, in addition to those modifications performed by the CUDA to HIP conversion tool 3820, correctly converting the CUDA code to HIP code may require modifications (e.g., manual editing).

[0312] In at least one embodiment, HIP compiler driver 3840 is a front end that determines target device 3846 and then configures a compiler compatible with target device 3846 to compile HIP source code 3830. In at least one embodiment, target device 3846 is a processor optimized for parallel instruction processing. In at least one embodiment, HIP compiler driver 3840 can determine target device 3846 in any technically feasible manner.

[0313] In at least one embodiment, if the target device 3846 is CUDA compatible (e.g., a CUDA-enabled GPU 3894), the HIP compiler driver 3840 generates HIP / NVCC compile commands 3842. In at least one embodiment and in conjunction with Figure 38B As described in more detail, HIP / NVCC compile command 3842 configures CUDA compiler 3850 to use, but not limited to, HIP to CUDA translation headers and CUDA runtime libraries to compile HIP source code 3830. In at least one embodiment and in response to HIP / NVCC compile command 3842, CUDA compiler 3850 generates host executable code 3870(1) and CUDA device executable code 3884.

[0314] In at least one embodiment, if the target device 3846 is not CUDA compatible, the HIP compiler driver 3840 generates HIP / HCC compilation commands 3844. In at least one embodiment and as in conjunction with Figure 38C As described in more detail, HIP / HCC compile command 3844 configures HCC 3860 to compile HIP source code 3830 using the HCC headers and HIP / HCC runtime libraries. In at least one embodiment and in response to HIP / HCC compile command 3844, HCC 3860 generates host executable code 3870(2) and HCC device executable code 3882. In at least one embodiment, HCC device executable code 3882 is a compiled version of the device code contained in HIP source code 3830 that can be executed on GPU 3892. In at least one embodiment, GPU 3892 can be any processor optimized for parallel instruction processing, not compatible with CUDA, and compatible with HCC. In at least one embodiment, GPU 3892 is developed by AMD, Inc. of Santa Clara, California. In at least one embodiment, GPU 3892 is a non-CUDA-enabled GPU 3892.

[0315] For illustrative purposes only, Figure 38A3890 and different devices. In at least one embodiment, three different flows that can be implemented to compile CUDA source code 3810 for execution on a CPU 3890 and different devices are depicted. In at least one embodiment, the direct CUDA flow compiles CUDA source code 3810 for execution on a CPU 3890 and a CUDA-enabled GPU 3894 without converting the CUDA source code 3810 into HIP source code 3830. In at least one embodiment, the indirect CUDA flow converts CUDA source code 3810 into HIP source code 3830 and then compiles the HIP source code 3830 for execution on a CPU 3890 and a CUDA-enabled GPU 3894. In at least one embodiment, the CUDA / HCC flow converts CUDA source code 3810 into HIP source code 3830 and then compiles the HIP source code 3830 for execution on a CPU 3890 and a GPU 3892.

[0316] A direct CUDA flow that can be implemented in at least one embodiment can be depicted by a dashed line and a series of bubble annotations A1-A3. In at least one embodiment, and as indicated by bubble annotation A1, a CUDA compiler 3850 receives a CUDA source code 3810 and a CUDA compile command 3848 that configures the CUDA compiler 3850 to compile the CUDA source code 3810. In at least one embodiment, the CUDA source code 3810 used in the direct CUDA flow is written in the CUDA programming language, which is based on a programming language other than C++ (e.g., C, Fortran, Python, Java, etc.). In at least one embodiment, and in response to the CUDA compile command 3848, the CUDA compiler 3850 generates a host executable code 3870 (1) and a CUDA device executable code 3884 (indicated by bubble annotation A2). In at least one embodiment and as indicated by bubble annotation A3, the host executable code 3870 (1) and the CUDA device executable code 3884 can be executed on a CPU 3890 and a CUDA-enabled GPU 3894, respectively. In at least one embodiment, the CUDA device executable code 3884 includes but is not limited to binary code. In at least one embodiment, the CUDA device executable code 3884 includes but is not limited to PTX code and is further compiled into binary code for a specific target device at runtime.

[0317] The indirect CUDA flow that can be implemented in at least one embodiment can be depicted by the dashed line and a series of bubble notes B1-B6. In at least one embodiment and as indicated by bubble note B1, a CUDA to HIP conversion tool 3820 receives CUDA source code 3810. In at least one embodiment and as indicated by bubble note B2, the CUDA to HIP conversion tool 3820 converts the CUDA source code 3810 into HIP source code 3830. In at least one embodiment and as indicated by bubble note B3, a HIP compiler driver 3840 receives the HIP source code 3830 and determines whether the target device 3846 is CUDA-enabled.

[0318] In at least one embodiment and as indicated by bubble note B4, the HIP compiler driver 3840 generates HIP / NVCC compile commands 3842 and sends both the HIP / NVCC compile commands 3842 and the HIP source code 3830 to the CUDA compiler 3850. Figure 38B As described in more detail, the HIP / NVCC compile command 3842 configures the CUDA compiler 3850 to compile the HIP source code 3830 using, but not limited to, the HIP to CUDA translation header and the CUDA runtime library. In at least one embodiment and in response to the HIP / NVCC compile command 3842, the CUDA compiler 3850 generates host executable code 3870 (1) and CUDA device executable code 3884 (indicated by bubble comment B5). In at least one embodiment and as indicated by bubble comment B6, the host executable code 3870 (1) and the CUDA device executable code 3884 can be executed on a CPU 3890 and a CUDA-enabled GPU 3894, respectively. In at least one embodiment, the CUDA device executable code 3884 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3884 includes, but is not limited to, PTX code and is further compiled into binary code for a specific target device at runtime.

[0319] The CUDA / HCC process that can be implemented in at least one embodiment can be described by a solid line and a series of bubble comments C1-C6. In at least one embodiment and as indicated by bubble comment C1, a CUDA to HIP conversion tool 3820 receives CUDA source code 3810. In at least one embodiment and as indicated by bubble comment C2, the CUDA to HIP conversion tool 3820 converts the CUDA source code 3810 into HIP source code 3830. In at least one embodiment and as indicated by bubble comment C3, a HIP compiler driver 3840 receives the HIP source code 3830 and determines that the target device 3846 is not CUDA-enabled.

[0320] In at least one embodiment, the HIP compiler driver 3840 generates HIP / HCC compile commands 3844 and sends both the HIP / HCC compile commands 3864 and the HIP source code 3830 to the HCC 3860 (indicated by bubble comment C4). Figure 38C As described in more detail, HIP / HCC compile command 3864 configures HCC 3860 to compile HIP source code 3830 using, but not limited to, HCC headers and HIP / HCC runtime libraries. In at least one embodiment and in response to HIP / HCC compile command 3844, HCC 3860 generates host executable code 3870(2) and HCC device executable code 3882 (indicated by bubble comment C5). In at least one embodiment and as indicated by bubble comment C6, host executable code 3870(2) and HCC device executable code 3882 can be executed on CPU 3890 and GPU 3892, respectively.

[0321] In at least one embodiment, after converting the CUDA source code 3810 to the HIP source code 3830, the HIP compiler driver 3840 can then be used to generate executable code for the CUDA-enabled GPU 3894 or GPU 3892 without having to re-implement the CUDA to HIP conversion tool 3820. In at least one embodiment, the CUDA to HIP conversion tool 3820 converts the CUDA source code 3810 to the HIP source code 3830, which is then stored in memory. In at least one embodiment, the HIP compiler driver 3840 then configures the HCC 3860 to generate a host executable code 3870 (2) and an HCC device executable code 3882 based on the HIP source code 3830. In at least one embodiment, the HIP compiler driver 3840 then configures the CUDA compiler 3850 to generate a host executable code 3870 (1) and a CUDA device executable code 3884 based on the stored HIP source code 3830.

[0322] Figure 38B 3890 and a CUDA-enabled GPU 3894 configured to compile and execute Figure 38A In at least one embodiment, the system 3804 includes, but is not limited to, CUDA source code 3810, a CUDA to HIP conversion tool 3820, HIP source code 3830, a HIP compiler driver 3840, a CUDA compiler 3850, a host executable 3870(1), a CUDA device executable 3884, a CPU 3890, and a CUDA-enabled GPU 3894.

[0323] In at least one embodiment and as previously incorporated herein Figure 38A As depicted, CUDA source code 3810 includes, but is not limited to, any number (including zero) of global functions 3812, any number (including zero) of device functions 3814, any number (including zero) of host functions 3816, and any number (including zero) of host / device functions 3818. In at least one embodiment, CUDA source code 3810 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

[0324] In at least one embodiment, the CUDA to HIP conversion tool 3820 converts the CUDA source code 3810 into HIP source code 3830. In at least one embodiment, the CUDA to HIP conversion tool 3820 converts each kernel call in the CUDA source code 3810 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the CUDA source code 3810 into any number of other functionally similar HIP calls.

[0325] In at least one embodiment, the HIP compiler driver 3840 determines that the target device 3846 is CUDA-enabled and generates HIP / NVCC compile commands 3842. In at least one embodiment, the HIP compiler driver 3840 then configures the CUDA compiler 3850 via the HIP / NVCC compile commands 3842 to compile the HIP source code 3830. In at least one embodiment, as part of configuring the CUDA compiler 3850, the HIP compiler driver 3840 provides access to a HIP to CUDA translation header 3852. In at least one embodiment, the HIP to CUDA translation header 3852 translates any number of mechanisms (e.g., functions) specified in any number of HIP APIs into any number of mechanisms specified in any number of CUDA APIs. In at least one embodiment, the CUDA compiler 3850 uses the HIP to CUDA translation header 3852 in conjunction with a CUDA runtime library 3854 corresponding to the CUDA runtime API 3802 to generate host executable code 3870(1) and CUDA device executable code 3884. In at least one embodiment, the host executable code 3870(1) and the CUDA device executable code 3884 can then be executed on the CPU 3890 and the CUDA-enabled GPU 3894, respectively. In at least one embodiment, the CUDA device executable code 3884 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3884 includes, but is not limited to, PTX code and is further compiled into binary code for a specific target device at runtime.

[0326] Figure 38C A system 3806 is shown that is configured to compile and execute code using a CPU 3890 and a non-CUDA enabled GPU 3892, according to at least one embodiment. Figure 38A CUDA source code 3810. In at least one embodiment, system 3806 includes, but is not limited to, CUDA source code 3810, a CUDA to HIP conversion tool 3820, HIP source code 3830, a HIP compiler driver 3840, HCC 3860, a host executable 3870(2), an HCC device executable 3882, a CPU 3890, and a GPU 3892.

[0327] In at least one embodiment, and as previously incorporated herein Figure 38AAs depicted, CUDA source code 3810 includes, but is not limited to, any number (including zero) of global functions 3812, any number (including zero) of device functions 3814, any number (including zero) of host functions 3816, and any number (including zero) of host / device functions 3818. In at least one embodiment, CUDA source code 3810 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

[0328] In at least one embodiment, CUDA to HIP conversion tool 3820 converts CUDA source code 3810 into HIP source code 3830. In at least one embodiment, CUDA to HIP conversion tool 3820 converts each kernel call in CUDA source code 3810 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in source code 3810 into any number of other functionally similar HIP calls.

[0329] In at least one embodiment, the HIP compiler driver 3840 then determines that the target device 3846 is not CUDA-enabled and generates HIP / HCC compile commands 3844. In at least one embodiment, the HIP compiler driver 3840 then configures the HCC 3860 to execute the HIP / HCC compile commands 3844, thereby compiling the HIP source code 3830. In at least one embodiment, the HIP / HCC compile commands 3844 configure the HCC 3860 to use, but are not limited to, the HIP / HCC runtime library 3858 and the HCC header 3856 to generate the host executable code 3870(2) and the HCC device executable code 3882. In at least one embodiment, the HIP / HCC runtime library 3858 corresponds to the HIP runtime API 3832. In at least one embodiment, the HCC header 3856 includes, but is not limited to, any number and type of interoperability mechanisms for the HIP and HCC. In at least one embodiment, host executable code 3870 ( 2 ) and HCC device executable code 3882 may execute on CPU 3890 and GPU 3892 , respectively.

[0330] Figure 37 According to at least one embodiment, Figure 38C38. CUDA source code 3810 illustrates an exemplary kernel converted by the CUDA to HIP conversion tool 3820. In at least one embodiment, the CUDA source code 3810 divides the overall problem that a given kernel is designed to solve into relatively coarse-grained sub-problems that can be solved independently using thread blocks. In at least one embodiment, each thread block includes, but is not limited to, an arbitrary number of threads. In at least one embodiment, each sub-problem is divided into relatively small pieces that can be solved in parallel by the threads in the thread block in a cooperative manner. In at least one embodiment, threads within a thread block can collaborate by sharing data through shared memory and by synchronizing execution to coordinate memory access.

[0331] In at least one embodiment, CUDA source code 3810 organizes the thread blocks associated with a given kernel into a one-dimensional, two-dimensional, or three-dimensional grid of thread blocks. In at least one embodiment, each thread block includes, but is not limited to, any number of threads, and the grid includes, but is not limited to, any number of thread blocks.

[0332] In at least one embodiment, a kernel is a function in device code defined using the "__global__" declaration specifier. In at least one embodiment, the CUDA kernel launch syntax 3910 is used to specify the size of the grid on which the kernel is executed and the associated streams for a given kernel call. In at least one embodiment, the CUDA kernel launch syntax 3910 is specified as "KernelName<<<GridSize,BlockSize,SharedMemorySize,Stream> >>(KernelArguments);". In at least one embodiment, the execution configuration syntax is a "<<< ... >>>" construct that is inserted between the kernel name ("KernelName") and the bracketed list of kernel arguments ("KernelArguments"). In at least one embodiment, the CUDA kernel launch syntax 3910 includes, but is not limited to, CUDA launch function syntax rather than execution configuration syntax.

[0333] In at least one embodiment, "GridSize" is of type dim3 and specifies the dimensions and size of the grid. In at least one embodiment, type dim3 is a CUDA-defined structure that includes, but is not limited to, unsigned integers x, y, and z. In at least one embodiment, if z is not specified, z defaults to 1. In at least one embodiment, if y is not specified, y defaults to 1. In at least one embodiment, the number of thread blocks in the grid is equal to the product of GridSize.x, GridSize.y, and GridSize.z. In at least one embodiment, "BlockSize" is of type dim3 and specifies the dimensions and size of each thread block. In at least one embodiment, the number of threads per thread block is equal to the product of BlockSize.x, BlockSize.y, and BlockSize.z. In at least one embodiment, each thread executing the kernel is given a unique thread ID that can be accessed within the kernel via a built-in variable (e.g., "threadIdx").

[0334] In at least one embodiment, with respect to CUDA kernel launch syntax 3910, "SharedMemorySize" is an optional parameter that specifies the number of bytes in shared memory that are dynamically allocated for each thread block for a given kernel call, in addition to statically allocated memory. In at least one embodiment and with respect to CUDA kernel launch syntax 3910, SharedMemorySize defaults to zero. In at least one embodiment and with respect to CUDA kernel launch syntax 3910, "stream" is an optional parameter that specifies the associated stream and defaults to zero to specify the default stream. In at least one embodiment, a stream is a sequence of commands that are executed in order (which may be issued by different host threads). In at least one embodiment, different streams may execute commands out of order or concurrently with respect to each other.

[0335] In at least one embodiment, the CUDA source code 3810 includes, but is not limited to, a kernel definition and a main function for an example kernel "MatAdd". In at least one embodiment, the main function is host code that executes on the host and includes, but is not limited to, a kernel call that causes the kernel MatAdd to execute on the device. In at least one embodiment, as shown, the kernel MatAdd adds two matrices A and B of size NxN, where N is a positive integer, and stores the result in a matrix C. In at least one embodiment, the main function defines the threadsPerBlock variable as 16 x 16 and the numBlocks variable as N / 16 x N / 16. In at least one embodiment, the main function then specifies the kernel call "MatAdd<<<numBlocks,threadsPerBlock> >>(A, B, C);". In at least one embodiment, and in accordance with CUDA kernel launch syntax 3910, kernel MatAdd is executed using a grid of thread blocks of size N / 16×N / 16, where each thread block has a size of 16×16. In at least one embodiment, each thread block includes 256 threads, a grid is created with enough blocks to have one thread per matrix element, and each thread in the grid executes kernel MatAdd to perform one pairwise addition.

[0336] In at least one embodiment, while converting CUDA source code 3810 to HIP source code 3830, CUDA to HIP conversion tool 3820 converts each kernel call in CUDA source code 3810 from CUDA kernel launch syntax 3910 to HIP kernel launch syntax 3920, and converts any number of other CUDA calls in source code 3810 to any number of other functionally similar HIP calls. In at least one embodiment, HIP kernel launch syntax 3920 is specified as "hipLaunchKernelGGL(KernelName, GridSize, BlockSize, SharedMemorySize, Stream, KernelArguments);". In at least one embodiment, each of KernelName, GridSize, BlockSize, SharedMemorySize, Stream, and KernelArguments has the same meaning in HIP kernel launch syntax 3920 as in CUDA kernel launch syntax 3910 (described previously herein). In at least one embodiment, the parameters SharedMemorySize and Stream are required in the HIP kernel launch syntax 3920 and optional in the CUDA kernel launch syntax 3910.

[0337] In at least one embodiment, in addition to the kernel call to cause the kernel MatAdd to execute on the device, Figure 39 A portion of the HIP source code 3830 depicted in Figure 39 3810 is identical to a portion of the CUDA source code 3810 depicted in FIG. In at least one embodiment, kernel MatAdd is defined in HIP source code 3830 with the same “__global__” declaration specifier as kernel MatAdd is defined in CUDA source code 3810. In at least one embodiment, the kernel call in HIP source code 3830 is “hipLaunchKernelGGL(MatAdd, numBlocks, threadsPerBlock, 0, 0, A, B, C);”, while the corresponding kernel call in CUDA source code 3810 is “MatAdd<<<numBlocks,threadsPerBlock> >>(A, B, C);".

[0338] Figure 40 More details are shown according to at least one embodiment. Figure 38C 3892 is a non-CUDA-enabled GPU. In at least one embodiment, the GPU 3892 is developed by Advanced Micro Devices, Inc. of Santa Clara, NC. In at least one embodiment, the GPU 3892 can be configured to perform computational operations in a highly parallel manner. In at least one embodiment, the GPU 3892 is configured to perform graphics pipeline operations, such as draw commands, pixel operations, geometry calculations, and other operations associated with rendering an image to a display. In at least one embodiment, the GPU 3892 is configured to perform operations unrelated to graphics. In at least one embodiment, the GPU 3892 is configured to perform both graphics-related operations and graphics-unrelated operations. In at least one embodiment, the GPU 3892 can be configured to execute device code included in the HIP source code 3830.

[0339] In at least one embodiment, GPU 3892 includes, but is not limited to, any number of programmable processing units 4020, a command processor 4010, an L2 cache 4022, a memory controller 4070, a DMA engine 4080(1), a system memory controller 4082, a DMA engine 4080(2), and a GPU controller 4084. In at least one embodiment, each programmable processing unit 4020 includes, but is not limited to, a workload manager 4030 and any number of compute units 4040. In at least one embodiment, command processor 4010 reads commands from one or more command queues (not shown) and dispatches the commands to workload managers 4030. In at least one embodiment, for each programmable processing unit 4020, the associated workload manager 4030 dispatches work to the compute units 4040 included in the programmable processing unit 4020. In at least one embodiment, each compute unit 4040 can execute any number of thread blocks, but each thread block executes on a single compute unit 4040. In at least one embodiment, a work group is a thread block.

[0340] In at least one embodiment, each compute unit 4040 includes, but is not limited to, any number of SIMD units 4050 and shared memory 4060. In at least one embodiment, each SIMD unit 4050 implements a SIMD architecture and is configured to execute operations in parallel. In at least one embodiment, each SIMD unit 4050 includes, but is not limited to, a vector ALU 4052 and a vector register file 4054. In at least one embodiment, each SIMD unit 4050 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in a warp belongs to a single thread block and is configured to process different data sets based on a single instruction set. In at least one embodiment, prediction can be used to disable one or more threads in a warp. In at least one embodiment, a channel is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block can be synchronized together and communicate via shared memory 4060.

[0341] In at least one embodiment, programmable processing units 4020 are referred to as "shader engines." In at least one embodiment, each programmable processing unit 4020 includes, but is not limited to, any number of specialized graphics hardware in addition to compute units 4040. In at least one embodiment, each programmable processing unit 4020 includes, but is not limited to, any number (including zero) of geometry processors, any number (including zero) of rasterizers, any number (including zero) of rendering backends, a workload manager 4030, and any number of compute units 4040.

[0342] In at least one embodiment, compute units 4040 share L2 cache 4022. In at least one embodiment, L2 cache 4022 is partitioned. In at least one embodiment, all compute units 4040 in GPU 3892 can access GPU memory 4090. In at least one embodiment, memory controller 4070 and system memory controller 4082 facilitate data transfers between GPU 3892 and a host, and DMA engine 4080(1) enables asynchronous memory transfers between GPU 3892 and the host. In at least one embodiment, memory controller 4070 and GPU controller 4084 facilitate data transfers between GPU 3892 and other GPUs 3892, and DMA engine 4080(2) enables asynchronous memory transfers between GPU 3892 and other GPUs 3892.

[0343] In at least one embodiment, GPU 3892 includes, but is not limited to, any number and type of system interconnects that facilitate data and control transfers between any number and type of directly or indirectly linked components within or external to GPU 3892. In at least one embodiment, GPU 3892 includes, but is not limited to, any number and type of I / O interfaces (e.g., PCIe) coupled to any number and type of peripheral devices. In at least one embodiment, GPU 3892 may include, but is not limited to, any number (including zero) of display engines and any number (including zero) of multimedia engines. In at least one embodiment, GPU 3892 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers (e.g., memory controller 4070 and system memory controller 4082) and memory devices (e.g., shared memory 4060) that are dedicated to a component or shared between multiple components. In at least one embodiment, GPU3892 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 4022), each of which can be private or shared among any number of components (e.g., SIMD units 4050, compute units 4040, and programmable processing units 4020).

[0344] Figure 41 41 illustrates how threads of an exemplary CUDA grid 4120 are mapped to Figure 404040. In at least one embodiment, and for illustration purposes only, the grid 4120 has a GridSize of BX times BY times 1 and a BlockSize of TX times TY times 1. Thus, in at least one embodiment, the grid 4120 includes, but is not limited to, (BX*BY) thread blocks 4130, each of which includes, but is not limited to, (TX*TY) threads 4140. Threads 4140 are Figure 41 Depicted as a curved arrow.

[0345] In at least one embodiment, grid 4120 is mapped to programmable processing units 4020(1), which include, but are not limited to, compute units 4040(1)-4040(C). In at least one embodiment and as shown, (BJ*BY) thread blocks 4130 are mapped to compute unit 4040(1), and the remaining thread blocks 4130 are mapped to compute unit 4040(2). In at least one embodiment, each thread block 4130 may include, but are not limited to, any number of warps, and each warp is mapped to Figure 40 The different SIMD units 4050.

[0346] In at least one embodiment, the warps in a given thread block 4130 may synchronize together and communicate via shared memory 4060 included in the associated compute unit 4040. For example, and in at least one embodiment, the warps in thread block 4130 (BJ, 1) may synchronize together and communicate via shared memory 4060 (1). For example, and in at least one embodiment, the warps in thread block 4130 (BJ+1, 1) may synchronize together and communicate via shared memory 4060 (2).

[0347] Figure 42The present invention shows how to migrate existing CUDA code to data parallel C++ code according to at least one embodiment. Data Parallel C++ (DPC++) can refer to an open, standard-based replacement for a single-architecture proprietary language that allows developers to reuse code across hardware targets (CPUs and accelerators such as GPUs and FPGAs) and also perform custom tuning for specific accelerators. DPC++ uses similar and / or identical C and C++ constructs based on ISO C++ that developers may be familiar with. DPC++ combines the standard SYCL from the Khronos group to support data parallelism and heterogeneous programming. SYCL refers to a cross-platform abstraction layer built on the underlying concepts, portability, and efficiency of OpenCL that enables code for heterogeneous processors to be written in a "single-source" style using standard C++. SYCL can enable single-source development, where C++ template functions can contain both host code and device code to build complex algorithms accelerated using OpenCL, and then reuse them across their source code on different types of data.

[0348] In at least one embodiment, the DPC++ compiler is used to compile DPC++ source code that can be deployed across different hardware targets. In at least one embodiment, the DPC++ compiler is used to generate DPC++ applications that can be deployed across different hardware targets, and DPC++ compatibility tools can be used to migrate CUDA applications to multi-platform programs in DPC++. In at least one embodiment, the DPC++ base toolkit includes: a DPC++ compiler for deploying applications across different hardware targets; a DPC++ library for improving productivity and performance across CPUs, GPUs, and FPGAs; a DPC++ compatibility tool for migrating CUDA applications to multi-platform applications; and any suitable combination thereof.

[0349] In at least one embodiment, the DPC++ programming model is utilized to simplify one or more aspects associated with programming CPUs and accelerators by using modern C++ features to express parallelism with a programming language known as DataParallel C++. The DPC++ programming language can be used to reuse code for hosts (e.g., CPUs) and accelerators (e.g., GPUs or FPGAs) using a single source language, where execution and memory dependencies are clearly communicated. Mappings within the DPC++ code can be used to convert applications to run on hardware or hardware device groups that are optimized to accelerate the workload. The host can be used to simplify the development and debugging of device code, even on platforms that do not have an available accelerator.

[0350] In at least one embodiment, CUDA source code 4200 is provided as input to a DPC++ compliant tool 4202 to generate human-readable DPC++ 4204. In at least one embodiment, human-readable DPC++ 4204 includes inline comments generated by the DPC++ compliant tool 4202 that instruct the developer on how and / or where to modify the DPC++ code to complete the encoding and tune for desired performance 4206, thereby generating DPC++ source code 4208.

[0351] In at least one embodiment, the CUDA source code 4200 is or includes a collection of human-readable source code in the CUDA programming language. In at least one embodiment, the CUDA source code 4200 is human-readable source code in the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension of the C++ programming language that includes, but is not limited to, mechanisms for defining device code and distinguishing between device code and host code. In at least one embodiment, device code is source code that is executable on a device (e.g., a GPU or FPGA) after compilation and may include one or more parallelizable workflows that can be executed on one or more processor cores of the device. In at least one embodiment, the device may be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU, a GPU, or another GPGPU, etc. In at least one embodiment, host code is source code that is executable on a host after compilation. In at least one embodiment, some or all of the host code and device code may be executed in parallel across the CPU and GPU / FPGA. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as a CPU. In combination Figure 42 The described CUDA source code 4200 may be based on those CUDA source codes discussed elsewhere herein.

[0352] In at least one embodiment, DPC++ compatibility tool 4202 refers to an executable tool, program, application, or any other suitable type of tool for facilitating the migration of CUDA source code 4200 to DPC++ source code 4208. In at least one embodiment, DPC++ compatibility tool 4202 is a command-line-based code migration tool that can be used as part of the DPC++ toolkit for porting existing CUDA source code to DPC++. In at least one embodiment, DPC++ compatibility tool 4202 converts some or all of the source code of a CUDA application from CUDA to DPC++ and generates a resulting file written at least partially in DPC++, referred to as human-readable DPC++ 4204. In at least one embodiment, human-readable DPC++ 4204 includes comments generated by DPC++ compatibility tool 4202 to indicate where user intervention may be necessary. In at least one embodiment, user intervention is necessary when CUDA source code 4200 calls a CUDA API that does not have a similar DPC++ API; other examples of requiring user intervention are discussed in more detail later.

[0353] In at least one embodiment, a workflow 4200 for migrating CUDA source code (e.g., an application or portion thereof) includes: creating one or more compilation database files; migrating CUDA to DPC++ using a DPC++ compatibility tool 4202; completing the migration and verifying correctness, thereby generating DPC++ source code 4208; and compiling the DPC++ source code 4208 using a DPC++ compiler to generate a DPC++ application. In at least one embodiment, the compatibility tool provides a utility that intercepts commands used when a Makefile is executed and stores them in a compilation database file. In at least one embodiment, the file is stored in JSON format. In at least one embodiment, the built commands are intercepted to convert the Makefile commands into DPC-compatible commands.

[0354] In at least one embodiment, the intercept build is a utility script that intercepts the build process to capture compile options, macro definitions, and include paths, and writes that data into a compile database file. In at least one embodiment, the compile database file is a JSON file. In at least one embodiment, the DPC++ compatibility tool 4202 parses the compile database and applies options when migrating input sources. In at least one embodiment, the use of the intercept build is optional, but highly recommended for environments based on Make or CMake. In at least one embodiment, the migration database includes commands, directories, and files: commands can include necessary compile flags; directories can include paths to header files; files can include paths to CUDA files.

[0355] In at least one embodiment, DPC++ compatibility tool 4202 migrates CUDA code (e.g., applications) written in CUDA to DPC++ by generating DPC++ where possible. In at least one embodiment, DPC++ compatibility tool 4202 can be used as part of a tool suite. In at least one embodiment, the DPC++ tool suite includes an interception build tool. In at least one embodiment, the interception build tool creates a compilation database that captures compilation commands for migrating CUDA files. In at least one embodiment, DPC++ compatibility tool 4202 uses the compilation database generated by the interception build tool to migrate CUDA code to DPC++. In at least one embodiment, non-CUDA C++ code and files are migrated as is. In at least one embodiment, DPC++ compatibility tool 4202 generates human-readable DPC++ 4204, which can be DPC++ code as generated by DPC++ compatibility tool 4202. This DPC++ code cannot be compiled by the DPC++ compiler and requires additional plumbing to verify the code portions that were not correctly migrated, and may involve manual intervention (such as by the developer). In at least one embodiment, DPC++ compatibility tool 4202 provides hints or tools embedded in the code to help developers manually migrate additional code that cannot be automatically migrated.In at least one embodiment, migration is a one-time activity for a source file, project, or application.

[0356] In at least one embodiment, DPC++ compatibility tool 42002 is capable of successfully migrating all portions of CUDA code to DPC++, and there may only be an optional step for manually verifying and tuning the performance of the generated DPC++ source code. In at least one embodiment, DPC++ compatibility tool 42002 directly generates DPC++ source code 4208, which is compiled by the DPC++ compiler without requiring or utilizing human intervention to modify the DPC++ code generated by DPC++ compatibility tool 4202. In at least one embodiment, DPC++ compatibility tool generates compilable DPC++ code that can be optionally tuned by the developer for performance, readability, maintainability, other various considerations, or any combination thereof.

[0357] In at least one embodiment, one or more CUDA source files are migrated to DPC++ source files using, at least in part, DPC++ compatibility tool 4202. In at least one embodiment, the CUDA source code includes one or more header files, which may include a CUDA header file. In at least one embodiment, the CUDA source file includes a<cuda.h> header files and<stdio.h> Header file. In at least one embodiment, a portion of a vector add kernel CUDA source file may be written as or related to:

[0358]

[0359]

[0360] In at least one embodiment and in conjunction with the CUDA source files presented above, DPC++ compatibility tool 4202 parses the CUDA source code and replaces the header files with the appropriate DPC++ and SYCL header files. In at least one embodiment, the DPC++ header files include helper declarations. In CUDA, there is the concept of a thread ID, and correspondingly, in DPC++ or SYCL, there is a local identifier for each element.

[0361] In at least one embodiment, and in conjunction with the CUDA source file presented above, there are two vectors A and B initialized, and the result of the vector addition is placed into vector C as part of VectorAdKernel(). In at least one embodiment, as part of migrating CUDA code to DPC++ code, DPC++ compatibility tool 4202 converts the CUDA thread ID used to index the work elements into SYCL standard addressing for the work elements by local ID. In at least one embodiment, the DPC++ code generated by DPC++ compatibility tool 4202 can be optimized—for example, by reducing the dimensionality of nd_item, thereby increasing memory and / or processor utilization.

[0362] In at least one embodiment, and in conjunction with the CUDA source files presented above, memory allocations are migrated. In at least one embodiment, cudaMalloc() is migrated to a unified shared memory SYCL call malloc_device() to which the device and context are passed, relying on SYCL concepts such as platforms, devices, contexts, and queues. In at least one embodiment, a SYCL platform can have multiple devices (e.g., host and GPU devices); a device can have multiple queues to which jobs can be submitted; each device can have a context; and a context can have multiple devices and manage shared memory objects.

[0363] In at least one embodiment, and in conjunction with the CUDA source file presented above, the main() function calls or calls VectorAdKernel() to add two vectors A and B together and store the result in vector C. In at least one embodiment, the CUDA code that calls VectorAdKernel() is replaced by DPC++ code to submit the kernel to the command queue for execution. In at least one embodiment, the command group handler cgh passes data submitted to the queue, synchronizes and computes, and calls parallel_for for multiple global elements and multiple work items in the work group that calls VectorAdKernel().

[0364] In at least one embodiment, and in conjunction with the CUDA source files presented above, the CUDA calls for copying device memory and then releasing the memory for vectors A, B, and C are migrated to corresponding DPC++ calls. In at least one embodiment, the C++ code (e.g., standard ISO C++ code for printing a vector of floating-point variables) is migrated as is, without being modified by the DPC++ compatibility tool 4202. In at least one embodiment, the DPC++ compatibility tool 4202 modifies the CUDA API for memory setup and / or host calls in order to execute the kernel on the acceleration device. In at least one embodiment, and in conjunction with the CUDA source files presented above, the corresponding human-readable DPC++ 4204 (e.g., which can be compiled) is written as or in association with the following:

[0365]

[0366]

[0367] In at least one embodiment, human-readable DPC++ 4204 refers to the output generated by DPC++ compatibility tool 4202 and can be optimized in one way or another. In at least one embodiment, human-readable DPC++ 4204 generated by DPC++ compatibility tool 4202 can be manually edited by the developer after migration to improve maintainability, performance, or other considerations. In at least one embodiment, the DPC++ code generated by DPC++ compatibility tool 42002 (such as the disclosed DPC++) can be optimized by removing repeated calls to get_current_device() and / or get_default_context() for each malloc_device() call. In at least one embodiment, the DPC++ code generated above can be restructured to use only a single dimension of 3D nd_range, thereby reducing memory usage. In at least one embodiment, the developer can manually edit the DPC++ code generated by DPC++ compatibility tool 4202 to replace the use of unified shared memory with attachments. In at least one embodiment, DPC++ compatibility tool 4202 includes an option to change how CUDA code is migrated to DPC++ code. In at least one embodiment, DPC++ compatibility tool 4202 is verbose because it is using generic templates to migrate CUDA code to DPC++ code, which works for a large number of cases.

[0368] In at least one embodiment, the CUDA to DPC++ migration workflow includes the following steps: preparing for migration using an interception build script; performing the migration of the CUDA project to DPC++ using the DPC++ compatibility tool 4202; manually reviewing and editing the migrated source files for completeness and correctness; and compiling the final DPC++ code to generate a DPC++ application. In at least one embodiment, manual review of the DPC++ source code may be required in one or more scenarios, including but not limited to: migrated APIs not returning error codes (CUDA code can return error codes, which can then be consumed by the application, but SYCL uses exceptions to report errors and therefore does not use error codes to surface errors); DPC++ does not support CUDA compute capability-related logic; declarations cannot be removed. In at least one embodiment, scenarios where manual intervention in the DPC++ code may include but are not limited to: error code logic replaced or commented with (*, 0) code; equivalent DPC++ APIs not available; CUDA compute capability-related logic; hardware-related APIs (clock()); missing feature-unsupported APIs; execution time measurement logic; handling built-in vector type conflicts; migration of cuBLAS APIs; and more.

[0369] Other variations are within the spirit of the present disclosure. Thus, while the disclosed technology is susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in the drawings and have been described above in detail. However, it should be understood that there is no intention to limit the disclosure to one or more specific forms disclosed, but on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the present disclosure as defined by the appended claims.

[0370] Unless otherwise noted or clearly contradicted by the context, the use of the terms "a" and "an" and "the" and similar references in the context of describing the disclosed embodiments (particularly in the context of the appended claims) should be interpreted as covering the singular and plural, rather than as definitions of terms. Unless otherwise noted, the terms "include," "have," "include," and "contain" should be interpreted as open-ended terms (meaning "including but not limited to"). The term "connected" (when unmodified, refers to a physical connection) should be interpreted as partially or completely contained within, attached to, or connected together, even if there is some intervention. Unless otherwise noted herein, references to numerical ranges herein are intended only to be used as a shorthand method of referring to each individual value falling within the range, and each individual value is incorporated into the specification as if it were separately recited herein. Unless otherwise noted or contradicted by the context, the use of the term "set" (e.g., "item set") or "subset" should be interpreted as a non-empty set comprising one or more members. Furthermore, unless otherwise indicated or contradicted by context, the term "subset" of a corresponding set does not necessarily mean a proper subset of the corresponding set, but rather a subset and a corresponding set may be equivalent.

[0371] Unless expressly indicated otherwise or clearly contradicted by context, conjunctions such as phrases of the form "at least one of A, B, and C" or "at least one of A, B, and C" are understood in context to generally refer to an item, clause, or the like that may be A or B or C, or any non-empty subset of the set A, B, and C. For example, in the illustrative example of a set having three members, the conjunctions "at least one of A, B, and C" and "at least one of A, B, and C" refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunctions are not generally intended to imply that certain embodiments require the presence of at least one of A, at least one of B, and at least one of C. Additionally, unless expressly indicated otherwise or contradicted by context, the term "plurality" refers to plurality (e.g., "a plurality of items" means a plurality of items). The number of items in a plurality of items is at least two, but may be more if expressly indicated or indicated by context. Further, unless stated otherwise or clear from context, the phrase "based on" means "based at least in part on" rather than "based solely on."

[0372] Unless otherwise indicated herein or clearly contradicted by the context, the operations of the processes described herein may be performed in any suitable order. In at least one embodiment, processes such as those described herein (or variations and / or combinations thereof) are performed under the control of one or more computer systems configured with executable instructions and are implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) that are collectively executed on one or more processors by hardware or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of, for example, a computer program that includes a plurality of instructions that can be executed by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable storage medium that excludes transient signals (e.g., propagated transient electrical or electromagnetic transmissions) but includes non-transitory data storage circuits (e.g., buffers, caches, and queues). In at least one embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media (or other memory for storing executable instructions) having executable instructions stored thereon, which, when executed by one or more processors of a computer system (i.e., as a result of being executed), causes the computer system to perform the operations described herein. In at least one embodiment, the set of non-transitory computer-readable storage media includes a plurality of non-transitory computer-readable storage media, and one or more of the individual non-transitory storage media in the plurality of non-transitory computer-readable storage media lacks all of the code, but rather the plurality of non-transitory computer-readable storage media collectively store all of the code. In at least one embodiment, the executable instructions are executed so that different instructions are executed by different processors, for example, a non-transitory computer-readable storage medium stores instructions, and a main central processing unit ("CPU") executes some instructions, while a graphics processing unit ("GPU") executes other instructions. In at least one embodiment, different components of the computer system have separate processors, and different processors execute different subsets of instructions.

[0373] Thus, in at least one embodiment, a computer system is configured to implement one or more services that individually or collectively perform the operations of the processes described herein, and such a computer system is configured with applicable hardware and / or software that enables the implementation of the operations. Furthermore, the computer system implementing at least one embodiment of the present disclosure is a single device, and in another embodiment is a distributed computer system comprising multiple devices operating in different ways such that the distributed computer system performs the operations described herein and such that no single device performs all of the operations.

[0374] The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended merely to better illustrate embodiments of the present disclosure and does not limit the scope of the disclosure unless otherwise required. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosure.

[0375] All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.

[0376] In the description and claims, the terms "coupled" and "connected," along with their derivatives, may be used. It should be understood that these terms may not be intended as synonyms for each other. Rather, in specific examples, "connected" or "coupled" may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. "Coupled" may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0377] Unless expressly stated otherwise, it is understood that throughout this specification, terms such as “process,” “calculate,” “compute,” “determine,” etc., refer to the actions and / or processes of a computer or computing system or similar electronic computing device that processes and / or converts data represented as physical quantities (e.g., electronic) in the registers and / or memories of the computing system into other data similarly represented as physical quantities in the memories, registers, or other such information storage, transmission, or display devices of the computing system.

[0378] In a similar manner, the term "processor" may refer to any device or portion of a memory that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that can be stored in registers and / or memory. As non-limiting examples, a "processor" may be a CPU or a GPU. A "computing platform" may include one or more processors. As used herein, a "software" process may include, for example, software and / or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Likewise, each process may refer to multiple processes to execute instructions continuously or intermittently, sequentially, or in parallel. The terms "system" and "method" may be used interchangeably herein, as long as a system may embody one or more methods, and a method may be considered a system.

[0379] In this document, reference may be made to obtaining, acquiring, receiving, or inputting analog or digital data into a subsystem, a computer system, or a computer-implemented machine. The process of obtaining, acquiring, receiving, or inputting analog and digital data can be accomplished in a variety of ways, such as by receiving data as parameters of a function call or a call to an application programming interface. In some implementations, the process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transmitting data via a serial or parallel interface. In another implementation, the process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transmitting data from a providing entity to an acquiring entity via a computer network. Reference may also be made to providing, outputting, transmitting, sending, or presenting analog or digital data. In various examples, the process of providing, outputting, transmitting, sending, or presenting analog or digital data can be accomplished by transmitting data as input or output parameters of a function call, an application programming interface, or an interprocess communication mechanism.

[0380] Although the above discussion sets forth example implementations of the described technology, other architectures may be used to implement the described functionality and are intended to fall within the scope of this disclosure. In addition, although specific responsibilities are defined above for discussion purposes, the various functions and responsibilities may be allocated and divided in different ways depending on the circumstances.

[0381] Furthermore, although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter claimed in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as example forms of implementing the claims.

Claims

1. A method comprising: determining a first set of values ​​representing one or more tonal ranges of an input image; generating a contrast image based at least in part on a difference between the input image and a second image generated by at least applying a smoothing factor; generating a set of contrast gain curves for the one or more tonal ranges of the input image based at least in part on the first set of values ​​and a second set of values, wherein the second set of values ​​includes a set of sigma values ​​representing one or more Gaussian curves; as well as An output image is generated by applying at least a contrast gain map to the contrast image, wherein the contrast gain map for a set of pixels of the input image is determined by applying at least a first contrast gain curve of the set of contrast gain curves to a first scale-space representation of the input image. 2 . The method of claim 1 , wherein the second image further comprises a scale-space representation of the input image. The method of claim 1 , wherein the smoothing factor is a Gaussian kernel applied to the input image.

4. The method according to claim 1, further comprising: A global tone map is applied to the input image to generate a modified input image. The method of claim 4 , wherein the one or more ranges comprise a set of ranges represented as a histogram.

6. The method according to claim 5, wherein the method further comprises: The histogram is generated based at least in part on the modified input image.

7. The method according to claim 1, further comprising: A global tone map is applied to at least one of the input image or the output image.

8. The method of claim 1, wherein the one or more tonal ranges further comprise at least one of a shadow range, a highlight range, or a mid-tone range.

9. The method of claim 8, wherein the first set of values ​​further comprises a set of average values ​​for the one or more tonal ranges.

10. The method of claim 9, wherein the shadow range further comprises a first group of pixels of the input image that are below a first threshold. The method of claim 10 , wherein a first average value in the set of average values ​​further comprises an average value of the first set of pixels. 12 . The method according to claim 11 , wherein the highlight range further includes a second group of pixels of the input image that are above a second threshold.

13. The method of claim 12, wherein the mid-tone range further includes a third group of pixels of the input image that are above the first threshold and below the second threshold. The method of claim 13 , wherein the first threshold represents a percentage of pixels of the input image.

15. The method of claim 1, wherein a contrast gain curve in the set of contrast gain curves is a function of an input tonal value that produces a corresponding gain.

16. The method of claim 1 , wherein the one or more tonal ranges further comprise a tonal range defined at least in part based on groups of pixels classified by a threshold pixel value, wherein The threshold pixel value is determined based at least in part on a percentage of pixels of the pixel group.

17. A system comprising: one or more processors; as well as a memory storing instructions that, as a result of execution of the instructions by the one or more processors, cause the system to: obtaining image data representing an input image; determining one or more tonal ranges and a first set of values ​​based at least in part on the image data, wherein a first value in the first set of values ​​corresponds to a first tonal range in the one or more tonal ranges; generating a contrast image based at least in part on a set of scale-space representations of the input image and a set of luminance values ​​of the input image; generating a first contrast gain function for the first tonal range using the input image based at least in part on the first value and a second set of values, wherein the second set of values ​​includes a set of sigma values ​​representing one or more Gaussian curves; as well as An output image is generated by applying at least a first contrast gain map to the contrast image, wherein the first contrast gain map is generated at least in part based on the first contrast gain function.

18. The system of claim 17, wherein the image data is a histogram of the input image.

19. The system of claim 17, wherein the image data is high dynamic range (HDR) image data.

20. The system of claim 17, wherein the memory further comprises instructions that, as a result of execution of the instructions by the one or more processors, cause the system to generate a second contrast gain function for a second tonal range in the set of tonal ranges.

21. The system of claim 20, wherein the memory further comprises instructions that, as a result of execution of the instructions by the one or more processors, cause the system to generate a second contrast gain map based at least in part on the second contrast gain function.

22. The system of claim 21 , wherein the instructions that cause the system to generate the output image by applying at least the first contrast gain map to the contrast image further comprise instructions that, as a result of execution of the instructions by the one or more processors, cause the system to generate the output image by applying at least the first contrast gain map and the second contrast gain map.

23. The system of claim 17, wherein the one or more tonal ranges further comprise at least one of a shadow range, a highlight range, or a mid-tone range.

24. The system of claim 17, wherein the image data further comprises statistical image data representative of the input image.

25. The system of claim 24, wherein the statistical image data further comprises a histogram.

26. A method comprising: Identify multiple tonal regions of an image; applying different gain functions to different ones of the plurality of tonal regions to generate a plurality of modified tonal regions, wherein the gain functions are generated based at least in part on a set of values ​​representing a Gaussian curve and a set of sigma values; as well as A modified version of the image is generated based on the modified tonal region.

27. The method of claim 26, wherein the plurality of tonal regions further comprises at least one of a shadow range, a highlight range, or a mid-tone range.

28. The method of claim 26, further comprising: The image is generated based at least in part on a difference between an input image and an image generated by applying at least a smoothing factor to the input image.

29. The method of claim 26, further comprising: A gain function corresponding to an individual hue region of the plurality of hue regions is generated.

30. The method of claim 26, wherein the set of values ​​represents a set of average values ​​of brightness for the set of tonal ranges.

31. The method of claim 30, wherein a first average in the set of averages is calculated based at least in part on a first set of pixels of the image, wherein the first set of pixels indicates brightness values ​​below a threshold.

32. The method of claim 30, wherein a first average in the set of averages is calculated based at least in part on a first set of pixels of the image, wherein the first set of pixels indicates brightness values ​​above a threshold.

33. The method of claim 30, wherein a first average in the set of averages is calculated based at least in part on a first set of pixels of the image, wherein the first set of pixels indicates brightness values ​​between a first threshold and a second threshold.

Images