Pixel

Abstract

The present invention relates to a pixel. The pixel includes: a first transistor including a first electrode, a second electrode, and a gate electrode connected to a first node; a second transistor including a first electrode, a second electrode connected to a data line, and a gate electrode connected to a first scan line; a storage capacitor including a first electrode connected to the first node and a second electrode connected to a second node; a third transistor including a gate electrode, a first electrode connected to the second node, and a second electrode connected to an initialization power supply; a fourth transistor including a first electrode connected to a first driving power supply, a second electrode connected to the first electrode of the first transistor, and a gate electrode connected to a light emitting control line; and a fifth transistor including a first electrode, a second electrode connected to the first node, and a gate electrode connected to a second scan line.

Description

[0001] This application is a divisional application of the patent application with application number 201710523554.3 filed on June 30, 2017 and titled “Pixel, stage circuit and organic light-emitting display device”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] The entire content of Korean Patent Application No. 10-2016-0083498, filed on Jul. 1, 2016, and entitled “Pixel, stage circuit, and organic light emitting display device having the same” is incorporated herein by reference in its entirety. Technical Field

[0004] One or more embodiments described herein relate to pixels, stage circuits, and organic light emitting display devices including the pixels and the stage circuits. Background Art

[0005] Various types of displays have been developed. Examples include liquid crystal displays (LCDs) and organic light-emitting displays (OLEDs). OLEDs generate images using pixels that include organic light-emitting diodes (OLEDs). The diodes generate light based on the recombination of electrons and holes in an organic light-emitting layer. This type of display has relatively high response speeds and low power consumption.

[0006] The pixels of an organic light-emitting display are connected to data lines and scan lines. Each pixel includes a drive transistor that adjusts the amount of current flowing through the organic light-emitting diode based on signals from the scan and data lines. The pixel emits light with a brightness based on the adjusted current.

[0007] Various attempts have been made to improve the performance of organic light-emitting displays. One approach involves setting the drive power supply to a low voltage. Another involves driving the display at a low frequency to reduce power consumption. However, these approaches allow leakage current to flow, for example, from the drive transistor of each pixel. As a result, the voltage of the data signal cannot be maintained during a frame period, which can adversely affect brightness. Summary of the Invention

[0008] According to one or more embodiments, a pixel includes: a pixel including an organic light emitting diode; a first transistor that controls the amount of current flowing from a first driving power source connected to a first electrode of the first transistor through the organic light emitting diode and to a second driving power source based on a voltage of a first node, the first transistor being an n-type low-temperature polycrystalline silicon (LTPS) thin film transistor; a second transistor connected between a data line and a first node, the second transistor being turned on when a scan signal is supplied to the first scan line, the second transistor being an n-type oxide semiconductor thin film transistor; a third transistor connected between the second electrode of the first transistor and an initialization power source, the third transistor being turned on when a scan signal is supplied to the second scan line, the third transistor being an n-type LTPS thin film transistor; a fourth transistor connected between the first driving power source and the first electrode of the first transistor, the fourth transistor being turned off when a light emission control signal is supplied to the light emission control line, the fourth transistor being an n-type LTPS thin film transistor; and a storage capacitor connected between the second node and the first node, the second node being connected to the second electrode of the first transistor.

[0009] The pixel may include a fifth transistor connected between a reference power supply and a first node, wherein the fifth transistor is turned on when a scan signal is supplied to a third scan line, and wherein the fifth transistor is an n-type oxide semiconductor thin film transistor. The pixel may include a first capacitor connected between the first drive power supply and the second node. When the first scan line is located on the i-th horizontal line, the second scan line may be set to the first scan line located on the i-1-th horizontal line, where i is a natural number.

[0010] According to one or more other embodiments, a stage circuit includes a buffer that connects a first input terminal or a second input terminal to an output terminal based on control of a signal generator, wherein the buffer includes a first transistor and a second transistor connected in parallel between the first input terminal and the output terminal, and a third transistor and a fourth transistor connected in parallel between the second input terminal and the output terminal, wherein the first transistor and the third transistor are n-type LTPS thin-film transistors, and wherein the second transistor and the fourth transistor are n-type oxide semiconductor thin-film transistors. The gate electrode of the first transistor can be electrically connected to the gate electrode of the second transistor. The gate electrode of the third transistor can be electrically connected to the gate electrode of the fourth transistor.

[0011] According to one or more other embodiments, an organic light-emitting display device includes: a plurality of pixels connected to scan lines, a light-emission control line, and a data line; a scan driver driving the scan lines and the light-emission control line; and a data driver driving the data line, wherein at least one of the pixels includes: an organic light-emitting diode; a first transistor controlling an amount of current flowing from a first driving power source connected to a first electrode of the first transistor through the organic light-emitting diode and to a second driving power source based on a voltage of a first node, wherein the first transistor is an n-type LTPS thin-film transistor; a second transistor connected between the data line and the first node, the second transistor being turned on when a scan signal is supplied to the first scan line, the second transistor being an n-type oxide semiconductor thin-film transistor; a third transistor connected between the second electrode of the first transistor and an initialization power source, the third transistor being turned on when a scan signal is supplied to the second scan line, the third transistor being an n-type LTPS thin-film transistor; a fourth transistor connected between the first driving power source and the first electrode of the first transistor, the fourth transistor being turned off when a light-emission control signal is supplied to the light-emission control line, the fourth transistor being an n-type LTPS thin-film transistor; and a storage capacitor connected between the second node and the first node, the second node being coupled to the second electrode of the first transistor.

[0012] At least one of the pixels may include a fifth transistor connected between a reference power supply and a first node, wherein the fifth transistor is turned on when a scan signal is supplied to a third scan line, and wherein the fifth transistor is an n-type oxide semiconductor thin film transistor. At least one of the pixels may include a first capacitor connected between a first drive power supply and a second node. When the first scan line is located on the i-th horizontal line, the second scan line is set to the first scan line located on the i-1-th horizontal line, where i is a natural number.

[0013] The scan driver includes a plurality of stage circuits to drive the scan lines and the light-emitting control lines. At least one of the stage circuits may include: a buffer that connects the first input terminal or the second input terminal to the output terminal based on control of a signal generator, wherein the buffer includes a first transistor and a second transistor connected in parallel between the first input terminal and the output terminal, and a third transistor and a fourth transistor connected in parallel between the second input terminal and the output terminal, wherein the first transistor and the third transistor are n-type LTPS thin-film transistors, and wherein the second transistor and the fourth transistor are n-type oxide semiconductor thin-film transistors. The gate electrode of the first transistor is electrically connected to the gate electrode of the second transistor. The gate electrode of the third transistor is electrically connected to the gate electrode of the fourth transistor.

[0014] According to one or more other embodiments, a pixel includes: a first transistor; a second transistor; and an organic light emitting diode, wherein the first transistor controls the amount of current flowing to the organic light emitting diode, and wherein the first transistor is a low temperature polycrystalline silicon (LTPS) thin film transistor, and the second transistor is different from the LTPS transistor. The first transistor and the second transistor may have the same conductivity type. The first transistor and the second transistor may be n-type transistors. The second transistor may be an oxide semiconductor thin film transistor and may be electrically connected to the gate electrode of the first transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Various features will become apparent to those skilled in the art by describing exemplary embodiments in detail with reference to the accompanying drawings, in which:

[0016] Figure 1 An embodiment of an organic light emitting display device is shown;

[0017] Figure 2 An embodiment of a pixel is shown;

[0018] Figure 3 An embodiment of a waveform diagram for driving a pixel is illustrated;

[0019] Figure 4 Another embodiment of a pixel is shown;

[0020] Figure 5 Another embodiment of a method for driving a pixel is shown;

[0021] Figure 6 Another embodiment of a pixel is shown;

[0022] Figure 7 Another embodiment of a waveform diagram illustrating driving a pixel; and

[0023] Figure 8 An embodiment of a diagram-level circuit is shown. DETAILED DESCRIPTION

[0024] Various example embodiments are described with reference to the accompanying drawings; however, these example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey exemplary implementations to those skilled in the art. Various embodiments (or portions thereof) may be combined to form additional embodiments.

[0025] In the accompanying drawings, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when a layer or element is referred to as being "on" another layer or substrate, it may be directly on the other layer or substrate, or there may be intervening layers. Further, it will be understood that when a layer is referred to as being "under" another layer, it may be directly under the other layer, and there may also be one or more intervening layers. Furthermore, it will be understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may also be one or more intervening layers. Throughout the text, the same reference numerals refer to the same elements.

[0026] When an element is referred to as being “connected” or “coupled” to another element, it may be directly connected or coupled to the other element, or may be indirectly connected or coupled to the other element with one or more intervening elements interposed therebetween. In addition, when an element is referred to as “including” a component, this means that the element may further include another component, rather than excluding the other component, unless otherwise disclosed.

[0027] Figure 1 An embodiment of an organic light-emitting display device is shown in the figure, which includes: pixels 140 connected to scan lines S11 to S1n and S21 to S2n, emission control lines E1 to En, and data lines D1 to Dm; a scan driver 110 driving the scan lines S11 to S1n and S21 to S2n and the emission control lines E1 to En; a data driver 120 driving the data lines D1 to Dm; and a timing controller 150 controlling the scan driver 110 and the data driver 120.

[0028] The timing controller 150 may generate a data drive control signal DCS and a scan drive control signal SCS based on an externally supplied synchronization signal. The data drive control signal DCS and the scan drive control signal SCS generated by the timing controller 150 may be supplied to the data driver 120 and the scan driver 110, respectively. In addition, the timing controller 150 may readjust the externally supplied data and supply the externally supplied data to the data driver 120.

[0029] The scan drive control signal SCS may include a start pulse and a clock signal. The start pulse may be supplied to control the first timing of the scan signal and the light emitting control signal. The clock signal may be supplied to shift the start pulse.

[0030] The data driving control signal DCS may include a source start pulse and a clock signal. The source start pulse may be supplied to control a sampling start point of data, and the clock signal may be supplied to control a sampling operation.

[0031] The scan driver 110 may receive a scan drive control signal SCS from the timing controller 150. Upon receiving the scan drive control signal SCS, the scan driver 110 may supply scan signals to the first scan lines S11 to S1n and the second scan lines S21 to S2n. For example, the scan driver 110 may sequentially supply first scan signals to the first scan lines S11 to S1n and sequentially supply second scan signals to the second scan lines S21 to S2n. When the first scan signals are sequentially supplied, the pixels 140 may be selected in units of horizontal lines.

[0032] The scan driver 110 may supply the second scan signal to the i-th second scan line S2i without overlapping with the first scan signal supplied to the i-th first scan line S1i, where i is a natural number. For example, the scan driver 110 may supply the second scan signal to the i-th second scan line S2i and then supply the first scan signal to the i-th first scan line S1i. Each of the first scan signal and the second scan signal may be set to a gate-on voltage. For example, each of the first scan signal and the second scan signal may be set to a high voltage.

[0033] The scan driver 110, which receives the scan drive control signal SCS, may supply a light emission control signal to the light emission control lines E1 to En. For example, the scan driver 110 may sequentially supply the light emission control signal to the light emission control lines E1 to En. Each light emission control signal may be supplied to control the emission time of each pixel 140 and to compensate for the threshold voltage of the driving transistor.

[0034] The light emission control signal supplied to the i-th light emission control line Ei may be supplied to partially overlap with a period of the first scan signal supplied to the i-th first scan line S1i and a period of the second scan signal supplied to the i-th second scan line S2i. The light emission control signal may be set to a gate-off voltage, for example, a low voltage.

[0035] Furthermore, the light-emission control signal supplied to the i-th light-emission control line Ei can be divided into a first light-emission control signal and a second light-emission control signal. The first light-emission control signal and the second light-emission control signal can be supplied sequentially, and no light-emission control signal can be supplied during a predetermined period between the first light-emission control signal and the second light-emission control signal. Therefore, during the predetermined period, the i-th light-emission control line Ei can be set to a gate-on voltage. Furthermore, the predetermined period can be set so as to compensate for the threshold voltage of the drive transistor and can partially overlap with the period of the first scan signal.

[0036] The scan driver 110 may be mounted on a substrate by a thin film process. In addition, the scan driver 110 may be located on both sides with the pixel unit 130 interposed therebetween. Figure 1The scan driver 110 is shown to supply the scan signal and the light emission control signal. However, in another embodiment, different drivers may supply the scan signal and the light emission control signal.

[0037] The data driver 120 may supply data signals to the data lines D1 to Dm based on the data drive control signal DCS. The data signals supplied to the data lines D1 to Dm may be supplied to the pixels 140 selected by the first scan signal. The data driver 120 may supply the data signals to the data lines D1 to Dm in synchronization with the first scan signal. Furthermore, before supplying the data signals, the data driver 120 may additionally supply a voltage of a reference power supply to the data lines D1 to Dm.

[0038] The pixel unit 130 may include pixels 140 coupled to scan lines S11 to S1n and S21 to S2n, emission control lines E1 to En, and data lines D1 to Dm. The pixels 140 may receive first and second driving power sources ELVDD and ELVSS and an initialization power source Vint from an external device.

[0039] Each pixel 140 may include a driving transistor and an organic light emitting diode (OLED), not shown. The driving transistor may control the amount of current flowing from a first driving power source (ELVDD) through the organic light emitting diode to a second driving power source (ELVSS) based on a data signal. An initialization power source (Vint) may be supplied to compensate for a threshold voltage and may be set to a voltage lower than a reference power source.

[0040] Figure 1 The diagram shows n scan lines S11 to S1n, n scan lines S21 to S2n, and n emission control lines E1 to En. However, in another embodiment, dummy scan lines and / or dummy emission control lines may be additionally formed based on the circuit configuration of the pixel 140.

[0041] also, Figure 1 The first scan lines S11 to S1n and the second scan lines S21 to S2n are shown. However, in another embodiment, a third scan line may be additionally formed based on the circuit configuration of the pixel 140.

[0042] Figure 2 The embodiment of the pixel 140 is shown in FIG. The pixel 140 may represent, for example, Figure 1 For illustration purposes, Figure 2 The pixel in is a pixel in the i-th horizontal line and is connected to the m-th data line Dm.

[0043] See also Figure 2, pixel 140 may include an oxide semiconductor thin film transistor and a low-temperature polycrystalline silicon (LTPS) thin film transistor. The oxide semiconductor thin film transistor may include a gate electrode, a source electrode, and a drain electrode. The oxide semiconductor thin film transistor may include an active layer including an oxide semiconductor. The oxide semiconductor may be configured as an amorphous oxide semiconductor or a crystalline oxide semiconductor. The oxide semiconductor thin film transistor may be an n-type transistor.

[0044] The LTPS thin film transistor may include a gate electrode, a source electrode, and a drain electrode. The LTPS thin film transistor may include an active layer including polycrystalline silicon. The LTPS thin film transistor may be a p-type thin film transistor or an n-type thin film transistor. According to an embodiment, it is assumed that the LTPS thin film transistor is an n-type thin film transistor. The LTPS thin film transistor may accordingly have high electron mobility and high driving characteristics. The oxide semiconductor thin film transistor may allow a low temperature process and have a lower charge mobility than the LTPS thin film transistor. The oxide semiconductor thin film transistor may have excellent cut-off current characteristics.

[0045] The pixel 140 may include a pixel circuit 142 and an organic light emitting diode OLED. The organic light emitting diode OLED has an anode coupled to the pixel circuit 142 and a cathode coupled to the second driving power source ELVSS. The organic light emitting diode OLED may generate light having a predetermined brightness based on the amount of current supplied from the pixel circuit 142.

[0046] The pixel circuit 142 can control the amount of current flowing from the first driving power source ELVDD through the organic light emitting diode OLED and to the second driving power source ELVSS based on the data signal. The pixel circuit 142 may include a first transistor M1 (L) (driving transistor), a second transistor M2 (O), a third transistor M3 (L), a fourth transistor M4 (L), and a storage capacitor Cst.

[0047] The first transistor M1(L) has a first electrode and a second electrode. The first electrode of the first transistor M1(L) is coupled to the second electrode of the fourth transistor M4(L), and the second electrode of the first transistor M1(L) may be connected to the anode of the organic light emitting diode OLED via the second node N2. The gate electrode of the first transistor M1(L) may be coupled to the first node N1. The first transistor M1(L) may control the amount of current flowing from the first driving power source ELVDD through the organic light emitting diode OLED to the second driving power source ELVSS based on the voltage of the first node N1. To achieve a predetermined (e.g., high) driving speed, the first transistor M1(L) may be an n-type LTPS thin-film transistor.

[0048] The second transistor M2(O) may be connected between the mth data line Dm and the first node N1. Furthermore, a gate electrode of the second transistor M2(O) may be coupled to the i-th first scan line S1i. When a first scan signal is supplied to the first scan line S1i, the second transistor M2(O) may be turned on. When the second transistor M2(O) is turned on, the data line Dm and the first node N1 may be electrically connected to each other.

[0049] When the second transistor M2(O) is an oxide semiconductor thin film transistor, the second transistor M2(O) may be an n-type thin film transistor. When the second transistor M2(O) is an oxide semiconductor thin film transistor, changes in the voltage of the first node N1 caused by leakage current can be prevented. As a result, an image with desired brightness can be displayed.

[0050] The third transistor M3(L) may be connected between the second node N2 and the initialization power supply Vint. A gate electrode of the third transistor M3(L) may be coupled to the i-th second scan line S2i. When a second scan signal is supplied to the second scan line S2i, the third transistor M3(L) may be turned on. When the third transistor M3(L) is turned on, the voltage of the initialization power supply Vint may be supplied to the second node N2. To achieve a predetermined (e.g., high) driving speed, the third transistor M3(L) may be an n-type LTPS thin-film transistor.

[0051] The fourth transistor M4(L) may be coupled between the first driving power source ELVDD and the first electrode of the first transistor M1(L). The gate electrode of the fourth transistor M4(L) may be coupled to the emission control line Ei. When an emission control signal is supplied to the emission control line Ei, the fourth transistor M4(L) may be turned off; and when the emission control signal is not supplied to the emission control line Ei, the fourth transistor M4(L) may be turned on. To achieve a predetermined (e.g., high) driving speed, the fourth transistor M4(L) may be an n-type LTPS thin-film transistor.

[0052] The storage capacitor Cst may be coupled between the first node N1 and the second node N2. The storage capacitor Cst may store a voltage corresponding to the data signal and a threshold voltage of the first transistor M1(L).

[0053] In the above embodiment, the second transistor M2(O) connected to the first node N1 may be an oxide semiconductor thin film transistor. When the second transistor M2(O) is an oxide semiconductor thin film transistor, changes in the voltage of the second node N2 caused by leakage current can be reduced. As a result, an image with desired brightness can be displayed.

[0054] Furthermore, transistors M4(L) and M1(L) located on a current supply path for supplying current to the organic light emitting diode OLED may be LTPS thin film transistors. When transistors M4(L) and M1(L) located on the current supply path are LTPS thin film transistors, current can be stably supplied to the organic light emitting diode OLED with high driving characteristics.

[0055] Figure 3 An embodiment of a method for driving a pixel is shown. The pixel may be, for example, Figure 2 Pixel 140 in. See Figure 3 , a light-emission control signal (low voltage) may be supplied to the light-emission control line Ei. As a result, the fourth transistor M4(L) may be turned off. The fourth transistor M4(L) is an n-type transistor. When the fourth transistor M4(L) is turned off, the electrical connection between the first driving power source ELVDD and the first transistor M1(L) may be blocked. Therefore, during the period when the light-emission control signal is supplied to the light-emission control line Ei, the pixel 140 may be set to a non-light-emitting state.

[0056] During a first period T11, a second scan signal may be supplied to the second scan line S2i. When the second scan signal is supplied to the second scan line S2i, the third transistor M3(L) may be turned on. The third transistor M3(L) is an n-type transistor. When the third transistor M3(L) is turned on, the voltage of the initialization power supply Vint may be supplied to the second node N2. The parasitic capacitor (e.g., organic capacitor Coled) of the organic light emitting diode OLED may be discharged. The voltage of the initialization power supply Vint may be lower than the voltage obtained by adding the threshold voltage of the organic light emitting diode OLED to the second driving power supply ELVSS. After the first period T11, the second scan signal may be stopped from being supplied to the second scan line S2i to maintain the third transistor M3(L) in an off state.

[0057] During the second period T12, a first scan signal may be supplied to the first scan line S1i. When the first scan signal is supplied to the first scan line S1i, the second transistor M2(O) may be turned on. The second transistor M2(O) is an n-type transistor. When the second transistor M2(O) is turned on, the data line Dm may be electrically connected to the first node N1. The voltage of the reference power supply Vref may be supplied from the data line Dm to the first node N1. The voltage of the reference power supply Vref may turn on the first transistor M1(L). For example, the voltage (Vref-Vint) obtained by subtracting the voltage of the initialization power supply Vint from the voltage of the reference power supply Vref may be greater than the threshold voltage of the first transistor M1(L). During the second period T12, the voltage Vgs of the first transistor M1(L) may be set to the voltage Vref-Vint, which is greater than the threshold voltage of the first transistor M1(L).

[0058] During the third period T13 between the second and fourth periods T12 and T14, the light emission control signal may be stopped from being supplied to the light emission control line Ei.

[0059] Therefore, during the third period T13, the fourth transistor M4 (L) may be temporarily turned on so that the voltage of the first driving power source ELVDD may be supplied to the first electrode of the first transistor M1 (L). Since the first transistor M1 (L) is set to the on state, the voltage of the second node N2 may be increased by the current from the first driving power source ELVDD.

[0060] During the third period T13, the first node N1 may maintain the voltage of the reference power supply Vref. Therefore, the voltage of the second node N2 may increase to a voltage obtained by subtracting the threshold voltage of the first transistor M1(L) from the voltage of the reference power supply Vref. The storage capacitor Cst may store the threshold voltage of the first transistor M1(L).

[0061] During the fourth period T14, a light emission control signal may be supplied to the light emission control line Ei to turn off the fourth transistor M4 (L). During the fourth period T14, a data signal DS may be supplied to the data line Dm. Since the second transistor M2 (O) is set to an on state during the fourth period T14, the data signal DS from the data line Dm may be supplied to the first node N1. The data signal DS supplied to the first node N1 may be stored in the storage capacitor Cst. In other words, during the third period T13 and the fourth period T14, a voltage corresponding to the data signal DS and the threshold voltage of the first transistor M1 (L) may be stored in the storage capacitor Cst.

[0062] During the fifth period T15, the supply of the light-emission control signal to the light-emission control signal line Ei may be stopped. The fifth period T15 may overlap with the period in which the first scan signal is supplied. Therefore, the second transistor M2(O) may be turned on during the fifth period T15 to maintain the first node N1 at the voltage of the data signal. When the supply of the light-emission control signal to the light-emission control signal line Ei is stopped, the fourth transistor M4(L) may be turned on.

[0063] When the fourth transistor M4(L) is turned on, the first driving power source ELVDD may be electrically connected to the first transistor M1(L). The first transistor M1(L) may be turned on, allowing a predetermined current to flow through the second node N2. A voltage corresponding to the current flowing from the first transistor M1(L) may be stored in a capacitance (C=Cst+Coled) obtained by coupling the storage capacitor Cst and the organic capacitor Coled. As a result, the voltage of the second node N2 may be increased.

[0064] The increase in the voltage of the second node N2 may correspond to the mobility of the first transistor M1(L), and may vary from pixel to pixel 140. For example, according to an embodiment, the fifth period T15 may be a period during which the mobility of the first transistor M1(L) is compensated. The time allocated to the fifth period T15 may be determined empirically to compensate for the mobility of the first transistor M1(L) included in each of the pixels 140.

[0065] During the sixth period T16, the first scan signal may be stopped from being supplied to the first scan line S1i, thereby turning off the second transistor M2(O). During the sixth period T16, the first transistor M1(L) may control the amount of current flowing from the first driving power source ELVDD through the organic light emitting diode OLED to the second driving power source ELVSS based on the voltage of the first node N1. The organic light emitting diode OLED may generate light having a predetermined brightness based on the current.

[0066] According to an embodiment, the second transistor M2(O) connected to the first node N1 may be an oxide semiconductor thin film transistor. As a result, leakage current from the first node N1 may be reduced, and the first node N1 may maintain a predetermined voltage during one frame period. For example, according to an embodiment, leakage current from the first node N1 may be reduced, and an image with desired brightness may be displayed.

[0067] Figure 4 Another embodiment of a pixel 140a is shown. Pixel 140a may include a pixel circuit 142' and an organic light-emitting diode (OLED). The organic light-emitting diode (OLED) has an anode connected to the pixel circuit 142' and a cathode coupled to a second driving power source (ELVSS). The organic light-emitting diode (OLED) may generate light having a predetermined brightness based on the amount of current supplied from the pixel circuit 142'.

[0068] The pixel circuit 142' may include a first transistor M1 (L), a second transistor M2 (O), a third transistor M3 (L), a fourth transistor M4 (L), a fifth transistor M5 (O) and a storage capacitor Cst. In addition to the pixel circuit 142' further including the fifth transistor M5 (O), the pixel circuit 142' may have the same Figure 2The pixel circuit 142 in FIG. 1 is configured substantially the same as the pixel circuit 142 in FIG. The fifth transistor M5(O) can supply the voltage of the reference power supply Vref to the first node N1. However, the reference power supply Vref may not be supplied to the data line Dm. Therefore, the data signal DS can be supplied to the data line Dm for a sufficient period of time, thereby improving driving reliability.

[0069] The fifth transistor M5(O) may be connected between a reference power source Vref and the first node N1. Furthermore, a gate electrode of the fifth transistor M5(O) may be coupled to the third scan line S3i. When a third scan signal is supplied to the third scan line S3i, the fifth transistor M5(O) may be turned on and may supply a voltage of the reference power source Vref to the first node N1.

[0070] The fifth transistor M5(O) may be an n-type oxide semiconductor thin film transistor. When the fifth transistor M5(O) is an oxide semiconductor thin film transistor, a change in the voltage of the first node N1 caused by leakage current may be prevented, and an image with desired brightness may be displayed.

[0071] Figure 5 An embodiment of a waveform diagram corresponding to a method for driving a pixel, which may be Figure 4 Pixel 140a in. Figure 5 , a light-emission control signal may be supplied to the light-emission control line Ei to turn off the fourth transistor M4(L). When the fourth transistor M4(L) is turned off, the electrical connection between the first driving power source ELVDD and the first transistor M1(L) may be blocked. Therefore, during the period when the light-emission control signal is supplied to the light-emission control line Ei, the pixel 140a may be set to a non-light-emitting state.

[0072] During the first period T11', a second scan signal may be supplied to the second scan line S2i, and a third scan signal may be supplied to the third scan line S3i. When the second scan signal is supplied to the second scan line S2i, the third transistor M3(L) may be turned on. When the third transistor M3(L) is turned on, the voltage of the initialization power supply Vint may be supplied to the second node N2. The organic capacitor Coled may be discharged. When the third scan signal is supplied to the third scan line S3i, the fifth transistor M5(O) may be turned on. When the fifth transistor M5(O) is turned on, the voltage of the reference power supply Vref may be supplied to the first node N1.

[0073] During the second period T12', the second scan signal may be stopped from being supplied, and the third transistor M3(L) may be set to an off state. In addition, during a portion of the second period T12', the light emission control signal may be stopped from being supplied to the light emission control line Ei.

[0074] When the light emission control signal is stopped from being supplied to the light emission control line Ei, the fourth transistor M4(L) may be turned on. When the fourth transistor M4(L) is turned on, the voltage of the first driving power source ELVDD may be supplied to the first electrode of the first transistor M1(L). When the voltage of the first driving power source ELVDD is supplied to the first electrode of the first transistor M1(L), the first transistor M1(L) may be turned on and the voltage of the second node N2 may be increased.

[0075] Since the first node N1 maintains the voltage of the reference power supply Vref, the voltage of the second node N2 can increase to a voltage obtained by subtracting the threshold voltage of the first transistor M1(L) from the voltage of the reference power supply Vref. The storage capacitor Cst can store the threshold voltage of the first transistor M1(L).

[0076] After the second period T12', the supply of the third scan signal to the third scan line S3i may be stopped. When the supply of the third scan signal to the third scan line S3i is stopped, the fifth transistor M5(O) may be turned off.

[0077] During the third period T13', a first scan signal may be supplied to the first scan line S1i. When the first scan signal is supplied to the first scan line S1i, the second transistor M2(O) may be turned on. When the second transistor M2(O) is turned on, the data line Dm and the first node N1 may be electrically connected to each other. The data signal DS from the data line Dm may be supplied to the first node N1.

[0078] The data signal DS supplied to the first node N1 may be stored in the storage capacitor Cst. For example, during the second and third periods T12' and T13', a voltage corresponding to the data signal DS and a threshold voltage of the first transistor M1(L) may be stored in the storage capacitor Cst.

[0079] During the fourth period T14', the light emitting control signal may be stopped from being supplied to the light emitting control line Ei. When the light emitting control signal is stopped from being supplied to the light emitting control line Ei, the fourth transistor M4 (L) may be turned on.

[0080] When the fourth transistor M4(L) is turned on, the first driving power source ELVDD and the first transistor M1(L) may be electrically connected to each other. When the first transistor M1(L) is turned on, a predetermined current may flow through the second node N2. A voltage corresponding to the current flowing out of the first transistor M1(L) may be stored in a capacitance (C=Cst+Coled) obtained by coupling the storage capacitor Cst and the organic capacitor Coled, thereby increasing the voltage of the second node N2. The increase in the voltage of the second node N2 may correspond to the mobility of the first transistor M1(L) and may vary depending on the pixel 140a. As a result, the mobility of the first transistor M1(L) may be compensated. The time allocated to the fourth period T14' may be determined empirically to compensate for the mobility of the first transistor M1(L) included in each of the pixels 140a.

[0081] During the fifth period T15', the first scan signal may be stopped from being supplied to the first scan line S1i, turning off the second transistor M2(O). During the fifth period T15', the first transistor M1(L) may control the amount of current flowing from the first driving power source ELVDD through the organic light emitting diode OLED to the second driving power source ELVSS based on the voltage of the first node N1. Thus, the organic light emitting diode OLED may generate light having a predetermined brightness based on the amount of current.

[0082] According to an embodiment, the second transistor M2(O) and the fifth transistor M5(O) coupled to the first node N1 may be oxide semiconductor thin film transistors. Therefore, leakage current from the first node N1 can be reduced, and the first node N1 can maintain a predetermined voltage during one frame period. For example, according to an embodiment, leakage current from the first node N1 can be reduced to display an image with desired brightness.

[0083] Figure 6 Another embodiment of a pixel 140b is shown. For illustrative purposes, the pixel 140b is a pixel located on the i-th horizontal line and the m-th data line Dm.

[0084] See also Figure 6 , the pixel 140b may include a pixel circuit 142″ and an organic light emitting diode OLED. The organic light emitting diode OLED has an anode connected to the pixel circuit 142″ and a cathode coupled to the second driving power source ELVSS. The organic light emitting diode OLED may generate light having a predetermined brightness based on the amount of current supplied from the pixel circuit 142″.

[0085] and Figure 2Compared to the pixel 140 in FIG. 1 , the pixel 140b may further include a first capacitor C1 between the first driving power source ELVDD and the second node N2. The first capacitor C1 may be connected in series with the organic capacitor Coled, thereby reducing the capacitance of the capacitor coupled to the second node N2.

[0086] In order to stably maintain the voltage Vgs of the first transistor M1 (L), the voltage of the second node N2 may vary based on the variation of the voltage of the first node N1.

[0087] When the pixel circuit 142″ does not include the first capacitor C1, the second node N2 may be coupled to the organic capacitor Coled. The organic capacitor Coled may have a capacitance greater than that of the storage capacitor Cst. Therefore, a change in the voltage of the second node N2 caused by a change in the voltage of the first node N1 may be reduced. For example, when the voltage of the first node N1 changes by 1V, the voltage of the second node N2 may change by 0.5V.

[0088] When the pixel circuit 142″ includes the first capacitor C1, the second node N2 can be coupled to the first capacitor C1 and the organic capacitor Coled. Since the first capacitor C1 and the organic capacitor Coled are coupled in series, the capacitance of the capacitor connected to the second node N2 can be reduced. Therefore, the voltage of the second node N2 can be stably changed based on the change in the voltage of the second node N2, thereby ensuring driving reliability. For example, if the pixel circuit 142″ includes the first capacitor C1, when the voltage of the first node N1 changes by 1V, the voltage of the second node N2 can change by 0.8V, which is greater than 0.5V.

[0089] In some embodiments, the first capacitor C1 may be located at Figure 2 and Figure 4 According to another embodiment, the gate electrode of the third transistor M3 (L) may be connected to the i-1th first scan line S1i-1. The second scan line S2i may be connected from Figure 2 The pixel circuit 142 is removed.

[0090] Figure 7 Another embodiment of a method for driving a pixel is shown. The pixel may be, for example, Figure 6 For the purpose of illustration, only the data signals corresponding to the (i-1)th horizontal line and the (i)th horizontal line are illustrated.

[0091] See also Figure 7In the embodiment of the present invention, two scan signals (e.g., a first scan signal and a second scan signal) may be sequentially supplied to the first scan line S1 at a predetermined time period. The second scan signal supplied to the (i-1)th first scan line S1i-1 may overlap with the first scan signal supplied to the (i)th first scan line S1i.

[0092] For example, a light-emission control signal may be supplied to the light-emission control line Ei to turn off the fourth transistor M4(L). When the fourth transistor M4(L) is turned off, the electrical connection between the first driving power source ELVDD and the first transistor M1(L) may be blocked. Therefore, during the period when the light-emission control signal is supplied to the light-emission control line Ei, the pixel 140b may be set to a non-light-emitting state.

[0093] During the first period T11″, the second scan signal may be supplied to the (i-1)th first scan line S1i-1, and the first scan signal may be supplied to the (i-1)th first scan line S1i. When the second scan signal is supplied to the (i-1)th first scan line S1i-1, the third transistor M3′(L) may be turned on. When the third transistor M3′(L) is turned on, the voltage of the initialization power supply Vint may be supplied to the second node N2.

[0094] When the first scan signal is supplied to the i-th first scan line S1i, the second transistor M2(O) may be turned on. When the second transistor M2(O) is turned on, the voltage of the reference power source Vref from the data line Dm may be supplied to the first node N1.

[0095] Subsequently, during the second period T12″, the supply of the first scan signal to the i-th first scan line S1i may be stopped to turn off the second transistor M2(O). The third transistor M3′(L) may be maintained in a turned-on state by the second scan signal supplied to the i-1-th first scan line S1i-1. As a result, the second node N2 may maintain the voltage of the initialization power supply Vint. In addition, since the voltage of the second node N2 does not change during the second period T12″, the first node N1 set to a floating state may maintain the voltage of the reference power supply Vref.

[0096] During the third period T13″, the supply of the light emitting control signal to the light emitting control line Ei may be stopped, and the second scan signal may be supplied to the i-th first scan line S1i. When the second scan signal is supplied to the i-th first scan line S1i, the second transistor M2(O) may be turned on. When the second transistor M2(O) is turned on, the data line Dm may be electrically connected to the first node N1. The voltage of the reference power supply Vref from the data line Dm may be supplied to the first node N1.

[0097] When the light emission control signal is stopped from being supplied to the light emission control line Ei, the fourth transistor M4(L) may be turned on. When the fourth transistor M4(L) is turned on, the voltage of the first driving power source ELVDD may be supplied to the first electrode of the first transistor M1(L). When the voltage of the first driving power source ELVDD is supplied to the first electrode of the first transistor M1(L), the first transistor M1(L) may be turned on to increase the voltage of the second node N2.

[0098] During the third period T13″, the first node N1 may maintain the voltage of the reference power supply Vref. Therefore, the voltage of the second node N2 may increase to a voltage obtained by subtracting the threshold voltage of the first transistor M1(L) from the voltage of the reference power supply Vref. The threshold voltage of the first transistor M1(L) may be stored in the storage capacitor Cst.

[0099] During the fourth period T14", the light emitting control signal may be supplied to the light emitting control line Ei to turn off the fourth transistor M4 (L). During the fourth period T14", the data signal DS may be supplied to the data line Dm. Since the second transistor M2 (O) is set to the on state during the fourth period T14", the data signal DS from the data line Dm may be supplied to the first node N1. The data signal DS supplied to the first node N1 may be stored in the storage capacitor Cst. For example, during the third period T13" and the fourth period T14", a voltage corresponding to the data signal DS and the threshold voltage of the first transistor M1 (L) may be stored in the storage capacitor Cst.

[0100] During the fifth period T15″, the supply of the light emitting control signal to the light emitting control line Ei is stopped. When the supply of the light emitting control signal to the light emitting control line Ei is stopped, the fourth transistor M4(L) may be turned on. When the fourth transistor M4(L) is turned on, the first driving power source ELVDD may be electrically connected to the first transistor M1(L). The first transistor M1(L) may control an amount of current flowing from the first driving power source ELVDD through the organic light emitting diode OLED and to the second driving power source ELVSS based on the voltage of the first node N1. The organic light emitting diode OLED may generate light having a predetermined brightness based on the amount of current.

[0101] According to one embodiment, the second transistor M2(O) coupled to the first node N1 may be an oxide semiconductor thin film transistor. As a result, leakage current from the first node N1 can be reduced, and the first node N1 can maintain a predetermined voltage during one frame period. For example, according to one embodiment, leakage current from the first node N1 can be reduced, and an image with desired brightness can be displayed.

[0102] The scan driver 110 may include a plurality of stage circuits to generate scan signals and light emission control signals. Each stage circuit may include a signal generator and a buffer for generating signals (scan signals and / or light emission control signals).

[0103] Figure 8 As shown in the figure, an embodiment of a stage circuit may include a signal generator 300 and a buffer 200. The signal generator 300 may control the buffer 200 based on a clock signal and a start pulse, for example. The buffer 200 may electrically connect the first input terminal 202 or the second input terminal 204 to the output terminal 206 based on the control of the signal generator 300. The buffer 200 may include an eleventh transistor M11 (L), a twelfth transistor M12 (O), a thirteenth transistor M13 (L), and a fourteenth transistor M14 (O).

[0104] The eleventh transistor M11(L) and the twelfth transistor M12(O) may be connected in parallel between the first input terminal 202 and the output terminal 206. A gate electrode of the eleventh transistor M11(L) may be electrically connected to a gate electrode of the twelfth transistor M12(O).

[0105] The eleventh transistor M11 (L) and the twelfth transistor M12 (O) can be turned on or off simultaneously to control the electrical connection between the first input terminal 202 and the output terminal 206. By controlling the electrical connection between the first input terminal 202 and the output terminal 206 using the eleventh transistor M11 (L) and the twelfth transistor M12 (O) connected in parallel between the first input terminal 202 and the output terminal 206, driving reliability can be ensured.

[0106] The eleventh transistor M11 (L) may be an n-type LTPS thin film transistor, and the twelfth transistor M12 (O) may be an n-type oxide semiconductor thin film transistor. The LTPS thin film transistor may have a top-gate structure, and the oxide semiconductor thin film transistor may have a bottom-gate structure.

[0107] During the manufacturing process, the eleventh transistor M11(L) and the twelfth transistor M12(O) may at least partially overlap with each other. For example, at least one of the gate electrode, source electrode, and drain electrode of the eleventh transistor M11(L) may overlap with at least one of the gate electrode, source electrode, and drain electrode of the twelfth transistor M12(O). When the eleventh transistor M11(L) and the twelfth transistor M12(O) overlap with each other, the installation area of ​​the buffer 200 can be reduced, thereby reducing the no-signal area.

[0108] The thirteenth transistor M13 (L) and the fourteenth transistor M14 (O) may be connected in parallel between the output terminal 206 and the second input terminal 204. In addition, the gate electrode of the thirteenth transistor M13 (L) may be electrically connected to the gate electrode of the fourteenth transistor M14 (O).

[0109] The thirteenth transistor M13 (L) and the fourteenth transistor M14 (O) can be turned on or off simultaneously to control the electrical connection between the second input terminal 204 and the output terminal 206. By controlling the electrical connection between the second input terminal 204 and the output terminal 206 using the thirteenth transistor M13 (L) and the fourteenth transistor M14 (O) connected in parallel between the second input terminal 204 and the output terminal 206, driving reliability can be ensured.

[0110] In addition, the thirteenth transistor M13 (L) may be an n-type LTPS thin film transistor, and the fourteenth transistor M14 (O) may be an n-type oxide semiconductor thin film transistor. The LTPS thin film transistor may have a top-gate structure, and the oxide semiconductor thin film transistor may have a bottom-gate structure.

[0111] During the manufacturing process, the thirteenth transistor M13(L) and the fourteenth transistor M14(O) may at least partially overlap with each other. For example, at least one of the gate electrode, source electrode, and drain electrode of the thirteenth transistor M13(L) may overlap with at least one of the gate electrode, source electrode, and drain electrode of the fourteenth transistor M14(O). When the thirteenth transistor M13(L) and the fourteenth transistor M14(O) overlap with each other, the installation area of ​​the buffer 200 can be reduced, and thus, the no-signal area can be reduced.

[0112] The methods described herein, processes and / or operations can be performed by the code or instructions to be run by a computer, processor, controller or other signal processing device. The computer, processor, controller or other signal processing device can be those described herein or can be an element other than the elements described herein. Because the algorithm forming the basis of the method (or the operation of the computer, processor, controller or other signal processing device) is described in detail, the code or instructions for realizing the operation of the method embodiment can convert the computer, processor, controller or other signal processing device into a special-purpose processor for performing the method described herein.

[0113] The drivers, generators, and other processing features of the embodiments disclosed herein may be implemented in logic, which may include, for example, hardware, software, or both. When implemented at least partially in hardware, the drivers, generators, and other processing features may be, for example, any of a variety of integrated circuits, including but not limited to application specific integrated circuits, field programmable gate arrays, combinations of logic gates, systems on chips, microprocessors, or other types of processing or control circuitry.

[0114] When implemented at least in part in software, the drivers, generators, and other processing features may include, for example, a memory or other storage device for storing code or instructions executed, for example, by a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be those described herein or may be an element other than the elements described herein. Because the algorithms forming the basis of the method (or the operation of the computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operation of the method embodiments may convert the computer, processor, controller, or other signal processing device into a dedicated processor for performing the methods described herein.

[0115] According to one or more of the foregoing embodiments, a pixel may include an oxide semiconductor thin film transistor and an ITPS thin film transistor. An oxide semiconductor thin film transistor having excellent off-state characteristics may be located in a leakage current path. Thus, leakage current may be reduced and an image with desired brightness may be displayed.

[0116] Furthermore, an LTPS thin-film transistor (TFT), which has excellent driving characteristics, can be positioned in the current supply path for supplying current to the organic light-emitting diode. As a result, the fast driving characteristics of the LTPS TFT ensure stable current supply to the organic light-emitting diode. Furthermore, the buffer can include both an oxide semiconductor TFT and an LTPS TFT. This improves driving characteristics while reducing the size of the buffer's mounting area.

[0117] Exemplary embodiments have been disclosed herein, and although specific terms are employed, these terms should be used and interpreted in a generic and illustrative sense only and not for purposes of limitation. In some cases, it will be apparent to one of ordinary skill in the art that, as of the date of filing this application, unless otherwise indicated, features, characteristics, and / or elements described herein in connection with a specific embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Accordingly, various changes in form and details may be made without departing from the spirit and scope of the embodiments set forth in the claims.

Claims

1. A pixel comprising: a first transistor including a first electrode, a second electrode, and a gate electrode connected to a first node; a second transistor comprising a first electrode connected to the first transistor, a second electrode connected to the data line, and a gate electrode connected to the first scan line; a storage capacitor comprising a first electrode connected to the first node and a second electrode connected to a second node; a third transistor including a gate electrode, a first electrode connected to the second node, and a second electrode connected to an initialization power source; a fourth transistor including a first electrode connected to a first driving power source, a second electrode connected to the first electrode of the first transistor, and a gate electrode connected to a light emitting control line; as well as a fifth transistor including a first electrode, a second electrode connected to the first node, and a gate electrode connected to a second scan line, wherein the fifth transistor is an n-type oxide semiconductor transistor; wherein the first transistor, the third transistor, and the fourth transistor are n-type low temperature polysilicon transistors; and The first scan line and the second scan line are separated from each other.

2. The pixel according to claim 1, further comprising: The light emitting diode includes a first electrode connected to the second node and a second electrode connected to a second driving power source.

3. The pixel according to claim 1, wherein The second transistor is an n-type oxide semiconductor transistor.

4. The pixel according to claim 1, wherein The first electrode of the fifth transistor is connected to a reference power source.

5. The pixel according to claim 1, wherein The second electrode of the first transistor is connected to the second node. The pixel according to claim 1 , wherein: The first electrode of the second transistor is connected to the first node.

7. The pixel according to claim 1, in, The gate electrode of the third transistor is connected to a third scan line, wherein a scan signal of an off level is supplied to the first scan line during a first period, wherein a scanning signal of an on level is supplied to the second scanning line during the first period, and The scan signal of the on level is supplied to the third scan line during the first period.

8. The pixel according to claim 7, in, A scan signal of an on level is supplied to the first scan line during a second period after the first period, wherein the off-level scan signal is supplied to the second scan line during the second period, The off-level scan signal is supplied to the third scan line during the second period.

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