A test element group and a test method thereof

Abstract

The application discloses a test element group and a test method. The test element group comprises: a plurality of output drivers, an IO node end of each output driver is electrically connected with a data IO end of a memory, and is used for testing output signal quality of the data IO end. Each output driver comprises a pull-up driver and a pull-down driver. The pull-up driver comprises a plurality of P-type transistors, and the pull-down driver comprises a plurality of N-type transistors. By designing that the plurality of output drivers are electrically connected with DQ ends of the memory respectively, high level and low level are input from the DQ ends of the memory respectively, and different transistors in the output drivers are selectively turned on, so that a plurality of current values can be measured. Since the current values can reflect output signal quality of a single DQ end, whether the output signal quality of the single DQ end is good or bad can be accurately judged. Moreover, a chip problem can be detected early in a TEG stage, so that a chip end face is corrected, and test cost and time are saved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a test element group and a test method thereof. BACKGROUND

[0002] In the semiconductor manufacturing process of a memory product, as the process is miniaturized, in the later stage of the memory product process, multiple product test stages are required to screen out good products and defective products, and the output signal quality test of the memory product is one of the test stages, that is, if the output signal quality is poor, it will cause the device to be unstable, the function to be executed incorrectly, and even malfunction.

[0003] In the related art, after the memory chip is produced (Fab out), the output signal waveforms of all DQ ends (i.e., data IO ends) of the memory chip are tested, and all DQ end output signal waveforms are superimposed to form an eye diagram, and then the quality of the memory chip output signal is judged according to the eye diagram.

[0004] However, this eye diagram test method will cause the deviation between different DQ ends of the memory chip, the mismatch of the on-die termination (ODT) of each DQ end, and the difference between each memory chip or wafer, etc., which will cause the loss of the eye diagram and affect the test result. SUMMARY

[0005] The present application aims to solve the above problems of the prior art, and provides a test element group and a test method thereof.

[0006] The first aspect of the present application provides a test element group for testing the data input / output IO end of a memory, comprising:

[0007] At least one output driver, the IO node end of each output driver is used to be electrically connected with one data IO end of the memory, and each output driver comprises a pull-up driver and a pull-down driver;

[0008] The pull-up driver comprises a plurality of P-type transistors, and the pull-down driver comprises a plurality of N-type transistors.

[0009] The second aspect of the present application provides a test method of a test element group, the method comprising:

[0010] Electrically connecting the IO node end of each output driver with one data IO end of the memory;

[0011] determining a currently selected output driver, and after controlling the data IO end of the memory to input a high level to the output driver, controlling multiple N-type transistors included in a pull-down driver in the output driver to be turned on in turn, and measuring current values of the IO node end to obtain multiple current values;

[0012] after controlling the data IO end of the memory to input a low level to the output driver, controlling multiple P-type transistors included in a pull-up driver in the output driver to be turned on in turn, and measuring current values of the IO node end to obtain multiple current values.

[0013] Based on the test element group and the test method thereof according to the first aspect and the second aspect, the present application has the following beneficial effects:

[0014] In the TEG (test element group) stage, the present application can measure multiple current values by designing multiple output drivers to be electrically connected with DQ ends of a memory chip respectively, inputting high level signals and low level signals from the DQ ends of the memory chip respectively, and selectively turning on different transistors in the output drivers. Since the current values can reflect the output signal quality of a single DQ end of the memory chip, the signal quality output by the single DQ end can be accurately judged, and the local problem of the chip can be accurately located. Compared with the existing production of the memory chip, the present application can detect the chip problem in the TEG stage, so that the chip end face can be corrected, the test cost and time can be saved, and the product yield can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0015] The accompanying drawings, which are included to provide a further understanding of the present application and constitute a part of this application, illustrate certain illustrative embodiments of the present application and together with the description serve to explain the present application. In the drawings:

[0016] Figure 1 a structure schematic diagram of a test element group according to an example embodiment of the present application;

[0017] Figure 2 a structure schematic diagram of an output driver according to the example embodiment of the present application; Figure 1

[0018] Figure 3 a test principle schematic diagram according to the example embodiment of the present application; Figure 2

[0019] a test principle schematic diagram according to the example embodiment of the present application; Figure 4 EMBODIMENT OF THE PRESENT INVENTION​​

[0020] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It is to be understood, however, that the description is merely exemplary of the present disclosure, but is not intended to limit the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid obscuring the concept of the present disclosure.

[0021] In the drawings, various structural diagrams according to embodiments of the present disclosure are shown. These diagrams are not drawn to scale in that certain details are exaggerated for the purpose of clarity, and that certain other details are omitted. The shapes of various regions, layers, and the relative sizes and positional relationships among them shown in the drawings are merely exemplary and can deviate in actuality due to manufacturing tolerances or technical limitations, and regions / layers having different shapes, sizes, and relative positions can be additionally designed by those skilled in the art as needed.

[0022] In the context of the present disclosure, when a layer / element is referred to as being located "on" another layer / element, the layer / element can be directly on the other layer / element, or an intervening layer / element can be present therebetween. In addition, if a layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed.

[0023] At present, the test on the output signal quality of a memory chip is performed after the chip is produced, in which the output signals of all DQ terminals of the memory chip are measured, the waveforms of all the output signals are superimposed to form an eye diagram, and then the overall performance of the memory chip is judged according to the eye diagram and the waveform of the output signal of the DQ terminal, so as to screen out good products and defective products.

[0024] However, the deviation between the DQ terminals of the memory chip due to the layout design and the mismatch of the on-chip terminal of the DQ terminal will cause eye diagram loss, affect the accurate judgment of the performance of the memory chip, and the test after production will also take a lot of time, which is not conducive to the production efficiency of the memory chip.

[0025] To solve the above technical problem, the present application provides a test element group to complete the output signal quality test of the DQ terminal of the memory chip in the TEG stage at the initial stage of the test, as shown in Figure 1 The test element group includes output driver 1, output driver 2, …, output driver n (n≥1), the IO node end A of each output driver is used to be electrically connected with one data IO terminal of the memory chip, and each output driver includes a pull-up driver and a pull-down driver.

[0026] It should be noted that the pull-up driver includes a plurality of P-type transistors, and the pull-down driver includes a plurality of N-type transistors.

[0027] In the present application, by designing multiple output drivers, the IO of one output driver is connected to multiple data IOs.

[0028] In the test, when a high level is input to the IO node end A from the data IO of the memory chip, multiple current values can be measured at the IO node end A by selectively turning on the N-type transistors in the pull-down driver in turn; after a low level is input to the IO node end A from the data IO of the memory chip, multiple current values can be measured at the IO node end A by selectively turning on the P-type transistors in the pull-up driver in turn.

[0029] It can be seen that, in the TEG stage, by designing multiple output drivers respectively electrically connected to the DQ ends of the memory chip, inputting high level signals and low level signals from the DQ ends of the memory chip respectively, and selectively turning on different transistors in the output drivers, multiple current values can be measured. Since these current values can reflect the output signal quality of a single DQ end of the memory chip, the signal quality output by a single DQ end can be accurately judged, and the local problem of the chip can be accurately located. Compared with the existing production after testing the overall performance of the memory chip, the chip problem can be detected in the TEG stage of the present application, so that the chip end face can be corrected, the test cost and time can be saved, and the product yield can be improved.

[0030] In some embodiments, as shown in Figure 1 , the test element group can further include a controller 30 and a decoder 20 to realize the selection and automatic control of multiple output drivers. Further, the controller 30 is electrically connected to the decoder 20, and the decoder 20 is electrically connected to the control end B of each output driver.

[0031] Among them, the controller 30 is used to send a selection signal of the output driver to the decoder 20; the decoder 20 is used to decode the selection signal to determine the selected output driver, and then send different control signals to the control end B of the selected output driver, so that the multiple N-type transistors included in the pull-down driver and the multiple P-type transistors included in the pull-up driver can be turned on in turn, and then the current value of the IO node end is measured once for each control transistor.

[0032] In some embodiments, as shown in Figure 1 , the test element group can further include a measurement device 40, which needs to be electrically connected to the IO node end A of each output driver for automatically measuring the current value of the IO node end A.

[0033] It should be noted that the measuring device 40 can also be electrically connected with the controller 30, so that the measuring device 40 can automatically determine the output driver to be measured according to the selection signal generated by the controller.

[0034] The specific structure of the output driver will be described below by taking an example of the pull-up driver and the pull-down driver in the output driver each including three transistors.

[0035] As shown in Figure 2 , the pull-up driver includes a first P-type transistor PU1, a second P-type transistor PU2 and a third P-type transistor PU3, so that the control end B of the output driver needs to include a first control end B1, a second control end B2 and a third control end B3.

[0036] The specific connection mode is that the first electrode of the first P-type transistor PU1, the first electrode of the second P-type transistor PU2 and the first electrode of the third P-type transistor PU3 are electrically connected with the power voltage end VDDQ; the second electrode of the first P-type transistor PU1, the second electrode of the second P-type transistor PU2 and the second electrode of the third P-type transistor PU3 are electrically connected with the IO node end A; the third electrode of the first P-type transistor PU1 is electrically connected with the first control end B1, the third electrode of the second P-type transistor PU2 is electrically connected with the second control end B2, and the third electrode of the third P-type transistor PU3 is electrically connected with the third control end B3.

[0037] As shown in Figure 2 , the pull-down driver includes a first N-type transistor PD1, a second N-type transistor PD2 and a third N-type transistor PD3, so that the control end B of the output driver needs to further include a fourth control end B4, a fifth control end B5 and a sixth control end B6.

[0038] The specific connection mode is that the first electrode of the first N-type transistor PD1, the first electrode of the second N-type transistor PD2 and the first electrode of the third N-type transistor PD3 are electrically connected with the IO node end A; the second electrode of the first N-type transistor PD1, the second electrode of the second N-type transistor PD2 and the second electrode of the third N-type transistor PD3 are electrically connected with the ground end VSSQ; the third electrode of the first N-type transistor PD1 is electrically connected with the fourth control end B4, the third electrode of the second N-type transistor PD2 is electrically connected with the fifth control end B5, and the third electrode of the third N-type transistor PD3 is electrically connected with the sixth control end B6.

[0039] It should be noted that, for both N-type transistors and P-type transistors, the first electrode is the source, the second electrode is the drain, and the third electrode is the gate.

[0040] Furthermore, since the gate input of the N-type transistor is high and the gate input of the P-type transistor is low, when controlling the three P-type transistors in the pull-up driver to conduct in turn, it is necessary to input low levels to the first control terminal B1, the second control terminal B2, and the third control terminal B3 in turn; when controlling the three N-type transistors in the pull-down driver to conduct in turn, it is necessary to input high levels to the fourth control terminal B4, the fifth control terminal B5, and the sixth control terminal B6 in turn.

[0041] like Figure 3 As shown, this illustrates the test principle for turning on the first N-type transistor. When a high-level signal is input to the IO node A of the output driver, high-level signals are also input to the first control terminal B1, the second control terminal B2, the third control terminal B3, and the fourth control terminal B4, while low-level signals are input to the fifth control terminal B5 and the sixth control terminal B6. At this time, the first N-type transistor PD1 is turned on, while the first P-type transistor PU1, the second P-type transistor PU2, the third P-type transistor PU3, the second N-type transistor PD2, and the third N-type transistor PD3 are all turned off. The current value at the IO node A is then measured.

[0042] Corresponding to the aforementioned test element group embodiments, this application also provides embodiments of test methods for the test element group.

[0043] Figure 4 This is a flowchart illustrating an embodiment of a test method for a test element group according to an exemplary embodiment of this application. Figures 1 to 3 Based on the illustrated embodiment, the testing method for this test element group includes the following steps:

[0044] Step 401: Electrically connect the I / O node of each output driver to a data I / O terminal of the memory.

[0045] Step 402: Determine the currently selected output driver, and after controlling the data I / O terminal of the memory to input a high level to the output driver, control the multiple N-type transistors included in the pull-down driver of the output driver to turn on in turn, and measure the current value at the I / O node terminal to obtain multiple current values.

[0046] Based on the above Figure 1 In the illustrated embodiment, the process of determining the currently selected output driver can be implemented through the controller's control program. That is, the controller sends an output driver selection signal to the decoder, and the decoder decodes the selection signal to determine the selected output driver.

[0047] Furthermore, the decoder executes a turn-on procedure to turn on multiple N-type transistors in turn, and the measuring device automatically measures the current value at the IO node of the selected output driver.

[0048] It should be noted that the current measured by the measuring device is the sum of the source-drain current of the conducting N-type transistor and the leakage current of the non-conducting N-type transistor. The leakage current is relatively small compared to the source-drain current and can be ignored.

[0049] For example, suppose 1 represents a high level and 0 represents a low level, such as Figure 2 As shown, when the level signals input by the decoder to the first control terminal B1 to the sixth control terminal B6 are sequentially 111100, the first N-type transistor is turned on, and the measuring device can measure a current value, which is the sum of the source-drain current of the first N-type transistor, the leakage current of the second N-type transistor, and the leakage current of the third N-type transistor; when the level signals input by the decoder to the first control terminal B1 to the sixth control terminal B6 are sequentially 111010, the second N-type transistor is turned on, and the measuring device can measure a current value, which is the sum of the source-drain current of the second N-type transistor, the leakage current of the first N-type transistor, and the leakage current of the third N-type transistor; when the level signals input by the decoder to the first control terminal B1 to the sixth control terminal B6 are sequentially 111001, the third N-type transistor is turned on, and the measuring device can measure a current value, which is the sum of the source-drain current of the third N-type transistor, the leakage current of the first N-type transistor, and the leakage current of the second N-type transistor.

[0050] Step 403: After the data I / O terminal of the control memory inputs a low level to the output driver, the multiple P-type transistors included in the pull-up driver of the output driver are turned on in turn, and the current value at the I / O node is measured to obtain multiple current values.

[0051] Based on the same principle as step 402 above, when the data I / O terminal of the control memory inputs a low level to the output driver, the measured current value is the sum of the source-drain current of the conducting P-type transistor and the leakage current of the non-conducting P-type transistor.

[0052] Continue as Figure 2As shown, when the level signals input by the decoder to the first control end B1 to the sixth control end B6 are 011000 in sequence, the first P-type transistor is turned on, and the measuring device can measure a current value, which is the sum of the source-drain current of the first P-type transistor, the leakage current of the second P-type transistor and the leakage current of the third P-type transistor; when the level signals input by the decoder to the first control end B1 to the sixth control end B6 are 101000 in sequence, the second P-type transistor is turned on, and the measuring device can measure a current value, which is the sum of the source-drain current of the second P-type transistor, the leakage current of the first P-type transistor and the leakage current of the third P-type transistor; when the level signals input by the decoder to the first control end B1 to the sixth control end B6 are 110000 in sequence, the third P-type transistor is turned on, and the measuring device can measure a current value, which is the sum of the source-drain current of the third P-type transistor, the leakage current of the second P-type transistor and the leakage current of the first P-type transistor.

[0053] It should be noted that the application does not specifically limit the execution sequence of the step 402 and the step 403, and the step 403 can be executed first, and then the step 402 is executed.

[0054] It should be further noted that after the test is completed, the output signal quality of each data IO end of the memory can be judged according to the measured current value, so as to determine whether local correction is needed.

[0055] The specific implementation process can include: for each output driver, judging the output signal quality of the data IO end of the memory electrically connected to the output driver according to the current value obtained by measuring the IO node end of the output driver, and determining whether the data IO end of the memory needs to be corrected according to the output signal quality judgment result.

[0056] In an example, IBIS (Input / Output Buffer Information Specification) can be used to simulate the test of the design circuit of the memory, so as to estimate the appropriate current range of the data IO end of the memory, and then compare the measured current value with the estimated appropriate current range to obtain the output signal quality judgment result.

[0057] For the specific implementation details of the above steps 401 to 403, please refer to the related description of the above Figures 1 to 3 The application will not be described in detail here.

[0058] At this point, the above steps 401 to 403 are completed. Figure 4The test flow shown, in the TEG stage, by designing a plurality of output drivers are respectively electrically connected with the DQ end of the memory chip, the high level signal and low level signal are inputted from the DQ end of the memory chip respectively, and the different transistors in the output driver are selectively turned on, so that a plurality of current values can be measured, since these current values can reflect the output signal quality of the single DQ end of the memory chip, so that the signal quality output by the single DQ end can be accurately judged, and the local problem of the chip can be accurately positioned, and compared with the existing production after testing the overall performance of the memory chip, the chip problem can be detected in the TEG stage, so that the chip end face correction can be carried out, the test cost and time can be saved, and the product yield can be improved.

[0059] In the above description, the patterning, etching and other technical details of each layer are not described in detail. However, those skilled in the art should understand that the layers, regions and the like with the required shape can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0060] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A test element assembly, characterized in that, The data input / output (I / O) terminals used for testing the memory include: At least one output driver, each output driver having an I / O node terminal for electrically connecting to a data I / O terminal of the memory, and each output driver including a pull-up driver and a pull-down driver; the pull-up driver including a plurality of P-type transistors, and the pull-down driver including a plurality of N-type transistors; A controller and a decoder, wherein the controller is electrically connected to the decoder, and the decoder is electrically connected to the control terminal of each output driver; The controller is used to send a selection signal for the output driver to the decoder; The decoder is used to decode the selection signal to determine the selected output driver, and to send different control signals to the control terminal of the selected output driver, so that the multiple N-type transistors included in the pull-down driver and the multiple P-type transistors included in the pull-up driver are turned on in turn, thereby measuring the current value at the I / O node terminal; wherein, when the data I / O terminal of the memory inputs a high level to the selected output driver, the different control signals are used to control the multiple N-type transistors included in the pull-down driver of the output driver to be turned on in turn; when the data I / O terminal of the memory inputs a low level to the selected output driver, the different control signals are used to control the multiple P-type transistors included in the pull-up driver of the output driver to be turned on in turn.

2. The test element assembly according to claim 1, characterized in that, The pull-up driver includes a first P-type transistor, a second P-type transistor, and a third P-type transistor; the control terminal includes a first control terminal to a third control terminal; The first electrode of the first P-type transistor, the first electrode of the second P-type transistor, and the first electrode of the third P-type transistor are all electrically connected to the power supply voltage terminal. The second electrode of the first P-type transistor, the second electrode of the second P-type transistor, and the second electrode of the third P-type transistor are all electrically connected to the I / O node terminal; The third electrode of the first P-type transistor is electrically connected to the first control terminal, the third electrode of the second P-type transistor is electrically connected to the second control terminal, and the third electrode of the third P-type transistor is electrically connected to the third control terminal.

3. The test element assembly according to claim 1, characterized in that, The pull-down driver includes a first N-type transistor, a second N-type transistor, and a third N-type transistor; the control terminal includes a fourth control terminal to a sixth control terminal. The first electrode of the first N-type transistor, the first electrode of the second N-type transistor, and the first electrode of the third N-type transistor are all electrically connected to the I / O node terminal; The second electrode of the first N-type transistor, the second electrode of the second N-type transistor, and the second electrode of the third N-type transistor are all electrically connected to ground. The third electrode of the first N-type transistor is electrically connected to the fourth control terminal, the third electrode of the second N-type transistor is electrically connected to the fifth control terminal, and the third electrode of the third N-type transistor is electrically connected to the sixth control terminal.

4. The test element assembly according to claim 1, characterized in that, Also includes: A measuring device, electrically connected to the I / O node of each output driver, is used to measure the current value at the I / O node.

5. A test method for the test element group as described in any one of claims 1 to 4, characterized in that, The method includes: Electrically connect the I / O node of each output driver to a data I / O terminal of the memory; After determining the currently selected output driver and controlling the data I / O terminal of the memory to input a high level to the output driver, the multiple N-type transistors included in the pull-down driver of the output driver are controlled to turn on in turn, and the current value at the I / O node is measured to obtain multiple current values. After the data I / O terminal of the memory inputs a low level to the output driver, the multiple P-type transistors in the pull-up driver of the output driver are turned on in turn, and the current value at the I / O node is measured to obtain multiple current values.

6. The method according to claim 5, characterized in that, The process of determining the currently selected output driver includes: The controller sends the output driver selection signal to the decoder; The decoder decodes the selection signal to determine the selected output driver.

7. The method according to claim 5, characterized in that, When the data I / O terminal of the control memory inputs a high level to the output driver, the measured current value is the sum of the source-drain current of the conducting N-type transistor and the leakage current of the non-conducting N-type transistor.

8. The method according to claim 5, characterized in that, When the data I / O terminal of the control memory inputs a low level to the output driver, the measured current value is the sum of the source-drain current of the conducting P-type transistor and the leakage current of the non-conducting P-type transistor.

9. The method according to claim 5, characterized in that, The method further includes: For each output driver, the quality of the data I / O output signal of the memory electrically connected to the output driver is determined based on the current value obtained by measuring the I / O node terminal of the output driver. The decision on whether to modify the data I / O terminals of the memory is based on the output signal quality assessment results.

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