Semiconductor structure and method of manufacturing the same

Abstract

The embodiment of the present disclosure provides a semiconductor structure and a preparation method thereof. The semiconductor structure comprises: a substrate, a plurality of semiconductor pillars arranged at intervals on the substrate, the semiconductor pillars comprising, in sequence along a direction away from a surface of the substrate, a first source-drain region, a first channel region, a second channel region, and a second source-drain region; a gate dielectric layer, the gate dielectric layer surrounding a side surface of the semiconductor pillar of the first channel region; a plurality of word lines extending along a first direction, each word line surrounding a plurality of semiconductor pillars arranged along the first direction, the word line surrounding the first channel region and the second channel region in the semiconductor pillar, the word line and the semiconductor pillar of the first channel region having the gate dielectric layer therebetween, and the word line and the semiconductor pillar of the second channel region having an air gap therebetween. The embodiment of the present disclosure is at least beneficial to reduce the gate-induced drain leakage current of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] As the integration density of dynamic memory (DRAM) continues to increase, higher demands are being placed on the arrangement and size of transistors in DRAM array structures. When used as transistors in DRAM, all-around gate transistors (AGBs) can achieve smaller pattern sizes under given process conditions, which is beneficial for increasing the integration density of DRAM.

[0003] While researching the arrangement of dynamic memory structures and how to reduce their size, it is also necessary to improve the electrical performance of small-sized dynamic memory. Specifically, as the size of dynamic memory structures shrinks, the impact of gate-induced drain leakage (GIDL) on the electrical performance of the semiconductor structure increases due to the reduced spacing between the gate electrode layer and the semiconductor channel. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and its fabrication method, which at least helps to reduce the gate-induced drain leakage current of the semiconductor structure.

[0005] This disclosure provides a semiconductor structure, comprising: a substrate having a plurality of spaced semiconductor pillars on the substrate, each semiconductor pillar including a first source / drain region, a first channel region, a second channel region, and a second source / drain region sequentially distributed along a direction away from the substrate surface; a gate dielectric layer surrounding the side of the semiconductor pillars in the first channel region; a plurality of word lines extending along a first direction, each word line surrounding the plurality of semiconductor pillars arranged along the first direction, the word lines surrounding the first channel region and the second channel region in the semiconductor pillars, a gate dielectric layer being provided between the word lines and the semiconductor pillars in the first channel region, and an air gap being provided between the word lines and the semiconductor pillars in the second channel region.

[0006] In some embodiments, the ratio of the length of the gate dielectric layer to the length of the air gap is greater than 1:3 in the direction away from the substrate surface.

[0007] In some embodiments, the thickness of the gate dielectric layer along the first direction is greater than or equal to the width of the air gap.

[0008] In some embodiments, the width of the air gap along the first direction is in the range of 1 to 5 nm.

[0009] In some embodiments, the word line includes: a first conductive layer surrounding a semiconductor pillar of a first channel region; and a second conductive layer located on the surface of the first conductive layer and surrounding a semiconductor pillar of a second channel region, wherein the material of the second conductive layer is different from that of the first conductive layer.

[0010] In some embodiments, the work function value of the material of the first conductive layer is different from the work function value of the material of the second conductive layer.

[0011] In some embodiments, the bottom surface of the first conductive layer is flush with the bottom surface of the gate dielectric layer, and the first conductive layer is exposed at a certain height of the side surface of the gate dielectric layer; the second conductive layer is also located at a certain height of the side surface of the gate dielectric layer exposed by the first conductive layer.

[0012] In some embodiments, it further includes: a word line overlay layer that covers the top surface of the word line and the top opening that covers the air gap.

[0013] In some embodiments, the system further includes: a plurality of bit lines extending along a second direction, each bit line being located between a plurality of semiconductor pillars arranged along the second direction and a substrate, and the bit lines being electrically connected to a first source / drain region; and an isolation layer being located between the bit lines and word lines, and also between adjacent word lines and adjacent bit lines.

[0014] In some embodiments, the isolation layer includes: a first isolation layer located between adjacent semiconductor pillars and between adjacent bit lines, wherein the top surface of the first isolation layer is in contact with the bottom surface of the word line and the bottom surface of the gate dielectric layer; and a second isolation layer extending along a first direction and penetrating the first isolation layer between adjacent semiconductor pillars arranged along a second direction, wherein the second isolation layer is located between adjacent word lines, and the top surface of the second isolation layer is higher than the top surface of the word line.

[0015] Another aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate having a plurality of spaced semiconductor pillars on the substrate, each semiconductor pillar including a first source / drain region, a first channel region, a second channel region, and a second source / drain region sequentially distributed along a direction away from the substrate surface; forming a gate dielectric layer surrounding the side of the semiconductor pillars in the first channel region; forming a plurality of word lines extending along a first direction, each word line surrounding a plurality of semiconductor pillars arranged along the first direction, the word lines surrounding the first channel region and the second channel region in the semiconductor pillars, a gate dielectric layer being provided between the word lines and the semiconductor pillars in the first channel region, and an air gap being provided between the word lines and the semiconductor pillars in the second channel region.

[0016] In some embodiments, the process steps for forming the gate dielectric layer include: forming a sacrificial layer on the sidewall of the semiconductor pillar in the second channel region; oxidizing the sidewall of the semiconductor pillar in the first channel region to form the gate dielectric layer; and removing the sacrificial layer.

[0017] In some embodiments, before forming the gate dielectric layer, the method further includes: forming a first isolation layer and a second isolation layer on the substrate, wherein the first isolation layer is located between adjacent semiconductor pillars, the top surface of the first isolation layer is lower than the top surface of the semiconductor pillars, and the second isolation layer penetrates the first isolation layer between adjacent semiconductor pillars along a first direction, and the top surface of the second isolation layer is higher than the top surface of the semiconductor pillars in the second channel region; in the step of forming the sacrificial layer, a sacrificial layer is also formed on the side of the second isolation layer, and the etching rate of the sacrificial layer and the etching rate of the second isolation layer are different in the same etching process.

[0018] In some embodiments, the process step of forming the sacrificial layer includes: forming a protective layer, the protective layer being located on the top surface of the first isolation layer and covering the semiconductor pillar side surface of the first channel region; forming a sacrificial film, the sacrificial film being located on the top surface of the protective layer, the semiconductor pillar side surface of the second channel region, and the side surface of the second isolation layer; removing the sacrificial film located on the top surface of the protective layer, the remaining sacrificial film serving as the sacrificial layer.

[0019] In some embodiments, the sacrificial film is made of silicon nitride, and the second isolation layer is made of silicon nitride; after removing the sacrificial film located on the top surface of the protective layer, the method further includes: subjecting the remaining sacrificial film to plasma treatment so that the etching rate of the sacrificial layer and the etching rate of the second isolation layer are different by the same etching process.

[0020] In some embodiments, before forming word lines, the process further includes: forming an epitaxial layer on the side of a semiconductor pillar in the second channel region using an epitaxial process; in the word line forming process step, the word line covers the side of the epitaxial layer; and after forming word lines, removing the epitaxial layer to form an air gap.

[0021] In some embodiments, the process steps for forming word lines include: forming a first conductive layer that covers the side surface of the gate dielectric layer and surrounds the semiconductor pillars of the first channel region; and forming a second conductive layer on the top surface of the first conductive layer that covers the side surface of the epitaxial layer and surrounds the semiconductor pillars of the second channel region.

[0022] In some embodiments, the process steps for forming the first conductive layer include: forming a first conductive film, the first conductive film surrounding the semiconductor pillars of the first channel region and the second channel region; etching back to remove a portion of the thickness of the first conductive film until the top surface of the remaining first conductive film is lower than the top surface of the gate dielectric layer, the remaining first conductive film serving as the first conductive layer.

[0023] The technical solutions provided in this disclosure have at least the following advantages:

[0024] In the above technical solution, semiconductor pillars are used to form the semiconductor channel of a transistor. The semiconductor pillars include a first source / drain region, a first channel region, a second channel region, and a second source / drain region distributed sequentially along the direction away from the substrate surface. The semiconductor pillars of the first source / drain region are used to form the source of the transistor, the semiconductor pillars of the second source / drain region are used to form the drain of the transistor, and the semiconductor pillars of the first channel region and the second channel region are used to form the semiconductor pillars of the channel region in the transistor semiconductor channel. Word lines surround the semiconductor pillars of the channel region. A gate dielectric layer is provided in the gap region between the word lines and the semiconductor pillars. The gate dielectric layer only covers the surface of the first channel region semiconductor pillar adjacent to the first source / drain region, making the gap region between the second channel region semiconductor pillar and the word lines an air gap. Since there are hot electrons that absorb energy and undergo transitions in the word lines and semiconductor pillars, the air gap allows the hot electrons in the word lines adjacent to the second source / drain region semiconductor pillars to be captured by the word lines, thereby preventing the hot electrons from being captured by the gate dielectric layer. This helps to reduce the leakage current generated between the word lines and the second source / drain region semiconductor pillars, which helps to reduce the GIDL of the transistor, and thus helps to improve the electrical performance of the semiconductor structure. Attached Figure Description

[0025] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of this disclosure;

[0027] Figures 2 to 19 This is a schematic diagram of the steps in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure. Detailed Implementation

[0028] As the background technology shows, as the spacing between the word line and the semiconductor channel decreases, the impact of GIDL (gate-induced drain leakage) on the electrical performance of the semiconductor structure increases. Specifically, taking a gate-all-around transistor as an example, to improve the conductivity of the source, drain, and channel regions of the transistor, the semiconductor pillars containing the source, drain, and channel regions are doped. The concentration of doped ions in the source, drain, and channel regions is relatively high, which increases the lateral electric field corresponding to the word line and the semiconductor pillar, generating GIDL. GIDL reduces the proportion of carriers turning on or off in the channel region, making it difficult for the word line to control the channel's shutdown, thus reducing the electrical performance of the semiconductor structure. Analysis shows that increasing the drain length helps reduce GIDL, but a longer drain is not only detrimental to small-volume integration but also increases the resistance of the transistor's semiconductor channel, affecting the electrical performance of the semiconductor structure.

[0029] This disclosure provides a semiconductor structure and its fabrication method. The semiconductor pillars in the semiconductor structure include a first source / drain region, a first channel region, a second channel region, and a second source / drain region sequentially distributed along a direction away from the substrate surface. The semiconductor pillars are used to form the semiconductor channel of a transistor. The semiconductor pillars of the first source / drain region are used to form the source of the transistor, and the semiconductor pillars of the second source / drain region are used to form the drain of the transistor. The semiconductor pillars of the first channel region and the semiconductor pillars of the second channel region are channel region semiconductor pillars used to form the transistor channel region. Word lines surround the semiconductor pillars of the channel regions. The gate dielectric layer is located only in the region between the semiconductor pillars of the first channel region and the word lines. The region between the semiconductor pillars of the second channel region and the word lines is an air gap. Without increasing the drain length, the air gap allows hot electrons in the word lines adjacent to the semiconductor pillars of the second source / drain region to be captured by the word lines, thereby preventing hot electrons from being captured by the gate dielectric layer. This helps to reduce GIDL, thereby improving the electrical performance of the semiconductor structure and reducing the size of the semiconductor structure.

[0030] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0031] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure.

[0032] refer to Figure 1This disclosure provides a semiconductor structure, comprising: a substrate 100 having a plurality of spaced semiconductor pillars 104 thereon, each semiconductor pillar 104 including a first source / drain region I, a first channel region II, a second channel region III, and a second source / drain region IV sequentially distributed along a direction away from the surface of the substrate 100; a gate dielectric layer 120 surrounding the side of the semiconductor pillars 104 of the first channel region II; a plurality of word lines 130 extending along a first direction X, each word line 130 surrounding the plurality of semiconductor pillars 104 arranged along the first direction X, the word lines 130 surrounding the first channel region II and the second channel region III in the semiconductor pillars 104, a gate dielectric layer 120 being provided between the word lines 130 and the semiconductor pillars 104 of the first channel region II, and an air gap 121 being provided between the word lines 130 and the semiconductor pillars 104 of the second channel region III.

[0033] The substrate 100 is made of a semiconductor material; in some embodiments, the substrate 100 is made of silicon. In other embodiments, the substrate 100 may be a germanium substrate, a germanium-silicon substrate, a silicon carbide substrate, or a silicon-on-insulator substrate.

[0034] Semiconductor pillar 104 serves as the semiconductor channel for a transistor. In some embodiments, the transistor can be a full-around-gate transistor (FOG), which allows for minimal pattern size under given process conditions, thus improving the integration density of the semiconductor structure. Furthermore, the material of semiconductor pillar 104 can be the same as that of the substrate 100. In some embodiments, the material of semiconductor pillar 104 can be silicon.

[0035] The direction away from the surface of the substrate 100 is the extension direction of the semiconductor pillar 104, i.e., the third direction Z. The semiconductor pillar 104 contains a first source / drain region I, a first channel region II, a second channel region III, and a second source / drain region IV sequentially distributed along the third direction Z. The first source / drain region I and the second source / drain region IV serve as the source and drain of subsequent transistors, respectively. The first channel region II and the second channel region III are the channel regions of the semiconductor pillar 104 used to form transistors. The first source / drain region I and the second source / drain region IV are doped regions. In some embodiments, the type of dopant ions in the doped regions may be different from the type of dopant ions in the channel regions. Specifically, in one example, the dopant ions in the doped regions may be N-type ions, and the dopant ions in the channel regions may be P-type ions. The P-type ions may be at least one of boron ions, indium ions, or gallium ions, and the N-type ions may be at least one of arsenic ions, phosphorus ions, or antimony ions. In another example, the dopant ions in the doped regions may be P-type ions, and the dopant ions in the channel regions may be N-type ions. In other embodiments, the type of dopant ions in the doped region may also be the same as the type of dopant ions in the channel region, i.e., the semiconductor pillar 104 may be used to form a junctionless field-effect transistor.

[0036] Furthermore, the semiconductor pillars 104 can be arranged in an array, with the rows arranged in a first direction X and the columns arranged in a second direction Y. The first direction X and the second direction Y are different. It should be noted that the definitions of "row" and "column" are relative; that is, the arrangement direction of the columns can also be defined as the first direction X, and the arrangement direction of the rows can be defined as the second direction Y.

[0037] Word lines 130 extend along a first direction X and surround the semiconductor pillars 104 of the channel region. Specifically, each word line 130 may surround a row of semiconductor pillars 104 arranged along the first direction X. The word lines 130 serve as the gate of a transistor, conducting the channel region based on a control signal to realize the transport of charge carriers between the source and drain. The material of the word lines 130 is a conductive material; in some examples, the material of the word lines 130 includes at least one of polysilicon, tungsten, molybdenum, titanium, cobalt, or ruthenium.

[0038] A gate dielectric layer 120 is located between the word line 130 and the semiconductor pillar 104 of the first channel region II, surrounding the semiconductor pillar 104 of the first channel region II. The gate dielectric layer 120 is used to enable the word line 130 to drive the source and drain of the transistor to conduct. An air gap 121 is formed between the word line 130 and the semiconductor pillar 104 of the second channel region III. The semiconductor pillar 104 of the second channel region III is adjacent to the semiconductor pillar 104 of the second source-drain region IV, which is the drain of the transistor. That is, the part of the word line 130 adjacent to the drain and the opposite semiconductor pillar 104 are separated by an air gap 121. The air gap 121 is beneficial to the capture of hot electrons in the word line 130 adjacent to the drain by the word line 130, and to the prevention of hot electrons from being captured by the gate dielectric layer 120. This is beneficial to reduce GIDL and improve the electrical performance of the semiconductor structure.

[0039] In some embodiments, the gate dielectric layer 120 may be made of silicon oxide. The process of forming silicon oxide on a silicon semiconductor pillar 104 using a thermal oxidation process is mature and helps reduce the fabrication difficulty of the gate dielectric layer 120. In other embodiments, the gate dielectric layer 120 may also be made of silicon nitride or silicon oxynitride.

[0040] In some embodiments, the ratio of the length of the gate dielectric layer 120 to the length of the air gap 121 in the direction away from the surface of the substrate 100 is greater than 1:3. The gate dielectric layer 120 is used to enable the word line 130 to drive the source and drain of the transistor to conduct. If the length of the gate dielectric layer 120 in the third direction Z is too small, it may reduce the ability of the word line 130 to drive the current, affect the electrical performance of the semiconductor structure, and even prevent the source and drain of the transistor from conducting, thus reducing the yield of the semiconductor structure. Setting the ratio of the length of the gate dielectric layer 120 to the length of the air gap 121 to be greater than 1:3 ensures, on the one hand, that there is an air gap 121 between the word line 130 and the semiconductor pillar 104 of the second channel region III, which is beneficial to reduce GIDL; on the other hand, it ensures that the gate dielectric layer 120 has a sufficient length so that the word line 130 has a better ability to drive the source and drain to conduct.

[0041] In some embodiments, the thickness of the gate dielectric layer 120 along the first direction X is greater than or equal to the width of the air gap 121. A wider air gap 121 reduces the ability of the word line 130 to drive the source and drain to conduct. Therefore, setting the thickness of the gate dielectric layer 120 to be greater than the width of the air gap 121 is beneficial to ensuring the ability of the word line 130 to drive the current, thereby improving the electrical performance of the semiconductor structure.

[0042] In some embodiments, the width of the air gap 121 along the first direction X is in the range of 1 to 5 nm. An excessively wide air gap 121 will reduce the ability of the word line 130 to drive the source and drain to conduct, while an excessively narrow air gap 121 will not effectively reduce GIDL. Therefore, setting the width of the air gap 121 to 1 to 5 nm is beneficial in two ways: firstly, it ensures the ability of the word line 130 to drive the source and drain to conduct; secondly, it effectively reduces GIDL and improves the electrical performance of the semiconductor structure.

[0043] In some embodiments, the word line 130 includes: a first conductive layer 131 surrounding the semiconductor pillar 104 of the first channel region II; and a second conductive layer 132 located on the surface of the first conductive layer 131 and surrounding the semiconductor pillar 104 of the second channel region III, wherein the material of the second conductive layer 132 is different from that of the first conductive layer 131. Since there is an air gap 121 between the word line 130 and the semiconductor pillar 104 of the second channel region III, to ensure that the word line 130 has a superior ability to drive the source and drain to conduct, the word line 130 can be configured as a first conductive layer 131 and a second conductive layer 132 stacked along the third direction Z with different materials. The first conductive layer 131 and the second conductive layer 132, with different materials, have different conductivity. The ability of the word line 130 to drive the source and drain to conduct can be adjusted by adjusting the materials of the first conductive layer 131 and the second conductive layer 132. Furthermore, if the first conductive layer 131 is made of a material with superior conductivity but higher manufacturing cost, and the second conductive layer 132 is made of a material with poor conductivity but lower manufacturing cost, then using the first conductive layer 131 and the second conductive layer 132 with different materials for the word line 130 is beneficial for reducing manufacturing costs compared to a word line 130 composed solely of the first conductive layer 131 or a word line 130 composed solely of the second conductive layer 132. Using the first conductive layer 131 and the second conductive layer 132 with different materials for the word line 130 not only helps ensure that the word line 130 has superior ability to drive the source and drain conduction, but also helps reduce the manufacturing cost of the word line 130.

[0044] In some embodiments, the work function value of the material of the first conductive layer 131 is different from that of the material of the second conductive layer 132. The smaller the difference between the work function value of the word line 130 and the work function value of the semiconductor pillar 104, the lower the threshold voltage of the transistor. A lower threshold voltage is beneficial to improving the sensitivity of channel region conduction or turn-off. Since the work function values ​​of the semiconductor pillar 104 are different for different types of transistors (e.g., PMOS or NMOS), it is necessary to configure different materials for the word line 130 for different transistors to adjust the threshold voltage of different types of transistors. Configuring different materials for the word line 130 for different transistors increases the difficulty of semiconductor structure fabrication. By setting the word line 130 as the first conductive layer 131 and the second conductive layer 132 with different work function values, it is beneficial to adjust the work function value of the word line 130 by adjusting the material, thickness, and other related parameters of the first conductive layer 131 and the second conductive layer 132, thereby reducing the difference between the work function value of the word line 130 and the work function value of the semiconductor pillar 104. Furthermore, this configuration of the word line 130 has several advantages. First, it helps to reduce the lateral electric field at the point where the word line 130 corresponds to the semiconductor pillar 104, further reducing GIDL and improving the sensitivity of controlling the channel region to turn on or off. Second, it helps to make the word line 130 suitable for different types of transistors by adjusting the relevant parameters of the first conductive layer 131 and the second conductive layer 132, thereby reducing the difficulty of fabricating the semiconductor structure.

[0045] In some embodiments, the bottom surface of the first conductive layer 131 is flush with the bottom surface of the gate dielectric layer 120, and the first conductive layer 131 exposes a portion of the side surface of the gate dielectric layer 120; the second conductive layer 132 is also located on the side surface of the gate dielectric layer 120 exposed by the first conductive layer 131. Specifically, along the third direction Z, the top surface of the first conductive layer 131 is lower than the top surface of the gate dielectric layer 120, and the lower part of the second conductive layer 132 is attached to the exposed portion of the side surface of the gate dielectric layer 120 of the first conductive layer 131. The second conductive layer 132 is in contact with the gate dielectric layer 120, making the influence of the work function change of the second conductive layer 132 on the transverse electric field corresponding to the word line 130 and the semiconductor pillar 104 more significant, which is beneficial for effectively adjusting the GIDL by adjusting the work function of the second conductive layer 132.

[0046] In some embodiments, the system further includes a word line overlay layer 105, which covers the top surface of the word line 130 and the top opening of the air gap 121. Thus, the bottom surface of the word line overlay layer 105, the side surface of the word line 130 opposite to the second channel region III semiconductor pillar 104, the side surface of the second channel region III semiconductor pillar 104, and the top surface of the gate dielectric layer 120 form the air gap 121. The word line overlay layer 105 helps to prevent subsequent impurities from entering the air gap 121 and affecting the performance of the semiconductor structure. Furthermore, the word line overlay layer 105 helps to provide support for the structure located on top of the air gap 121, improving the structural stability of the air gap 121 in the semiconductor structure.

[0047] In some embodiments, the system further includes: a plurality of bit lines 102 extending along a second direction Y, each bit line 102 being located between a plurality of semiconductor pillars 104 arranged along the second direction Y and the substrate 100, and the bit line 102 being electrically connected to a first source / drain region I; and an isolation layer located between the bit lines 102 and word lines 130, and also between adjacent word lines 130 and adjacent bit lines 102. The bit lines 102 facilitate the extraction of the transistor source, thereby facilitating the provision of electrical signals to the transistor source. The isolation layer not only facilitates isolation between adjacent word lines 130, between adjacent bit lines 102, and between bit lines 102 and word lines 130, but also provides support for subsequent structures and internal support for the semiconductor structure, thereby improving the stability of the semiconductor structure.

[0048] Specifically, bit line 102 may contact the bottom of a row of semiconductor pillars 104 arranged along the second direction Y. The material of bit line 102 may be a conductive material. In some embodiments, the material of bit line 102 includes metal silicide, which is a buried bit line 102 formed using a silicon metallization process. In other embodiments, the material of bit line 102 may also include metal silicide and metal. The isolation layer is an insulating material. In some examples, the material of the isolation layer may be at least one of silicon oxide or silicon nitride.

[0049] In some embodiments, the isolation layer includes: a first isolation layer 101, located between adjacent semiconductor pillars 104 and adjacent bit lines 102, with the top surface of the first isolation layer 101 contacting the bottom surface of the word line 130 and the bottom surface of the gate dielectric layer 120; and a second isolation layer 103, extending along a first direction X and penetrating through the first isolation layer 101 between adjacent semiconductor pillars 104 arranged along a second direction Y, located between adjacent word lines 130, with the top surface of the second isolation layer 103 higher than the top surface of the word lines 130. The first isolation layer 101 facilitates isolation of adjacent bit lines 102 and provides support for the gate dielectric layer 120 and word lines 130, while the second isolation layer 103 facilitates isolation of adjacent word lines 130.

[0050] In some embodiments, the material of the first isolation layer 101 is different from that of the second isolation layer 103. The different materials of the first isolation layer 101 and the second isolation layer 103 make it easier to selectively remove part of the material of the first isolation layer 101 or the second isolation layer 103 through different etching processes, so as to form the first isolation layer 101 and the second isolation layer 103 with different shapes, which helps to reduce the difficulty of preparing the first isolation layer 101 and the second isolation layer 103.

[0051] In the semiconductor structure provided in the above embodiments, semiconductor pillars 104 are used to form semiconductor channels of transistors, semiconductor pillars 104 of the first source-drain region I are used to form the source of transistors, semiconductor pillars 104 of the second source-drain region IV are used to form the drain of transistors, semiconductor pillars 104 of the first channel region II and the second channel region III are used to form channel region semiconductor pillars 104 of transistor channels, word lines 130 surround the semiconductor pillars 104 of the channel regions, gate dielectric layer 120 is located only in the region between semiconductor pillars 104 of the first channel region II and word lines 130, and the region between semiconductor pillars 104 of the second channel region III and word lines 130 is an air gap 121. The air gap 121 is advantageous for capturing hot electrons in word lines 130 adjacent to semiconductor pillars 104 of the second source-drain region IV without increasing the drain length, which is beneficial for reducing GIDL and reducing the size of the semiconductor structure. In addition, word line 130 can be configured to include a first conductive layer 131 and a second conductive layer 132 with different work function values. This is beneficial to reduce the difference between the work function value of word line 130 and the work function value of semiconductor pillar 104 by adjusting the relevant parameters of the first conductive layer 131 and the second conductive layer 132. This is beneficial to reduce the transverse electric field at the corresponding points of word line 130 and semiconductor pillar 104, further reduce GIDL, and improve the electrical performance of semiconductor structure.

[0052] This disclosure also provides a method for fabricating a semiconductor structure for the semiconductor structure described in the above embodiments. The method for fabricating the semiconductor structure provided in this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the parts that are the same as or corresponding to those in the foregoing embodiments can be referred to in the detailed description of the foregoing embodiments, and will not be repeated hereafter.

[0053] Figures 2 to 19 This diagram illustrates the steps of a method for fabricating a semiconductor structure according to an embodiment of this disclosure. It should be noted that... Figures 2 to 19 middle, Figure 6 for Figure 5 The diagram shows a cross-sectional view of the semiconductor structure along a direction perpendicular to the third direction Z, including the semiconductor pillars. Figure 7 , Figures 9 to 19 for Figure 6 The cross-sectional view at point A-A1 is shown. Figure 8 for Figure 6 The cross-sectional view at point C-C1 is shown.

[0054] refer to Figures 2 to 5 A substrate 100 is provided, on which a plurality of spaced-apart semiconductor pillars 104 are arranged. Each semiconductor pillar 104 includes a first source / drain region I, a first channel region II, a second channel region III, and a second source / drain region IV, sequentially distributed along a direction away from the surface of the substrate 100. Specifically, an initial substrate is provided; the initial substrate is patterned to form a plurality of grooves extending along a first direction X, and an isolation material 106 is filled within the grooves; the initial substrate having the isolation material 106 is patterned to form a plurality of grooves extending along a second direction Y, and a plurality of spaced-apart semiconductor pillars 104 are formed. This method of patterning the initial substrate to form the semiconductor pillars 104 simplifies the process flow and reduces fabrication costs. The isolation material 106 can be the commonly used silicon oxide.

[0055] In some embodiments, the initial substrate can be patterned using SADP (Self-aligned Double Patterning) or SAQP (Self-aligned Quadruple Patterning) processes. SADP or SAQP processes can form smaller patterns, which is beneficial for improving the precision of the initial substrate patterning process and for forming smaller semiconductor pillars 104, thereby helping to reduce the size of the semiconductor structure.

[0056] In some embodiments, after forming the semiconductor pillar 104, a doping process may be performed on the semiconductor pillar 104 to form a channel region and doped regions located on both sides of the channel region, namely, forming a first channel region II, a second channel region III, a first source / drain region I, and a second source / drain region IV. The doped regions located on both sides of the channel region constitute the source and drain of the semiconductor structure. Specifically, in some embodiments, either ion implantation or thermal diffusion may be used to dope the semiconductor pillar 104. In other embodiments, the initial substrate may be doped before forming the semiconductor pillar 104, and after forming the independent semiconductor pillars 104, the semiconductor pillar 104 may have a channel region and doped regions located on both sides of the channel region.

[0057] In some embodiments, the method further includes forming a plurality of bit lines extending along the second direction Y. The formed bit lines are located between a plurality of semiconductor pillars 104 arranged along the second direction Y and the substrate 100, and the bit lines are electrically connected to the first source / drain region I. Specifically, refer to... Figure 4 Metal silicide technology can be used to form embedded bit lines at the bottom of semiconductor pillars 104. Bit lines 102 can be electrically connected to a row of semiconductor pillars 104 arranged along the second direction Y.

[0058] In some embodiments, the semiconductor structure fabrication method further includes, before forming the gate dielectric layer 120, forming a first isolation layer 101 and a second isolation layer 103 on the substrate 100. The first isolation layer 101 is located between adjacent semiconductor pillars 104, with its top surface lower than the top surface of the semiconductor pillars 104. The second isolation layer 103 penetrates the first isolation layer 101 between adjacent semiconductor pillars 104 along a first direction X, and its top surface is higher than the top surface of the semiconductor pillars 104 in the second channel region III. The first isolation layer 101 is used to isolate adjacent bit lines, and the second isolation layer 103 is used to isolate subsequently formed adjacent word lines, preventing electrical interference between adjacent conductive structures. Furthermore, the first isolation layer 101 and the second isolation layer 103 also assist in the formation of the subsequent gate dielectric layer and word lines.

[0059] Specifically, the steps for forming the first isolation layer 101 and the second isolation layer 103 can be as follows: (Refer to...) Figures 4 to 8 ,exist Figure 4 A second insulating layer 103 extending along the first direction X is formed within a portion of the groove shown. The groove outside the second insulating layer 103 is filled with insulating material 106 to form... Figure 5 The structure shown, wherein the isolation material 106 and the second isolation layer 103 are formed by a deposition process. (See reference...) Figure 7 and Figure 8 Remove a portion of the insulation material 106 to form the first insulation layer 101.

[0060] refer to Figures 9 to 14 A gate dielectric layer 120 is formed, which surrounds the side of the semiconductor pillar 104 in the first channel region II, as referenced. Figure 11 In some embodiments, the process steps for forming the gate dielectric layer 120 may include forming a sacrificial layer 112 on the side of the semiconductor pillar 104 in the second channel region III. The sacrificial layer 112 helps to prevent the semiconductor pillar 104 in the second channel region III and the second source / drain region IV from being contaminated during the formation of the gate dielectric layer 120.

[0061] Specifically, in some embodiments, the process steps for forming the sacrificial layer 112 include: referring to Figure 9 A protective layer 110 is formed, located on the top surface of the first isolation layer 101 and covering the side surface of the semiconductor pillar 104 of the first channel region II. This helps prevent contamination of the semiconductor pillar 104 of the first channel region II during the formation of the sacrificial layer 112, and provides support for the subsequently formed sacrificial layer 112, assisting in its formation. The material of the protective layer 110 can be silicon oxide. In other embodiments, when a portion of the isolation material 106 is removed to form the first isolation layer 101, the top surface height of the first isolation layer 101 can be made flush with the top surface height of the semiconductor pillar 104 of the first channel region II. That is, a portion of the first isolation layer 101 is directly used as the protective layer 110, which helps reduce the fabrication difficulty of the protective layer 110.

[0062] refer to Figure 10 A sacrificial film 111 is formed, which is located on the top surface of the protective layer 110, the side surface of the semiconductor pillar 104 of the second channel region III, and the side surface of the second isolation layer 103; Reference Figure 11 The sacrificial film 111 located on the top surface of the protective layer 110 is removed, and the remaining sacrificial film 111 serves as the sacrificial layer 112. Specifically, the sacrificial film 111 can be formed by a deposition process, and a portion of the sacrificial film 111 on the top surface of the protective layer 110 can be removed by a back etching process, while the sacrificial film 111 on the sidewall of the semiconductor pillar 104 is retained to form the sacrificial layer 112.

[0063] Furthermore, in the step of forming the sacrificial layer 112, a sacrificial layer 112 is also formed on the side of the second isolation layer 103, and the etching rate of the sacrificial layer 112 by the same etching process is different from the etching rate of the second isolation layer 103. Since the materials of the sacrificial layer 112 and the second isolation layer 103 are different, an etching process with higher selectivity for the sacrificial layer 112 can be used to selectively remove the sacrificial layer 112, while retaining the second isolation layer 103 to assist in the formation of the word line 130, which helps to reduce the fabrication difficulty of the word line 130.

[0064] In some embodiments, the sacrificial film 111 and the second isolation layer 103 are made of the same material, such as silicon nitride. After removing the sacrificial film 111 located on the top surface of the protective layer 110, the remaining sacrificial film 111 is subjected to plasma treatment so that the etching rate of the sacrificial layer 112 and the etching rate of the second isolation layer 103 by the same etching process are different. The preparation process of silicon nitride is mature, and choosing silicon nitride as the sacrificial layer 112 is beneficial to reducing the preparation difficulty of the sacrificial layer 112. If the material of the second isolation layer 103 is the same as the material of the sacrificial layer 112, the sacrificial layer 112 needs to be subjected to plasma treatment. Specifically, the sacrificial layer 112 can be subjected to a plasma doping process so that the sacrificial layer 112 and the second isolation layer 103 have different etching selectivity ratios. This is beneficial to selectively remove the sacrificial layer 112 by using an etching process with a higher etching selectivity ratio for the sacrificial layer 112, while retaining the second isolation layer 103 used to assist in the formation of the word line 130.

[0065] refer to Figure 12 After the sacrificial layer 112 is formed, a wet etching process with higher etching selectivity for the protective layer 110 can be used compared to the sacrificial layer 112, the second isolation layer 103, the first isolation layer 101, and the semiconductor silicon pillar 104 to remove the protective layer 110, exposing the side of the semiconductor pillar 104 in the first channel region II. The semiconductor pillar 104 in the second channel region III and the semiconductor pillar 104 in the second source / drain region IV are covered by the sacrificial layer 112. Therefore, referring to... Figure 13 By oxidizing the semiconductor pillar 104 using a thermal oxidation process, a gate dielectric layer 120 can be formed on the side of the semiconductor pillar 104 in the first channel region II, which helps to reduce the fabrication difficulty of the gate dielectric layer 120. (Reference) Figure 14 After the gate dielectric layer 120 is formed, the sacrificial layer 112 is removed by an etching process that has a higher selectivity for etching the sacrificial layer 112 compared to other materials.

[0066] refer to Figures 15 to 18 After removing the sacrificial layer 112, multiple word lines 130 extending along the first direction X are formed. Each word line 130 surrounds multiple semiconductor pillars 104 arranged along the first direction X. The word lines 130 surround the first channel region II and the second channel region III in the semiconductor pillars 104. A gate dielectric layer 120 is provided between the word lines 130 and the semiconductor pillars 104 of the first channel region II, and an air gap 121 is provided between the word lines 130 and the semiconductor pillars 104 of the second channel region III. The air gap is beneficial for capturing hot electrons in the word lines 130 adjacent to the second source / drain region IV semiconductor pillars 104 without increasing the drain length, which helps to reduce GIDL and improve the electrical performance of the semiconductor structure.

[0067] For details, please refer to Figure 15In some embodiments, the process steps for forming the word line 130 include: before forming the word line 130, using an epitaxial process, forming an epitaxial layer 113 on the side of the semiconductor pillar 104 in the second channel region III. The epitaxial layer 113 helps to prevent the subsequently formed word line 130 from contacting the semiconductor pillar 104 in the second channel region III, and is used to assist in forming an air gap, which helps to reduce the difficulty of fabricating the air gap. Furthermore, the epitaxial layer 113 formed using a selective epitaxial process has a different etching selectivity ratio than the gate dielectric layer 120, which not only helps to reduce the difficulty of fabricating the epitaxial layer 113, but also helps to avoid damage to the gate dielectric layer 120 during the subsequent removal of the epitaxial layer 113. It should be noted that an epitaxial layer 113 is also formed on the side of the semiconductor pillar 104 in the second source / drain region IV, and the material of the epitaxial layer 113 can be silicon germanide.

[0068] In some embodiments, reference Figure 16 and Figure 17 The process steps for forming word line 130 include: forming a conductive material on the top surface of the first isolation layer 101 and removing a portion of the conductive material to form word line 130 surrounding the semiconductor pillar 104 of the channel region.

[0069] refer to Figure 17 Word line 130 covers the side of epitaxial layer 113 that is in contact with semiconductor pillar 104 of second channel region III. After forming word line 130, refer to Figure 18 The epitaxial layer 113 is removed using an etching process with high selectivity to form an air gap 121. It should be noted that the method for forming the air gap 121 in this embodiment, compared to removing a portion of the gate dielectric layer material to form the air gap 121, allows for controllable morphology of the air gap 121 and avoids damage to the gate dielectric layer 120. This facilitates precise control of the morphology of the gate dielectric layer 120 and improves the electrical performance of the semiconductor structure.

[0070] refer to Figures 16 to 17 In some embodiments, the process steps for forming the word line 130 further include: forming a first conductive layer 131, which covers the side of the gate dielectric layer 120 and surrounds the semiconductor pillar 104 of the first channel region II; and forming a second conductive layer 132 on the top surface of the first conductive layer 131, which covers the side of the epitaxial layer 113 and surrounds the semiconductor pillar 104 of the second channel region III. That is, first conductive layers 131 and second conductive layers 132 with different work function values ​​are formed. This allows for adjustment of the lateral electric field at the corresponding location of the word line 130 and the semiconductor pillar 104 by adjusting the relevant parameters of the first conductive layer 131 and the second conductive layer 132, which helps to reduce the GIDL and thus improve the electrical performance of the semiconductor structure.

[0071] Specifically, in some embodiments, the process steps for forming the first conductive layer 131 may include: forming a first conductive film surrounding the semiconductor pillars 104 of the first channel region II and the second channel region III; etching back to remove a portion of the thickness of the first conductive film until the top surface of the remaining first conductive film is lower than the top surface of the gate dielectric layer 120, with the remaining first conductive film serving as the first conductive layer 131. The top surface of the first conductive layer 131 being lower than the top surface of the gate dielectric layer 120 allows the second conductive layer 132 to contact the gate dielectric layer 120. This facilitates a more significant impact of the work function change of the second conductive layer 132 on the lateral electric field corresponding to the word line 130 and the semiconductor pillar 104, and allows for effective adjustment of the GIDL by adjusting the work function of the second conductive layer 132.

[0072] refer to Figure 19 In some embodiments, after forming the word line 130, a word line capping layer 105 is formed on the top surface of the word line 130 and at the top opening of the air gap 121 using a chemical vapor deposition process with weaker hole-filling capability. This helps to prevent impurities from entering the air gap 121 and affecting the performance of the semiconductor structure.

[0073] The semiconductor structure formation method provided in the above embodiments is advantageous in forming an air gap 121 between the word line 130 and the semiconductor pillar 104 of the second channel region III without increasing the drain length. This allows hot electrons in the word line 130 adjacent to the semiconductor pillar 104 of the second source / drain region IV to be captured by the word line 130, which is beneficial for reducing GIDL and minimizing the size of the semiconductor structure. Furthermore, compared to the method of forming an air gap 121 and the gate dielectric layer by removing a portion of the gate dielectric layer material after forming the gate dielectric layer material on the semiconductor pillar 104 of the channel region, the method of forming the air gap 121 by removing the epitaxial layer 113 in this embodiment avoids damage to the gate dielectric layer 120, facilitates precise control of the morphology of the gate dielectric layer 120, and improves the electrical performance of the semiconductor structure.

[0074] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own variations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate having a plurality of spaced semiconductor pillars, each semiconductor pillar including a first source / drain region, a first channel region, a second channel region, and a second source / drain region sequentially distributed along a direction away from the surface of the substrate; A gate dielectric layer that surrounds the semiconductor pillar sidewall of the first channel region; Multiple word lines extending along a first direction, each word line surrounding multiple semiconductor pillars arranged along the first direction, the word lines surrounding a first channel region and a second channel region in the semiconductor pillars, a gate dielectric layer being provided between the word lines and the semiconductor pillars in the first channel region, and an air gap being provided between the word lines and the semiconductor pillars in the second channel region; The word line includes: a first conductive layer surrounding the semiconductor pillar of the first channel region; and a second conductive layer located on the surface of the first conductive layer and surrounding the semiconductor pillar of the second channel region, wherein the material of the second conductive layer is different from the material of the first conductive layer. The bottom surface of the first conductive layer is flush with the bottom surface of the gate dielectric layer, and the first conductive layer is exposed at a certain height on the side surface of the gate dielectric layer; the second conductive layer is also located at a certain height on the side surface of the gate dielectric layer.

2. The semiconductor structure as described in claim 1, characterized in that, Along the direction away from the substrate surface, the ratio of the length of the gate dielectric layer to the length of the air gap is greater than 1:

3.

3. The semiconductor structure as described in claim 1, characterized in that, Along the first direction, the thickness of the gate dielectric layer is greater than or equal to the width of the air gap.

4. The semiconductor structure as described in claim 3, characterized in that, Along the first direction, the width of the air gap is in the range of 1~5nm.

5. The semiconductor structure as described in claim 1, characterized in that, The work function value of the material of the first conductive layer is different from that of the material of the second conductive layer.

6. The semiconductor structure as described in claim 1, characterized in that, Also includes: A letter overlay that covers the top surface of the letter and the top opening of the air gap.

7. The semiconductor structure as described in claim 1, characterized in that, Also includes: Multiple bit lines extending along a second direction, each bit line being located between multiple semiconductor pillars arranged along the second direction and the substrate, and the bit line being electrically connected to the first source / drain region; An isolation layer is located between the bit line and the word line, and also between adjacent word lines and adjacent bit lines.

8. The semiconductor structure as described in claim 7, characterized in that, The isolation layer includes: A first isolation layer is located between adjacent semiconductor pillars and between adjacent bit lines, and the top surface of the first isolation layer is in contact with the bottom surface of the word line and the bottom surface of the gate dielectric layer. A second isolation layer extends along the first direction and penetrates the first isolation layer between adjacent semiconductor pillars arranged along the second direction, and the second isolation layer is located between adjacent word lines, with the top surface of the second isolation layer higher than the top surface of the word lines.

9. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, wherein a plurality of semiconductor pillars are spaced apart, the semiconductor pillars including a first source / drain region, a first channel region, a second channel region and a second source / drain region sequentially distributed along a direction away from the surface of the substrate; A gate dielectric layer is formed, the gate dielectric layer surrounding the sidewall of the semiconductor pillar in the first channel region; Multiple word lines are formed extending along a first direction, each word line surrounds multiple semiconductor pillars arranged along the first direction, the word line surrounds a first channel region and a second channel region in the semiconductor pillars, a gate dielectric layer is provided between the word line and the semiconductor pillar in the first channel region, and an air gap is provided between the word line and the semiconductor pillar in the second channel region. The process steps for forming the gate dielectric layer include: A sacrificial layer is formed on the sidewall of the semiconductor pillar in the second channel region; The sidewalls of the semiconductor pillars in the first channel region are oxidized to form the gate dielectric layer; Remove the sacrificial layer.

10. The method for preparing the semiconductor structure as described in claim 9, characterized in that, Before forming the gate dielectric layer, the method further includes: forming a first isolation layer and a second isolation layer on the substrate, wherein the first isolation layer is located between adjacent semiconductor pillars, the top surface of the first isolation layer is lower than the top surface of the semiconductor pillars, and the second isolation layer penetrates the first isolation layer between adjacent semiconductor pillars along the first direction, and the top surface of the second isolation layer is higher than the top surface of the semiconductor pillars in the second channel region. In the step of forming the sacrificial layer, the sacrificial layer is also formed on the side of the second isolation layer, and the etching rate of the sacrificial layer and the etching rate of the second isolation layer are different by the same etching process.

11. The method for fabricating the semiconductor structure as described in claim 10, characterized in that, The process steps for forming the sacrificial layer include: A protective layer is formed, the protective layer being located on the top surface of the first isolation layer and covering the side surface of the semiconductor pillar in the first channel region; A sacrificial film is formed, the sacrificial film being located on the top surface of the protective layer, the side surface of the semiconductor pillar in the second channel region, and the side surface of the second isolation layer; Remove the sacrificial film located on the top surface of the protective layer, leaving the remaining sacrificial film as the sacrificial layer.

12. The method for preparing the semiconductor structure as described in claim 11, characterized in that, The sacrificial film is made of silicon nitride, and the second isolation layer is made of silicon nitride. After removing the sacrificial film located on the top surface of the protective layer, the process further includes: subjecting the remaining sacrificial film to plasma treatment so that the etching rate of the sacrificial layer is different from the etching rate of the second isolation layer by the same etching process.

13. The method for preparing the semiconductor structure as described in claim 9, characterized in that, Before forming the word lines, the process also includes: An epitaxial layer is formed on the sidewall of the semiconductor pillar in the second channel region using an epitaxial process; In the process of forming the word lines, the word lines cover the side surface of the epitaxial layer; After the word lines are formed, the epitaxial layer is removed to form the air gap.

14. The method for preparing the semiconductor structure as described in claim 13, characterized in that, The process steps for forming the character lines include: A first conductive layer is formed, which covers the side of the gate dielectric layer and surrounds the semiconductor pillar of the first channel region; A second conductive layer is formed on the top surface of the first conductive layer, the second conductive layer covering the side surface of the epitaxial layer and surrounding the semiconductor pillar of the second channel region.

15. The method for preparing the semiconductor structure as described in claim 14, characterized in that, The process steps for forming the first conductive layer include: A first conductive film is formed, the first conductive film surrounding the semiconductor pillars of the first channel region and the second channel region; The first conductive film with a portion of its thickness is etched back until the top surface of the remaining first conductive film is lower than the top surface of the gate dielectric layer, and the remaining first conductive film serves as the first conductive layer.

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