Mosfet device and manufacturing method therefor, and layout arrangement structure

Abstract

The present invention relates to the technical field of semiconductors, and provides a MOSFET device and a manufacturing method therefor, and a layout arrangement structure. A P-type buried layer is disposed within an N-type voltage-withstanding layer between the bottom of a trench and a substrate, and the P-type buried layer is electrically connected to a source, thereby solving the problem of insufficient electric field protection at the bottom of a trench gate and achieving effective protection of a gate dielectric layer under a high drain voltage. In addition, because a gap exists between the P-type buried layer and the bottom of a channel, current can still flow between the bottom of the trench and the P-type buried layer, and the design of the P-type buried layer does not hinder current flow, thereby comprehensively improving the operational performance of the MOSFET device.

Description

A MOSFET device and its fabrication method and layout structure

[0001] This application claims priority to Chinese Patent Application No. 202411622159.7, filed on November 13, 2024, entitled "A MOSFET Device and Its Fabrication Method and Layout Structure", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and in particular to a MOSFET device and its fabrication method and layout structure. Background Technology

[0003] With the continuous development of science and technology, more and more electronic devices are being widely used in people's daily lives and work, bringing great convenience to people's daily lives and work, and becoming an indispensable tool for people today.

[0004] The main structure that enables various functions of electronic devices is the integrated circuit, and MOSFET devices are an important electronic component of integrated circuits.

[0005] Wide bandgap semiconductor trench MOSFETs have become a major development direction in the semiconductor field due to their excellent characteristics in high-power applications.

[0006] Existing wide-bandgap semiconductor trench MOSFET devices still have shortcomings, and their structure and fabrication methods need to be further optimized to improve their performance. Summary of the Invention

[0007] In view of the above problems, this application provides a MOSFET device and its fabrication method and layout structure to improve the operating performance of the MOSFET device. The specific solution is as follows:

[0008] A first aspect of this application provides a MOSFET device, the MOSFET device comprising: a substrate;

[0009] An N-type withstand voltage layer located on one side of the substrate; a drain electrode located on the side of the substrate opposite to the N-type withstand voltage layer;

[0010] A P-type well region, a source region, and a trench gate are disposed on the surface of the N-type withstand layer facing away from the substrate; the trench gate includes a trench and a gate located in the trench, and a gate dielectric layer is provided between the gate and the trench.

[0011] The source region includes an N-type source region and a P-type source region; the N-type source region is located on the side of the P-type well region away from the substrate, the P-type source region is located on both sides of the trench, and the trench penetrates the N-type source region and the P-type well region.

[0012] The source electrode that is in contact with the N-type source region and the P-type source region;

[0013] A P-type buried layer is located within the N-type withstand voltage layer and between the bottom of the trench and the substrate; the P-type buried layer is electrically connected to the source electrode, and there is a gap between the P-type buried layer and the bottom of the trench.

[0014] Preferably, in the above-described MOSFET device, the width of the P-type buried layer is equal to the width of the trench;

[0015] Alternatively, the width of the P-type buried layer is smaller than the width of the trench;

[0016] Alternatively, the width of the P-type buried layer is greater than the width of the trench.

[0017] Preferably, in the above-described MOSFET device, there is a gap between the geometric center of the P-type buried layer and the geometric center of the bottom of the trench in a direction parallel to the plane of the substrate.

[0018] Preferably, in the above-described MOSFET device, the MOSFET device further includes: a P-type ground plane;

[0019] The P-type grounding layer is in contact with the P-type buried layer and the P-type source region, respectively.

[0020] Preferably, in the above-described MOSFET device, the MOSFET device further includes:

[0021] An N-type current diffusion region is located between the P-type well region and the P-type buried layer. The N-type current diffusion region has the same doping type as the N-type withstand voltage layer, and the doping concentration of the N-type current diffusion region is greater than or equal to the doping concentration of the N-type withstand voltage layer.

[0022] Preferably, in the above-described MOSFET device, the N-type current diffusion region at least partially encloses the P-type buried layer.

[0023] Preferably, in the above-described MOSFET device, the MOSFET device further includes: a P-type ground layer; the P-type ground layer is in contact with the P-type buried layer and the P-type source region respectively;

[0024] The N-type current diffusion region is located between at least one sidewall of the trench and the P-type source region.

[0025] Preferably, in the above-described MOSFET device, the MOSFET device further includes: a P-type ground plane;

[0026] The P-type grounding layer is in contact with the P-type buried layer and the P-type source region, respectively.

[0027] The N-type current diffusion region is located on the side of the P-type ground layer away from the substrate.

[0028] Preferably, in the above-described MOSFET device, the surface of the P-type source region facing away from the substrate and the surface of the N-type source region facing away from the substrate are located in the same plane.

[0029] Preferably, in the above-described MOSFET device, the surface of the P-type source region facing away from the substrate is located between the first surface and the second surface;

[0030] The first surface is the surface of the N-type source region facing away from the substrate, and the second surface is the surface of the P-type well region facing the substrate.

[0031] Preferably, in the above-described MOSFET device, the distance between the surface of the P-type source region facing away from the substrate and the substrate is less than the distance between the surface of the P-type well region facing the substrate and the substrate.

[0032] The source electrode forms a Schottky contact with the sidewall of the exposed N-type current diffusion region.

[0033] Preferably, in the above-mentioned MOSFET device, the P-type source region includes at least two sub-P-type source regions arranged sequentially at intervals in the length extension direction of the trench, and / or, the P-type buried layer includes at least two sub-P-type buried layers arranged sequentially at intervals in the length extension direction of the trench.

[0034] Preferably, in the above-mentioned MOSFET device, the pattern of the sub-P-type source region is square, triangular, polygonal, or circular; the pattern of the sub-P-type buried layer is square, triangular, polygonal, or circular.

[0035] Preferably, in the above-described MOSFET device, the MOSFET device further includes: a P-type ground plane;

[0036] The sub-P-type buried layer is connected to at least one of the sub-P-type source regions via the P-type grounding layer.

[0037] Preferably, in the above-mentioned MOSFET device, the P-type ground layers located on both sides of the trench are arranged alternately or symmetrically.

[0038] Preferably, in the above-described MOSFET device, in the P-type ground layers located on both sides of the trench, at least one sub-P-type source region is spaced between two adjacent P-type ground layers in the length extension direction of the trench.

[0039] Preferably, in the above-described MOSFET device, the length extension direction of the P-type ground layer intersects the length extension direction of the trench.

[0040] Preferably, in the above-described MOSFET device, the N-type source region and the P-type source region are arranged alternately in the length extension direction of the trench;

[0041] Alternatively, the orthographic projection of the N-type source region on the substrate surrounds the orthographic projection of the P-type source region on the substrate.

[0042] Preferably, in the above-described MOSFET device, the P-type source region is in contact with the sidewall of the trench and the P-type buried layer.

[0043] Preferably, in the above-described MOSFET device, when the P-type source region includes at least two sequentially spaced sub-P-type source regions in the length extension direction of the trench, at least one of the sub-P-type source regions is in contact with the sidewall of the trench and the P-type buried layer.

[0044] Preferably, in the above-described MOSFET device, the length extension direction of the trench intersects with the length extension direction of the P-type buried layer.

[0045] Preferably, in the above-described MOSFET device, the MOSFET device further includes: a P-type layer;

[0046] One side of the P-type layer is located at the bottom of the channel, and the other side extends toward the side where the substrate is disposed, at least through the P-type buried layer.

[0047] A second aspect of this application provides a method for fabricating a MOSFET device, the method comprising:

[0048] Provide a substrate;

[0049] An N-type pressure-resistant layer is formed on one side of the substrate;

[0050] A P-type well region, a source region, and a P-type buried layer are formed within the N-type pressure-resistant layer;

[0051] A trench gate is formed; the trench gate includes a trench and a gate located within the trench, with a gate dielectric layer between the gate and the trench; the source region includes an N-type source region and a P-type source region; the N-type source region is located on the side of the P-type well region away from the substrate, the P-type source regions are located on both sides of the trench, and the trench penetrates the N-type source region and the P-type well region; a P-type buried layer is located between the bottom of the trench and the substrate; and there is a gap between the P-type buried layer and the bottom of the trench;

[0052] A source and a drain are formed; the drain is located on the side of the substrate away from the N-type withstand layer, the source is in contact with the N-type source region and the P-type source region, and the P-type buried layer is electrically connected to the source.

[0053] A third aspect of this application provides a layout structure for a MOSFET device, the layout structure of which includes: a plurality of MOSFET cells;

[0054] The cross-sectional pattern of the MOSFET cells varies depending on their location.

[0055] By employing the above technical solution, this application provides a MOSFET device and its fabrication method and layout structure. A P-type buried layer is disposed in the N-type withstand layer between the bottom of the trench and the substrate. The P-type buried layer is electrically connected to the source, which solves the problem of insufficient protection of the electric field at the bottom of the trench and achieves effective protection of the gate dielectric layer under high drain voltage. Furthermore, since there is a gap between the P-type buried layer and the bottom of the trench, current can still flow between the bottom of the trench and the P-type buried layer. There is no problem of the P-type buried layer design hindering current flow, thereby comprehensively improving the working performance of the MOSFET device. Attached Figure Description

[0056] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0057] Figure 1 is a cross-sectional and top view schematic diagram of a MOSFET device provided in an embodiment of the present invention;

[0058] Figure 2 is a cross-section and top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0059] Figure 3 is a cross-sectional and top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0060] Figure 4 is a cross-section and top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0061] Figure 5 is a schematic diagram of the current path of the MOSFET device in Figure 2 provided by an embodiment of the present invention;

[0062] Figure 6 is a cross-sectional and top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0063] Figure 7 is a cross-sectional and top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0064] Figure 8 is a cross-sectional and top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0065] Figure 9 is a cross-sectional schematic diagram of a MOSFET device provided in an embodiment of the present invention;

[0066] Figure 10 is a cross-sectional and top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0067] Figure 11 is a cross-sectional and top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0068] Figure 12 is a cross-sectional and top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0069] Figure 13 is a cross-sectional schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0070] Figure 14 is a cross-sectional schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0071] Figure 15 is a cross-sectional schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0072] Figure 16 is a top view schematic diagram of a MOSFET device provided in an embodiment of the present invention;

[0073] Figure 17 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0074] Figure 18 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0075] Figure 19 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0076] Figure 20 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0077] Figure 21 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0078] Figure 22 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0079] Figure 23 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0080] Figure 24 is a cross-sectional view along the cutting line C in Figure 23 provided by an embodiment of the present invention;

[0081] Figure 25 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0082] Figure 26 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0083] Figure 27 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0084] Figure 28 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0085] Figure 29 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0086] Figure 30 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0087] Figure 31 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0088] Figure 32 is a schematic diagram of a composite cross section along cutting line A and cutting line B in Figure 31 provided by an embodiment of the present invention;

[0089] Figure 33 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0090] Figure 34 is a schematic cross-sectional view along cutting line A in Figure 33 provided by an embodiment of the present invention;

[0091] Figure 35 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0092] Figure 36 is a schematic diagram of a composite cross-section along cutting line A and cutting line B in Figure 35 provided by an embodiment of the present invention;

[0093] Figure 37 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0094] Figure 38 is a schematic diagram of a composite cross section along cutting line A and cutting line B in Figure 37 provided by an embodiment of the present invention;

[0095] Figure 39 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0096] Figure 40 is a schematic diagram of a composite cross section along cutting line A and cutting line B in Figure 39 provided by an embodiment of the present invention;

[0097] Figure 41 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0098] Figure 42 is a schematic diagram of a composite cross section along cutting line A and cutting line B in Figure 41 provided by an embodiment of the present invention;

[0099] Figure 43 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0100] Figure 44 is a cross-sectional schematic diagram along cutting line A in Figure 43 provided by an embodiment of the present invention;

[0101] Figure 45 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0102] Figure 46 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0103] Figure 47 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0104] Figure 48 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0105] Figure 49 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0106] Figure 50 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention;

[0107] Figure 51 is a schematic diagram showing different cross-sectional views of a MOSFET cell placed at different positions according to an embodiment of the present invention.

[0108] Figure 52 is a top view schematic diagram of the layout structure of a MOSFET device provided in an embodiment of the present invention;

[0109] Figure 53 is a top view of another MOSFET device layout structure provided in an embodiment of the present invention;

[0110] Figure 54 is a top view schematic diagram of the layout structure of another MOSFET device provided in an embodiment of the present invention;

[0111] Figure 55 is a top view of the layout structure of another MOSFET device provided in an embodiment of the present invention;

[0112] Figure 56 is a top view schematic diagram of the layout structure of another MOSFET device provided in an embodiment of the present invention;

[0113] Figure 57 is a top view of the layout structure of another MOSFET device provided in an embodiment of the present invention;

[0114] Figure 58 is a top view of the layout structure of another MOSFET device provided in an embodiment of the present invention;

[0115] Figure 59 is a top view schematic diagram of the layout structure of another MOSFET device provided in an embodiment of the present invention;

[0116] Figure 60 is a schematic cross-sectional view along the cutting line D in Figures 54, 55, 56, 57 and 59 provided by an embodiment of the present invention;

[0117] Figure 61 is a cross-sectional schematic diagram of Figures 53, 55 and 57 along the cutting line F according to an embodiment of the present invention;

[0118] Figure 62 is a top view schematic diagram of the layout structure of another MOSFET device provided in an embodiment of the present invention;

[0119] Figure 63 is a top view schematic diagram of the layout structure of another MOSFET device provided in an embodiment of the present invention;

[0120] Figure 64 is a top view schematic diagram of the layout structure of another MOSFET device provided in an embodiment of the present invention;

[0121] Figure 65 is a top view of the layout structure of another MOSFET device provided in an embodiment of the present invention;

[0122] Figure 66 is a schematic flowchart of a method for fabricating a MOSFET device according to an embodiment of the present invention. Detailed Implementation

[0123] The embodiments of this application are described below with reference to the accompanying drawings. The terminology used in the implementation section of this application is only for explaining specific embodiments and is not intended to limit the application. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0124] Ultra-wide bandgap semiconductor materials with band gaps greater than silicon carbide (SiC) and gallium nitride (GaN) also include gallium oxide (Ga2O3), diamond, and aluminum nitride (AlN). As wide and ultra-wide bandgap semiconductor materials, they have attracted widespread attention from the industry due to their excellent material properties. Compared with traditional Si materials, they have advantages in physical properties such as band gap width, critical breakdown electric field strength, and electron saturation drift velocity. Power devices fabricated from them, such as diodes and transistors, have superior electrical characteristics and can meet the high-power, high-voltage, high-frequency, and high-temperature application requirements that silicon-based devices cannot satisfy. This represents one of the breakthrough paths beyond Moore's Law, and therefore they are widely used in the new energy field (photovoltaics, energy storage, charging piles, electric vehicles, etc.), driving the development of the "new energy revolution."

[0125] As wide and ultra-wide bandgap semiconductor materials, their superior optical and electrical properties have made them an exciting and challenging new research area. The larger bandgap allows devices to be used in many extreme environments. For example, in geothermal energy production and oil and gas extraction, they can achieve higher drilling speeds and lower failure rates. In high-temperature environments, they enable electronically controlled aluminum plants, steel mills, and coal-fired and gas-fired power plants to operate at higher temperatures, thereby improving the energy efficiency of these industrial processes.

[0126] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0127] It should be noted that the directional terms used in this invention are based on the relative positional relationships shown in the accompanying drawings and should not be taken as absolute limitations on this application.

[0128] Referring to Figure 1, which is a cross-sectional and top view schematic diagram of a MOSFET device provided in an embodiment of the present invention, Figure 1a is a corresponding cross-sectional schematic diagram, and Figure 1b is a corresponding top view schematic diagram; referring to Figure 2, which is a cross-sectional and top view schematic diagram of another MOSFET device provided in an embodiment of the present invention, Figure 2a is a corresponding cross-sectional schematic diagram, and Figure 2b is a corresponding top view schematic diagram; referring to Figure 3, which is a cross-sectional and top view schematic diagram of yet another MOSFET device provided in an embodiment of the present invention, Figure 3a is a corresponding cross-sectional schematic diagram, and Figure 3b is a corresponding top view schematic diagram; referring to Figure 4, which is a cross-sectional and top view schematic diagram of yet another MOSFET device provided in an embodiment of the present invention, Figure 4a is a corresponding cross-sectional schematic diagram, and Figure 4b is a corresponding top view schematic diagram. The MOSFET device provided in this embodiment of the present invention includes: a substrate 11.

[0129] An N-type withstand voltage layer 12 located on one side of the substrate 11; a drain electrode 13 located on the side of the substrate 11 opposite to the N-type withstand voltage layer 12.

[0130] A P-type well region 14, a source region, and a trench gate are disposed on the surface of the N-type withstand voltage layer 12 on the side opposite to the substrate 11; the trench gate includes a trench and a gate 15 located in the trench, and a gate dielectric layer 16 is provided between the gate 15 and the trench.

[0131] The source region includes an N-type source region 17 and a P-type source region 18; the N-type source region 17 is located on the side of the P-type well region 14 away from the substrate 11, and the P-type source region 18 is located on both sides of the trench, the trench penetrating the N-type source region 17 and the P-type well region 14.

[0132] The source electrode 19 is in contact with the N-type source region 17 and the P-type source region 14.

[0133] A P-type buried layer 20 is located within the N-type withstand voltage layer 12 and between the bottom of the trench and the substrate 11; the P-type buried layer 20 is electrically connected to the source electrode, and there is a gap between the P-type buried layer 20 and the bottom of the trench.

[0134] Specifically, in this embodiment of the invention, the P-type source region 18 is located on both sides of the trench, and the injection depth of the P-type source region 18 is relatively deep, which can shield part of the potential from the drain 13. On this basis, a P-type buried layer 20 is disposed in the N-type withstand voltage layer 12 between the bottom of the trench and the substrate 11. The P-type buried layer 20 is electrically connected to the source, which solves the problem of insufficient protection of the electric field at the bottom of the trench by the P-type source region 18, improves the protection effect of the electric field at the bottom of the trench, and achieves effective protection of the gate dielectric layer under high drain voltage. Referring to Figure 5, Figure 5 is a schematic diagram of the current path of the MOSFET device in Figure 2 provided by an embodiment of the present invention. Since there is a gap between the P-type buried layer 20 and the bottom of the trench, the current can also flow between the bottom of the trench and the P-type buried layer 20. There is no problem that the design of the P-type buried layer 20 hinders the current flow, thereby comprehensively improving the working performance of the MOSFET device.

[0135] In an optional embodiment of the present invention, referring to FIG6, FIG6 is a cross-sectional and top view schematic diagram of another MOSFET device provided in the embodiment of the present invention, FIG6a is a corresponding cross-sectional schematic diagram, and FIG6b is a corresponding top view schematic diagram; referring to FIG7, FIG7 is a cross-sectional and top view schematic diagram of another MOSFET device provided in the embodiment of the present invention, FIG7a is a corresponding cross-sectional schematic diagram, and FIG7b is a corresponding top view schematic diagram; referring to FIG8, FIG8 is a cross-sectional and top view schematic diagram of another MOSFET device provided in the embodiment of the present invention, FIG8a is a corresponding cross-sectional schematic diagram, and FIG8b is a corresponding top view schematic diagram. The width of the P-type buried layer 20 is equal to the width of the trench; or, the width of the P-type buried layer 20 is less than the width of the trench; or, the width of the P-type buried layer 20 is greater than the width of the trench.

[0136] In a direction parallel to the plane of the substrate 11, there is a gap between the geometric center of the P-type buried layer 20 and the geometric center of the bottom of the trench.

[0137] Specifically, in this embodiment of the invention, as shown in FIG. 6, the width of the P-type buried layer 20 is smaller than the width of the trench, i.e., L1 < L2; as shown in FIG. 7, the width of the P-type buried layer 20 is larger than the width of the trench, i.e., L3 > L4. As shown in FIG. 8, in a direction parallel to the plane of the substrate 11, there is a gap between the geometric center of the P-type buried layer 20 and the geometric center of the bottom of the trench. It can be understood that the geometric center of the P-type buried layer 20 is offset to the right by a certain distance based on the geometric center of the bottom of the trench.

[0138] In other words, the positional and dimensional relationships between the P-type buried layer 20 and the trench can be freely varied in the embodiments of the present invention, which indirectly reflects the structural diversity of the MOSFET device in the technical solution of this application. That is, the width of the P-type buried layer 20 can be equal to, wider than, or narrower than that of the trench, and this is not limited in the embodiments of the present invention. Furthermore, the relative position of the P-type buried layer 20 and the trench can be varied, for example, shifted to the left or to the right.

[0139] The structure where the width of the P-type buried layer 20 is greater than the width of the trench can give the MOSFET device better gate oxide reliability; the structure where the width of the P-type buried layer 20 is less than the width of the trench can give the MOSFET device better conduction performance; the structure where the P-type buried layer 20 can be offset to the left or right relative to the trench position can give the MOSFET device structure greater process tolerance and simplify the process.

[0140] In an optional embodiment of the present invention, as shown in Figures 2, 3, 4 and 5, the MOSFET device further includes a P-type ground layer 22.

[0141] The P-type grounding layer 22 is in contact with the P-type buried layer 20 and the P-type source region 18, respectively.

[0142] Specifically, in this embodiment of the invention, the electrical connection between the P-type buried layer 20 and the P-type source region 18 can be achieved by setting a P-type ground layer 22 to contact both of them, thereby improving the stability of the electrical connection between the P-type buried layer 20 and the P-type source region 18. In some structural designs, the MOSFET device may not require a P-type ground layer 22; it is sufficient to ensure an electrical connection between the P-type buried layer 20 and the P-type source region 18. The specific electrical connection method can be determined according to the actual situation.

[0143] In an optional embodiment of the present invention, as shown in Figures 1, 2, and 4-8, the MOSFET device further includes an N-type current diffusion region 21 located between the P-type well region 14 and the P-type buried layer 20. The N-type current diffusion region 21 has the same doping type as the N-type withstand voltage layer 12, and the doping concentration of the N-type current diffusion region 21 is greater than or equal to the doping concentration of the N-type withstand voltage layer 12.

[0144] Specifically, in this embodiment of the invention, when the doping concentration of the N-type current diffusion region 21 is equal to the doping concentration of the N-type withstand voltage layer 12, the function of the N-type current diffusion region 21 is the same as that of the N-type withstand voltage layer 12. When the doping concentration of the N-type current diffusion region 21 is greater than the doping concentration of the N-type withstand voltage layer 12, since the N-type current diffusion region 21 has a relatively high doping concentration, the width of the depletion region can be reduced, thereby increasing the current conduction path and enhancing the conduction capability of the MOSFET device.

[0145] In an optional embodiment of the present invention, referring to FIG9, FIG9 is a cross-sectional schematic diagram of a MOSFET device provided by an embodiment of the present invention. The N-type current diffusion region 21 at least partially encloses the P-type buried layer 20.

[0146] Specifically, in this embodiment of the invention, when the doping concentration of the N-type current diffusion region 21 is greater than the doping concentration of the N-type withstand voltage layer 12, the design of the N-type current diffusion region 21 at least partially enclosing the P-type buried layer 20 can further enhance the conduction capability of the MOSFET device. As shown in Figure 9, the example of the N-type current diffusion region 21 fully enclosing the P-type buried layer 20 is illustrated.

[0147] In an optional embodiment of the present invention, referring to FIG10, FIG10 is a cross-sectional and top view schematic diagram of another MOSFET device provided in the embodiment of the present invention, FIG10a is a corresponding cross-sectional schematic diagram, and FIG10b is a corresponding top view schematic diagram; referring to FIG11, FIG11 is a cross-sectional and top view schematic diagram of another MOSFET device provided in the embodiment of the present invention, FIG11a is a corresponding cross-sectional schematic diagram, and FIG11b is a corresponding top view schematic diagram; referring to FIG12, FIG12 is a cross-sectional and top view schematic diagram of another MOSFET device provided in the embodiment of the present invention, FIG12a is a corresponding cross-sectional schematic diagram, and FIG12b is a corresponding top view schematic diagram. The MOSFET device further includes: a P-type ground layer 22; the P-type ground layer 22 is in contact with the P-type buried layer 20 and the P-type source region 18 respectively; the N-type current diffusion region 21 is located at least between one sidewall of the trench and the P-type source region 18, or the N-type current diffusion region 21 is located on the side of the P-type ground layer 22 away from the substrate 11.

[0148] Specifically, in this embodiment of the invention, as shown in Figure 10, the P-type ground layer 22 is located on the left side and bottom of the trench, and the N-type current diffusion region 21 is located on the right side of the trench; as shown in Figure 11, the P-type ground layer 22 is located on the right side and bottom of the trench, and the N-type current diffusion region 21 is located on the left side of the trench; as shown in Figure 12, the P-type ground layer 22 is located at the bottom of the trench, and the N-type current diffusion region 21 is located on both the left and right sides of the trench; as shown in Figure 2, the N-type current diffusion region 21 is located on the side of the P-type ground layer 22 facing away from the substrate.

[0149] In this embodiment of the invention, the location and number of N-type current diffusion regions 21 can be flexibly adjusted. Locations with N-type current diffusion regions 21 have higher current density, while locations without N-type current diffusion regions 21 have lower current density, or even no current due to the presence of the P-type grounding layer 22. In this embodiment, the distribution of the N-type current diffusion regions 21 and the P-type grounding layer 22, and their proportion to the entire layout (the location and area ratio of layout openings), can be adjusted to control the current and heat distribution, thereby enhancing short-circuit, surge, and UIS avalanche withstand capabilities. Examples include one-sided conduction, two-sided conduction, and neither-sided conduction.

[0150] It should be noted that Figures 10-12 only illustrate the relative positional relationship between some of the N-type current diffusion region 21 and the P-type grounding layer 22. There are other variations in the positional relationship between the N-type current diffusion region 21 and the P-type grounding layer 22. A reasonable design can be made based on the purpose to be achieved.

[0151] In an optional embodiment of the present invention, as shown in Figures 11-12, the surface of the P-type source region 18 facing away from the substrate 11 and the surface of the N-type source region 17 facing away from the substrate 11 are located on the same plane. Alternatively, referring to Figure 13, which is a cross-sectional schematic diagram of another MOSFET device provided in an embodiment of the present invention, and referring to Figure 14, which is a cross-sectional schematic diagram of yet another MOSFET device provided in an embodiment of the present invention, the surface of the P-type source region 18 facing away from the substrate 11 is located between a first surface and a second surface; the first surface is the surface of the N-type source region 17 facing away from the substrate 11, and the second surface is the surface of the P-type well region 14 facing the substrate 11.

[0152] Specifically, in this embodiment of the invention, as shown in FIG13, the surface of the P-type source region 18 facing away from the substrate 11 and the surface of the P-type well region 14 facing away from the substrate 11 are located on the same plane. This design can increase the contact area between the source 19, the P-type source region 18, and the N-type source region 17, thereby reducing the cell size. As shown in FIG14, the surface of the P-type source region 18 facing away from the substrate 11 and the surface of the P-type well region 14 facing the substrate 11 are located on the same plane. This design can increase the ion implantation depth of the P-type source region 18 and save the implantation energy of the P-type source region 18.

[0153] In an optional embodiment of the present invention, referring to FIG15, FIG15 is a cross-sectional schematic diagram of another MOSFET device provided in an embodiment of the present invention. The distance between the surface of the P-type source region 18 facing away from the substrate 11 and the substrate 11 is less than the distance between the surface of the P-type well region 14 facing the substrate 11 and the substrate; the source 19 forms a Schottky contact with the sidewall of the exposed N-type current diffusion region 21.

[0154] Specifically, as shown in Figure 15 of this embodiment, there exists a relationship H1 < H2, meaning that the distance between the surface of the P-type source region 18 facing away from the substrate 11 and the substrate 11 is less than the distance between the surface of the P-type well region 14 facing the substrate 11 and the substrate. In this case, a portion of the sidewall of the N-current diffusion region 21 will form a Schottky contact with the source 19, forming a Schottky diode 23 between them, thereby improving the freewheeling characteristics of the MOSFET device in the third quadrant.

[0155] In an optional embodiment of the present invention, referring to FIG16, FIG16 is a top view schematic diagram of a MOSFET device provided in an embodiment of the present invention; referring to FIG17, FIG18 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention; referring to FIG18, FIG18 is a top view schematic diagram of yet another MOSFET device provided in an embodiment of the present invention; referring to FIG19, FIG19 is a top view schematic diagram of yet another MOSFET device provided in an embodiment of the present invention. The P-type source region 18 includes at least two sub-P-type source regions arranged sequentially at intervals in the length extension direction of the trench, and / or, the P-type buried layer 20 includes at least two sub-P-type buried layers arranged sequentially at intervals in the length extension direction of the trench.

[0156] Specifically, in this embodiment of the invention, as shown in FIG16, the P-type source region 18 is continuous in the length extension direction of the trench, and the P-type buried layer 20 includes at least two sub-P-type buried layers arranged alternately in the length extension direction of the trench; as shown in FIG17-FIG19, the P-type source region 18 includes at least two sub-P-type source regions arranged alternately in the length extension direction of the trench, and the P-type buried layer 20 includes at least two sub-P-type buried layers arranged alternately in the length extension direction of the trench.

[0157] The shape of the sub-P-type source region 18 includes, but is not limited to, a square, a triangle, a polygon, or a circle; the shape of the sub-P-type buried layer 20 includes, but is not limited to, a square, a triangle, a polygon, or a circle. As shown in Figure 17, the shape of the sub-P-type source region is square; as shown in Figure 18, the shape of the sub-P-type source region is triangular; as shown in Figure 19, the shape of the sub-P-type source region is semi-circular.

[0158] Optionally, referring to Figure 20, which is a top view of another MOSFET device provided in an embodiment of the present invention; referring to Figure 21, which is a top view of another MOSFET device provided in an embodiment of the present invention; and referring to Figure 22, which is a top view of another MOSFET device provided in an embodiment of the present invention. As shown in Figure 20, the P-type source region 18 is continuous in the length extension direction of the trench, and the P-type buried layer 20 is continuous in the length extension direction of the trench, while the P-type ground layer 22 includes at least two sequentially spaced sub-P-type ground layers in the length extension direction of the trench; as shown in Figures 21 and 22, the P-type source region 18 includes at least two sequentially spaced sub-P-type source regions in the length extension direction of the trench, the P-type buried layer 20 is continuous in the length extension direction of the trench, and the P-type ground layer 22 includes at least two sequentially spaced sub-P-type ground layers in the length extension direction of the trench.

[0159] Referring to Figure 23, which is a top view of another MOSFET device provided in an embodiment of the present invention, a cross-sectional view along cut line A in Figure 23 is shown in Figure 2a; a cross-sectional view along cut line B in Figure 23 is shown in Figure 1a; a cross-sectional view along cut line C in Figure 23 is shown in Figure 24, which is a cross-sectional view along cut line C in Figure 23 provided in an embodiment of the present invention; and a cross-sectional view along cut line D in Figure 23 is shown in Figure 3a.

[0160] As shown in Figures 17, 18, 21 and 23, the MOSFET device further includes a P-type ground layer 22; the sub-P-type buried layer is connected to at least one of the sub-P-type source regions through the P-type ground layer 22.

[0161] As described above, in this embodiment of the invention, the P-type buried layer 20 and the P-type source region 18 can be continuously present along the length extension direction of the trench, or at least arranged in two segments at intervals. The shapes of the P-type buried layer 20 and the P-type source region 18 can be square, triangular, hexagonal, circular, or other shapes. The P-type grounding layer 22 can be adjusted according to the continuity of the P-type buried layer 20 and the P-type source region 18, as long as it ensures that the P-type buried layer 20 is connected to at least one sub-P-type source region through the P-type grounding layer 22.

[0162] In an optional embodiment of the present invention, referring to FIG25, FIG25 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention; referring to FIG26, FIG26 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention; referring to FIG27, FIG27 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention. The P-type ground layers 22 located on both sides of the trench are arranged alternately or symmetrically. In the P-type ground layers 22 located on both sides of the trench, in the length extension direction of the trench, at least one sub-P-type source region is spaced between two adjacent P-type ground layers 22.

[0163] Specifically, in the embodiments of the present invention, as shown in FIG17, the P-type grounding layers 22 located on both sides of the trench are symmetrically arranged; as shown in FIG25 and FIG26, the P-type grounding layers 22 located on both sides of the trench are alternately arranged; as shown in FIG27, one of the P-type grounding layers 22 is in contact with two adjacent sub-P-type buried layers at the same time.

[0164] Furthermore, as shown in Figures 17, 25, 26 and 27, in the P-type grounding layers 22 located on both sides of the trench, at least one sub-P-type source region is spaced between two adjacent P-type grounding layers 22 in the length extension direction of the trench.

[0165] Optionally, in another embodiment of the present invention, referring to FIG28, FIG28 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention, and referring to FIG29, FIG29 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention. The length extension direction of the P-type ground layer 22 intersects the length extension direction of the trench.

[0166] Specifically, in this embodiment of the invention, the connection between the P-type ground layer 22, the P-type source region 18, and the P-region buried layer 20 can be a horizontal connection, an inclined connection, a cross connection, or a star-shaped connection, etc. In this embodiment of the invention, no limitation is made, and the pattern of the P-type ground layer 22 can be determined according to the actual layout and other factors.

[0167] Optionally, in another embodiment of the present invention, referring to FIG30, FIG30 is a top view of another MOSFET device provided in an embodiment of the present invention; referring to FIG31, FIG31 is a top view of another MOSFET device provided in an embodiment of the present invention; referring to FIG32, FIG32 is a combined cross-sectional view along cut line A and cut line B in FIG31 provided in an embodiment of the present invention; referring to FIG33, FIG33 is a top view of another MOSFET device provided in an embodiment of the present invention; and referring to FIG34, FIG34 is a cross-sectional view along cut line A in FIG33 provided in an embodiment of the present invention. In the length extension direction of the trench, the N-type source region 17 and the P-type source region 18 are arranged alternately; or, the orthographic projection of the N-type source region 17 on the substrate 11 surrounds the orthographic projection of the P-type source region 18 on the substrate 11.

[0168] Specifically, in this embodiment of the invention, as shown in FIG30, the N-type source region 17 and the P-type source region 18 are arranged alternately along the length extension direction of the trench. As shown in FIG31 and 33, the orthographic projection of the N-type source region 17 on the substrate 11 surrounds the orthographic projection of the P-type source region 18 on the substrate 11. That is, in this embodiment of the invention, the N-type source region 17 and the P-type source region 18 can be arranged alternately, or the N-type source region 17 can surround the P-type source region 18. The scheme in which the N-type source region 17 surrounds the P-type source region 18 can achieve the purpose of saving area and reducing cell spacing.

[0169] Optionally, in another embodiment of the present invention, referring to FIG35, FIG35 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention; referring to FIG36, FIG36 is a composite cross-sectional schematic diagram along cut line A and cut line B in FIG35 provided in an embodiment of the present invention; referring to FIG37, FIG37 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention; referring to FIG38, FIG38 is a composite cross-sectional schematic diagram along cut line A and cut line B in FIG37 provided in an embodiment of the present invention; referring to FIG39, FIG39 is another MOSFET device provided in an embodiment of the present invention. Referring to Figure 40, which is a combined cross-sectional view along cut lines A and B in Figure 39 provided in an embodiment of the present invention; referring to Figure 41, which is a top view of another MOSFET device provided in an embodiment of the present invention; referring to Figure 42, which is a combined cross-sectional view along cut lines A and B in Figure 41 provided in an embodiment of the present invention; referring to Figure 43, which is a top view of another MOSFET device provided in an embodiment of the present invention; and referring to Figure 44, which is a cross-sectional view along cut line A in Figure 43 provided in an embodiment of the present invention. The P-type source region 18 contacts the sidewall of the trench and the P-type buried layer 20. When the P-type source region 18 includes at least two sequentially spaced sub-P-type source regions in the length extension direction of the trench, at least one of the sub-P-type source regions contacts the sidewall of the trench and the P-type buried layer 20.

[0170] Specifically, in this embodiment of the invention, by making the P-type source region 18 contact the sidewall of the trench and the P-type buried layer 20, or by making at least one of the sub-P-type source regions contact the sidewall of the trench and the P-type buried layer 20, the P-type source region 18 or the sub-P-type source region can act as the P-type grounding layer 22. In this case, the P-type grounding layer 22 can be omitted, thereby further saving area and reducing the cell spacing.

[0171] Referring to Figure 45, which is a top view of another MOSFET device provided in an embodiment of the present invention; referring to Figure 46, which is a top view of another MOSFET device provided in an embodiment of the present invention; referring to Figure 47, which is a top view of another MOSFET device provided in an embodiment of the present invention; and referring to Figure 48, which is a top view of another MOSFET device provided in an embodiment of the present invention.

[0172] Without the P-type grounding layer 22, as shown in Figures 45 and 46, the P-type source region 18 includes at least two sequentially spaced sub-P-type source regions along the length of the trench, while the P-type buried layer 20 is continuous along the length of the trench, wherein at least one of the sub-P-type source regions contacts the sidewall of the trench and the P-type buried layer 20. As shown in Figures 47 and 48, the P-type source region 18 includes at least two sequentially spaced sub-P-type source regions along the length of the trench, and the P-type buried layer 20 includes at least two sequentially spaced sub-P-type buried layers along the length of the trench, wherein at least one of the sub-P-type source regions contacts the sidewall of the trench and the P-type buried layer 20.

[0173] In an optional embodiment of the present invention, referring to FIG49, FIG49 is a top view schematic diagram of another MOSFET device provided in the embodiment of the present invention. A cross-sectional schematic diagram along cut line A in FIG49 is shown in FIG2a; a cross-sectional schematic diagram along cut line B in FIG49 is shown in FIG1a; a cross-sectional schematic diagram along cut line C in FIG49 is shown in FIG24; and a cross-sectional schematic diagram along cut line D in FIG49 is shown in FIG3a. The length extension direction of the trench intersects with the length extension direction of the P-type buried layer 20.

[0174] In summary, the MOSFET devices provided in the embodiments of the present invention have diverse designs and are not limited to a specific structure. They can be determined according to actual needs and are not limited in the embodiments of the present invention.

[0175] In an optional embodiment of the present invention, referring to FIG50, FIG50 is a top view schematic diagram of another MOSFET device provided in an embodiment of the present invention. The MOSFET device further includes: a P-type layer 24; one side of the P-type layer 24 is located at the bottom of the channel, and the other side extends toward the side where the substrate 11 is disposed, at least through the P-type buried layer 20.

[0176] Specifically, in this embodiment of the invention, a P-type layer 24 is provided, and a superjunction structure is formed by combining the P-type layer 24 with the P-type sources 18 on the left and right sides and the N-type current diffusion region 21 between the P-type layer 24 and the P-type sources 18, thereby improving the working performance of the MOSFET device.

[0177] Based on the above embodiments of the present invention, another embodiment of the present invention also provides a layout structure of a MOSFET device, the layout structure of the MOSFET device including: a plurality of MOSFET cells; the cross-sectional pattern of the MOSFET cells is different at different positions.

[0178] Specifically, referring to Figure 51 in this embodiment of the invention, Figure 51 is a schematic diagram showing different cross-sectional patterns of MOSFET cells placed at different positions according to this embodiment of the invention. By adjusting the distribution position and proportion of different types of cross-sections in the layout structure of the MOSFET device, as shown in Figure 51, the current flow path and heat generation position during MOSFET device operation can be dispersed, avoiding excessive heat concentration that could cause premature device burnout.

[0179] Referring to Figure 52, which is a top view of a layout structure of a MOSFET device according to an embodiment of the present invention; referring to Figure 53, which is a top view of another layout structure of a MOSFET device according to an embodiment of the present invention; referring to Figure 54, which is a top view of yet another layout structure of a MOSFET device according to an embodiment of the present invention; referring to Figure 55, which is a top view of yet another layout structure of a MOSFET device according to an embodiment of the present invention; referring to Figure 56, which is a top view of yet another layout structure of a MOSFET device according to an embodiment of the present invention; referring to Figure 57, which is a top view of yet another layout structure of a MOSFET device according to an embodiment of the present invention; referring to Figure 58, which is a top view of yet another layout structure of a MOSFET device according to an embodiment of the present invention; and referring to Figure 59, which is a top view of yet another layout structure of a MOSFET device according to an embodiment of the present invention. Figure 52-59 shows a cross-sectional view along cutting line A as shown in Figure 2a; Figure 52-59 shows a cross-sectional view along cutting line B as shown in Figure 1a; Figure 52-59 shows a cross-sectional view along cutting line C as shown in Figure 24; Figure 52-59 shows a cross-sectional view along cutting line D as shown in Figure 3a; Figure 54, 55, 56, 57 and 59 shows a cross-sectional view along cutting line E as shown in Figure 60, which is a cross-sectional view along cutting line D in Figures 54, 55, 56, 57 and 59 provided by an embodiment of the present invention; Figure 53, 55 and 57 shows a cross-sectional view along cutting line F as shown in Figure 61, which is a cross-sectional view along cutting line F in Figures 53, 55 and 57 provided by an embodiment of the present invention. The MOSFET cell is a hexagonal cell. By adjusting the distribution position and proportion of different types of cross sections in the layout structure of the MOSFET device, the current flow path and heat generation position of the MOSFET device can be dispersed, avoiding excessive heat concentration that could cause the device to burn out prematurely.

[0180] Referring to Figure 62, which is a top view of another MOSFET device layout structure provided in an embodiment of the present invention; referring to Figure 63, which is a top view of another MOSFET device layout structure provided in an embodiment of the present invention; referring to Figure 64, which is a top view of another MOSFET device layout structure provided in an embodiment of the present invention; and referring to Figure 65, which is a top view of another MOSFET device layout structure provided in an embodiment of the present invention. The cross-sectional view along cutting line A in Figures 62-65 is shown in Figure 2a; the cross-sectional view along cutting line B in Figures 62-65 is shown in Figure 1a; the cross-sectional view along cutting line C in Figures 62-65 is shown in Figure 24; and the cross-sectional view along cutting line F in Figures 63 and 65 is shown in Figure 61. The MOSFET cells are square cells. By adjusting the distribution position and proportion of different types of cross-sections in the layout structure of the MOSFET device, the current flow path and heat generation position during MOSFET device operation can be dispersed, avoiding excessive heat concentration that could lead to premature device burnout.

[0181] Based on the above embodiments of the present invention, another embodiment of the present invention also provides a method for fabricating a MOSFET device. Referring to FIG66, FIG66 is a schematic flowchart of a method for fabricating a MOSFET device according to an embodiment of the present invention. The method for fabricating a MOSFET device provided in this embodiment of the present invention includes:

[0182] S101: Provide a substrate 11.

[0183] S102: An N-type pressure-resistant layer 12 is formed on one side of the substrate 11.

[0184] S103: A P-type well region 14, a source region, and a P-type buried layer 20 are formed within the N-type pressure-resistant layer 12.

[0185] S104: Forming a trench gate; the trench gate includes a trench and a gate 15 located within the trench, with a gate dielectric layer 16 between the gate 15 and the trench; the source region includes an N-type source region 17 and a P-type source region 18; the N-type source region 17 is located on the side of the P-type well region 14 away from the substrate 11, the P-type source region 18 is located on both sides of the trench, and the trench penetrates the N-type source region 17 and the P-type well region 14; the P-type buried layer 20 is located between the bottom of the trench and the substrate 11; and there is a gap between the P-type buried layer 20 and the bottom of the trench.

[0186] S105: Form source 19 and drain 13; the drain 13 is located on the side of the substrate 11 away from the N-type withstand layer 12, the source 19 is in contact with the N-type source region 17 and the P-type source region 18, and the P-type buried layer 20 is electrically connected to the source.

[0187] Specifically, in this embodiment of the invention, a functional film layer such as a P-type buried layer 20 is formed first, and then a trench gate is formed. This decouples the influence between the width of the trench and the width of the P-type buried layer 20, which can not only further reduce the width of the trench and the cell size of the MOSFET device to improve the conduction performance of the MOSFET device, but also make the MOSFET device have better process compatibility.

[0188] For example, assuming the trench width is 1µm, if ion implantation is performed in the trench, the width of the implanted P-type buried layer 20 cannot exceed 1µm. However, if ion implantation is performed on the plane before trench etching, the trench width does not need to be considered. The trench width does not affect the width of the P-type buried layer 20. In other words, the width of the P-type buried layer 20 and the trench width are not coupled and can be designed freely.

[0189] Conversely, if the design of a MOSFET device requires a P-type buried layer 20 width of at least 2µm, and a trench is formed first and then the P-type buried layer 20 is formed, then the trench width must be at least 2µm. However, using the fabrication method of this technology, the trench width can be reduced to only 1µm. Therefore, the size of the MOSFET device cell based on the width of this technology can be reduced by at least 1µm. More MOSFET device cells (or more conducting units) can be placed on the same area of ​​chip, resulting in better conduction performance.

[0190] The foregoing has provided a detailed description of the MOSFET device, its fabrication method, and its layout structure provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

[0191] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. Regarding the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0192] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that elements inherent to a process, method, article, or apparatus that comprises a list of elements, or elements inherent to such processes, methods, articles, or apparatus, are also included. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0193] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A MOSFET device, characterized by, The MOSFET device includes: Substrate; An N-type withstand voltage layer located on one side of the substrate; a drain electrode located on the side of the substrate opposite to the N-type withstand voltage layer; A P-type well region, a source region, and a trench gate are disposed on the surface of the N-type withstand layer facing away from the substrate; the trench gate includes a trench and a gate located in the trench, and a gate dielectric layer is provided between the gate and the trench. The source region includes an N-type source region and a P-type source region; the N-type source region is located on the side of the P-type well region away from the substrate, the P-type source region is located on both sides of the trench, and the trench penetrates the N-type source region and the P-type well region. The source electrode that is in contact with the N-type source region and the P-type source region; A P-type buried layer is located within the N-type withstand voltage layer and between the bottom of the trench and the substrate; the P-type buried layer is electrically connected to the source electrode, and there is a gap between the P-type buried layer and the bottom of the trench.

2. The MOSFET device of claim 1, wherein, The width of the P-type buried layer is equal to the width of the trench; Alternatively, the width of the P-type buried layer is smaller than the width of the trench; Alternatively, the width of the P-type buried layer is greater than the width of the trench.

3. The MOSFET device of claim 1, wherein, In a direction parallel to the plane of the substrate, there is a gap between the geometric center of the P-type buried layer and the geometric center of the bottom of the trench.

4. The MOSFET device of claim 1, wherein, The MOSFET device further includes: a P-type ground plane; The P-type grounding layer is in contact with the P-type buried layer and the P-type source region, respectively.

5. The MOSFET device of claim 1, wherein, The MOSFET device further includes: An N-type current diffusion region is located between the P-type well region and the P-type buried layer. The N-type current diffusion region has the same doping type as the N-type withstand voltage layer, and the doping concentration of the N-type current diffusion region is greater than or equal to the doping concentration of the N-type withstand voltage layer.

6. The MOSFET device of claim 5, wherein, The N-type current diffusion region at least partially encloses the P-type buried layer.

7. The MOSFET device of claim 5, wherein, The MOSFET device further includes: a P-type ground layer; the P-type ground layer is in contact with the P-type buried layer and the P-type source region respectively; The N-type current diffusion region is located between at least one sidewall of the trench and the P-type source region.

8. The MOSFET device of claim 5, wherein, The MOSFET device further includes: a P-type ground plane; The P-type grounding layer is in contact with the P-type buried layer and the P-type source region, respectively. The N-type current diffusion region is located on the side of the P-type ground layer away from the substrate.

9. The MOSFET device of claim 1, wherein, The surface of the P-type source region facing away from the substrate and the surface of the N-type source region facing away from the substrate are located in the same plane.

10. The MOSFET device of claim 1, wherein, The surface of the P-type source region facing away from the substrate is located between the first surface and the second surface; The first surface is the surface of the N-type source region facing away from the substrate, and the second surface is the surface of the P-type well region facing the substrate.

11. The MOSFET device of claim 1, wherein, The distance between the surface of the P-type source region facing away from the substrate and the substrate is less than the distance between the surface of the P-type well region facing the substrate and the substrate. The source electrode forms a Schottky contact with the sidewall of the exposed N-type current diffusion region.

12. The MOSFET device of claim 1, wherein, The P-type source region includes at least two sub-P-type source regions arranged at intervals in sequence along the length extension direction of the trench, and / or the P-type buried layer includes at least two sub-P-type buried layers arranged at intervals in sequence along the length extension direction of the trench.

13. The MOSFET device of claim 12, wherein, The shape of the sub-P-type source region is square, triangular, polygonal, or circular; the shape of the sub-P-type buried layer is square, triangular, polygonal, or circular.

14. The MOSFET device of claim 12, wherein, The MOSFET device further includes: a P-type ground plane; The sub-P-type buried layer is connected to at least one of the sub-P-type source regions via the P-type grounding layer.

15. The MOSFET device of claim 14, wherein, The P-type grounding layers located on both sides of the trench are arranged alternately or symmetrically.

16. The MOSFET device of claim 14, wherein, In the P-type grounding layers located on both sides of the trench, at least one sub-P-type source region is spaced between two adjacent P-type grounding layers in the length extension direction of the trench.

17. The MOSFET device of claim 14, wherein, The length extension direction of the P-type grounding layer intersects the length extension direction of the trench.

18. The MOSFET device of claim 1, wherein, Along the length extension direction of the trench, the N-type source region and the P-type source region are arranged alternately in sequence; Alternatively, the orthographic projection of the N-type source region on the substrate surrounds the orthographic projection of the P-type source region on the substrate.

19. The MOSFET device of claim 1, wherein, The P-type source region is in contact with the sidewall of the trench and the P-type buried layer.

20. The MOSFET device of claim 19, wherein, When the P-type source region includes at least two sequentially spaced sub-P-type source regions along the length extension direction of the trench, at least one of the sub-P-type source regions is in contact with the sidewall of the trench and the P-type buried layer.

21. The MOSFET device of claim 1, wherein, The length extension direction of the trench intersects with the length extension direction of the P-type buried layer.

22. The MOSFET device of any one of claims 1-21, wherein, The MOSFET device further includes: a P-type layer; One side of the P-type layer is located at the bottom of the channel, and the other side extends toward the side where the substrate is disposed, at least through the P-type buried layer.

23. A method of fabricating a MOSFET device, comprising: The method for fabricating the MOSFET device includes: Provide a substrate; An N-type pressure-resistant layer is formed on one side of the substrate; A P-type well region, a source region, and a P-type buried layer are formed within the N-type pressure-resistant layer; A trench gate is formed; the trench gate includes a trench and a gate located within the trench, with a gate dielectric layer between the gate and the trench; the source region includes an N-type source region and a P-type source region; the N-type source region is located on the side of the P-type well region away from the substrate, the P-type source regions are located on both sides of the trench, and the trench penetrates the N-type source region and the P-type well region; a P-type buried layer is located between the bottom of the trench and the substrate; and there is a gap between the P-type buried layer and the bottom of the trench; A source and a drain are formed; the drain is located on the side of the substrate away from the N-type withstand layer, the source is in contact with the N-type source region and the P-type source region, and the P-type buried layer is electrically connected to the source.

24. A layout arrangement of a MOSFET device, comprising: The layout structure of the MOSFET device includes: multiple MOSFET cells; The cross-sectional pattern of the MOSFET cells varies depending on their location.

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