Message Filtering Device and Communication Chip

Abstract

The present invention discloses a packet filter device and a communication chip. Among them, the packet filter device includes: a quick comparison module for comparing the current data packet according to the stored hit information; a hardware comparison module for comparing the current data packet according to the configured filtering rules; a processing module for directly processing the current data packet when it is determined by the comparison result of the quick comparison module that the current data packet is hit by the quick comparison module, and processing the current data packet according to the comparison result of the hardware comparison module when the current data packet is not hit by the quick comparison module, and updating the stored hit information according to the comparison result of the hardware comparison module. Since the quick comparison module in the device can cache the previous hit information, subsequent data packets belonging to the same data stream can pass quickly, improving the comparison speed, saving the comparison time, and thus improving the overall packet filtering speed of the packet filter device.

Description

Technical Field

[0001] The present invention relates to the technical field of mobile communications, and in particular, to a message filter device and a communication chip. Background Art

[0002] In mobile communications, message filters are widely used for data splitting and filtering. For example, filters defined on a BP / AP (Baseband Processor / Application Processor) for filtering TCP / IP (Transmission Control Protocol / Internet Protocol) applications are used to match received downlink IP packets; uplink TFT (Traffic Flow Template) filters defined in the 3GPP (3rd Generation Partnership Project) protocol are used to determine the QOS (Quality of Service) processing of uplink packets.

[0003] To meet the requirements of high-speed transmission rate and higher-level security in mobile communications, the hardware design of message filters has accordingly been proposed and applied to communication chips. The main filtering basis for message filtering is to filter data packets according to the IP headers of messages. Figure 1 FIG. is a schematic structural diagram of a filter in the related art. This filter adopts a fixed structure and uses a Mask to indicate whether to perform a comparison. For example, if the Mask corresponding to the SADDR (source address) is 0, the SADDR is not compared; otherwise, the SADDR is compared, and so on, thereby implementing the message filtering function.

[0004] Figure 2 For Figure 1 FIG. is a storage schematic diagram of the shown filter. As Figure 2 can be seen, since the structure of each filter is fixed, when filtering messages, only the fixed filter structure can be used to traverse from top to bottom to match a suitable filter, and accelerated matching cannot be performed. Especially when there are many filtering rules, the filtering speed is seriously affected. Summary of the Invention

[0005] The present invention aims to solve at least one of the technical problems in the related art to some extent. To this end, the first object of the present invention is to propose a packet filter device, which caches the previous hit information through a fast comparison module and uses the cached hit information to compare subsequent data packets, enabling subsequent data packets belonging to the same data stream to pass quickly, improving the comparison speed, saving comparison time, and thus improving the overall packet filtering speed of the packet filter device.

[0006] The second object of the present invention is to propose a communication chip.

[0007] To achieve the above object, an embodiment of the first aspect of the present invention proposes a packet filter device, including: a fast comparison module for comparing a current data packet according to stored hit information; a hardware comparison module for comparing the current data packet according to configured filtering rules; and a processing module for directly processing the current data packet when it is determined by the comparison result of the fast comparison module that the current data packet is hit by the fast comparison module, and processing the current data packet according to the comparison result of the hardware comparison module when the current data packet is not hit by the fast comparison module, and updating the stored hit information according to the comparison result of the hardware comparison module.

[0008] According to the packet filter device of the embodiment of the present invention, the previous hit information is cached through the fast comparison module, and the cached hit information is used to compare subsequent data packets, enabling subsequent data packets belonging to the same data stream to pass quickly, improving the comparison speed, saving comparison time, and thus improving the overall packet filtering speed of the packet filter device.

[0009] To achieve the above object, an embodiment of the second aspect of the present invention proposes a communication chip, including the foregoing packet filter device.

[0010] According to the communication chip of the embodiment of the present invention, through the foregoing packet filter device, the communication chip can obtain a higher packet filtering speed, thereby improving the communication speed of the communication chip, realizing the optimization and improvement of the communication chip.

[0011] Additional aspects and advantages of the present invention will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present invention. Description of the Drawings

[0012] Figure 1 It is a schematic structural diagram of a filter in the related art;

[0013] Figure 2 For Figure 1 A storage schematic diagram of the shown filter;

[0014] Figure 3 Schematic structural diagram of a packet filter device according to an embodiment of the present invention;

[0015] Figure 4 Schematic architecture diagram of a fast comparison module according to an embodiment of the present invention;

[0016] Figure 5 Schematic structural diagram of a packet filter device according to another embodiment of the present invention;

[0017] Figure 6 Schematic architecture diagram of a first filter unit according to an embodiment of the present invention;

[0018] Figure 7 Schematic architecture diagram of an IPV4HW filter according to an embodiment of the present invention;

[0019] Figure 8 Schematic architecture diagram of the bit mask configuration value of an IPV4HW filter according to an embodiment of the present invention;

[0020] Figure 9 Schematic header architecture diagram of an HF filter according to an embodiment of the present invention;

[0021] Figure 10 Schematic architecture diagram of the filtering rule area of an HF filter according to an embodiment of the present invention;

[0022] Figure 11 Schematic architecture diagram of the bitmap of an HF filter according to an embodiment of the present invention;

[0023] Figure 12 Schematic diagram of the storage of an HF filter on the RAM according to an embodiment of the present invention;

[0024] Figure 13 Schematic structural diagram of an IP packet according to an embodiment of the present invention;

[0025] Figure 14 Schematic structural diagram of the IP header of IPV4 according to an embodiment of the present invention;

[0026] Figure 15 Schematic structural diagram of a communication chip according to an embodiment of the present invention. Detailed implementation manners

[0027] The embodiments of the present invention will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present invention and should not be construed as limiting the present invention.

[0028] The packet filter device and communication chip proposed in the embodiments of the present invention will be described below with reference to the accompanying drawings.

[0029] Figure 3 As a structural schematic diagram of a packet filter device according to an embodiment of the present invention, refer to Figure 3 As shown, the packet filter device 100 includes: a quick comparison module 110, a hardware comparison module 120, and a processing module 130.

[0030] Among them, the quick comparison module 110 is used to compare the current data packet according to the stored hit information; the hardware comparison module 120 is used to compare the current data packet according to the configured filtering rules; the processing module 130 is used to directly process the current data packet when it is determined that the current data packet is hit by the quick comparison module 110 according to the comparison result of the quick comparison module 110, and process the current data packet according to the comparison result of the hardware comparison module 120 when the current data packet is not hit by the quick comparison module 110, and update the stored hit information according to the comparison result of the hardware comparison module 120.

[0031] Specifically, the processing module 130 is responsible for judging and sorting out the comparison result of the hardware comparison module 120, and feeding back the hit information to the quick comparison module 110. The quick comparison module 110 will store the previous hit information. When the next data packet enters the packet filter device 100, this module will query the previous hit information, so as to achieve quick comparison.

[0032] For example, when the first data packet is input, the hit information stored in the quick comparison module 110 is empty. At this time, the hardware comparison module 120 compares the first data packet according to the configured filtering rules. After the comparison is completed, the hardware comparison module 120 outputs the comparison result to the processing module 130. The processing module 130 processes and outputs the first data packet according to the comparison result to complete the filtering of the first data packet. At the same time, the processing module 130 determines the hit information of the first data packet and transmits it to the quick comparison module 110, and the quick comparison module 110 stores the hit information of the first data packet.

[0033] When the second data packet is input, the fast comparison module 110 and the hardware comparison module 120 compare the second data packet at the same time, wherein the fast comparison module 110 compares the second data packet based on the stored hit information. If the second data packet matches the stored hit information, it means that the second data packet and the first data packet belong to the same data stream. At this time, the fast comparison module 110 transmits the second data packet and the corresponding hit information to the processing module 130, and the processing module 130 directly processes the second data packet according to the processing method of the first data packet to complete the filtering of the second data packet; if the second data packet does not match the stored hit information, the hardware comparison module 120 outputs the comparison result to the processing module 130, and the processing module 130 processes and outputs the second data packet according to the comparison result to complete the filtering of the second data packet, and at the same time determines the hit information of the second data packet and feeds it back to the fast comparison module 110, and the fast comparison module 110 stores the hit information of the second data packet.

[0034] The filtering method for subsequent data packets is similar to that for completing the message filtering function.

[0035] It should be noted that since data packets of the same data stream will match the same filtering rule, and in high-speed traffic scenarios, two adjacent data packets usually belong to the same data stream. Therefore, when the previous data packet matches a certain filtering rule, the next data packet can be quickly matched based on the hit information cached by the fast comparison module 110. Compared with matching by traversing each hardware filtering rule, the matching time is greatly shortened, thereby effectively improving the filtering speed of the message, especially when there are many hardware filtering rules, the filtering speed can be significantly improved.

[0036] In the above embodiment, the previous hit information is cached by the fast comparison module, and the cached hit information is used to compare subsequent data packets, so that subsequent data packets belonging to the same data stream can pass quickly, reducing the amount of information to be compared, and improving the comparison speed, thereby improving the overall message filtering speed of the message filter device. Especially in high-speed traffic scenarios, the fast comparison module can improve the message filtering speed more significantly.

[0037] In some embodiments, the hit information may include the DSC-ID (Data Session Context ID) of the data packet, 5-tuple (five-tuple information) and Action (hit result), see Figure 4 As shown, the fast comparison module 110 can store the hit information in the form of a table, wherein the DSC-ID and 5-tuple are used to identify the data packet, and the Action corresponds to the processing method of the processing module 130 for the data packet.

[0038] When a data packet is input, the fast comparison module 110 compares it with the stored hit information. For example, it compares whether the DSC-ID and 5-tuple of the current data packet are the same as a certain piece of stored hit information. If they are the same, it means that the current data packet and the data packet corresponding to this piece of hit information belong to the same data stream. The fast comparison module 110 sends the current data packet and the Action in this piece of hit information to the processing module 130 together. The processing module 130 processes the current data packet directly according to the Action, which can greatly save the comparison time of the filter device and improve the data bandwidth.

[0039] It should be noted that Figure 4 The shown table can be dynamically updated. Specifically, an update rule similar to the LRU (Least Recently Used) algorithm can be adopted for dynamic update. For example, when the fast comparison module 110 compares the current data packet, if the DSC-ID and 5-tuple of the current data packet are the same as a certain piece of stored hit information, only the hit information in the table is aged, and the specific content of the hit information in the table is not changed; if the DSC-ID and 5-tuple of the current data packet are not the same as all the stored hit information, then the hardware comparison module 120 compares the current data packet based on the configured filtering rules and outputs the comparison result to the processing module 130. The processing module 130 processes and outputs according to the comparison result, determines the hit information of the data packet at the same time, and feeds back the hit information to the fast comparison module 110. The fast comparison module 110 replaces the hit information with the highest aging degree in the table with the current hit information.

[0040] In addition, Figure 4 The specification size and quantity of the shown table can be set according to the actual situation. Among them, when the number of tables is greater than 1, multi-table simultaneous comparison can be performed. For example, when the number of tables is 4, the current data packet can be compared with the hit information in 4 tables at the same time, which can further improve the comparison speed. It can be understood that when each table corresponds to a fast comparison module 110, the number of fast comparison modules 110 can be set according to the actual situation.

[0041] In the above embodiment, the previous hit information is stored in the form of a table. When subsequent data packets are input, by querying the hit information in the table and comparing it with the data packets, fast comparison of the data packets can be realized, saving the comparison time of the data packets of the same data stream, thereby effectively improving the overall packet filtering speed of the packet filter device; at the same time, multiple tables can be set to achieve synchronous comparison of multiple tables, which can further improve the comparison speed and the overall packet filtering speed.

[0042] In some embodiments, referring to Figure 5 As shown, the hardware comparison module 120 includes a first filter unit 121 and / or a second filter unit 122. That is to say, the hardware comparison module 120 may include the first filter unit 121, or the second filter unit 122, or both the first filter unit 121 and the second filter unit 122. Among them, the first filter unit 121 adopts a register configuration for filtering rules, and the second filter unit 122 adopts a memory configuration for filtering rules.

[0043] Furthermore, the comparison speed of the first filter unit 121 is less than the comparison speed of the fast comparison module 110, and the comparison speed of the first filter unit 121 is greater than the comparison speed of the second filter unit 122.

[0044] Specifically, the first filter unit 121 is a filter unit directly implemented by registers. The software can directly write the configured filtering rules into the first filter unit 121 through registers. The second filter unit 122 is a filter unit directly implemented by a memory. The filtering rules are directly stored in the memory. For example, it is a filter unit implemented by RAM (Random Access Memory) or DDR (Double Data Rate SDRAM). The filtering rules are directly stored in the RAM or DDR.

[0045] Since the first filter unit 121 is implemented by registers, it is not only convenient for hardware design implementation, but also beneficial for software configuration, facilitating subsequent changes to the filtering rules, with high convenience and flexibility. At the same time, compared with the memory, registers have the characteristic of fast read and write speeds. Therefore, the first filter unit 121 has a faster comparison speed than the second filter unit 122. However, compared with the memory, registers have a smaller data capacity. Therefore, common filtering rules can be configured in the first filter unit 121 to ensure a faster comparison speed; a large number of filtering rules are stored in the second filter unit 122. For example, when there are many filtering rules, a part of the filtering rules can be stored in the RAM, and another part of the filtering rules can be stored in the DDR to meet the application requirements of packet filtering using more filtering rules.

[0046] In addition, the fast comparison module 110 compares the current data packet based on the stored hit information. Compared with the first filter unit 121, the comparison time can be reduced to a certain extent. For example, when the hit information includes the DSC-ID, 5-tuple, and Action of the data packet, the fast comparison module 110 only compares the DSC-ID and 5-tuple of the data packet, without traversing all the filtering rules to compare the entire data packet, effectively reducing the amount of information to be compared. Therefore, the comparison speed of the fast comparison module 110 is higher than that of the first filter unit 121 and also higher than that of the second filter unit 122.

[0047] It should be noted that in practical applications, one or two of the first filter unit 121 and the second filter unit 122 can be selected according to the data packets to be filtered to cooperate with the fast comparison module 110 for data packet filtering. After one of the comparison methods completes the comparison first, the other comparison methods stop comparing, thus realizing a combination of comparison methods with multiple speed levels, enabling the packet filter device 100 to have the advantages of each comparison method and improving the overall comparison speed.

[0048] In the above embodiments, by dividing the hardware comparison module into filter units with different speeds and cooperating with the fast comparison module with a faster comparison speed, a combination of comparison methods with multiple speed levels is realized. While meeting the packet filtering requirements, the comparison speed can be further improved, thereby improving the filtering speed and flexibility of the packet filter device.

[0049] In some embodiments, the first filter unit 121 includes an IPV4HW filter and an IPV6HW filter.

[0050] That is to say, the first filter unit 121 configures the filtering rules for two Internet protocols, IPV4 (Internet Protocol version 4) and IPV6 (Internet Protocol version 6), using registers. That is, the first filter unit 121 supports the comparison of data packets of both IPV4 and IPV6 Internet protocols simultaneously to improve the applicability of the first filter unit 121. Of course, the filtering rules of other protocols can also be configured using registers to meet the actual application requirements, making the first filter unit 121 highly flexible.

[0051] As a specific example, refer to Figure 6As shown, the first filter unit 121 can support 16 IPV4HW filters (IPV4_HW_Fiter1, IPV4_HW_Fiter2, …, IPV4_HW_Fiter16 respectively) and 16 IPV6HW filters (IPV6_HW_Fiter1, IPV6_HW_Fiter2, …, IPV6_HW_Fiter16 respectively). Further, the structure of the IPV4HW filter is as Figure 7 shown, with a total of 128 bits. Among them, 8 bits are used to store the DSC-ID; 8 bits are used to store the Action and Action code (the code corresponding to the hit result); 8 bits are used to store the bitmask configuration value bitmask; the remaining 104 bits are used to store the 5-tuple, where 32 bits are used to store the source address under the IPv4 protocol, 32 bits are used to store the destination address under the IPV4 protocol, 16 bits are used to store the Source port, 16 bits are used to store the Destination port, and 8 bits are used to store the Protocol type. Since the size of the IPV4HW filter is 128 bytes, 4 registers are required to implement it.

[0052] It should be noted that the structure of the IPV6HW filter is similar to that of the IPV4HW filter and will not be elaborated here. Both filters can support the comparison of broadcast or multicast packets and also support the comparison of special packets. For example, a Multicast address value or Broadcast address value can be written in the 32-bit source address storage area as Figure 7 shown, while a corresponding Multicast address mask or Broadcast address mask is written in the 32-bit destination address storage area to implement the comparison of corresponding packets with broadcast and multicast functions. Additionally, in actual use, the specifications and quantities of the IPV4HW filter and IPV6HW filter can be flexibly set according to actual requirements.

[0053] In the above embodiment, by configuring the IPV4HW filter and IPV6HW filter in the first filter unit, the first filter unit can support the IPV4 and IPV6 protocols and also support the broadcast and multicast functions, thus enhancing the applicability of the first filter unit. Of course, the filtering rules of other protocols can also be configured through registers, improving the flexibility of the first filter unit.

[0054] Further, the first filter unit 121 is further configured to compare whether the current data packet meets the corresponding filtering rule according to the bitmask configuration value. That is, the comparison of the data packet is selected by the bitmask configuration value bitmask, and the hardware compares whether the current data packet meets the filtering rule of the first filter unit 121 according to the bitmask configuration value bitmask.

[0055] Specifically, Figure 7 taking the bitmask configuration value bitmask of the IPV4HW filter shown as an example for illustration, the specific structure is as Figure 8 shown. This bitmask configuration value bitmask is used to select whether the IPV4HW filter uses the corresponding field to compare the current data packet. Among them, bits 0 to 4 correspond to quintuple information, bits 5 and 6 correspond to Multicast address mask and Broadcast address mask information respectively, and bit 7 is a reserved bit. The filtering rule of the current IPV4HW filter can be determined through the 8-bit bitmask configuration value bitmask for subsequent comparison. For example, when bits 0 to 4 of the bitmask configuration value bitmask are all valid, it can be determined that the filtering rule of the current IPV4HW filter is to compare the quintuple information of the current data packet. If the quintuple information of the current data packet is the same as that of the current IPV4HW filter, it means that the current data packet passes through the current IPV4HW filter. At this time, the processing module 130 processes the current data packet according to the Action of the current IPV4HW filter to complete the filtering of the data packet. It should be noted that the working principle of the IPV6HW filter is similar to that of the IPV4HW filter and will not be elaborated here.

[0056] Thus, by selecting the filtering rule based on the bitmask configuration value and the hardware comparing whether the current data packet meets the filtering rule of the first filter unit according to the bitmask configuration value, the comparison function of the first filter unit for the data packet is realized. And since the first filter unit is implemented by registers, the fast comparison and filtering of the data packet can be achieved.

[0057] In some embodiments, as shown in Figure 5 the second filter unit 122 includes an HF filter, and the size of the filtering rule of the HF filter is determined according to the configured bitmap. Further, the second filter unit 122 is further configured to compare whether the current data packet meets the corresponding filtering rule according to the configured bitmap.

[0058] Specifically, the HF filter mainly consists of a header and a filtering rule area. As Figure 9As shown, the header size can be fixed at 128 bits (each row represents 8 bits). The header is used to store general information of filters such as Action, DSC-ID, Length, as well as the bitmap Bitmap and its corresponding offset value OFFSET (from TOS_TC to OFFSET_32). TOS_TC in the offset value OFFSET is protocol information, such as IPV4 and IPV6, which is directly stored in the header. Offset values such as OMV_128_0 and OMV_128_1 are 8-bit binary numbers. The value represents the offset starting from the header of the current data packet (such as the IP header) when comparing the current data packet. The 128 in the name indicates that a 128-bit field needs to be intercepted from the header of the data packet for comparison when making the comparison. The architecture of the filtering rule area is as Figure 10 shown. In the filtering rule area, there are corresponding MASK and VALUE values for the filtering rules. When comparing, the MASK and VALUE values of the filtering rules are used to compare with the intercepted part of the data packet. The architecture of the bitmap Bitmap is as Figure 11 shown. Bits 0 to 10 in the bitmap Bitmap correspond to the offset value OFFSET in the header, and the remaining bits are reserved. Which bit in the bitmap Bitmap is valid indicates that the HF filter has this filtering rule, that is, the specific comparison of the second filter unit 122 is carried out according to the configuration of the bitmap Bitmap.

[0059] It should be noted that the size of the filtering rule area is variable according to the configuration size of the bitmap Bitmap. For example, if only bits 0 and 1 are valid in the bitmap Bitmap, then the size of the filtering rule area is 0 bits, and the filter only has a header with a size of 128 bits; if only bit 4 is valid in the bitmap Bitmap, then the size of the filtering rule area is 128 bits, and the filter size is 256 bits. Figure 12 This is a schematic diagram of the storage of the above HF filter in the memory. The data bit width of this memory is 128 bits. When storing, the header of a single HF filter is a fixed size of 128 bits. Therefore, the header of a single HF filter occupies one row, while the size of the filtering rule area is not fixed and varies according to the configuration size of the bitmap Bitmap. When a new filtering rule needs to be added, the filtering rule can be added to the bitmap Bitmap, and at the same time, the MASK and VALUE values of the filtering rule are added to the filtering rule area. Compared with filters with fixed bit numbers, it has good flexibility and can effectively avoid the waste of storage space caused by fixed bit numbers, saving the chip area overhead.

[0060] Next, taking Figure 13 the shown packet structure and the filtering rule OMV_32_0 as an example, the comparison mechanism of the second filter unit 122 will be described. Assume that the header of a data packet with the IPV4 protocol is as Figure 13As shown, when comparing the current data packet through the second filter unit 122, first obtain the bitmap of the HF filter. If the 4th bit of the bitmap is valid, that is, the filtering rule HF_RULE_OMV_32_0 is valid, it indicates that this filter unit needs to compare OMV_32_0. At this time, first obtain the value of OMV_32_0 from the Figure 9 header shown. This value represents the offset value from the header of the data packet, that is, Figure 14 the position of the arrow in. Then, according to this value, intercept 32 bits of the header from the input data packet (denoted as Packet_Omv_32), and compare these 32 bits with Figure 10 OMV_32_0_MASK and OMV_32_0_VALUE in the filtering rule area shown. Specifically, it can be determined whether the formula (Packet_Omv_32&OMV_32_0_MASK)^(OMV_32_0_VALUE&OMV_32_0_MASK) == 32’b0 holds. Here, & represents the logical AND operation, and ^ represents the logical exclusive OR operation. If it holds, it means the comparison passes; otherwise, it means the comparison fails. Thus, it can intercept any position from the header of the data packet according to the offset value OFFSET and compare it with the filtering rule, improving the flexibility of filtering.

[0061] In the above embodiment, based on the offset value, it is possible to intercept any position from the header of the data packet and compare it with the filtering rule, having high comparison flexibility, scalability, and compatibility. For example, when the filtering rule changes, based on the offset value, it is possible to implement the comparison of the new filtering rule, with good flexibility, scalability, and strong compatibility. At the same time, the size of the filtering rule is variable, making the filter unit have good flexibility and scalability, and the area will also change according to the configuration of the filtering rule, effectively saving the area overhead.

[0062] In some embodiments, referring to Figure 5 shown, the packet filter device 100 further includes a configuration module 140 for configuring the filtering rule of the first filter unit 121 and writing the configured filtering rule through a register.

[0063] That is to say, the configuration module 140 can pre-write the filtering rule into the first filter unit 121 through a register to configure the filtering rule of the first filter unit 121, and can update the filtering rule of the first filter unit 121 to meet different packet filtering requirements, improving the flexibility of the packet filter device.

[0064] In some embodiments, continue to refer to Figure 5As shown in the figure, the message filter device 100 further includes a control module 150 for controlling the activation or deactivation of the fast comparison module 110, the first filter unit 121, and the second filter unit 122. Further, the control function of the control module 150 for the fast comparison module 110, the first filter unit 121, and the second filter unit 122 is pre-configured by a configuration module 140.

[0065] That is to say, the control module 150 can be pre-configured by the configuration module 140 to achieve the activation or deactivation control of the fast comparison module 110, the first filter unit 121, and the second filter unit 122, thereby realizing the state transition and overall control of the entire filter device, achieving flexible configuration of the message filter device 100, and meeting different message filtering requirements. For example, when filtering messages of the same IP data stream, the fast comparison module 110 can be activated to achieve fast filtering. Thus, flexible adjustment of the three comparison methods is realized, further improving the flexibility of the message filter device 100.

[0066] In summary, for the message filter device according to the embodiment of the present invention, the fast comparison module caches the hit information and compares the data packets based on the hit information, enabling subsequent data packets belonging to the same data stream to pass quickly, reducing the comparison time of data packets of the same data stream, and improving the comparison speed; by using the first filter unit that configures the filtering rules with registers and using the bit mask configuration value to implement the selection of filtering rules, the comparison speed and flexibility of the data packets are improved, and it is convenient to use; by using the second filter unit that configures the filtering rules with a memory and obtaining any position from the data packet for comparison through an offset value, and by using a bitmap for the selection of filtering rules, the message filter device has high flexibility, scalability, and compatibility, and at the same time, the chip area can be saved. Through the organic combination of the above three modules, the comparison speed, usability, and scalability of the message filter device are effectively improved, the overall performance is improved, and at the same time, the above three modules can be effectively managed based on the configuration module, so that the message filter device is well optimized and improved in terms of comparison speed, flexibility, scalability, and area overhead.

[0067] An embodiment of the present invention further provides a communication chip.

[0068] Refer to Figure 15 As shown in the figure, the communication chip 1000 includes the aforementioned message filter device 100.

[0069] For the communication chip according to the embodiment of the present invention, through the aforementioned message filter device, the communication chip can obtain a higher message filtering speed, thereby improving the communication speed of the communication chip, realizing the optimization and improvement of the communication chip.

[0070] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples.

[0071] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present invention, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise specifically and clearly defined.

[0072] In the present invention, unless otherwise clearly specified and limited, terms such as "mounted", "connected", "coupled", "fixed", etc. shall be construed in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements, unless otherwise clearly limited. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0073] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. A message filter device, characterized in that, Comprising: A quick comparison module, configured to compare a current data packet according to stored hit information. Wherein, if the current data packet and the data packet corresponding to the hit information belong to the same data stream, it is determined that the current data packet matches the hit information, and the hit information corresponds to the data packet before the current data packet; A hardware comparison module, configured to compare the current data packet according to configured filtering rules. The hardware comparison module includes a first filter unit and a second filter unit. Wherein, the first filter unit configures the filtering rules using registers, and the second filter unit configures the filtering rules using a memory. The second filter unit includes an HF filter, and the size of the filtering rules of the HF filter is determined according to a configured bitmap; A processing module, configured to, when it is determined that the current data packet is hit by the quick comparison module according to the comparison result of the quick comparison module, directly filter the current data packet using the filtering rules matched by the data stream corresponding to the hit information matched by the current data packet, and when the current data packet is not hit by the quick comparison module, filter the current data packet according to the comparison result of the hardware comparison module, and update the stored hit information according to the comparison result of the hardware comparison module. Wherein, the current data packet being hit by the quick comparison module means that the current data packet matches the hit information.

2. The message filter device according to claim 1, characterized in that The comparison speed of the first filter unit is less than the comparison speed of the quick comparison module, and the comparison speed of the first filter unit is greater than the comparison speed of the second filter unit.

3. The message filter device according to claim 1, wherein The first filter unit includes an IPV4HW filter and an IPV6 HW filter.

4. The message filter device according to claim 1, characterized in that The first filter unit is further configured to compare whether the current data packet meets the corresponding filtering rules according to a bit mask configuration value.

5. The message filter device according to claim 1, wherein The second filter unit is further configured to compare whether the current data packet meets the corresponding filtering rules according to a configured bitmap.

6. The message filter device according to claim 1, characterized in that It further includes a configuration module, configured to configure the filtering rules of the first filter unit and write the configured filtering rules through the register.

7. The message filter device according to claim 6, characterized in that It further includes a control module, configured to control the on or off of the quick comparison module, the first filter unit, and the second filter unit.

8. The message filter device according to claim 7, characterized in that, The control function of the control module for the quick comparison module, the first filter unit, and the second filter unit is pre-configured by the configuration module.

9. A communication chip, characterized in that, Comprising the message filter device according to any one of claims 1-8.

Images