Low-offset differential charge transfer amplifier for quantum image sensor applications

Abstract

The present invention relates to the technical field of quantum image sensors. In order to propose a low-offset differential charge transfer amplifier circuit structure, the weak photoelectron signal of QIS is accurately amplified with high gain to improve the consistency of the comparator threshold voltage and reduce the bit error rate of photon counting. To this end, the technical solution adopted by the present invention is a low-offset differential charge transfer amplifier based on the application of quantum image sensors, including a differential charge transfer amplifier DCTA, a differential symmetric input module and an offset storage compensation module, a differential symmetric input module is added to the input end of DCTA, and an offset storage compensation module is added to the output end of DCTA. The present invention is mainly used in the design and manufacture of quantum image sensors.

Description

Technical Field

[0001] The invention relates to the technical field of quantum image sensors, and in particular to a low-offset differential charge transfer amplifier applied to a quantum image sensor for amplifying weak photoelectron signals. Background Art

[0002] As the feature size of IC process becomes smaller and smaller, pixels with deep sub-diffraction limit scale will appear. The small exposure area and full well capacity of pixels will significantly reduce the performance of traditional CMOS image sensors. To solve this problem, quantum image sensors (QIS) are proposed. QIS has billions of tiny pixel units with high conversion gain, small spacing, low readout noise, and the characteristics of temporal and spatial oversampling. It is widely used in aerospace, medical imaging, low-light imaging and other fields. Since each pixel unit jot of QIS has a small area and a short exposure time, the number of photons incident on a single jot is extremely small, which makes the QIS quantization signal very small. The weak signal makes QIS very sensitive to the offset of the subsequent circuit. Therefore, a pre-amplification circuit is required before the comparator to reduce the intrinsic offset of the comparator. Differential charge transfer amplifier (DCTA) has the advantages of simple structure, low power consumption and low noise. It is used in the QIS readout circuit, which can not only solve the high static power consumption problem of continuous time amplifier, but also the high gain amplification after cascading can greatly reduce the intrinsic offset of the subsequent comparator circuit. Although the cascaded high-gain DCTA can effectively suppress the misalignment of the subsequent circuit, its own misalignment has not been well resolved. Figure 1 As shown, it mainly consists of NMOS tubes (MN1~MN4) and PMOS tubes (MP1~MP4), switches (S1, S2), and transfer capacitors (C T1 , C T2 )、Input coupling capacitor (C i1 , C i2 ), load capacitance (C O1 , C O2 ) composition. Due to switch charge injection, MOS tube process deviation and other reasons, especially because the positive input and negative input of DCTA are not symmetrical with the common mode voltage, the DCTA circuit has obvious inherent offset. This obvious offset will not only produce column-level fixed pattern noise, but also cause deviation in the set comparator threshold voltage, thereby greatly increasing the photon counting bit error rate of QIS. In view of the problem that the DCTA's own offset will affect the photon counting accuracy, the present invention proposes a DCTA circuit structure with differential symmetrical input and offset storage compensation function to reduce the inherent offset and suppress the readout noise. Summary of the invention

[0003] In order to overcome the shortcomings of the prior art, the present invention aims to propose a low-offset differential charge transfer amplifier circuit structure, which can accurately amplify the weak photoelectron signal of QIS with high gain to improve the consistency of the comparator threshold voltage and reduce the bit error rate of photon counting. To this end, the technical solution adopted by the present invention is a low-offset differential charge transfer amplifier based on the application of quantum image sensor, including a differential charge transfer amplifier DCTA, a differential symmetric input module and an offset storage compensation module, a differential symmetric input module is added to the input end of DCTA, and an offset storage compensation module is added to the output end of DCTA.

[0004] The detailed structure is as follows:

[0005] It consists of NMOS tubes MN1~MN4, PMOS tubes MP1~MP4, switches S0~S2, S c , S m , S n , transfer capacitor C T1 , C T2 , input coupling capacitor C i1 , C i2 and load capacitance C O1 , C O2 Composition; pixel reset signal V rst and pixel output signal V sig All through the switch S c The input coupling capacitors C i1 , C i2 The left plate is connected to the i1 and C i2 The left plates of MN1 and MP1 are connected together through switch S0; the gate terminals of MN1 and MP1 are connected, and the gate terminals of MN2 and MP2 are connected, and are connected to C i1 , C i2 The right plate is connected to the i1 and C i2 The right plate of the pre The source terminals of MN1 and MP1 are connected to the transmission capacitor C through switch S'1. T1 , C T2 The source terminals of MN2 and MP2 are also connected to the transmission capacitor C through switch S'1. T1 , C T2 The lower plate of the switch S'1 is a pair of complementary switches; the source terminals of MP3 and MP4 are connected to the power supply voltage VDD, and the gate and drain of the two tubes are first short-circuited and then connected to C through the switch S1. T1 The upper plate, C T2The source terminals of MN3 and MN4 are connected to GND, and the gate and drain of the two tubes are short-circuited and then connected to C through switch S1. T2 The upper plate, C T1 The lower plate; MN1 is connected to the drain end of MP1, and MN2 is connected to the drain end of MP2, and both are connected to the precharge voltage V through the switch S2. pre connected together; the drains of MN1 and MP1 are connected through switch S n Connected to the load capacitor C O1 The upper plate of the switch S m Connected to the load capacitor C O2 The drain terminals of MN2 and MP2 are connected through switch S n Connected to the load capacitor C O2 The upper plate of the switch S m Connected to the load capacitor C O1 The upper plate; C O1 and C O2 The lower plates of the switches (S0, S c ) and the input coupling capacitor (C i1 , C i2 ) forms a differential symmetrical input module, the switch (S m , S n ) and load capacitance (C O1 , C O2 ) constitutes an offset storage compensation module.

[0006] The 4-stage DCTA cascade circuit structure is as follows: the gate terminals of MN1 and MP1, and the gate terminals of MN2 and MP2 in the first stage DCTA are connected to the C i1 , C i2 The right pole plate is connected; the gate terminals of MN1 and MP1 in the second-stage DCTA, and the gate terminals of MN2 and MP2 are connected to the drain terminals of MN1 and MP1 in the first-stage DCTA, and the drain terminals of MN2 and MP2 respectively; the gate terminals of MN1 and MP1 in the third-stage DCTA, and the gate terminals of MN2 and MP2 are connected to the drain terminals of MN1 and MP1 in the second-stage DCTA, and the drain terminals of MN2 and MP2 respectively; the gate terminals of MN1 and MP1 in the fourth-stage DCTA, and the gate terminals of MN2 and MP2 are connected to the drain terminals of MN1 and MP1 in the third-stage DCTA, and the drain terminals of MN2 and MP2 respectively; in addition, the output terminals of the first, second, and third-stage DCTAs are all connected to a pair of load capacitors (C O1 , C O2 ), the drain terminals of MN1 and MP1 in the fourth-stage DCTA are connected through the switch S in the offset storage compensation module n Connected to the load capacitor C O1 The upper plate is connected to the load capacitor C through the switch Sm. O2The drain terminals of MN2 and MP2 are connected through the switch S in the offset storage compensation module. n Connected to the load capacitor C O2 The upper plate of the switch S m Connected to the load capacitor C O1 The upper plate.

[0007] The characteristics and beneficial effects of the present invention are:

[0008] The 4-stage cascade differential charge transfer amplifier circuit structure of the present invention has the functions of differential symmetrical input at the input end and offset storage cancellation at the output end. Compared with the traditional cascade DCTA circuit, the proposed circuit structure has the characteristics of lower switch charge injection offset and MOS tube process deviation offset. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Schematic diagram of the traditional DCTA circuit structure.

[0010] Figure 2 Schematic diagram of the new low-offset 1-stage DCTA circuit structure.

[0011] Figure 3 Schematic diagram of the simplified circuit structure of the new low-offset 4-level DCTA cascade.

[0012] Figure 4 Detailed circuit diagram of the new low-offset 4-stage DCTA cascade.

[0013] Figure 5 Timing diagram of the new low-offset DCTA circuit.

[0014] Figure 6 Schematic diagram of the storage compensation process of the output offset of the new DCTA circuit. DETAILED DESCRIPTION

[0015] The present invention proposes a differential charge transfer amplifier structure with differential symmetrical input and offset storage cancellation function, aiming to store and cancel the output offset of the DCTA output end. The principle is that the DCTA's own offset is first stored in one cycle, and then mostly offset in the next cycle, thereby reducing the fixed pattern noise of the column-level DCTA circuit, thereby suppressing the readout noise of the QIS and reducing the bit error rate of photon counting.

[0016] In order to achieve the above object, the present invention adopts the following technical solution:

[0017] The low offset differential charge transfer amplifier for QIS application is optimized based on the traditional DCTA structure for its input and output. For the new low offset 1-stage DCTA circuit structure, such as Figure 2As shown, it consists of NMOS (MN1 ~ MN4) and PMOS (MP1 ~ MP4), switches (S0 ~ S2, S c , S m , S n ), transfer capacitor (C T1 , C T2 )、Input coupling capacitor (C i1 , C i2 ) and load capacitance (C O1 , C O2 ) is composed of. Pixel reset signal V rst and pixel output signal V sig All through the switch S c The input coupling capacitors C i1 , C i2 The left plate is connected to the i1 and C i2 The left plates of MN1 and MP1 are connected together through switch S0. The gate terminals of MN1 and MP1 are connected, and the gate terminals of MN2 and MP2 are connected, and are connected to C i1 , C i2 The right plate is connected to the i1 and C i2 The right plate of the pre The source terminals of MN1 and MP1 are connected to the transfer capacitor C through switch S'1. T1 , C T2 The source terminals of MN2 and MP2 are also connected to the transmission capacitor C through switch S'1. T1 , C T2 The switch S'1 and switch S1 are a pair of complementary switches. The source terminals of MP3 and MP4 are connected to the power supply voltage VDD, and the gate and drain of the two tubes are first short-circuited and then connected to C through switch S1. T1 The upper plate, C T2 The source terminals of MN3 and MN4 are connected to GND, and the gate and drain of the two tubes are short-circuited and then connected to C through switch S1. T2 The upper plate, C T1 The drain terminals of MN1 and MP1 are connected, and the drain terminals of MN2 and MP2 are connected, and both are connected to the precharge voltage V through switch S2. pre In addition, the drain terminals of MN1 and MP1 are connected together through switch S n Connected to the load capacitor C O1 The upper plate of the switch S m Connected to the load capacitor C O2 The drain terminals of MN2 and MP2 are connected through switch S n Connected to the load capacitor C O2The upper plate of the switch S m Connected to the load capacitor C O1 The upper plate. O1 and C O2 The lower plates of the switches (S0, S c ) and the input coupling capacitor (C i1 , C i2 ) forms a differential symmetrical input module, the switch (S m , S n ) and load capacitance (C O1 , C O2 ) constitutes an offset storage compensation module.

[0018] The photoelectron signal quantized by QIS is extremely small, and a 4-stage DCTA cascade is usually used to achieve a gain of several hundred times. On the one hand, it amplifies the pixel jump signal, and on the other hand, it greatly reduces the intrinsic offset of the subsequent comparator. In theory, four new low-offset 1-stage DCTA structures can be cascaded to minimize the offset, but this will increase the complexity of the circuit and the area of ​​the layout. To address this problem, the new low-offset 4-stage DCTA circuit cascade in the present invention only adds a differential symmetrical input module to the input end of the first stage, and adds an offset storage compensation module to the output end of the fourth stage. The second and third stages still use the traditional DCTA structure. The simplified schematic diagram is shown in FIG. Figure 3 In this way, the total internal offset at the output can still be effectively suppressed, greatly reducing the offset while also simplifying the circuit structure.

[0019] For the detailed low offset 4-stage DCTA cascade circuit structure, such as Figure 4 As shown, the gate terminals of MN1 and MP1, and the gate terminals of MN2 and MP2 in the first-stage DCTA are connected to C in the differential symmetrical input module. i1 , C i2 The right pole plate is connected; the gate terminals of MN1 and MP1 in the second-stage DCTA, and the gate terminals of MN2 and MP2 are connected to the drain terminals of MN1 and MP1 in the first-stage DCTA, and the drain terminals of MN2 and MP2; the gate terminals of MN1 and MP1 in the third-stage DCTA, and the gate terminals of MN2 and MP2 are connected to the drain terminals of MN1 and MP1 in the second-stage DCTA, and the drain terminals of MN2 and MP2; the gate terminals of MN1 and MP1 in the fourth-stage DCTA, and the gate terminals of MN2 and MP2 are connected to the drain terminals of MN1 and MP1 in the third-stage DCTA, and the drain terminals of MN2 and MP2. In addition, the output terminals of the first, second, and third-stage DCTAs are all connected to a pair of load capacitors (C O1 , C O2 ), the drain terminals of MN1 and MP1 in the fourth-stage DCTA are connected through the switch S in the offset storage compensation module n Connected to the load capacitor CO1 The upper plate of the switch S m Connected to the load capacitor C O2 The drain terminals of MN2 and MP2 are connected through the switch S in the offset storage compensation module. n Connected to the load capacitor C O2 The upper plate of the switch S m Connected to the load capacitor C O1 The upper plate.

[0020] For the new low offset 1-level DCTA structure and 4-level cascade DCTA structure, their timing is the same. It takes two cycles (i.e., offset storage cycle and offset compensation cycle) to realize the amplification function of a pixel jump signal. Each cycle has three stages, and its timing diagram is as follows Figure 5 shown.

[0021] The function of the offset storage cycle is as follows:

[0022] The first stage t1-t2: switch S c , S1, S2, S m Connect, S0, S n Disconnected, DCTA is in reset state. V rst Stored in C i1 The left plate, V sig Stored in C i2 The left plate, while C i1 and C i2 The right plate and C O1 and C O2 The upper plates are charged to V pre In addition, the four diodes MN3 / MN4 and MP3 / MP4 are all in the saturation region. When reset, they can turn C T1 The upper plate is charged to a voltage slightly greater than V pre +|V TP |, the lower plate is charged to a value slightly less than V pre -|V TN |, C T2 The lower plate is charged to a voltage slightly greater than V pre +|V TP |, the upper plate is charged to a value slightly less than V pre -|V TN |, where V TP and V TN They are the threshold voltages of the PMOS tube (MP1 / MP2) and the NMOS tube (MN1 / MN2) respectively.

[0023] The second stage t2-t3: S1, S0, S n Disconnect, S c , S m, S2 is turned on, and DCTA is in the pre-charge state. Due to the role of the four saturated diodes in the reset state mentioned above, the |V GS |Slightly larger than |V TN |, PMOS tube MP1 ~ MP2 |V GS |Slightly larger than |V TP |, thereby speeding up the pre-charging speed while avoiding the peak current and reducing the power consumption caused by large peak current.

[0024] The third stage t3-t4: S1, S2, S0, S n Disconnect, S c , S m In an ideal state, the positive and negative input terminals of DCTA do not jump, but in fact, the disconnection of switch S2 will cause charge injection. At the input terminal, the small offset voltage generated by the charge injection and the partial offset voltage generated by the threshold deviation of the MOS tube will be amplified and finally cross-stored in C O2 and C O1 The output offset of the upper plate, i.e. the positive terminal, is stored in the negative terminal capacitor C O2 The negative output offset is stored in the positive capacitor C O1 Since the output of the DCTA circuit is V pre The positive and negative outputs are symmetrical, so the output offset is also V pre Therefore, at t4, C O2 and C O1 The upper plate voltages are:

[0025] V o2 =V′ 输出失调

[0026] V o1 = -V′ 输出失调

[0027] The function of the offset cancellation cycle is as follows:

[0028] The first stage t4-t5: switch S c , S1, S2 are connected, S0, S n , S m The first and second stages of the offset storage cycle are similar in function to the first and second stages. The only difference is that C O2 and C O1 Not charging to V pre , but rather maintains the stored offset voltage.

[0029] Stage 3 t6-t8: S n Connect, S0 is connected first and then disconnected, S c , S1, S2, S m When S0 is turned on, C i1 and C i2 The left plate charge is averaged, and the averaged C i1 and C i2 The voltage jumps of the left plate are:

[0030]

[0031]

[0032] From the above formula, we can see that due to C i1 and C i2 The absolute value of the voltage jump on the right plate is the same, so the differential input of the DCTA circuit is along the common-mode voltage V pre At this time, the pixel differential input jump, charge injection offset, and process deviation offset at the DCTA input are all in the amplification state. m Disconnect, S n When turned on, the amplified output voltage is no longer cross-stored, but the positive output is stored in the positive capacitor C O1 The negative output is stored in the negative capacitor C O2 In the previous offset storage stage, because the output end of DCTA cross-stores the output offset voltage before the input jump, the output voltage of DCTA at this time is composed of three parts: the output offset stored before the input jump, the output offset after the jump, and the amplified input jump signal.

[0033] After S0 is turned on, there will be C O1 and C O2 The charge on the left plate causes the average plate voltage to deviate from the ideal value, so the timing of S0 needs to be optimized. At t7, S0 is disconnected. Under the influence of the switch charge injection, the residual charge in the channel is released again, so that the plate voltage quickly returns to the ideal value. This shows that during the entire amplification process, the S0 switch does not produce an offset at the input. Therefore, at t8, the output offset stored before the input jump is the same as the output offset after the jump. Taking the new low-offset 1-level DCTA circuit as an example, at t8, C O1 and C O2 The upper plate voltages are:

[0034]

[0035]

[0036] in is the gain of the 1st-stage DCTA circuit, α is related to the sampling frequency, C T is the transfer capacitance, C O is the load capacitance, and the 4-stage cascade gain is the product of the gains of each stage. The storage cancellation process of the output offset of the new DCTA circuit is as follows: Figure 6 As shown in the figure, the input offset voltage of the DCTA circuit is first stored and then completely eliminated. If there is a slight process deviation in the load capacitor, it will make the offset voltage stored at the positive and negative output ends of the DCTA slightly asymmetric, and a small output end deviation offset is not offset in the offset cancellation stage. This deviation offset voltage ΔV os and the offset voltage ΔV′ that has been offset os They can be expressed as:

[0037] ΔV os =|2(V o2 +V o1 )|

[0038] ΔV′ os =min{|V o2 |,|V o1 |}

[0039] V o2 +V o1 ≈0, from the above formula we can know that ΔV os <<ΔV′ os , that is, compared with the offset voltage that has been offset, the offset voltage that has not been offset is very small. Therefore, compared with the traditional DCTA structure, if there is no process deviation in the load capacitor, the intrinsic offset of the new DCTA structure can be completely eliminated; even if there is a slight process deviation in the load capacitor, the intrinsic offset of the new DCTA structure can be effectively reduced.

[0040] In order to make the purpose, technical solution and advantages of the present invention clearer, a preferred example is used for illustration. In order to minimize the inherent offset of the new DCTA circuit, the S2 switch needs to be designed to minimize the impact of charge injection. Under the 110nm process, S2 uses a CMOS switch, where P tube: W = 700n, L = 280n, N tube: W = 135n, L = 325n. Simulation shows that the input coupling capacitor C i1 =C i2 =648f F, the charge injection caused by S2 at the positive and negative inputs of the new DCTA is only about 53μV, and the differential input can further reduce the offset caused by charge injection at the positive and negative inputs. The charge injection of the S0 switch does not cause intrinsic offset under the optimized timing design.

[0041] The designed low offset 4-stage DCTA cascade circuit has gains of 5.4, 4.2, 3, and 6.7 times from the first to the fourth stage, respectively, and a total gain of about 460 times. The power supply voltage VDD = 3V, the common mode reference voltage V pre =1.5V: Monte Carlo simulation shows that the output offset stored in the offset storage cycle is about 52.2mV, and the equivalent input reference offset is about 113μV. After the offset compensation cycle, the output offset is well eliminated, and the DCTA amplified pixel jump signal is more accurate, thereby reducing the readout noise of the QIS circuit.

[0042] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed in the present invention should be covered within the protection scope of the present invention.

Claims

1. A low offset differential charge transfer amplifier for quantum image sensor applications, characterized in that: It includes a differential charge transfer amplifier DCTA, a differential symmetrical input module and an offset storage compensation module. A differential symmetrical input module is added to the DCTA input end, and an offset storage compensation module is added to the DCTA output end. The detailed structure is as follows: It consists of NMOS tubes MN1~MN4, PMOS tubes MP1~MP4, switches S0~S2, S c , S m , S n , transfer capacitor C T1 , C T2 , input coupling capacitor C i1 , C i2 and load capacitance C O1 , C O2 Composition; pixel reset signal V rst and pixel output signal V sig All through the switch S c The input coupling capacitors C i1 , C i2 The left plate is connected to the i1 and C i2 The left plates of MN1 and MP1 are connected together through switch S0; the gate terminals of MN1 and MP1 are connected, and the gate terminals of MN2 and MP2 are connected, and are connected to C i1 , C i2 The right plate is connected to the i1 and C i2 The right plate of the pre The source terminals of MN1 and MP1 are connected to the transmission capacitor C through switch S'1. T1 , C T2 The source terminals of MN2 and MP2 are also connected to the transmission capacitor C through switch S'1. T1 , C T2 The lower plate of the switch S'1 is a pair of complementary switches; the source terminals of MP3 and MP4 are connected to the power supply voltage VDD, and the gate and drain of the two tubes are first short-circuited and then connected to C through the switch S1. T1 The upper plate, C T2 The source terminals of MN3 and MN4 are connected to GND, and the gate and drain of the two tubes are short-circuited and then connected to C through switch S1. T2 The upper plate, C T1 The lower plate; MN1 is connected to the drain end of MP1, and MN2 is connected to the drain end of MP2, and both are connected to the precharge voltage V through the switch S2. pre connected together; the drain terminals of MN1 and MP1 are connected through switch S n Connected to the load capacitor C O1 The upper plate of the switch S m Connected to the load capacitor C O2 The drain terminals of MN2 and MP2 are connected through switch S n Connected to the load capacitor C O2 The upper plate of the switch S m Connected to the load capacitor C O1 The upper plate; C O1 and C O2 The lower plates of the switches (S0, S c ) and the input coupling capacitor (C i1 , C i2 ) forms a differential symmetrical input module, the switch (S m , S n ) and load capacitance (C O1 , C O2 ) constitute an offset storage compensation module.

2. The low offset differential charge transfer amplifier based on quantum image sensor application as claimed in claim 1, characterized in that: The 4-stage DCTA cascade circuit structure is as follows: the gate terminals of MN1 and MP1, and the gate terminals of MN2 and MP2 in the first stage DCTA are connected to the C i1 , C i2 The right plate is connected; the gate terminals of MN1 and MP1 in the second-stage DCTA, and the gate terminals of MN2 and MP2 are connected to the drain terminals of MN1 and MP1 and the drain terminals of MN2M2 in the first-stage DCTA respectively; the gate terminals of MN1 and MP1 in the third-stage DCTA, and the gate terminals of MN2 and MP2 are connected to the drain terminals of MN1 and MP1 and the drain terminals of MN2 and MP2 in the second-stage DCTA respectively; the gate terminals of MN1 and MP1 in the fourth-stage DCTA, and the gate terminals of MN2 and MP2 are connected to the drain terminals of MN1 and MP1 and the drain terminals of MN2 and MP2 in the third-stage DCTA respectively; in addition, the output terminals of the first, second, and third-stage DCTAs are all connected to a pair of load capacitors (C O1 , C O2 ), the drain terminals of MN1 and MP1 in the fourth-stage DCTA are connected through the switch S in the offset storage compensation module n Connected to the load capacitor C O1 The upper plate is connected to the load capacitor C through the switch Sm. O2 The drain terminals of MN2 and MP2 are connected through the switch S in the offset storage compensation module. n Connected to the load capacitor C O2 The upper plate of the switch S m Connected to the load capacitor C O1 The upper plate.

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