Method of controlling operation of a data storage device, data storage device and controller thereof

Abstract

A method for controlling operation of a data storage device, the data storage device, and a controller thereof are disclosed. The method can include selecting a block of a plurality of blocks of a non-volatile memory component of a plurality of non-volatile memory components, receiving a data write instruction from a host, generating a plurality of operation instructions corresponding to the data write instruction, and performing data write in a plurality of non-reserved word lines of the block, wherein the block includes the plurality of non-reserved word lines and a plurality of reserved word lines, and each of the plurality of non-reserved word lines includes a plurality of pages, and writing user data to a reserved word line of the plurality of reserved word lines by a single level cell write mode, such that the reserved word line includes a single page.

Description

[0001] This application is a divisional application of Chinese invention application filed on January 15, 2018, with application number 201810034108.0 and entitled "Method for controlling the operation of a data storage device and a data storage device and its controller". Technical Field

[0002] This invention relates to access of flash memory, and more particularly to a method for controlling the operation of a data storage device, as well as the associated data storage device and its controller. Background Technology

[0003] In recent years, due to the continuous development of memory technology, various portable or non-portable data storage devices (such as memory cards conforming to SD / MMC, CF, MS, XD, or UFS standards; solid-state drives; and embedded storage devices conforming to UFS or eMMC specifications) have been widely implemented in many applications. Therefore, the access control of memory in these data storage devices has become a very popular topic.

[0004] Commonly used NAND flash memory can be mainly divided into two categories: single-level cell (SLC) and multiple-level cell (MLC). In single-level cell flash memory, each transistor acting as a memory cell has only two charge values, representing logic 0 and logic 1 respectively. In contrast, in multiple-level cell flash memory, the storage capacity of each transistor acting as a memory cell is fully utilized, using higher voltages to record at least two sets of bit information (such as 00, 01, 11, 10) within a single transistor through different voltage levels. Theoretically, the recording density of multiple-level cell flash memory can be at least twice that of single-level cell flash memory, which is very good news for the NAND flash memory industry, which has previously encountered bottlenecks in its development.

[0005] Compared to single-cell flash memory, multi-cell flash memory quickly became the mainstream choice for data storage devices due to its lower cost and ability to provide larger capacity within a limited space. However, problems caused by the instability of multi-cell flash memory also emerged. To ensure that the data storage device's access control to flash memory complies with relevant specifications, the flash memory controller typically has certain management mechanisms to properly manage data access.

[0006] Even with these management mechanisms, data storage devices still have shortcomings, according to relevant technologies. For example, when using newer flash memory manufacturing technologies, the bit error rate (BER) of the first and last word lines within a block can be significantly higher than that of other word lines in the same block. This can make the block easily identified as a bad block. If many blocks have similar problems, the lifespan of the data storage device may become very short. Therefore, a novel method and related architecture are needed to improve the performance of data storage devices without or with minimal side effects. Summary of the Invention

[0007] The purpose of this invention is to provide a method for controlling the operation of a data storage device, as well as a related data storage device and its controller, to solve the above-mentioned problems.

[0008] Another object of the present invention is to provide a method for controlling the operation of a data storage device, and related data storage devices and controllers, so as to achieve optimal performance of the data storage device without side effects or with little or no possibility of side effects.

[0009] At least one embodiment of the present invention provides a method for controlling the operation of a data storage device, wherein the data storage device includes non-volatile memory (NV memory), and the non-volatile memory includes a plurality of non-volatile memory elements. The method may include: selecting a block from a plurality of blocks of non-volatile memory components; receiving a data write instruction from a host device, wherein the data write instruction is one of a plurality of host commands from the host; generating a plurality of operation instructions corresponding to the data write instruction, and transmitting the plurality of operation instructions to the non-volatile memory to write data to a plurality of non-reserved word lines of the block, wherein the block includes the plurality of non-reserved word lines and a plurality of reserved word lines, and each of the plurality of non-reserved word lines includes multiple pages; and writing user data or non-user data to any page in one of the reserved word lines using a single-page write mode.

[0010] At least one embodiment of the present invention provides a data storage device, which may include: non-volatile memory for storing information, wherein the non-volatile memory includes a plurality of non-volatile memory components; and a controller coupled to the non-volatile memory for controlling the operation of the data storage device. The controller may include processing circuitry that can control the controller according to a plurality of host instructions from a host, so as to allow the host to access the non-volatile memory through the controller. For example: the controller selects one block from a plurality of blocks of non-volatile memory components; the controller receives a data write instruction from the host, wherein the data write instruction is one of a plurality of host instructions from the host; the controller generates a plurality of operation instructions corresponding to the data write instruction and transmits the plurality of operation instructions to the non-volatile memory to write data to a plurality of non-reserved word lines in the block, wherein the block includes the plurality of non-reserved word lines and a plurality of reserved word lines, and each of the plurality of non-reserved word lines includes multiple pages; and the controller writes user data or non-user data to any page in one of the reserved word lines in the plurality of reserved word lines using a single-page write mode.

[0011] At least one embodiment of the present invention provides a controller for a data storage device, wherein the data storage device includes the controller and non-volatile memory, and the non-volatile memory includes a plurality of non-volatile memory components. The controller may include processing circuitry that can control the controller according to a plurality of host instructions from a host to allow the host to access the non-volatile memory through the controller. For example: the controller selects one block from a plurality of blocks of non-volatile memory components; the controller receives a data write instruction from the host, wherein the data write instruction is one of a plurality of host instructions from the host; the controller generates a plurality of operation instructions corresponding to the data write instruction and transmits the plurality of operation instructions to the non-volatile memory to write data to a plurality of non-reserved word lines in the block, wherein the block includes the plurality of non-reserved word lines and a plurality of reserved word lines, and each of the plurality of non-reserved word lines includes multiple pages; and the controller writes user data or non-user data to any page in one of the reserved word lines in the plurality of reserved word lines using a single-page write mode.

[0012] One of the many advantages of this invention is that, through reserved word-line management, the operation of the controller can be properly controlled to avoid shortening the lifespan of the data storage device. Furthermore, implementation according to embodiments of this invention does not incur many additional costs. Therefore, the problems of related technologies can be solved without significantly increasing the overall cost. Compared to related technologies, this invention achieves optimized performance of the data storage device without or with a low likelihood of causing side effects. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of a data storage device and a host device according to an embodiment of the present invention. Figure 2 This is a schematic diagram of a method for controlling the operation of a data storage device according to an embodiment of the present invention.

[0014] Figure 3 Draw Figure 2 The method shown improves the bit error rate (BER).

[0015] Figure 4 Draw Figure 2 The data writing order in the illustrated method in the embodiment.

[0016] Figure 5 Draw Figure 2 The workflow of the method shown in the embodiment.

[0017] Figure 6 Draw Figure 2 The data writing order of the method shown in another embodiment.

[0018] Figure 7 Draw Figure 2 The workflow of the method shown in another embodiment.

[0019] The reference numerals in the attached figures are explained as follows:

[0020] 50 host

[0021] 100 Data storage devices

[0022] 110 Memory Controller

[0023] 112 microprocessor

[0024] 112C program code

[0025] 112M Read-Only Memory

[0026] 114 Control Logic Circuit

[0027] 116 Buffer memory

[0028] 118 Transmission Interface Circuit

[0029] 120 Non-volatile Memory

[0030] 122-1, 122-2, ..., 122-N Non-volatile memory components

[0031] 210,220,P(0),P(1),P(2),P(3),P(4),

[0032] P(5),P(6),…,P(511),P(512),…,

[0033] P(762), P(763), P(764),

[0034] Pages P(765), P(766), P(767)

[0035] 300, 500 Workflow

[0036] DATA(0),DATA(1),DATA(2),

[0037] DATA(3),…user data

[0038] S20, S22, S24, S26, S28, S30, S32

[0039] S50, S52, S54, S56, S58, S60, S62

[0040] Steps S64, S66, S68

[0041] vBLK(0), vBLK(1) virtual blocks

[0042] WL(0),WL(1),WL(2),…,

[0043] WL(M-3),WL(M-2),WL(M-1) word lines Detailed Implementation

[0044] I. Memory System

[0045] Please refer to Figure 1 , Figure 1This is a schematic diagram of a data storage device 100 and a host device 50 according to a first embodiment of the present invention. For example, the data storage device 100 may be a portable data storage device (e.g., a memory card conforming to SD / MMC, CF, MS, or XD standards) or a solid-state drive (SSD). Additionally, examples of the host device 50 may include (but are not limited to): a multifunctional mobile phone, a tablet computer, a wearable device, and a personal computer such as a desktop computer and a laptop computer. According to this embodiment, the data storage device 100 may include a controller such as a memory controller 110, and may further include non-volatile memory (NV memory) 120, wherein the controller is used to access the NV memory 120, and the NV memory 120 is used to store information. The NV memory 120 may include a plurality of NV memory elements 122-1, 122-2, ..., and 122-N, wherein the symbol "N" may represent a positive integer greater than 122-1. For example, non-volatile memory 120 may be flash memory, and non-volatile memory components 122-1, 122-2, ... and 122-N may be a plurality of flash memory chips or a plurality of flash memory dies, but the present invention is not limited thereto.

[0046] like Figure 1As shown, the memory controller 110 may include processing circuitry such as a microprocessor 112, memory such as a read-only memory (ROM) 112M, control logic circuitry 114, buffer memory 116, and transmission interface circuitry 118, wherein these components are coupled to each other via a bus. The buffer memory 116 is implemented as random access memory (RAM). Additionally, in this embodiment, the read-only memory 112M is used to store program code 112C, and the microprocessor 112 is used to execute program code 112C to control access to non-volatile memory 120. Note that program code 112C may also be stored in the buffer memory 116 or any form of memory. In addition, the control logic circuit 114 may include error correction code circuitry (not shown) to protect data and / or perform error correction, while the transmission interface circuit 118 may conform to a specific communication standard (such as Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCIE), or Non-Volatile Memory Express (NVME)) and may communicate in accordance with that specific communication standard.

[0047] In this embodiment, the host 50 can indirectly access the non-volatile memory 120 in the data storage device 100 by transmitting a plurality of host commands and corresponding logical addresses to the memory controller 110. The memory controller 110 receives the plurality of host commands and logical addresses, and translates the plurality of host commands into memory operation instructions (hereinafter referred to as operation instructions). Then, the operation instructions control the non-volatile memory 120 to read, write / program memory units or data pages at specific physical addresses in the non-volatile memory 120, where the physical address corresponds to the logical address.

[0048] II. A novel approach using multiple reserved word-lines

[0049] Various techniques are available for manufacturing the non-volatile memory 120, such as planar NAND flash memory technology that arranges memory cells in a single layer; and 3D NAND flash memory technology that arranges memory cells in multiple vertical stacks. According to some embodiments, the non-volatile memory 120 can be implemented as a planar NAND flash architecture with a single layer of memory cells. According to some embodiments, the non-volatile memory 120 can be implemented as a 3D NAND flash architecture with multiple vertically stacked memory cells.

[0050] Figure 2 This is a schematic diagram of a method for controlling the operation of a data storage device according to an embodiment of the present invention. The method can be applied to a data storage device 100 and to a controller such as a memory controller 110. For example, non-volatile memory components 122-1, 122-2, ..., 122-N can be triple-level cell (TLC) non-volatile memory components, and any non-volatile memory component 122-n (where "n" can represent any integer in the interval [1, N]) can include multiple blocks, where N is a positive integer. A block including M word rows {WL(0), WL(1), WL(2), ..., WL(M-3), WL(M-2), WL(M-1)} can be an example of any of these multiple blocks, where M is a positive integer, for example, 256. The memory controller 110 can use TLC write mode (as the default write mode) to write user data to one page of one word of a block; in other words, one word can store three pages of user data.

[0051] like Figure 2 As shown in the left half, assume that the write operation for each word row in this block is performed using the TLC write mode. When implementing flash memory with the planar NAND flash architecture described above, this (using the TLC write mode for each word row in the block) might be fine. However, when implementing flash memory with the 3D NAND flash architecture described above, due to the characteristics of the 3D NAND flash architecture, doing this (using the TLC write mode for each word row in the block) might cause the block to be easily identified as a bad block. This method avoids this problem. As... Figure 2As shown in the right half, when the non-volatile memory 120 is implemented using the above-mentioned three-dimensional NAND flash architecture, the memory controller 110 operating based on this method can use the first word row (such as word row WL(0)) and the last word row (such as word row WL(M-1)) in the block as reserved word rows. In particular, user data can be written to the first word row (such as word row WL(0)) and the last word row (such as word row WL(M-1)) through single-level cell (SLC) write mode, or only write user data to one page of the first word row and the last word row (or single-page write), so that word row WL(0) includes a single page 210 and word row WL(M-1) includes a single page 220, so as to effectively reduce the number of error bits of user data stored in the first word row and the last word row, so that the block is no longer easily judged as a bad block. In addition, the first and last lines can still be used to store and write user data, but they are better used to store block closing information.

[0052] Figure 3 Draw Figure 2 The method shown improves the bit error rate (BER). Figure 3 As shown in the left half, assuming that the write operation of each word row in this block is performed using the TLC write mode, where the flash memory is implemented using the above-described planar NAND flash architecture. In this case, the bit error rate of the first word row (such as word row WL(0)) and the last word row (such as word row WL(M-1)) is significantly greater than the bit error rate of other word rows. To overcome this physical characteristic, related technologies usually require changes to certain algorithms, especially increasing the number of times the read-retry procedure is initiated and changing the flash memory operation parameters. In contrast, the above-described method of the present invention avoids the problems of related technologies. Since the memory controller 110 can treat the first word row (such as word row WL(0)) and the last word row (such as word row WL(M-1)) as reserved word rows and operate in the SLC write mode, or only perform single-page writes, this method can suppress the bit error rate of the first word row (such as word row WL(0)) and the last word row (such as word row WL(M-1)), such as Figure 3 As shown in the right half. It is conceivable that users can use SLC write mode or single-page write to write user data to multiple word lines, such as the first and second word lines (WL(0) and WL(1)) and the last two word lines (such as word lines WL(M-2) and WL(M-1)), to achieve a similar purpose.

[0053] Figure 4 Draw Figure 2The data writing order in the illustrated embodiment is shown. From the viewpoint of a data page, line WL(0) may include three pages such as pages {P(0), P(1), P(2)}, line WL(1) may include three pages such as pages {P(3), P(4), P(5)}, and so on. For example, the block may include pages {P(0), P(1), P(2), P(3), P(4), P(5), P(6), ..., P(762), P(763), P(764), P(765), P(766), P(767)}. Figure 4 As shown in the left half, it is assumed that the write operation of each word line in the block is performed using the TLC write mode, where the flash memory is implemented using the above-described planar NAND flash architecture. In this case, writing a series of data such as user data {DATA(0),DATA(1),DATA(2),DATA(3),…} typically starts from page P(0), and the user data can be stored in most of the pages in the block, up to page P(766). Finally, the End of Block (EOB) information is written to P(767). In contrast, the above method of the present invention may include writing user data into a plurality of non-reserved word lines, such as word lines {WL(1),…,WL(M-2)}, which in this embodiment may correspond to pages {{P(3),P(4),P(5)},…,{P(762),P(763),P(764)}} respectively. Figure 4 As shown in the right half, when user data {DATA(0),DATA(1),DATA(2),DATA(3),…} is to be written to this block, the memory controller 110 may start writing from page P(3). For the plurality of reserved word lines (e.g., the first and last word lines of the block), the memory controller 110 may switch to SLC write mode or perform single-page write only.

[0054] In practice, the present invention can achieve the above objectives by setting the programming order of blocks. The programming order can be an array or a table listing the physical addresses where user data should be stored, wherein the physical addresses can be consecutive page numbers, i.e., {P(3), P(4), P(5), ..., P(764), P(0), P(765)}. In another embodiment, the programming order preferably adopts a Z-shaped order, i.e., non-consecutive page numbers, for example: {P(3), P(6), P(4), P(9), ..., P(764), P(0), P(765)}, to conform to the operating characteristics of non-volatile memory 120. In another embodiment, the user sets the programming order of non-reserved word lines and the programming order of reserved word lines respectively. When writing user data, the memory controller 110 uses the default write mode and the programming order of non-reserved word lines. When writing non-user data (e.g., EOB information), the memory controller 110 uses SLC write mode or performs single-page writes according to the programming order of reserved word lines to write non-user data to the non-volatile memory 120. Through SLC write mode or single-page writes, the memory controller 110 can write non-user data to any of the plurality of reserved word lines. Additionally, the memory controller 110 can write non-user data to any of the plurality of reserved word lines and write a backup of the non-user data to another of the plurality of reserved word lines.

[0055] Figure 5 Draw Figure 2 The method shown is described in the workflow 300 of the embodiment. For example, under the control of the processing circuitry such as the microprocessor 112, the controller such as the memory controller 110 can perform the workflow 300.

[0056] In step S20, the memory controller 110 selects a block as an active block to store user data. An active block is such as the block described above that includes the M word rows {WL(0), WL(1), WL(2), ..., WL(M-3), WL(M-2), WL(M-1)}. After the data storage device 100 completes initialization, the memory controller 110 selects one block from the non-volatile memory 120 as the active block. The active block can be used to store user data from the host 50, or as a destination block in the garbage collection process to store valid user data from the source block, or as a destination block in the wear-leveling process to store user data from the source block.

[0057] In step S22, the memory controller 110 may receive a data write instruction from the host 50, wherein the data write instruction includes at least one user data and at least one logical address, and the user data and logical address preferably correspond one-to-one. In another embodiment, the data write instruction includes at least one user data and at least one specified physical address, the user data and specified physical address preferably correspond one-to-one, and the memory controller 110 preferably programs the user data into the specified physical address. In addition, at least one user data may be first stored in the memory of the host 50, and the memory controller 110 downloads at least one user data from the memory of the host 50 according to the instruction.

[0058] In step S24, the memory controller 110 may generate a plurality of operation instructions corresponding to the default write mode of the data write instruction. The memory controller 110 translates the data write instruction into a plurality of operation instructions in the default write mode according to the data write instruction, the programming order, and other parameters, so as to correctly program at least one piece of user data into the non-volatile memory 120. The storage address (physical address) of the at least one piece of user data may be determined by the memory controller 110 or by the data write instruction.

[0059] In step S26, the memory controller 110 executes a plurality of operation instructions in the default write mode to program at least one user data to a non-reserved word line of the active block. For example, the memory controller 110 executes a plurality of operation instructions in the TLC write mode to program at least one user data (such as user data {DATA(0),DATA(1),DATA(2),DATA(3),…}) to at least one page (such as page {P(3),P(4),P(5),…,P(762),P(763),P(764)}) of a non-reserved word line (such as word line {WL(1),WL(2),…,WL(M-3),WL(M-2)}), but the invention is not limited thereto.

[0060] In step S28, the memory controller 110 may check whether all non-reserved word rows have been written with user data. For example, in the loop formed by steps S22 to S28, the memory controller 110 may sequentially write the series of user data (such as user data {DATA(0),DATA(1),DATA(2),DATA(3),…}) into the non-reserved word rows (such as word rows {WL(1),WL(2),…,WL(M-3),WL(M-2)}) of the block, but the present invention is not limited thereto. When all non-reserved word rows have been written with user data, proceed to step S30; otherwise, proceed to step S22.

[0061] In step S30, the memory controller 110 executes a plurality of operation instructions of another mode to program block close information into at least one of the reserved word lines of the active block, such as word lines WL(0) and WL(M-1) (e.g., word line WL(0); or, for example, word line WL(M-1); or, for example, word lines WL(0) and WL(M-1)), but the invention is not limited thereto.

[0062] In step S32, the memory controller 110 may designate the active block as a data block. After block close information is written into the active block, the data block may represent a fully programmed block, and the active block is changed to a data block, no longer used to write any user data.

[0063] Figure 6 Draw Figure 2 The data writing order in another embodiment of the method shown. From the viewpoint of a data page, line WL(0) may include three pages such as pages {P(0), P(1), P(2)}, line WL(1) may include three pages such as pages {P(3), P(4), P(5)}, and so on. For example, the block may include pages {P(0), P(1), P(2), P(3), P(4), P(5), ..., P(511), P(512), ..., P(765), P(766), P(767)}. Figure 6 As shown in the left half, assuming that the write operation of each word row in this block uses the TLC write mode to write data, where the flash memory is implemented using the above-described planar NAND flash architecture. In this case, writing a series of data such as user data {DATA(0),DATA(1),DATA(2),...} usually starts from page P(0). In contrast, the above method of the present invention may include writing user data to non-reserved word rows, such as word rows {WL(1),...,WL(M-2)}, which in this embodiment may also correspond to pages {{P(3),P(4),P(5)},...,{P(762),P(763),P(764)}} respectively. Figure 6 As shown in the right half, when writing a series of data such as user data {DATA(0),DATA(1),DATA(2),…} to this block, the memory controller 110 can start writing from page P(3). For the reserved word lines such as word lines WL(0) and WL(M-1), the memory controller 110 can switch to SLC write mode or perform single-page write only.

[0064] Compared to Figure 4 In the illustrated embodiment, the block may include a plurality of virtual blocks. For example, the memory controller 110 may divide the block into two virtual blocks, such as... Figure 6The right half shows virtual blocks vBLK(0) and vBLK(1). Memory controller 110 can first write a first portion of user data into the non-reserved word lines of virtual block vBLK(0); then, through the SLC write mode or through single-page write, memory controller 110 can write non-user data (e.g., EOB information of virtual block vBLK(0)) into the first reserved word line among these reserved word lines, such as word line WL(0). Next, memory controller 110 can write a second portion of user data into the non-reserved word lines of virtual block vBLK(1); then, through the single-cell write mode or through single-page write, memory controller 110 can write non-user data (e.g., EOB information of virtual block vBLK(1)) into the second reserved word line among these reserved word lines, such as word line WL(M-1). The content similar to the previous embodiments will not be repeated here.

[0065] According to some embodiments, the way the virtual blocks in the block are divided (e.g., the size of virtual block vBLK(0), the size of virtual block vBLK(1), and / or the position of the boundary between virtual blocks vBLK(0) and vBLK(1)) can be varied. According to some embodiments, the number and size of the virtual blocks in the block can be varied.

[0066] Figure 7 Draw Figure 2 The illustrated method is described in another embodiment as workflow 500. For example, under the control of the processing circuitry such as microprocessor 112, the controller, such as memory controller 110, can perform workflow 500.

[0067] In step S50, the memory controller 110 may select a block as an active block to store user data. The active block is such as the block mentioned above that includes the M word rows {WL(0),WL(1),WL(2),...,WL(M-3),WL(M-2),WL(M-1)}.

[0068] In step S52, the memory controller 110 may divide the active block into a plurality of virtual blocks, such as the virtual blocks vBLK(0) and vBLK(1) mentioned above, but the present invention is not limited thereto.

[0069] In step S54, the memory controller 110 may select one of the plurality of virtual blocks, and in particular, may select a virtual block that has not yet been selected among the plurality of virtual blocks.

[0070] In step S56, the memory controller 110 may receive a data write instruction from the host 50. For example, the data write instruction includes at least one user data and at least one logical address, and the user data and logical address preferably correspond one-to-one. Another example: the data write instruction includes at least one user data and at least one specified physical address, the user data and specified physical address preferably correspond one-to-one, and the memory controller 110 preferably programs the user data into the specified physical address.

[0071] In step S58, the memory controller 110 may generate a plurality of operation instructions corresponding to the default write mode of the data write instruction.

[0072] In step S60, the memory controller 110 may execute a plurality of operation instructions in the default write mode to program at least one piece of user data into the non-reserved word line of the virtual block. For example, the memory controller 110 may execute a plurality of operation instructions in the TLC write mode to program at least one piece of user data (such as a portion of user data {DATA(0), DATA(1), DATA(2), ...}) into at least one page of the non-reserved word line of the virtual block (e.g., when the virtual block selected in step S54 is virtual block vBLK(0), the at least one page may include pages {P(3), P(4), P(5), ..., P(511)}; or, for example, when the virtual block selected in step S54 is virtual block vBLK(1), the at least one page may include pages {P(512), ..., P(764)}), but the present invention is not limited thereto.

[0073] In step S62, for the virtual block, the memory controller 110 can check whether all non-reserved word lines have been written with user data. For example, in the loop formed by steps S56 to S62, the memory controller 110 can sequentially write a portion of the series of data (such as user data {DATA(0), DATA(1), DATA(2), ...}) into the non-reserved word lines of the virtual block, but the present invention is not limited thereto. When all these non-reserved word lines have been written with data, proceed to step S64; otherwise, proceed to step S56.

[0074] In step S64, the memory controller 110 may execute a plurality of operation instructions in another mode to program block close information into a reserved word line of the virtual block, such as word line WL(0) or WL(M-1), but the invention is not limited thereto. For example, when the virtual block represents virtual block vBLK(0), the memory controller 110 may program the block close information of virtual block vBLK(0) into a reserved word line of virtual block vBLK(0), such as word line WL(0). As another example, when the virtual block represents virtual block vBLK(1), the memory controller 110 may program the block close information of virtual block vBLK(1) into a reserved word line of virtual block vBLK(1), such as word line WL(M-1).

[0075] In step S66, the memory controller 110 can determine whether all virtual blocks (among the plurality of virtual blocks) have been selected. If yes, proceed to step S68; otherwise, proceed to step S54.

[0076] In step S68, the memory controller 110 may designate the active block as a data block. For example, the data block may represent a fully programmed block. Details similar to those in the previous embodiments will not be repeated here.

[0077] According to certain embodiments, the write mode used to write user data to any non-reserved line of text (e.g., each non-reserved line of text) in the block may be an X-order cell write mode (where the order is equal to X), and the number of pages in the non-reserved line of text may be equal to X, where X may be a positive integer, especially a positive integer greater than 3. For example, when X ≥ 3, the non-reserved line of text may include at least three pages.

[0078] The method of the present invention (e.g., its workflows 300 and 500) and the corresponding devices (e.g., microprocessor 112, memory controller 110, and data storage device 100) can be properly controlled to avoid shortening the lifespan of the non-volatile memory 120. Problems of related technologies can be solved, and the overall cost will not increase too much. Compared with related technologies, the present invention can achieve optimized performance of the data storage device without side effects or with a low probability of causing side effects.

[0079] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for controlling the operation of a data storage device, the data storage device including non-volatile memory, the non-volatile memory including a plurality of non-volatile memory components, the method comprising: Select one block from a plurality of blocks of non-volatile memory components; The first or last line of a block is used as a plurality of reserved lines of the block, and the remaining lines of the block are used as a plurality of non-reserved lines of the block, wherein each of the plurality of non-reserved lines comprises multiple pages; Receive a data write instruction from the host, wherein the data write instruction is one of a plurality of host instructions from the host; Generate a plurality of operation instructions corresponding to the data write instruction to write data to the plurality of non-reserved word lines of the block; as well as In single-page write mode, user data or non-user data can be written to any page in one of the multiple reserved word lines.

2. The method of claim 1, further comprising: Write the block closing information for this block to this reserved word line.

3. The method as described in claim 2, characterized in that, The block comprises a plurality of virtual blocks; and the block closing information is the block closing information of one of the plurality of virtual blocks.

4. The method of claim 2, further comprising: The block closing information is backed up and written to another reserved line among the plurality of reserved lines using the single-page write mode, such that the other reserved line contains a single page.

5. The method of claim 1, further comprising: User data is written to another reserved line of the plurality of reserved lines using this single-page write mode, such that the other reserved line comprises a single page.

6. The method of claim 1, further comprising: Modify the entity addresses that point to at least a portion of the word lines of the block to write a series of data into the plurality of non-reserved word lines, while avoiding writing the series of data into the first word line of the block, wherein the plurality of reserved word lines include the first word line.

7. A data storage device, comprising: Non-volatile memory is used to store information, wherein the non-volatile memory comprises a plurality of non-volatile memory components; as well as A controller, coupled to the non-volatile memory, is used to control the operation of the data storage device, wherein the controller includes: The processing circuitry controls the controller based on a plurality of host instructions from the host, allowing the host to access the non-volatile memory through the controller, wherein: The controller selects one block from a plurality of blocks of non-volatile memory components. The first or last line of a block is used as a plurality of reserved lines of the block, and the remaining lines of the block are used as a plurality of non-reserved lines of the block, wherein each of the plurality of non-reserved lines comprises multiple pages; The controller receives a data write instruction from the host, wherein the data write instruction is one of a plurality of host instructions from the host; The controller generates a plurality of operation instructions corresponding to the data write instruction, to write data to the plurality of non-reserved word lines of the block; and The controller writes user data or non-user data to any page in one of the multiple reserved word lines using a single-page write mode.

8. The data storage device of claim 7, wherein the controller writes block close information of the block to the reserved word line.

9. A controller for a data storage device, the data storage device including the controller and non-volatile memory, the non-volatile memory including a plurality of non-volatile memory components, the controller comprising: The processing circuitry controls the controller based on a plurality of host instructions from the host, allowing the host to access the non-volatile memory through the controller, wherein: The controller selects one block from a plurality of blocks of non-volatile memory components. The first or last line of a block is used as a plurality of reserved lines of the block, and the remaining lines of the block are used as a plurality of non-reserved lines of the block, wherein each of the plurality of non-reserved lines comprises multiple pages; The controller receives a data write instruction from the host, wherein the data write instruction is one of a plurality of host instructions from the host; The controller generates a plurality of operation instructions corresponding to the data write instruction, to write data to the plurality of non-reserved word lines of the block; and The controller writes user data or non-user data to any page in one of the multiple reserved word lines using a single-page write mode.

10. The controller of claim 9, wherein the controller writes the block close information of the block to the reserved word line.

Images