Architecture for memory-based system and method of operating the same
An optical switch with memory buffer addresses latency and inefficiency in scale-out architectures by enhancing data exchange efficiency and supporting larger systems, doubling efficiency and enabling systems with hundreds of thousands of nodes.
WO2026148119A1PCT designated stage Publication Date: 2026-07-09XSCAPE PHOTONICS INC
View PDF 0 Cites 0 Cited by
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- XSCAPE PHOTONICS INC
- Filing Date
- 2025-12-31
- Publication Date
- 2026-07-09
AI Technical Summary
Technical Problem
Scale-out architectures in large systems suffer from back pressure and inefficient utilization of processors due to limited processing capabilities of intermediate buffers, leading to latency issues and suboptimal performance.
Method used
Implementing an optical switch with memory as an intermediate buffer between processors, utilizing high-bandwidth optical memory (HBOM) to offload demanding operations and reduce latency, thereby enhancing data exchange efficiency.
Benefits of technology
The solution doubles data exchange efficiency compared to conventional systems, supports larger systems with hundreds of thousands of nodes, and avoids the limitations of copper-based I/O ports.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure US2025061835_09072026_PF_FP_ABST
Abstract
A system includes: an optical switch module comprising a plurality of high bandwidth optical memory (HBOM) modules optically connected to a photonic integrated circuit comprising an optical switch configured to transmit optical signals between the HBOM modules and a plurality of ports; a plurality of processors each optically connected to at least one port of the optical switch module through a respective fiber connection; and a control module programmed to control data routing between the plurality of processors via the optical switch module, wherein the data routing comprises buffering data routed from a first processor of the plurality of processors to a second processor of the plurality of processors on one or more of the HBOM modules.
Need to check novelty before this filing date? Find Prior Art