UniPro cport protocol data realignment circuit

Abstract

Provided are UniPro CPort protocol data real-time alignment circuits. The provided CPort alignment circuit includes a shift register, a valid data counter, a FIFO write control unit, a FIFO and CPort signal output unit; the shift register buffers received CPort segment valid data; the valid data counter counts the valid data buffered by the shift register; the FIFO write control unit writes the data of the shift register to the FIFO; and the CPort signal output unit takes out entries from the FIFO and generates valid data aligned CPort segments according to the entries.

Description

Technical Field

[0001] This application relates to electronic technology, and more specifically, to a circuit and method for real-time alignment processing of UniPro CPort data in a circuit. Background Technology

[0002] UFS (Universal Flash Storage) is an interface standard for flash storage devices developed by the JEDEC standards organization, with standard numbers such as JESD220C. The UFS protocol uses UPIUs (UFS Protocol Information Units) as the transmission unit to exchange commands between the host and the storage device. UPIUs include various types, such as command units, RTT units, read data units, write data units, and response units.

[0003] UFS utilizes the MIPI Unified Protocol (UniPro) as its interconnect layer to provide basic transport capabilities to the UFS Transport Protocol (UTP) layer. UniPro Transport Layer CPorts are service primitives for communication between UTP and UniPro in the data plane. UniPro provides CPorts as a conceptual interface to application or protocol layers. The implementation of CPorts is not defined in the protocol itself.

[0004] The MIPI Alliance provides the UniPro protocol (Specification for Unified Protocol (UniPro)).

[0005] Figure 1 The diagram shows the architecture of the UniPro protocol and CPort.

[0006] The host accesses the devices coupled to it via the UFS protocol. Both the host and the device include a UniPro layer for interconnection. The UniPro layer includes one or more CPort interfaces. Upper-layer units (e.g., applications) on the host access the host's UniPro layer's CPort interface (hereinafter referred to as CPort). For example, a UPIU (User-defined Interface) to be sent by the host to the UFS device is encapsulated as a Protocol Data Unit (PDU) and provided to the UniPro via CPort. It is understood that the application on the host is, for example, application software or hardware. The host's UniPro transmits the PDU obtained from CPort to the device's UniPro layer according to the protocol specifications, and provides it to the application on the device through the device's UniPro layer's CPort. For example, the device's application obtains the PDU from CPort and assembles it into a UPIU to identify and process the UFS commands indicated by the UPIU.

[0007] The CPort signal interface is defined in Annex D of the UniPro Specification for Unified Protocol (UniPro) provided by the MIPI Alliance.

[0008] Figure 2A and Figure 2B This demonstrates the interface signal definition for data transmission between the CPort provided by the UniPro protocol and the application.

[0009] Figure 2A This demonstrates the signals an application uses to receive data from CPort. As the recommended signal definition in the protocol, CPort provides data to the application through multiple sets of signals. The RxData signal is the data provided by CPort to the application, transmitting, for example, 8 bytes, 16 bytes, or more of data each time. The RxDataValid signal indicates that the data on the current RxData signal line is valid. The application uses the RxDataAccept signal to indicate to CPort that data has been successfully received. CPort uses the RxDataByteEn signal to indicate to the application which bytes of the multiple bytes transmitted in the corresponding RxData signal are valid data. The RxDataSom signal is the start marker of the message, while the RxDataEom signal is the end marker of the message. Each PDU transmitted by CPort is called a segment. A message can consist of multiple segments. The first segment carrying the message includes a start marker, while the last segment includes an end marker.

[0010] Figure 2BThis demonstrates the signals the application uses to provide data to CPort. The TxData signal represents the data CPort receives from the application, and the TxDataValid signal indicates that the data on the current TxData signal line is valid. CPort uses the TxDataAccept signal to indicate to the application that data has been successfully received. The application uses the TxDataByteEn signal to indicate to CPort which bytes of the multiple bytes transmitted in the corresponding TxData signal are valid data. The TxDataSom signal marks the start of a message, while the TxDataEom signal marks the end of a message.

[0011] For clarity and without causing confusion, the RxData and TxData signals defined in the UniPro protocol are collectively referred to as data signals, the RxDataByteEn and TxDataByteEn signals are collectively referred to as valid data markers, the RxDataValid and TxDataValid signals are referred to as valid data signals, and the RxDataAccept and TxDataAccept signals are collectively referred to as data acceptance markers.

[0012] Figure 3 This is a waveform diagram of CPort providing data to the application.

[0013] During clock cycles 2 through 7, the RxDataValid signal becomes active, with the PDU transmitted in cycle 2 carrying a start marker and the PDU transmitted in cycle 7 carrying an end marker. Each bit of the RxDataByteEn signal indicates whether the corresponding byte of the RxData signal is valid. In cycle 2, the RxDataByteEn signal indicates 0xfc, meaning that the lowest 2 bytes of data in the RxData signal corresponding to cycle 2 are invalid, while the other 6 bytes are valid. In cycle 4, the RxDataByteEn signal indicates 0xf0, meaning that the lowest 4 bytes of data in the RxData signal corresponding to cycle 4 are invalid, while the other 4 bytes are valid. During the cycle when the RxDataByteEn signal indicates 0xff, all data in the corresponding RxData signal is valid. Summary of the Invention

[0014] Because some data in the RxData signal is invalid during certain cycles, the CPort or the receiving circuitry of the application needs to receive all the data transmitted by the RxData signal in each cycle. The presence of invalid data causes the received valid data to be discontinuous, which is also known as valid data misalignment. Misaligned or discontinuous valid data increases the complexity of further processing of valid data at the receiving end, and transmitting invalid data also wastes bus bandwidth, affecting the speed and efficiency of data transmission.

[0015] The goal is to provide circuitry that minimizes or eliminates invalid data in the RxData signal transmitted by CPort, ensuring that the valid data transmitted by the RxData signal of CPort is continuous or aligned. Furthermore, the aligned valid data should still be transmitted in a signal format conforming to the protocol, and the delay introduced by the valid data alignment operation should be minimized.

[0016] According to a first aspect of this application, a first CPort alignment unit is provided, comprising a shift register, a valid data counter, a FIFO write control unit, and a FIFO and CPort signal output unit; the shift register buffers valid data of received CPort segments; the valid data counter counts the valid data buffered by the shift register; the FIFO write control unit writes the data of the shift register into the FIFO; and the CPort signal output unit retrieves entries from the FIFO and generates valid data-aligned CPort segments based on the entries.

[0017] According to a first CPort alignment unit of a first aspect of this application, a second CPort alignment unit of a first aspect of this application is provided, wherein the CPort alignment unit is coupled to a CPort interface of a UniPro unit and an application; the CPort interface and the application communicate according to the UniPro protocol.

[0018] According to the first or second CPort alignment unit of the first aspect of this application, a third CPort alignment unit according to the first aspect of this application is provided, wherein the shift register is coupled as a data signal as input to the CPort alignment unit; in response to a data valid signal, a CPort segment is identified, and valid data in the data signal of the CPort segment is identified based on a valid data marker, and the identified valid data is written byte by byte into the shift register.

[0019] According to the third CPort alignment unit of the first aspect of this application, a fourth CPort alignment unit according to the first aspect of this application is provided, wherein an invalid data reception flag is generated in response to the shift register being full; the depth of the shift register is the same as the width of the data signal, or an integer multiple of the width of the data signal.

[0020] According to the first to fourth CPort alignment units of the first aspect of this application, a fifth CPort alignment unit according to the first aspect of this application is provided, wherein in response to a counter full signal generated by the valid data counter or the shift register being full, the FIFO write control unit writes data from the shift register into the FIFO to add an entry to the tail of the FIFO. The added entry includes a data field and a valid data flag field. The data field of the added entry records data from the shift register, and the valid data flag field of the added entry indicates that each byte of the data field of the added entry is valid data.

[0021] According to the fifth CPort alignment unit of the first aspect of this application, a sixth CPort alignment unit according to the first aspect of this application is provided, wherein in response to the received CPort segment carrying a valid start flag, a valid start flag is set; when the FIFO write control unit writes the data of the shift register into the FIFO, if a valid start flag exists, a start flag field is also set in the added entry, and the valid start flag is cleared.

[0022] According to the fifth or sixth CPort alignment unit of the first aspect of this application, a seventh CPort alignment unit according to the first aspect of this application is provided, wherein in response to the received CPort segment carrying a valid end marker, and in response to writing all valid data of the received CPort segment into the shift register, a valid end marker is set; when the FIFO write control unit writes the data of the shift register into the FIFO, if a valid end marker exists, a start end field is also set in the added entry, and the valid end marker is cleared.

[0023] According to the seventh CPort alignment unit of the first aspect of this application, an eighth CPort alignment unit according to the first aspect of this application is provided, wherein in response to the received CPort segment carrying a valid end marker, and if part but not all of the valid data of the received CPort segment is written to the shift register and the shift register is full, a valid end marker is not set.

[0024] According to the fifth to eighth CPort alignment units of the first aspect of this application, a ninth CPort alignment unit according to the first aspect of this application is provided, wherein in response to the received CPort segment carrying a valid end marker, and in response to writing all valid data of the received CPort segment into the shift register, the FIFO write control unit writes data from the shift register into the FIFO to add an entry to the tail of the FIFO, the data field of the added entry records data from the shift register, the valid data flag field of the added entry comes from the valid data counter, and each bit of the valid data flag field of the added entry indicates whether each byte of the data field of the added entry is valid data.

[0025] According to the fifth to ninth CPort alignment units of the first aspect of this application, a tenth CPort alignment unit according to the first aspect of this application is provided, wherein a one-bit hot signal is generated based on the count value of the valid data counter as the valid data marker field of the added entry.

[0026] According to the first to tenth CPort alignment units of the first aspect of this application, an eleventh CPort alignment unit according to the first aspect of this application is provided, wherein in response to the FIFO being non-empty, the CPort signal output unit takes an entry from the head of the FIFO and generates a valid data aligned CPort segment based on the entry; wherein a data signal and a valid data marker of the valid data aligned CPort segment are generated based on the data field and the valid data marker field of the entry, respectively.

[0027] According to the eleventh CPort alignment unit of the first aspect of this application, a twelfth CPort alignment unit according to the first aspect of this application is provided, wherein the CPort signal output unit generates a start flag of the validly data-aligned CPort segment according to the start flag field of the entry, and generates an end flag of the validly data-aligned CPort segment according to the end flag field of the entry.

[0028] According to the first to twelfth CPort alignment units of the first aspect of this application, a thirteenth CPort alignment unit according to the first aspect of this application is provided, wherein the CPort signal output unit generates an invalid data reception flag for the CPort segment as input to the CPort alignment unit in response to receiving an invalid data reception flag for a CPort segment after valid data alignment for its output.

[0029] According to the first to thirteenth CPort alignment units of the first aspect of this application, a fourteenth CPort alignment unit according to the first aspect of this application is provided, wherein the valid data counter is cleared in response to the FIFO write control unit writing data of the shift register into the FIFO.

[0030] According to the first to fourteenth CPort alignment units of the first aspect of this application, a fifteenth CPort alignment unit according to the first aspect of this application is provided, wherein in response to the FIFO being full, an invalid data reception tag for the CPort segment as input to the CPort alignment unit is generated.

[0031] According to a second aspect of this application, a first UFS device according to the second aspect of this application is provided, including a UniPro unit, an application unit, and a CPort alignment unit according to the first aspect of this application; the CPort alignment unit couples the CPort interface of the UniPro unit to the application unit.

[0032] According to the first UFS device of the second aspect of this application, a second UFS device according to the second aspect of this application is provided, wherein the CPort interface of the UniPro unit outputs CPort segments; the CPort alignment unit acquires the CPort segments; the CPort alignment unit outputs CPort segments after valid data alignment; and the application unit acquires the CPort segments after valid data alignment.

[0033] According to the first or second UFS device of the second aspect of this application, a third UFS device according to the second aspect of this application is provided, further comprising a second CPort alignment unit according to the first aspect of this application; the application unit outputs a second CPort segment; the second CPort alignment unit according to the first aspect of this application acquires the second CPort segment; the second CPort alignment unit according to the first aspect of this application outputs a second valid data aligned CPort segment; and the CPort interface of the UniPro unit acquires the second valid data aligned CPort segment.

[0034] According to a third aspect of this application, a first CPort valid data alignment method according to the third aspect of this application is provided, comprising: acquiring CPort segments; writing valid data of the CPort segments one by one into a shift register; generating entries with the data in the shift register and writing them into a FIFO; acquiring the entries from the FIFO, and generating valid data aligned CPort segments based on the acquired entries.

[0035] According to the first CPort valid data alignment method of the third aspect of this application, a second CPort valid data alignment method according to the third aspect of this application is provided, wherein the occurrence of the CPort segment is identified in response to a valid data signal; valid data and invalid data in the data signal of the CPort segment are identified based on valid data markers, and invalid data of the CPort segment is not written to the shift register.

[0036] According to the first or second CPort valid data alignment method of the third aspect of this application, a third CPort valid data alignment method according to the third aspect of this application is provided, which further includes: the CPort segment has a start mark, and a valid start mark is set; when generating an entry with data from the shift register and writing it into the FIFO, if a valid start mark exists, a start mark field is also set in the generated entry, and the valid start mark is cleared.

[0037] According to the first to third CPort valid data alignment methods of the third aspect of this application, a fourth CPort valid data alignment method according to the third aspect of this application is provided, further comprising: if the CPort segment has an end marker, in response to writing all valid data of the CPort segment into the shift register, setting a valid end marker; when generating an entry with the data of the shift register and writing it into the FIFO, if a valid end marker exists, also setting an end field in the entry and clearing the valid end marker.

[0038] According to the fourth CPort valid data alignment method of the third aspect of this application, a fifth CPort valid data alignment method according to the third aspect of this application is provided, further comprising: if the CPort segment has an end marker, and if part but not all of the valid data of the CPort segment is written to the shift register and the shift register is full, then a valid end marker is not set; when generating entries with the data of the shift register and writing them to the FIFO, an end field is not set in the entries.

[0039] According to the first to fifth CPort valid data alignment methods of the third aspect of this application, a sixth CPort valid data alignment method according to the third aspect of this application is provided, wherein the entry includes a data field and a valid data marker field, the data field of the entry records data from the shift register, and the valid data marker field of the entry indicates valid data and / or invalid data in the data field of the entry.

[0040] According to the sixth CPort valid data alignment method of the third aspect of this application, a seventh CPort valid data alignment method according to the third aspect of this application is provided, wherein in response to the shift register being full or the valid data written to the shift register reaching a specified threshold, an entry is generated using the data of the shift register and written to a FIFO, and the valid data marker field of the entry indicates that each byte of the data field of the entry is valid data.

[0041] According to the sixth or seventh CPort valid data alignment method of the third aspect of this application, an eighth CPort valid data alignment method according to the third aspect of this application is provided, wherein the CPort segment carries an end marker, and in response to writing all valid data of the CPort segment into the shift register, an entry is generated with the data of the shift register and written into a FIFO, and a valid data marker field of the entry is generated according to the number of valid data written to the shift register, wherein each bit of the valid data marker field of the entry indicates whether each byte of the data field of the entry is valid data.

[0042] According to the eighth CPort valid data alignment method of the third aspect of this application, a ninth CPort valid data alignment method according to the third aspect of this application is provided, wherein a one-bit hot signal is generated based on the number of valid data written to the shift register as the valid data marker field of the entry.

[0043] According to the first to ninth CPort valid data alignment methods of the third aspect of this application, a tenth CPort valid data alignment method according to the third aspect of this application is provided, wherein in response to the FIFO being non-empty, an entry is taken from the head of the FIFO and a valid data aligned CPort segment is generated based on the entry; wherein a data signal and a valid data marker of the valid data aligned CPort segment are generated based on the data field and the valid data marker field of the entry, respectively.

[0044] According to the tenth CPort valid data alignment method of the third aspect of this application, an eleventh CPort valid data alignment method according to the third aspect of this application is provided, wherein a start marker of the valid data aligned CPort segment is generated according to the start marker field of the entry; and / or an end marker of the valid data aligned CPort segment is generated according to the end marker field of the entry.

[0045] According to the first to eleventh CPort valid data alignment methods of the third aspect of this application, a twelfth CPort valid data alignment method according to the third aspect of this application is provided, further comprising: in response to receiving an invalid data reception flag indicated by the receiver of the CPort segment after valid data alignment, generating an invalid data reception flag and providing it to the sender of the acquired CPort segment.

[0046] According to the twelfth CPort valid data alignment method of the third aspect of this application, a thirteenth CPort valid data alignment method according to the third aspect of this application is provided, further comprising: in response to the FIFO being full, generating an invalid data reception flag and providing it to the sender of the acquired CPort segment.

[0047] According to the thirteenth CPort valid data alignment method of the third aspect of this application, a fourteenth CPort valid data alignment method according to the third aspect of this application is provided, wherein the receiver is a CPort interface of a UniPro module or an application; the sender is a CPort interface of a UniPro module or an application; and the CPort interface communicates with the application according to the CPort interface signal defined by the UniPro protocol. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0049] Figure 1 The diagram shows the architecture of the UniPro protocol and CPort.

[0050] Figure 2A and Figure 2B This demonstrates the interface signal definition for data transmission between the CPort provided by the UniPro protocol and the application.

[0051] Figure 3 This is a waveform diagram of CPort providing data to the application.

[0052] Figure 4A and Figure 4B This is a block diagram of a UFS device according to an embodiment of this application.

[0053] Figure 5A and Figure 5B The waveforms of the CPort interface signals before and after processing by the CPort alignment unit are shown respectively.

[0054] Figure 6 This is a block diagram of the CPort alignment unit according to an embodiment of this application.

[0055] Figure 7 A flowchart illustrating the valid data for CPort alignment unit alignment segments according to an embodiment of this application is provided.

[0056] Figure 8A , Figure 8B and Figure 8C A flowchart illustrating the valid data for the CPort alignment unit alignment segment according to yet another embodiment of this application is provided. Detailed Implementation

[0057] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0058] Figure 4A and Figure 4B This is a block diagram of a UFS device according to an embodiment of this application.

[0059] Devices that support UFS (i.e.) Figure 4A and Figure 4B The device (in the context) includes a UniPro module that provides the UniPro layer and an application module. The application module and the UniPro module are coupled through the CPort interface provided by the UniPro module. The CPort interface interacts with the application module using signals defined, for example, by the UniPro protocol.

[0060] According to embodiments of this application, a CPort alignment unit is also provided. The CPort alignment unit is coupled between the CPort of the UniPro module and the application module. The CPort interface interacts with the CPort alignment unit using signals defined by, for example, the UniPro protocol. The CPort alignment unit also interacts with the application module using signals defined by, for example, the UniPro protocol. Therefore, although the CPort alignment unit according to embodiments of this application is coupled between the CPort and the application module, both the application module and the CPort interface can interact with each other using signals defined by the UniPro protocol without being aware of the existence of the CPort alignment unit.

[0061] The CPort alignment unit obtains segments from, for example, CPort, eliminates invalid data (from the RxData signal), aligns the valid data, and provides the aligned valid data to the application module. Conversely, the CPort alignment unit obtains segments from the application module, eliminates invalid data (from the TxData signal), aligns the valid data, and provides it to CPort.

[0062] See Figure 4B UniPro may include multiple CPorts, and the application module may access each CPort individually. Accordingly, according to embodiments of this application, multiple CPort alignment units are included, each CPort alignment unit coupling one of the CPorts to the application module, so that the application module can access each CPort by accessing each CPort alignment unit.

[0063] Understandably, the CPort alignment unit according to this application can also be applied to the CPort of the coupled host and the application.

[0064] Figure 5A and Figure 5B The waveforms of the CPort interface signals before and after processing by the CPort alignment unit are shown respectively.

[0065] Figure 5A This is a waveform diagram of the CPort interface signals before the CPort alignment unit processing. In cycles 2, 4, and 5, invalid data exists on the RxData signal (the RxDataByteEn signal value is not 0xff). Cycle 2 has a start marker, while cycle 7 has an end marker. The corresponding messages occupy 6 segments, with a total of 39 bytes of valid data and 9 bytes of invalid data.

[0066] Figure 5B Yes Figure 5A The waveform shown is a CPort interface signal waveform obtained after processing by the CPort alignment unit according to the embodiment of this application. Figure 5B In the waveform diagram, the second cycle has a start marker, and the sixth cycle has an end marker. The corresponding message occupies 5 segments, with a total of 39 bytes of valid data. Figure 5A The waveform is the same (the data is not identical to the waveform), with 1 byte of invalid data. In cycles 2 through 5, the RxData signal contains valid data (RxDataByteEn signal value is 0xff), and valid data only exists on the RxData signal in cycle 6, which has a termination marker (RxDataByteEn signal value is 0x7f). Therefore, transmitting the same message results in less invalid data. Figure 5B The waveform diagram uses fewer segments than Figure 5A The waveform diagram. And, Figure 5B The waveform diagram shown still conforms to, for example, the UniPro protocol. Therefore, the transmitting end and / or receiving end coupled with the CPort alignment unit do not need to be modified, and can utilize the CPort alignment unit according to the embodiments of this application in accordance with the UniPro protocol.

[0067] Figure 6 This is a block diagram of the CPort alignment unit according to an embodiment of this application.

[0068] As an example Figure 6 The CPort alignment unit shown is coupled to the CPort interface of the UniPro module to align the valid data provided to the application by the CPort interface.

[0069] The CPort alignment unit includes a shift register, a valid data counter, a FIFO write control unit, a FIFO (First-In-First-Out) memory, and a CPort signal output unit.

[0070] Shift registers, for example, buffer the valid data transmitted by the RxData signal byte by byte. The depth of the shift register is the same as the width of the RxData signal. For example, if the RxData signal transmits 8 bytes of data in one cycle, the corresponding shift register depth is 8 bytes, holding a maximum of 8 bytes of data. Optionally, the width of the RxData signal is 16 bytes, and the corresponding shift register depth is 16 bytes. Still optionally, the depth of the Rx shift register is an integer multiple of the width of the RxData signal.

[0071] The shift register performs a shift in response to each byte of valid data in the RxData signal to buffer valid data in the shift register. The valid data in the RxData signal is identified based on the RxDataByteEn signal provided by the CPort interface. For invalid data in the RxData signal, the shift register does not buffer it. For example, in response to the RxDataByteEn signal indicating 0xfe, the 0th byte of the RxData signal is invalid data, and the others are valid data; the shift register shifts and buffers bytes 1 through 7 of the RxData signal. For each segment, in response to buffering all valid data indicated by the RxDataByteEn signal, the CPort alignment unit or shift register also generates a valid RxDataAccept signal for the CPort port. Optionally, if the CPort alignment unit cannot buffer valid data, an invalid RxDataAccept signal is generated for the CPort port to temporarily suspend data transmission at the CPort port.

[0072] The valid data counter counts the number of bytes of valid data buffered in the shift register according to the RxDataByteEn signal. For example, the RxDataByteEn signal of CPort is provided to the valid data counter to identify the number of valid data bytes in each segment. The counting threshold of the valid data counter is, for example, the same as the shift register depth. For example, if the shift register depth is 8, the counting range of the valid data counter is from 0 to 7, and a counter full count signal is output each time it counts to 7. The counter full count signal is provided to the FIFO write control unit. Optionally, the counter full count signal is also provided to the shift register.

[0073] The FIFO write control unit controls the writing of data from the shift register into the FIFO. In response to receiving a full counter signal, the FIFO write control unit controls the writing of data from the shift register into the FIFO. In addition to responding to the full counter signal, according to embodiments of this application, the FIFO write control unit also writes data from the shift register into the FIFO in response to receiving an end-of-transmission signal from the CPort, even if the shift register is not full. However, since the RxDataEom signal indicates that a message has been transmitted successfully, all valid data belonging to that message should be transmitted out as soon as possible.

[0074] Understandably, because invalid data may exist in the RxData signal provided by CPort, the data in the shift register may come from one, two, or more segments provided by the CPort interface. The shift register buffers only valid data according to the indication of the RxDataByteEn signal, thereby reducing or eliminating invalid data.

[0075] Optionally, in response to the FIFO write control unit writing data from the shift register to the FIFO, the shift register is also cleared, so that subsequent valid data is written to a blank shift register.

[0076] The CPort alignment unit also records a message start flag and an end flag in association with the shift register. In response to obtaining a start flag from the CPort interface, the CPort alignment unit records the start flag and clears it after the next FIFO write control unit writes the data from the shift register to the FIFO. Similarly, in response to obtaining an end flag from the CPort interface, the CPort alignment unit records the end flag and clears it after the next FIFO write control unit writes the data from the shift register to the FIFO.

[0077] Optionally, the FIFO write control unit records the message start and end markers. The FIFO write control unit also generates a ByteEn signal to be stored in the FIFO based on the valid data counter. Furthermore, the FIFO write control unit generates a corresponding one-hot signal as the ByteEn signal based on the count value of the valid data counter when data is written to the FIFO. For example, the ByteEn signal corresponding to count value 7 is 0xff, the ByteEn signal corresponding to count value 4 is 0x1f, and the ByteEn signal corresponding to count value 1 is 0x01.

[0078] A FIFO consists of multiple entries. Each FIFO entry includes a data field, a start flag field, an end flag field, and a ByteEn signal field (also known as a valid data marker field). The data field of a FIFO entry records valid data from the shift register. The start and end flag fields correspond to the start and end flags of the CPort interface, respectively. The ByteEn signal field comes from the RxByteEn signal of the CPort interface or from the valid data counter. In response to the FIFO write control unit controlling the writing of data to the FIFO, all valid data in the shift register is written to the tail entry of the FIFO, and the corresponding ByteEn signal field is also written to that entry. If the start and / or end flags are valid at this time, they are also recorded in the corresponding fields of the tail entry of the FIFO.

[0079] In the FIFO entries, the valid data field corresponds to the ByteEn signal field. Each bit of the ByteEn signal field indicates whether each byte of the valid data field is valid data. According to the embodiments of this application, invalid data in the RxData signal has been removed as much as possible, but the segments output by the CPort alignment unit still carry invalid data. These segments can only be segments carrying an end marker. The valid data of the RxData signal received by the CPort alignment unit is buffered in a shift register. When a segment with an end marker is received from the CPort interface, if the valid data of the segment cannot fill the shift register, the shift register will contain invalid data. This invalid data will be written into the FIFO entries, and the ByteEn signal indicates the position of the invalid data. Optionally, the shift register retains the invalid data to be written to the FIFO at the end of the shift register by shifting, so that when the CPort alignment unit outputs the FIFO entry storing the invalid data, the valid data stored in the FIFO entry is output continuously with the valid data of the previous FIFO, while the invalid data is placed after the valid data for processing by the receiving end.

[0080] In response to an entry being filled into the FIFO, the CPort signal output unit retrieves the entry from the FIFO and outputs it according to the signal format defined by the UniPro protocol. Figure 6 In the text, the “new_xxx” flag indicates the signal output by the CPort alignment unit, where “xxx” indicates the signal name defined in the UniPro protocol.

[0081] The CPort signal output unit, for each output segment (in each cycle), generates a new_RxData signal from the data field of the entry retrieved from the FIFO, a new_RxByteEn signal from the ByteEn signal field of the entry retrieved from the FIFO, a new_RxDataSom signal from the start flag field of the entry retrieved from the FIFO, and a new_RxDataEom signal from the end flag field of the entry retrieved from the FIFO. In response to each output segment, the CPort signal output unit also generates a valid new_RxDataValid signal.

[0082] The CPort signal output unit also receives the new_RxDataAccept signal. If the new_RxDataAccept signal is invalid, the CPort signal output unit suspends acquiring entries from the FIFO; if the new_RxDataAccept signal is valid, the CPort signal output unit acquires entries from the FIFO in each cycle and outputs the corresponding segments. If the FIFO is empty, the CPort signal output unit suspends acquiring entries from the FIFO and also generates an invalid new_RxDataValid signal.

[0083] If the FIFO is full, the CPort alignment unit also provides an invalid RxDataAccept signal to CPort.

[0084] Figure 7 A flowchart illustrating the valid data for CPort alignment unit alignment segments according to an embodiment of this application is provided.

[0085] See also Figure 6According to an embodiment of this application, the CPort alignment unit is coupled to the CPort interface of the UniPro module and obtains segments (710) from the CPort interface. A segment is identified in the CPort interface in response to, for example, a valid RxDataValid signal. Valid data in the RxData signal is identified based on the RxDataByteEn signal, and the valid data is buffered in a shift register (720). Since the segments provided by the CPort interface may include invalid data, and the CPort alignment unit eliminates invalid data, the segments output by the CPort alignment unit do not correspond one-to-one with the segments obtained from the CPort interface. The CPort alignment unit generates data for a new segment in response to a full count signal from the valid data counter, or in response to receiving a valid RxDataValid signal from the CPort interface, and adds it as a FIFO entry to the FIFO (730). The FIFO entry includes a data field, a start flag field, an end flag field, and a ByteEn signal field. The shift register is also cleared in response to the generation of data for the new segment. Therefore, when receiving a segment that indicates a valid RxDataSom signal, the shift register is completely empty.

[0086] If no full counter signal or valid RxDataEom signal is received, valid data from one or more segments received from the CPort interface will be continuously written into the shift register sequentially. Thus, the position of the data in the shift register corresponds to the order in which it was received. This ensures that the order of valid data in one or more segments of the constituent message output by the CPort alignment unit is the same as the order in which the message was received from the CPort interface.

[0087] When receiving a segment that indicates a valid RxDataSom signal (the first segment of the message), the shift register is completely empty, allowing all data in that segment to be completely recorded. However, if the segment (denoted as S2) received by the CPort alignment unit from the CPort interface is not the first segment of the message (without indicating a valid RxDataSom signal), the shift register may not be empty (because it stores valid data from previous segments), and the complete valid data of segment S2 may not be written to the shift register. In this case, the valid data of segment S2 is written to the shift register in sequence (the order of the valid data on the RxData signal lines). In response to the counter full signal, data for the new segment is generated using the filled shift register and written to the FIFO, and the shift register is cleared. Then, the remaining valid data of segment S2 is written to the shift register in sequence.

[0088] If, within one cycle of a segment transmission on the CPort interface, the CPort alignment unit is unable to acquire all valid data for the segment, it generates an invalid RxDataAccept signal for the CPort interface. For example, if the FIFO is full, and the shift register cannot hold all valid data for the segment currently output by the CPort interface, the CPort alignment unit generates an invalid RxDataAccept signal. Optionally, the shift register operates at a frequency higher than the frequency at which the CPort interface transmits segments.

[0089] In response to the FIFO being non-empty, an entry is retrieved from the FIFO, and a new segment is generated based on the content of the entry as the output of the CPort alignment unit (740).

[0090] Figure 8A , Figure 8B and Figure 8C A flowchart illustrating the valid data for the CPort alignment unit alignment segment according to yet another embodiment of this application is provided.

[0091] Figure 8A The flowchart shown is used to extract valid data from segments obtained from the CPort interface and generate FIFO entries for new segments. Figure 8B The demonstrated procedure is for operating the FIFO. Figure 8C The demonstrated process is used to generate FIFO entries for new segments from shift registers.

[0092] See Figure 8AIn response to a segmentation occurring at the CPort interface, valid data is retrieved from the RxData signal (810) based on signals such as RxDataValid, RxData, and RxDataByteEn. It also identifies whether the current segment is the end segment of a message based on, for example, the validity of the RxDataEom signal. If the current segment carries an end marker (a valid RxDataEom signal) (815), the valid data of the current segment is recorded in the shift register (820). For example, based on the indication of the RxDataByteEn signal, the valid data in the RxData signal is added byte by byte to the shift register. In some cases, the shift register is full and cannot be added to temporarily; in this case, adding valid data to the shift register is paused, and the shift register waits for available storage space. It also determines whether all valid data of the current segment retrieved from the CPort interface has been recorded in the shift register (825). If some valid data of the current segment has not yet been moved to the shift register, the process returns to step 820 to continue moving valid data of the current segment to the shift register. If all valid data in the current segment has been moved to the shift register, a valid end marker is also set (830) to generate a new segment to be output, since the current segment carries an end marker. Regardless of whether the current shift register is full, a FIFO entry is generated using the data in the shift register (835), and the generated entry is added to the tail of the FIFO queue. Understandably, in addition to the valid data in the shift register, the generated FIFO entry also includes a ByteEn signal field and an end marker field. The end marker field comes from the end marker set in step 830, while the ByteEn signal field comes from, for example, the current value of the valid data counter.

[0093] This completes the acquisition of segments appearing on the CPort interface. Optionally, the process returns to step 810, waiting for new segments to appear on the CPort interface. Still optionally, in response to the completion of acquiring segments appearing on the CPort interface, a valid signal, such as RxDataAccept, is provided to the CPort interface to indicate successful reception of the current segment. Further optionally, in step 810, an invalid signal, such as RxDataAccept, is also provided to the CPort interface to indicate that reception of the current segment has not yet been completed.

[0094] In some cases, the current segment obtained from the CPort interface carries an end-of-segment marker. After some valid data of this segment is written to the shift register, the shift register becomes full. In response, the data in the shift register is read out and a FIFO entry is generated (steps 830 and 835 are not performed; see also...). Figure 8CHowever, at this point, another portion of valid data in the current segment has not yet been written to the shift register. Therefore, the generated FIFO entry does not include the end marker.

[0095] For step 815, if the current segment does not carry an end marker, the valid data of the current segment is recorded in the shift register (822). In some cases, the shift register is full and cannot be added with more data temporarily. In this case, adding valid data to the shift register is paused, and the shift register is allowed to have available storage space. It is also necessary to determine whether all valid data of the current segment obtained from the CPort interface has been recorded in the shift register (824). If some valid data of the current segment has not yet been moved to the shift register, the process returns to step 822 to continue moving the valid data of the current segment to the shift register. If all valid data of the current segment has been moved to the shift register, the process optionally returns to step 810, waiting for a new segment to appear on the CPort interface.

[0096] In step 820 or 822, if the current segment has a start flag, a valid start flag is also set. When generating FIFO entries based on the valid data in the shift register, the generated FIFO entries also include a start flag field. The start flag field comes from the start flag set in step 820 or 822. Therefore, a FIFO entry may include both a start flag and an end flag.

[0097] See Figure 8B See also Figure 6 The CPort signal output unit performs corresponding processing based on the various states of the FIFO. If the FIFO is detected as not empty, an entry is retrieved from the head of the FIFO queue, a new segment is generated based on the FIFO entry, and then output. The output segment also conforms to the UniPro protocol, thus allowing the receiver (e.g., an application) coupled to the CPort alignment unit to receive the segments provided by the CPort signal output unit according to the UniPro protocol. The CPort alignment unit can be regarded as the CPort interface without the recipient being aware of its existence. If the FIFO is detected as full, it cannot accommodate any new entries before retrieving and outputting entries. Therefore, an invalid RxDataAccept signal is generated and provided to the CPort interface to temporarily prevent the CPort interface from providing new segments to the CPort alignment unit, and also to keep the segments currently provided to the CPort alignment unit valid and waiting to be received.

[0098] See Figure 8C See also Figure 6In addition to generating FIFO entries using the shift register after receiving all valid data of the segment with the end marker, FIFO entries are also generated based on the data in the shift register when it is full. If the shift register is not full and not all valid data of the segment with the end marker has been received, there is no need to read the data buffered in the shift register. Optionally, in response to the shift register being full, an invalid RxDataAccept signal is also generated and provided to the CPort interface to temporarily prevent the CPort interface from providing new segments to the CPort alignment unit.

[0099] The CPort signal output unit also identifies signals such as the new_RxDataAccept signal provided by the unit receiving its output (e.g., an application). If the new_RxDataAccept signal is invalid, the CPort signal output unit suspends entry acquisition from the FIFO and optionally retains the current output segment.

[0100] The above description, using the example of obtaining segments from the CPort interface and providing new segments with valid data alignment to a receiver such as an application, illustrates a CPort alignment unit according to an embodiment of this application. Those skilled in the art will understand that embodiments of this application are also used to process segments provided from an application to the CPort interface, obtaining segments from the application, and providing new segments with valid data alignment to the CPort interface of, for example, a UniPro unit.

[0101] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application. Clearly, those skilled in the art can make various alterations and variations to this application without departing from its spirit and scope. Thus, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A CPort alignment unit comprising a shift register, a valid data counter, a FIFO write control unit, a FIFO and CPort signal output unit; the shift register buffers valid data of a received CPort segment; the valid data counter counts the valid data buffered in the shift register; the FIFO write control unit writes data of the shift register into the FIFO in response to the received CPort segment carrying a valid end flag and all valid data of the received CPort segment being written into the shift register; and the CPort signal output unit takes an entry from the FIFO and generates a valid data aligned CPort segment based on the entry; and adds an entry to the tail of the FIFO, the added entry having a data field recording data from the shift register, a valid data flag field from the valid data counter, and each bit of the valid data flag field indicating whether a corresponding byte of the data field of the added entry is valid data.

2. The CPort alignment unit of claim 1, wherein the shift register is coupled to a data signal as an input of the CPort alignment unit; a CPort segment is identified in response to a data valid signal, and valid data in the data signal of the CPort segment is identified based on a valid data flag and written into the shift register byte by byte.

3. The CPort alignment unit of claim 1 or 2, wherein the FIFO write control unit writes data of the shift register into the FIFO in response to a counter count full signal generated by the valid data counter or the shift register being full, to add an entry to the tail of the FIFO, the added entry having a data field and a valid data flag field, the data field of the added entry recording data from the shift register, and the valid data flag field of the added entry indicating that each byte of the data field of the added entry is valid data.

4. The CPort alignment unit of claim 3, wherein a valid end flag is set in response to the received CPort segment carrying a valid end flag and in response to all valid data of the received CPort segment being written into the shift register; when the FIFO write control unit writes data of the shift register into the FIFO, the end field is set in the added entry and the valid end flag is cleared if the valid end flag exists.

5. The CPort alignment unit of claim 4, wherein the CPort signal output unit takes an entry from the head of the FIFO and generates a valid data aligned CPort segment based on the entry in response to the FIFO not being empty; wherein ​ ​ According to the data field and the valid data flag field of the entry, a data signal of the CPort segment after valid data alignment and a valid data flag are generated respectively.

6. A UFS device comprising a UniPro unit, an application unit and a CPort alignment unit according to any one of claims 1-5; the CPort alignment unit is coupled to a CPort interface of the UniPro unit and the application unit.

7. A method for CPort valid data alignment, comprising: receiving a CPort segment; writing valid data of the CPort segment into a shift register one by one; if the received CPort segment carries a valid end flag and all valid data of the received CPort segment are written into the shift register, generating an entry with data of the shift register and writing the entry into a FIFO; retrieving the entry from the FIFO and generating a CPort segment after valid data alignment according to the retrieved entry; counting valid data buffered in the shift register by a valid data counter; and adding an entry to the tail of the FIFO, the data field of the added entry recording data from the shift register, the valid data flag field of the added entry coming from the valid data counter, and each bit of the valid data flag field of the added entry indicating whether each byte of the data field of the added entry is valid data.

8. The method of claim 7, further comprising: if the CPort segment carries a start flag, setting a valid start flag; when generating the entry with data of the shift register and writing the entry into the FIFO, if the valid start flag exists, setting a start flag field in the generated entry and clearing the valid start flag.

9. The method of claim 7 or 8, further comprising: if the CPort segment carries an end flag, setting a valid end flag in response to all valid data of the CPort segment being written into the shift register; when generating the entry with data of the shift register and writing the entry into the FIFO, if the valid end flag exists, setting an end field in the generated entry and clearing the valid end flag.

10. The method of claim 9, further comprising: if the CPort segment carries an end flag, and if part but not all valid data of the CPort segment is written into the shift register and the shift register is full, not setting the valid end flag; when generating the entry with data of the shift register and writing the entry into the FIFO, not setting an end field in the generated entry.

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