monitor

Abstract

A display includes a plurality of pixel devices coupled in series. The plurality of pixel devices include a first and a second pixel device. The first pixel device includes a first control circuit and a first light-emitting circuit. The first control circuit is used to generate a first light-emitting signal according to a first clock signal and a data signal during a first period. The first light-emitting circuit is coupled to the first control circuit and is used to emit light during a second period and a third period according to the first light-emitting signal. The second pixel device includes a second control circuit and a second light-emitting circuit. The second control circuit is used to generate a second light-emitting signal according to a second clock signal and a data signal during a second period. The second light-emitting circuit is coupled to the second control circuit and is used to emit light during a third period according to the second light-emitting signal. The first to third periods are arranged sequentially and continuously.

Description

Technical Field

[0001] The invention relates to a display technology, and in particular to a display. Background Art

[0002] Traditional light-emitting diode (LED) displays use passive matrix (PM) drive to control the brightness and ratio of pixels. However, the demand for ultra-fine pitch (UFP) of LED displays has increased greatly, and the corresponding integrated circuit (IC) is a highly integrated IC. The IC needs to be connected to multiple pixel devices, which leads to the following problems. The circuit layout of the display is quite complicated and may require a multi-layer printed circuit board (PCB) to implement. When the pitch is less than 0.6 mm, the process technology of the driver IC and PCB will encounter bottlenecks, which is not conducive to market promotion. PM drive is a scanning method to perform multiplexing and instantaneous lighting of LEDs, which is prone to flickering problems. A large number of scans require a higher switching speed of the LED. The power requirement of the IC connecting multiple pixel devices is high. Therefore, how to develop related technologies that can overcome the above problems is an important topic in this field. Summary of the invention

[0003] An embodiment of the present invention includes a display including a plurality of pixel devices coupled in series. The plurality of pixel devices include a first pixel device and a second pixel device. The first pixel device includes a first control circuit and a first light-emitting circuit. The first control circuit is used to generate a first light-emitting signal according to a first clock signal and a data signal during a first period. The first light-emitting circuit is coupled to the first control circuit, and is used to emit light during a second period and a third period according to the first light-emitting signal. The second pixel device includes a second control circuit and a second light-emitting circuit. The second control circuit is used to generate a second light-emitting signal according to a second clock signal and a data signal during the second period. The second light-emitting circuit is coupled to the second control circuit, and is used to emit light during the third period according to the second light-emitting signal. The first to third periods are arranged sequentially and continuously.

[0004] In some embodiments, the first control circuit is also used to generate a first light-emitting signal in a fourth period according to the first clock signal and the data signal, the first light-emitting circuit is also used to emit light in a fifth period according to the first light-emitting signal, the second light-emitting circuit is also used to emit light in the fourth period according to the second light-emitting signal, and the first to fifth periods are arranged sequentially and continuously.

[0005] In some embodiments, the light-emitting operation of the first light-emitting circuit in the second period and the third period corresponds to a first bit of the data signal, and the light-emitting operation of the first light-emitting circuit in the fifth period corresponds to a second bit of the data signal.

[0006] In some embodiments, the second control circuit is further used to generate a second light-emitting signal according to the second clock signal and the data signal during the fifth period, the second light-emitting circuit is further used to emit light during a sixth period according to the second light-emitting signal, and the first to sixth periods are arranged sequentially and continuously.

[0007] In some embodiments, the light-emitting operation of the first light-emitting circuit and the second light-emitting circuit in the third period corresponds to a first bit of the data signal, and the light-emitting operation of the first light-emitting circuit and the second light-emitting circuit in the sixth period corresponds to a second bit of the data signal.

[0008] In some embodiments, the first lighting circuit does not emit light during the fourth period.

[0009] In some embodiments, the first light emitting circuit is further configured to emit light in a fourth period according to the first light emitting signal, and the light emitting operation of the first light emitting circuit in the second to fourth periods corresponds to a first bit of the data signal.

[0010] In some embodiments, the first control circuit is also used to generate a first light-emitting signal in a fourth period according to the first clock signal and the data signal, and the first light-emitting circuit is also used to emit light in a fifth period according to the first light-emitting signal. The first to fifth periods are arranged sequentially and continuously, and the time length of the first to third periods is twice the time length of the fourth to fifth periods.

[0011] In some embodiments, the first control circuit is further used to control the first light-emitting circuit according to the first to N bits of the data signal during the first to Nth write periods in a frame time, and the first light-emitting circuit is further used to emit light during the first to Nth light-emitting periods in the frame time according to the first to Nth bits, respectively. The first to Nth write periods and the first to Nth light-emitting periods are alternately arranged in the frame time, and the time length of the Mth write period and the Mth light-emitting period is equal to twice the time length of the (M+1)th write period and the (M+1)th light-emitting period, wherein N is an integer greater than or equal to two, M is a positive integer less than N, and the first period corresponds to the Mth write period, and the second to third periods correspond to the Mth light-emitting period.

[0012] In some embodiments, the first control circuit is also used to control the first light-emitting circuit according to the first to N bits of the data signal during the first to N write periods in a frame time, and the first light-emitting circuit is also used to emit light during the first to N light-emitting periods in the frame time according to the first to N bits respectively. The first to N write periods and the first to N light-emitting periods are alternately arranged in the frame time, and the time length of each write period and each light-emitting period in the first to N write periods and the first to N light-emitting periods is equal to one-Nth of the time length of the frame time, where N is a positive integer greater than or equal to two, and the first period corresponds to one of the first to N write periods, and the second to third periods correspond to one of the first to N light-emitting periods.

[0013] In some embodiments, the first control circuit is further used to generate a first light-emitting signal in a fourth period and a fifth period according to the first clock signal and the data signal, and the first light-emitting circuit is further used to emit light in a sixth period and a seventh period according to the first light-emitting signal. The first to fourth, sixth, fifth and seventh periods are arranged sequentially and continuously, the time length of the first to third periods is equal to the time length of the fourth and sixth periods, and the time length of the fourth and sixth periods is equal to twice the time length of the fifth and seventh periods.

[0014] In some embodiments, the first control circuit is further used to generate a first light-emitting signal according to the first clock signal and the data signal during an eighth period, the first light-emitting circuit is further used to emit light during a ninth period according to the first light-emitting signal, and to not emit light during a tenth period, the seventh, tenth, eighth and ninth periods are arranged sequentially and continuously, and the time lengths of the fourth and sixth periods are equal to the time lengths of the fifth, seventh and tenth periods.

[0015] In some embodiments, the first control circuit is further used to control the first light-emitting circuit according to the first to (N+M) bits of the data signal during the first to (N+M)th write periods in a frame time, and the first light-emitting circuit is further used to emit light during the first to (N+M)th light-emitting periods in the frame time according to the first to (N+M)th bits, respectively. The first to (N+M)th write periods and the first to (N+M)th light-emitting periods are alternately arranged in the frame time, and the time length of each write period and each light-emitting period in the first to Nth write periods and the first to Nth light-emitting periods is equal to one (N+M)th of the time length of the frame time, and the time length of the (N+L)th write period and the (N+L)th light-emitting period is half of the time length of the (N+L-1)th write period and the (N+L-1)th light-emitting period, wherein N and M are positive integers, and L is a positive integer less than or equal to M.

[0016] In some embodiments, the first light-emitting circuit does not emit light during the first to Mth disable periods in the frame time, the Lth disable period is continuously arranged after the (N+L)th light-emitting period, and the time lengths of the Lth disable period, the (N+L)th writing period and the (N+L)th light-emitting period are equal to one (N+M)th time length of the frame time.

[0017] An embodiment of the present invention includes a display including a plurality of pixel devices coupled in series. The plurality of pixel devices include a first pixel device and a second pixel device. The first pixel device includes a first control circuit and a first light-emitting circuit. The first control circuit is used to output a first bit of a data signal according to a first clock signal during a first period. The first light-emitting circuit is coupled to the first control circuit, and is used to emit light according to the first bit during a second period and a third period. The second pixel device includes a second control circuit and a second light-emitting circuit. The second control circuit is used to output the first bit during the second period according to a second clock signal. The second light-emitting circuit is coupled to the second control circuit, and is used to emit light according to the first bit during a third period and a fourth period. The first control circuit is also used to output a second bit of the data signal according to the first clock signal during the fourth period. The first to fourth periods are arranged sequentially and continuously.

[0018] In some embodiments, the first light-emitting circuit is further used to emit light during a fifth period and a sixth period according to the second bit, the second control circuit is further used to output the second bit during the fifth period according to the second clock signal, the second light-emitting circuit is further used to emit light during the sixth period according to the second bit, and the first to sixth periods are arranged sequentially and continuously.

[0019] In some embodiments, the first light emitting circuit is further configured to emit light in a fourth period according to the first bit, and the second light emitting circuit is further configured to emit light in a fifth period according to the first bit.

[0020] In some embodiments, the first control circuit is further used to output the first bit, the second bit, and the third to Nth bits of the data signal according to the first clock signal during the first to Nth write periods in a frame time, respectively, where N is an integer greater than or equal to three, and the first light-emitting circuit is further used to emit light during the first to Nth light-emitting periods in the frame time according to the first to Nth bits, respectively, the first to Nth write periods and the first to Nth light-emitting periods are alternately arranged in the frame time, and the first period and the fourth period correspond to the Mth write period and the (M+1)th write period, respectively, and the second to the third periods correspond to the Mth light-emitting period, where M is a positive integer less than N.

[0021] In some embodiments, the time lengths of the Mth writing period and the Mth light emitting period are equal to twice the time lengths of the (M+1)th writing period and the (M+1)th light emitting period.

[0022] In some embodiments, the time length of the Mth writing period and the Mth light-emitting period is equal to the time length of the (M+1)th writing period and the (M+1)th light-emitting period, the time length of the (M+1)th writing period and the (M+1)th light-emitting period is equal to twice the time length of the (M+2)th writing period and the (M+2)th light-emitting period, and M is a positive integer less than (N-1). BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic diagram of a display system according to an embodiment of the present invention;

[0024] Figure 2A is a schematic diagram of a display according to an embodiment of the present invention;

[0025] Figure 2B is a schematic diagram of a display according to an embodiment of the present invention;

[0026] Figure 2C is a schematic diagram of a pixel device group according to an embodiment of the present invention;

[0027] Figure 3 A timing diagram illustrating a light emitting operation of a pixel device according to an embodiment of the present invention;

[0028] Figure 4A A timing diagram illustrating a light emitting operation of a display according to an embodiment of the present invention;

[0029] Figure 4B A timing diagram illustrating a light emitting operation of a display according to an embodiment of the present invention;

[0030] Figure 5A A timing diagram illustrating a light emitting operation of a display according to an embodiment of the present invention;

[0031] Figure 5B A timing diagram illustrating a light emitting operation of a display according to an embodiment of the present invention;

[0032] Figure 6 A timing diagram illustrating a light emitting operation of a pixel device according to an embodiment of the present invention;

[0033] Figure 7 A timing diagram illustrating a light emitting operation of a pixel device according to an embodiment of the present invention;

[0034] Figure 8 FIG. 4 is a timing diagram illustrating a light emitting operation of a pixel device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0035] In this document, when an element is referred to as "connected" or "coupled", it may refer to "electrically connected" or "electrically coupled". "Connected" or "coupled" may also be used to indicate that two or more elements cooperate or interact with each other. In addition, although the terms "first", "second", etc. are used in this document to describe different elements, the terms are only used to distinguish between elements or operations described by the same technical terms. Unless the context clearly indicates otherwise, the terms do not specifically refer to or imply an order or sequence, nor are they used to limit the present invention.

[0036] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present invention, and will not be interpreted as an idealized or overly formal meaning unless explicitly defined as such herein.

[0037] The terms used herein are only for the purpose of describing specific embodiments and are not restrictive. As used herein, unless the content clearly indicates, the singular forms "a", "an" and "the" are intended to include plural forms, including "at least one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more related listed items. It should also be understood that when used in this specification, the terms "include" and / or "comprise" specify the presence and / or parts of the features, regions, entireties, steps, operations, elements, but do not exclude the presence or addition of one or more other features, regions, entireties, steps, operations, elements, parts and / or their combinations.

[0038] The following will disclose multiple implementations of the present invention with the accompanying drawings. For the sake of clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit the present invention. In other words, in some implementations of the present disclosure, these practical details are not necessary. In addition, in order to simplify the drawings, some known and commonly used structures and components will be depicted in a simple schematic manner in the drawings.

[0039] Figure 1 FIG. 1 is a schematic diagram of a display system 100 according to an embodiment of the present invention. Figure 1 As shown, the display system 100 includes a signal source 110 , a signal controller 120 , a timing controller 130 and a display 140 .

[0040] In some embodiments, the signal source 110 is used to provide a signal, such as a High Definition Multimedia Interface (HDMI) signal and / or a Digital Visual Interface (DVI) signal. The signal controller 120 is used to operate according to the signal provided by the signal source, for example, using a Serial Peripheral Interface Bus (SPI), an Inter-Integrated Circuit (I2C) and / or a Low-Voltage Differential Signaling (LVDS) technology to process the signal. In some embodiments, the signal controller 120 is implemented as an application specific integrated circuit (ASIC) and / or a field programmable gate array (FPGA).

[0041] In some embodiments, the timing controller 130 is used to operate according to the signal processed by the signal controller 120. Figure 1 As shown, the timing controller 130 generates a clock signal CLK and a data signal DT, and outputs the clock signal CLK and the data signal DT through the clock line LC and the data line LD. Different numbers of the clock signal CLK, the data signal DT, the clock line LC and the data line LD are all within the scope of the present invention.

[0042] In some embodiments, the display 140 is coupled to the timing controller 130 via a clock line LC and a data line LD. In some embodiments, the display 140 is used to perform data writing operations and light emitting operations according to the clock signal CLK and the data signal DT.

[0043] Figure 2A FIG. 2 is a schematic diagram of a display 200A according to an embodiment of the present invention. Figure 2A As shown, the display 200A is used to operate according to the clock signals CLK(1)-CLK(n) and the data signals DT(1)-DT(m). Figure 2A and Figure 1 , the display 200A, the clock signals CLK(1)-CLK(n) and the data signals DT(1)-DT(m) are respectively Figure 1 The display 140, the clock signal CLK and the data signal DT are shown in FIG.

[0044] like Figure 2AAs shown, display 200A includes pixel device columns C(1)-C(m) and pixel device rows R(1)-R(n). Each of pixel device columns C(1)-C(m) and pixel device rows R(1)-R(n) includes a plurality of pixel devices. For example, pixel device column C(1) includes pixel devices 210 and 220.

[0045] like Figure 2A As shown, the pixel device rows C(1)-C(m) are used to receive data signals DT(1)-DT(m), and the pixel device rows R(1)-R(n) are used to receive clock signals CLK(1)-CLK(n). For example, the pixel device 210 included in the pixel device row C(1) and the pixel device row R(1) is used to receive the data signal DT(1) and the clock signal CLK(1) for operation. The pixel device 220 included in the pixel device row C(1) and the pixel device row R(2) is used to receive the data signal DT(1) and the clock signal CLK(2) for operation.

[0046] like Figure 2A As shown, each of the plurality of pixel devices in the display 200 includes a control circuit and a light emitting circuit. The control circuit is used to receive a corresponding one of the data signals DT(1)-DT(m) and a corresponding one of the clock signals CLK(1)-CLK(n) to generate a light emitting signal. The light emitting circuit is coupled to the control circuit and performs a light emitting operation according to the light emitting signal.

[0047] like Figure 2A As shown, the pixel device 210 includes a control circuit 212 and a light emitting circuit 214. In some embodiments, the control circuit 212 is used to generate a light emitting signal EM(1) according to a data signal DT(1) and a clock signal CLK(1). The light emitting circuit 214 is coupled to the control circuit 212 and is used to emit light according to the light emitting signal EM(1).

[0048] like Figure 2A As shown, the pixel device 220 includes a control circuit 222 and a light emitting circuit 224. In some embodiments, the control circuit 222 is used to generate a light emitting signal EM(2) according to a data signal DT(1) and a clock signal CLK(2). The light emitting circuit 224 is coupled to the control circuit 222 and is used to emit light according to the light emitting signal EM(2).

[0049] In some embodiments, the light emitting signal EM(1) corresponds to the result of an AND operation between the data signal DT(1) and the clock signal CLK(1), and the light emitting signal EM(2) corresponds to the result of an AND operation between the data signal DT(1) and the clock signal CLK(2).

[0050] exist Figure 2AIn the illustrated embodiment, each of the plurality of control circuits, such as the control circuit 212 or 222, is coupled to the power supply voltage VDD and the ground voltage VG. Each of the plurality of light emitting circuits, such as the light emitting circuit 214 or 224, is coupled to the power supply voltage VDD, but the embodiment of the present invention is not limited thereto. In different embodiments, the control circuit, the light emitting circuit, the power supply voltage VDD, and the ground voltage VG may also be in other coupling relationships.

[0051] In some previous practices, a control circuit connects multiple pixel devices for operation, which makes the current prone to errors and the circuits are complex, requiring a printed circuit board (PCB) with a high number of layers for implementation.

[0052] Compared to the above-mentioned method, the embodiment of the present invention is implemented with an active matrix (AM), and each control circuit is connected to a corresponding light-emitting circuit for operation, for example, the control circuits 212 and 222 are respectively connected to the light-emitting circuits 214 and 224. In this way, the current error is lower, and the circuit complexity is lower, and a PCB with a lower number of layers can be used for implementation, and the cost is also reduced.

[0053] Figure 2B FIG. 2 is a schematic diagram of a display 200B according to an embodiment of the present invention. Figure 2B and Figure 1 , the display 200B is Figure 1 An embodiment of the display 140 is shown. Figure 2B and Figure 2A , the display 200B is Figure 1 A variation of display 200A is shown.

[0054] like Figure 2B As shown, the display 200B includes a source driver 230, a gate driver 240, and a pixel device group 250 including a plurality of pixel devices. In some embodiments, the pixel device group 250 is used to perform a light emitting operation according to signals provided by the source driver 230 and the gate driver 240. In some embodiments, the source driver 230 is used to provide data signals DT(1)-DT(m), and the gate driver 240 is used to provide clock signals CLK(1)-CLK(n).

[0055] like Figure 2B As shown, the pixel device group 250 includes pixel devices 210' and 220'. Figure 2A and Figure 2B , pixel devices 210' and 220' are respectively Figure 2AThe embodiments of the pixel devices 210 and 220 are shown. In some embodiments, the pixel device 210' is used to receive the clock signal CLK(1) and the data signal DT(1), and the pixel device 220' is used to receive the clock signal CLK(2) and the data signal DT(1).

[0056] like Figure 2B As shown, the pixel device 210' includes a control circuit 212' and a light-emitting circuit 214', and the pixel device 220' includes a control circuit 222' and a light-emitting circuit 224'. In some embodiments, the control circuit 212' is used to generate a light-emitting signal EM(1) according to a clock signal CLK(1) and a data signal DT(1). The light-emitting circuit 214' is coupled to the control circuit 212' and is used to emit light according to the light-emitting signal EM(1). The control circuit 222' is used to generate a light-emitting signal EM(2) according to a clock signal CLK(2) and a data signal DT(1). The light-emitting circuit 224' is coupled to the control circuit 222' and is used to emit light according to the light-emitting signal EM(2).

[0057] The display may be an LED display, where pixels are formed by LEDs. Figure 2B As shown, the light-emitting circuit 214' includes three light-emitting elements LR1, LB1 and LG1. The light-emitting circuit 224' includes three light-emitting elements LR2, LB2 and LG2. The light-emitting elements LR2, LB2 and LG2 emit red light, blue light and green light respectively to form pixels. The light-emitting elements LR2, LB2 and LG2 emit red light, blue light and green light respectively to form pixels. The light-emitting elements LR1, LB1, LG1, LR2, LB2 and LG2 can be implemented, for example, by light-emitting diodes or micro light-emitting diodes (Micro LED). In different embodiments, the light-emitting circuits 214' and 224' include other light-emitting elements of different numbers and for emitting different colors of light to form pixels of the display. For example, the light-emitting circuit 224' includes four light-emitting elements LR1, LB1, LG1 and LY1 that emit red light, blue light, green light and yellow light respectively.

[0058] like Figure 2B As shown, in some embodiments, the control circuits 212 ′ and 222 ′ are used to receive the power voltage VDD, and the light emitting elements LR1 , LB1 , LG1 , LR2 , LB2 , and LG2 are used to receive the ground voltage VG.

[0059] In some embodiments, the control circuits 212 ′ and 222 ′ may be implemented by, for example, an integrated circuit (IC) or a micro integrated circuit (Micro IC).

[0060] Figure 2C FIG. 2 is a schematic diagram of a pixel device set 250C according to an embodiment of the present invention. Figure 2B and Figure 2C , the pixel device group 250C is Figure 2B A variation of the pixel device group 250 is shown.

[0061] like Figure 2C As shown, the pixel device group 250 includes pixel devices 210" and 220". Please refer to Figure 2C and Figure 2B , pixel devices 210" and 220" are respectively Figure 2B The pixel device group 250C, the pixel devices 210 ″ and 220 ″ are similar to the pixel device group 250 , the pixel devices 210 ′ and 220 ′, respectively, and thus the similarities are not repeated.

[0062] like Figure 2C As shown, the pixel device 210" includes a control circuit 212" and a light-emitting circuit 214", and the pixel device 220" includes a control circuit 222" and a light-emitting circuit 224". In some embodiments, the control circuit 212" is used to generate a light-emitting signal EM(1) based on a clock signal CLK(1) and a data signal DT(1). The light-emitting circuit 214" is coupled to the control circuit 212", and is used to emit light based on the light-emitting signal EM(1). The control circuit 222" is used to generate a light-emitting signal EM(2) based on a clock signal CLK(2) and a data signal DT(1). The light-emitting circuit 224" is coupled to the control circuit 222", and is used to emit light based on the light-emitting signal EM(2).

[0063] exist Figure 2C In the illustrated embodiment, the control circuits 212 ″ and 222 ″ are used to receive a power voltage VDD and a ground voltage VG, and the light emitting circuits 214 ″ and 224 ″ are used to receive the power voltage VDD.

[0064] Figure 3 A timing diagram 300 is shown for a pixel device according to an embodiment of the present invention for performing a light emitting operation. The timing diagram 300 includes periods P31 to P312 in sequence. In some embodiments, the timing diagram 300 corresponds to Figure 2A For illustrative purposes, Figure 3 In the illustrated embodiment, the clock signal CLK( 1 ) received by the pixel device 210 ′ is taken as an example for description.

[0065] like Figure 3As shown, during the period P31-P34, the clock signal CLK(1) has an enabling voltage level VGH, so that the control circuit 212' generates a light-emitting signal EM(1) according to the first data bit BT(1) of the data signal DT(1). Correspondingly, during the period P35, the light-emitting circuit 214' performs a light-emitting operation corresponding to the first data bit BT(1) according to the light-emitting signal EM(1). In other words, the control circuit 212' outputs the first data bit BT(1) during the period P31-P34, and the light-emitting circuit 214' emits light according to the first data bit BT(1).

[0066] More specifically, during period P31, the control circuit 212' generates a light emitting signal EM(1) corresponding to whether the light emitting element LR1 emits light during period P35 according to the first data bit BT(1). For example, when the data signal DT(1) has an enable voltage level during period P31, that is, the first data bit BT(1) has a logic high level, the light emitting element LR1 emits light during period P35. On the contrary, when the data signal DT(1) has a disable voltage level during period P31, that is, the first data bit BT(1) has a logic low level, the light emitting element LR1 does not emit light during period P35. For more details about the data signal DT(1) and the first data bit BT(1), please refer to Figure 4B The illustrated embodiment is further described.

[0067] Similarly, during period P32, the control circuit 212' generates a light-emitting signal EM(1) corresponding to whether the light-emitting element LG1 emits light during period P35 according to the first data bit BT(1). During period P33, the control circuit 212' generates a light-emitting signal EM(1) corresponding to whether the light-emitting element LB1 emits light during period P35 according to the first data bit BT(1).

[0068] During the period P34, the control circuit 212' generates the light emitting signal EM(1) according to the first data bit BT(1) corresponding to the current received by the light emitting circuit 214' when emitting light. For example, when the data signal DT(1) has an enabling voltage level during the period P34, that is, the first data bit BT(1) has a logic high level, the current flowing through the light emitting circuit 214' during the period P35 has a first current level, so that at least one of the light emitting elements LR1, LG1 and LB1 emits light with a first light intensity. On the contrary, when the data signal DT(1) has a disabling voltage level during the period P34, that is, the first data bit BT(1) has a logic low level, the current flowing through the light emitting circuit 214' during the period P35 has a second current level, so that at least one of the light emitting elements LR1, LG1 and LB1 emits light with a second light intensity. The first current level is different from the second current level, and the first light intensity is different from the second light intensity. In other words, the control circuit 212 ′ adjusts the light intensity of the light emitting circuit 214 ′ in the period P35 according to the first data bit BT( 1 ) in the period P34 .

[0069] During period P36, the clock signal CLK(1) has an enabling voltage level VGH, so that the control circuit 212' generates a light-emitting signal EM(1) according to the second data bit BT(2) of the data signal DT(1). Correspondingly, during period P37, the light-emitting circuit 214' performs a light-emitting operation corresponding to the second data bit BT(2) according to the light-emitting signal EM(1). In other words, the control circuit 212' outputs the second data bit BT(2) during period P36, and the light-emitting circuit 214' emits light according to the second data bit BT(2).

[0070] The operation of the control circuit 212' and the light-emitting circuit 214' corresponding to the second data bit BT(2) during the period P36-P37 is similar to the operation corresponding to the first data bit BT(1) during the period P31-P35. For example, during the period P36, the control circuit 212' generates a light-emitting signal EM(1) corresponding to whether each of the light-emitting elements LR1, LG1 and LB1 emits light during the period P37 based on the second data bit BT(2). Therefore, some details are not repeated.

[0071] During period P38, the control circuit 212' and the light-emitting circuit 214' sequentially perform operations similar to those during periods P36-P37 corresponding to each of the third to (k-1)th data bits BT(3)-BT(k-1), so that the light-emitting circuit 214' sequentially performs light-emitting operations according to each of the third to (k-1)th data bits BT(3)-BT(k-1), wherein k is a positive integer greater than one.

[0072] During periods P39-P310, the control circuit 212' and the light emitting circuit 214' perform operations similar to those during periods P36-P37 corresponding to the (k)th data bit BT(k), so that the light emitting circuit 214' performs light emitting operations according to each of the (k)th data bits BT(k).

[0073] In some embodiments, the time length of the periods P31 to P310 corresponds to a frame time, for example Figure 3 The frame time FT1 is shown.

[0074] In some embodiments, the control circuit 212' and the light emitting circuit 214' perform operations similar to the frame time FT1 during the frame time FT2 after the frame time FT1. For example, during the period P311-P312, the control circuit 212' and the light emitting circuit 214' perform a light emitting operation according to the first data bit BY(1) of the data signal DT(1), wherein the first data bit BY(1) may be different from the first data bit BT(1).

[0075] In some previous methods, in one frame time, the control circuit generates a light signal corresponding to multiple data bits according to multiple data bits of the data signal, and then the light circuit emits light in the frame time according to the light signal. The above method has low flexibility, and the algorithm used to operate the control circuit cannot be changed after the IC circuit design is completed.

[0076] Compared to the above-mentioned method, the embodiment of the present invention divides a frame time into multiple sub-periods, such as periods P31-P35, P36-P37, and P39-P10. In each sub-period, the control circuit 212' and the light-emitting circuit 214' perform a light-emitting operation according to one of the multiple data bits BT(1)-BT(k). In this way, the light-emitting mode of the light-emitting circuit 214' can be updated in each sub-period. Compared to the previous method, the embodiment of the present invention has higher flexibility and can modify the light-emitting mode in conjunction with the algorithm.

[0077] Figure 4A The timing diagram 400A is a timing diagram for illustrating a display 200B in accordance with an embodiment of the present invention for performing a light emitting operation. The timing diagram 400A includes periods Q41 to Q45 in sequence. In some embodiments, the timing diagram 400A corresponds to Figure 2B The signals shown, for example, operate on the data signal DT(1) and the clock signal CLK(1).

[0078] like Figure 4AAs shown, during periods Q42 to Q44, the clock signal CLK(1) has an enabling voltage level VGH, so that the control circuit 212' generates a light-emitting signal EM(1) according to the S-th data bit BT(S) of the data signal DT(1), where S is an integer greater than one. Correspondingly, during period Q45, the light-emitting circuit 214' performs a light-emitting operation according to the light-emitting signal EM(1) corresponding to the S-th data bit BT(S). In some embodiments, during period Q41, the light-emitting circuit 214' performs a light-emitting operation according to the light-emitting signal EM(1) corresponding to the (S-1)-th data bit BT(S-1) of the data signal DT(1).

[0079] like Figure 4A As shown, the clock signal CLK(1) has three pulses, and the three pulses are respectively located in periods Q42-Q44. In some embodiments, the control circuit 212' generates the light emitting signal EM(1) according to the data signal DT(1) and the three pulses in periods Q42-Q44. Further details are given below regarding Figure 4B The embodiments are discussed in the examples.

[0080] In some embodiments, the control circuit 212' is further used to control the current IOUT flowing through the light emitting circuit 214'. In some embodiments, the light emitting circuit 214' is used to start when the current IOUT has a current level I1, and to turn off when the current IOUT has a current level I2. In some embodiments, the current level I1 is higher than the current level I2. In some embodiments, the current level I2 is substantially equal to a zero current level.

[0081] exist Figure 4A In the embodiment shown, during period Q41, the current IOUT has a current level I1, so that the light-emitting circuit 214' emits light according to the light-emitting signal EM(1). During periods Q42-Q44, the current IOUT has a current level I2, so that the light-emitting circuit 214' does not emit light. During period Q45, the current IOUT has a current level I1, so that the light-emitting circuit 214' emits light according to the light-emitting signal EM(1). In other words, during period Q46, the current IOUT has a current level I2, so that the light-emitting circuit 214' emits light according to the light-emitting signal EM(1). Figure 4A In the illustrated embodiment, the pixel device 210 ′ does not emit light when the control circuit 212 ′ writes the data signal DT( 1 ) to generate the light-emitting signal EM( 1 ) according to the clock signal CLK( 1 ).

[0082] Figure 4B The timing diagram 400 is a timing diagram for illustrating the light emitting operation of the display 200B according to an embodiment of the present invention. The timing diagram 400 includes periods P41 to P49 in sequence. In some embodiments, the timing diagram 400 corresponds to Figure 2B The signals shown, for example, operate on the data signal DT(1) and the clock signals CLK(1)-CLK(n).

[0083] Please refer to Figure 4A and Figure 4B , periods P41 to P43 correspond to periods Q42 to Q44 respectively, and periods P45 to P46 correspond to period Q45.

[0084] like Figure 4B As shown, the voltage level of the data signal DT(1) during the periods P41-P46 corresponds to the first data bit BT(1), and the voltage level of the data signal DT(1) during the periods P47-P49 corresponds to the second data bit BT(2).

[0085] like Figure 4B As shown, during the periods P41 to P44, the clock signal CLK(1) has an enabling voltage level VGH, so that the control circuit 212' generates a light-emitting signal EM(1) according to the first data bit BT(1) of the data signal DT(1). Correspondingly, during the periods P45 to P46, the light-emitting circuit 214' performs a light-emitting operation according to the light-emitting signal EM(1) corresponding to the first data bit BT(1).

[0086] like Figure 4B As shown, the clock signal CLK(1) has pulses in periods P41-P44. In some embodiments, the control circuit 212' generates a light-emitting signal EM(1) for controlling whether the light-emitting elements LR1, LG1 and LB1 are activated according to the data signal DT(1) and the three pulses in periods P41-P43. The three pulses in periods P41-P43 correspond to the light-emitting elements LR1, LG1 and LB1, respectively. Figure 4B In the illustrated embodiment, three pulses of the clock signal CLK(1) corresponding to the light emitting elements LR1, LG1 and LB1 are labeled R, G and B respectively.

[0087] More specifically, during period P41, the clock signal CLK(1) has an enabling voltage level VGH, so that the control circuit 212' generates a light-emitting signal EM(1) according to the voltage level of the data signal DT(1) to control the light-emitting operation of the light-emitting element LR1 during periods P45-P46. Figure 4B In the illustrated embodiment, during period P41, the data signal DT(1) has an enabling voltage level VBH. Correspondingly, during periods P45-P46, the light emitting element LR1 is activated to perform a light emitting operation.

[0088] like Figure 4B As shown, during period P42, the clock signal CLK(1) has an enabling voltage level VGH, so that the control circuit 212' generates a light-emitting signal EM(1) according to the voltage level of the data signal DT(1) to control the light-emitting operation of the light-emitting element LG1 during periods P45-P46. Figure 4BIn the illustrated embodiment, during the period P42, the data signal DT(1) has a disable voltage level VBL. Correspondingly, during the periods P45-P46, the light emitting element LG1 is turned off.

[0089] like Figure 4B As shown, during period P43, the clock signal CLK(1) has an enabling voltage level VGH, so that the control circuit 212' generates a light-emitting signal EM(1) according to the voltage level of the data signal DT(1) to control the light-emitting operation of the light-emitting element LB1 during periods P45-P46. Figure 4B In the illustrated embodiment, during period P43, the data signal DT(1) has a disable voltage level VBL. Correspondingly, during periods P45-P46, the light emitting element LB1 is turned off.

[0090] like Figure 4B As shown, during period P44, the clock signal CLK(1) has an enabling voltage level VGH, so that the control circuit 212' generates a light-emitting signal EM(1) according to the voltage level of the data signal DT(1) to control the current flowing through the light-emitting circuit 214' during periods P45-P46. Figure 4B In the illustrated embodiment, during period P44, the data signal DT(1) has an enabling voltage level VBH. Correspondingly, during periods P45-P46, the current flowing through the light-emitting circuit 214' has a first current level, so that the light-emitting element LR1 in the light-emitting circuit 214' emits light at a first light intensity corresponding to the first current level.

[0091] In other embodiments, during period P44, the data signal DT(1) has a disable voltage level VBL. Correspondingly, during periods P45-P46, the current flowing through the light emitting circuit 214' has a second current level, so that the light emitting circuit 214' emits light at a second light intensity corresponding to the second current level.

[0092] like Figure 4B As shown, during period P45, the clock signal CLK(2) has an enabling voltage level VGH, so that the control circuit 222' generates a light-emitting signal EM(2) according to the first data bit BT(1) of the data signal DT(1). Correspondingly, during periods P46-P47, the light-emitting circuit 224' performs a light-emitting operation according to the light-emitting signal EM(2) corresponding to the first data bit BT(1).

[0093] In some embodiments, the operation of the control circuit 222' and the light-emitting circuit 224' according to the clock signal CLK(2) during periods P45-P47 is similar to the operation of the control circuit 212' and the light-emitting circuit 214' according to the clock signal CLK(1) during periods P41-P46, so some details are not repeated.

[0094] like Figure 4B As shown, during period P45, the clock signal CLK(2) has four pulses, wherein the first three pulses correspond to the light-emitting operations of the light-emitting elements LR2, LG2 and LB2 during periods P46-P47. Figure 4B In the illustrated embodiment, the three pulses of the clock signal CLK(2) corresponding to the light emitting elements LR2, LG2 and LB2 are marked with R, G and B respectively.

[0095] like Figure 4B As shown, during period P45, the pulse of the data signal DT(1) corresponding to the light emitting elements LG2 and LB2 has an enabling voltage level VBH, and the pulse of the data signal DT(1) corresponding to the light emitting element LR2 has a disabling voltage level VBL. Correspondingly, during periods P46-P47, the light emitting elements LG2 and LB2 are activated to emit light, and the light emitting element LR2 is turned off.

[0096] In some embodiments, during period P45, the fourth pulse of the clock signal CLK(2) corresponds to the current passing through the light-emitting circuit 224' during periods P46-P47. Figure 4B As shown, the data signal DT(1) has a disable voltage level VBL corresponding to the current pulse. Correspondingly, during the period P46-P47, the current flowing through the light-emitting circuit 224' has a second current level, so that the light-emitting elements LG2 and LB2 in the light-emitting circuit 224' emit light with a second light intensity corresponding to the second current level.

[0097] like Figure 4B As shown, during the period P46, the light-emitting circuits 214' and 224' perform a light-emitting operation according to the first data bit BT(1) of the data signal DT(1).

[0098] In some embodiments, during period P46, other pixel devices in the pixel device group 250 receive the first data bit BT(1) of the data signal DT(1) in sequence according to the clock signals CLK(3)-CLK(n), and correspondingly generate light-emitting signals EM(3)-EM(n) to perform light-emitting operations.

[0099] like Figure 4B As shown, during period P47, the clock signal CLK(1) has an enabling voltage level VGH, so that the control circuit 212' generates a light-emitting signal EM(1) according to the second data bit BT(2) of the data signal DT(1). Correspondingly, during periods P48-P49, the light-emitting circuit 214' performs a light-emitting operation according to the light-emitting signal EM(1) corresponding to the second data bit BT(2).

[0100] In some embodiments, the operations of the control circuit 212' and the light emitting circuit 214' corresponding to the second data bit BT(2) during periods P47-P49 are similar to the operations corresponding to the first data bit BT(1) during periods P41-P46, and thus some details are not repeated.

[0101] like Figure 4B As shown, during period P47, the clock signal CLK(1) has four pulses, wherein the first three pulses correspond to the light-emitting operations of the light-emitting elements LR1, LG1 and LB1 during periods P48-P49. Figure 4B In the illustrated embodiment, the three pulses of the clock signal CLK(2) corresponding to the light emitting elements LR1, LG1 and LB1 are marked with R, G and B respectively.

[0102] like Figure 4B As shown, during period P47, the pulse of the data signal DT(1) corresponding to the light emitting elements LG1 and LB1 has an enable voltage level VBH, and the pulse of the data signal DT(1) corresponding to the light emitting element LR1 has a disable voltage level VBL. Correspondingly, during periods P48-P49, the light emitting elements LG2 and LB2 are turned on to emit light, and the light emitting element LR2 is turned off.

[0103] exist Figure 4B In the illustrated embodiment, during the period P47, the light emitting circuit 214' does not perform a light emitting operation, and the light emitting circuit 224' performs a light emitting operation according to the first data bit BT(1).

[0104] like Figure 4B As shown, during period P48, the clock signal CLK(2) has an enabling voltage level VGH, so that the control circuit 222' generates a light-emitting signal EM(2) according to the second data bit BT(2) of the data signal DT(1). Correspondingly, during period P49, the light-emitting circuit 224' performs a light-emitting operation according to the light-emitting signal EM(2) corresponding to the second data bit BT(2).

[0105] In some embodiments, the operation of the control circuit 222' and the light-emitting circuit 224' according to the clock signal CLK(2) during periods P48-P49 is similar to the operation of the control circuit 212' and the light-emitting circuit 214' according to the clock signal CLK(1) during periods P47-P48, so some details are not repeated.

[0106] like Figure 4B As shown, during period P48, the clock signal CLK(2) has four pulses, wherein the first three pulses correspond to the light-emitting operations of the light-emitting elements LR2, LG2 and LB2 during periods P46-P47. Figure 4BIn the illustrated embodiment, the three pulses of the clock signal CLK(2) corresponding to the light emitting elements LR2, LG2 and LB2 are marked with R, G and B respectively.

[0107] like Figure 4B As shown, during period P48, the pulse of the data signal DT(1) corresponding to the light emitting elements LG2 and LB2 has a disable voltage level VBL, and the pulse of the data signal DT(1) corresponding to the light emitting element LR2 has an enable voltage level VBH. Correspondingly, during period P49, the light emitting elements LG2 and LB2 are turned off, and the light emitting element LR2 is turned on to emit light.

[0108] exist Figure 4B In the illustrated embodiment, during the period P48, the light emitting circuit 224' does not perform a light emitting operation, and the light emitting circuit 214' performs a light emitting operation according to the second data bit BT(2).

[0109] like Figure 4B As shown, during the period P49, the light-emitting circuits 214' and 224' perform a light-emitting operation according to the first data bit BT(2) of the data signal DT(1).

[0110] In some embodiments, during period P49, other pixel devices in the pixel device group 250 sequentially receive the second data bit BT(2) of the data signal DT(1) according to the clock signals CLK(3)-CLK(n), and correspondingly generate light-emitting signals EM(3)-EM(n) to perform light-emitting operations.

[0111] In some embodiments, after the period P49 , the pixel device group 250 performs light emitting operation sequentially according to the third to k-th data bits BT( 3 )-BT(k) of the data signal DT( 1 ).

[0112] In some previous methods, multiple pixel devices in a display receiving the same data signal emit light in turn according to corresponding scanning signals. In the above methods, the light emission time of each pixel device is short, and a higher current is required to maintain the brightness of the display, and there will be a serious strobe problem.

[0113] Compared to the above method, in the embodiment of the present invention, multiple light-emitting circuits in the display 200B emit light simultaneously, for example, the light-emitting circuits 214' and 224' emit light simultaneously during periods P46 and P49. In this way, the current required for light emission is lower, the problem of flicker is less likely to occur, and the image quality is better.

[0114] Figure 5A The timing diagram 500A is a timing diagram for illustrating the light-emitting operation of the display 200B according to an embodiment of the present invention. The timing diagram 500A includes periods Q51 to Q53 in sequence. Figure 4AThe illustrated timing diagram 400A is a variation of the operation of the periods Q51 to Q53. The operation of the periods Q41 to Q45 is similar to the operation of the periods Q52 to Q44, wherein the period Q51 corresponds to the periods Q41 to Q45, and the periods Q51 and Q53 correspond to the periods Q41 and Q45, respectively, so the repeated parts are not repeated.

[0115] exist Figure 5A In the illustrated embodiment, during the periods Q51-Q53, the current IOUT has a current level I1, so that the light emitting circuit 214' emits light according to the light emitting signal EM(1). Figure 5A In the illustrated embodiment, the pixel device 210 ′ continues to emit light when the control circuit 212 ′ writes the data signal DT( 1 ) according to the clock signal CLK( 1 ).

[0116] In different embodiments, the user can select the operation corresponding to the timing diagram 400A or 500A according to different situations, so that the pixel device 210' continues to emit light when the control circuit 212' writes the data signal DT(1) or does not emit light when the control circuit 212' writes the data signal DT(1).

[0117] Figure 5B The timing diagram 500 is a timing diagram of a display 200B according to an embodiment of the present invention for performing a light emitting operation. The timing diagram 500 includes periods P51 to P56 in sequence. Figure 4B The illustrated timing diagram 400 is a variation of the operation of the periods P51 to P56. The operation of the periods P51 to P56 is similar to the operation of the periods P41 to P49, wherein the period P51 corresponds to the periods P41 to P44, and the periods P52 to P56 correspond to the periods P45 to P49, respectively, so the repeated parts are not repeated.

[0118] like Figure 5B As shown, during period P54, the control circuit 212' generates the light-emitting signal EM(1) according to the second data bit BT(2) of the data signal DT(1). At this time, the light-emitting circuit 214' performs a light-emitting operation according to the first data bit BT(1). In other words, the light-emitting circuit 214' performs a light-emitting operation according to the first data bit BT(1) during periods P52-P54.

[0119] Similarly, during period P55, the control circuit 222' generates the light-emitting signal EM(2) according to the second data bit BT(2) of the data signal DT(1). At this time, the light-emitting circuit 224' performs a light-emitting operation according to the first data bit BT(1). In other words, the light-emitting circuit 224' performs a light-emitting operation according to the first data bit BT(1) during periods P53-P55.

[0120] exist Figure 5BIn the illustrated embodiment, during the periods P53-P54, the light emitting circuit 214' and the light emitting circuit 224' perform a light emitting operation according to the first data bit BT(1).

[0121] Compared to Figure 4B ,exist Figure 5B In the illustrated embodiment, the lighting circuits 214' and 224' continue to emit light when the control circuits 212' and 222' generate the lighting signals EM(1) and EM(2) according to the next data bit, and then change the lighting state according to the lighting signals EM(1) and EM(2).

[0122] Figure 6 A timing diagram 600 is shown for a pixel device according to an embodiment of the present invention to perform a light emitting operation. Figure 4B A variation of the timing diagram 400 shown in FIG. 6 is a timing diagram illustrating the operation of the clock signal CLK(1) in the frame time F6. The frame time F6 includes periods P61 to P66 in sequence. The operation of the clock signal CLK(1) in the periods P61 to P64 is similar to the operation in the periods P41 to P49, wherein the period P61 corresponds to the periods P41 to P44, the period P62 corresponds to the periods P45 to P46, the period P63 corresponds to the period P47, and the period P64 corresponds to the periods P48 to P49, so the repeated parts are not repeated.

[0123] like Figure 6 As shown, during period P61, the clock signal CLK(1) has an enabling voltage level VGH, so that the control circuit 212' generates a light-emitting signal EM(1) according to the first data bit BT(1) of the data signal DT(1). Correspondingly, during period P62, the light-emitting circuit 214' performs a light-emitting operation according to the light-emitting signal EM(1) corresponding to the first data bit BT(1).

[0124] Similarly, during the period P63-P64, the pixel device 210' performs a light emitting operation according to the second data bit BT(2) of the data signal DT(1). During the period P65-P66, the pixel device 210' performs a light emitting operation according to the third data bit BT(3) of the data signal DT(1). Figure 6 In the frame time F6 shown, the pixel device 210 ′ performs a light emitting operation in sequence according to the first to k-th data bits BT( 1 )-BT(k) of the data signal DT( 1 ).

[0125] In some embodiments, during the periods P61, P63 and P65, the data signal DT(1) is written into the pixel device 210' to control the light emitting circuit 214', and thus the periods P61, P63 and P65 are referred to as writing periods. During the periods P62, P64 and P66, the light emitting circuit 214' emits light according to the data signal DT(1), and thus the periods P62, P64 and P66 are referred to as light emitting periods.

[0126] In some embodiments, in the frame time F6 , the time lengths of the periods of light emitting operations corresponding to each of the first to k-th data bits BT( 1 )-BT(k) are arranged in descending order.

[0127] For example, the time length of the period P61-P62 corresponding to the first data bit BT(1) is twice the time length of the period P63-P64 corresponding to the second data bit BT(2), and the time length of the period P63-P64 is twice the time length of the period P65-P66 corresponding to the third data bit BT(3). Similarly, in the frame time F6, the time length corresponding to the i-th data bit BT(i) is twice the time length corresponding to the (i+1)-th data bit BT(i+1), where i is a positive integer less than k.

[0128] exist Figure 6 In the embodiment shown, the time length of each of the light-emitting period and the writing period corresponding to the first to kth data bits BT(1)-BT(k) is twice the latter, but the embodiment of the present invention is not limited thereto. In different embodiments, the time length of the light-emitting period and the writing period may also be other multiples.

[0129] Figure 7 A timing diagram 700 is shown for a pixel device according to an embodiment of the present invention to perform a light emitting operation. Figure 6 A variation of the timing diagram 600 shown in FIG. 700 illustrates the operation of the clock signal CLK(1) in the frame time F7. The frame time F7 includes periods P71 to P79 in sequence. The operation of the clock signal CLK(1) in the periods P71 to P76 is similar to the operation in the periods P61 to P66, wherein the periods P71 to P76 correspond to the periods P61 to P66, respectively, and therefore the repeated parts are not repeated.

[0130] like Figure 7As shown, during the period P71-P72, the pixel device 210' performs a light emitting operation according to the first data bit BT(1) of the data signal DT(1). During the period P73-P74, the pixel device 210' performs a light emitting operation according to the second data bit BT(2) of the data signal DT(1). During the period P75-P76, the pixel device 210' performs a light emitting operation according to the third data bit BT(3) of the data signal DT(1). And so on. Figure 7 In the frame time F7 shown, the pixel device 210' performs a light emitting operation in sequence according to the first to k'th data bits BT(1)-BT(k') of the data signal DT(1), where k' is a positive integer. In the period P77, the pixel device 210' performs a light emitting operation according to the fourth to (k'-1)th data bits BT(4)-BT(k'-1) of the data signal DT(1). In the periods P78-P79, the pixel device 210' performs a light emitting operation according to the (k')th data bit BT(k') of the data signal DT(1).

[0131] In some embodiments, during the periods P71, P73, P75 and P78, the data signal DT(1) is written into the pixel device 210' to control the light emitting circuit 214', and thus the periods P71, P73, P75 and P78 are referred to as writing periods. During the periods P72, P74, P76 and P79, the light emitting circuit 214' emits light according to the data signal DT(1), and thus the periods P72, P74, P76 and P79 are referred to as light emitting periods.

[0132] In some embodiments, in the frame time F7, the time length of the period of light emitting operation corresponding to each of the first to k'-th data bits BT(1)-BT(k') is the same. For example, the time lengths of the periods P71-P72 corresponding to the first data bit BT(1), the periods P73-P74 corresponding to the second data bit BT(2), the periods P75-P76 corresponding to the third data bit BT(3), and the periods P78-P79 corresponding to the k'-th data bit BT(k') are the same.

[0133] In some embodiments, the duration of each writing period and each light emitting period is substantially equal to one k' of the duration of the frame time F7. For example, the duration of the periods P71-P72 is k' times the duration of the frame time F7.

[0134] Figure 8 A timing diagram 800 is shown for a pixel device according to an embodiment of the present invention to perform a light emitting operation. Figure 7A variation of the timing diagram 700 is shown. The timing diagram 800 illustrates the operation of the clock signal CLK(1) in the frame time F8. The frame time F8 includes the periods P81-P813 in sequence.

[0135] like Figure 8 As shown, in the frame time F8, the pixel device 210' performs a light emitting operation in sequence according to the first to (N+M)th data bits BT(1)-BT(N+M) of the data signal DT(1), where N and M are positive integers.

[0136] In some embodiments, the period corresponding to each of the first to (N+M)th data bits BT(1)-BT(N+M) includes a writing period and a light-emitting period. For example, periods P83, P85, P87, and P810 correspond to the writing periods of data bits BT(N-1), BT(N), BT(N+1), and BT(N+2), respectively, and periods P84, P86, P88, and P811 correspond to the light-emitting periods of data bits BT(N-1), BT(N), BT(N+1), and BT(N+2), respectively.

[0137] Please refer to Figure 7 and Figure 8 The operations of the data bits BT(1) to BT(N) during the periods P81 to P86 are similar to the operations of the data bits BT(1) to BT(k') during the periods P71 to P79, so the repeated parts will not be described again.

[0138] In some embodiments, the time lengths of each period corresponding to the data bits BT(1) to BT(N) are the same. For example, the time length of the period P81 corresponding to the data bit BT(1), the time length of the period P82 corresponding to the data bit BT(2), the time lengths of the periods P83 to P84 corresponding to the data bit BT(N-1), and the time lengths of the periods P85 to P86 corresponding to the data bit BT(N) are the same.

[0139] like Figure 8 As shown, during period P87, the clock signal CLK(1) has an enabling voltage level VGH, so that the control circuit 212' generates a light-emitting signal EM(1) according to the (N+1)th data bit BT(N+1) of the data signal DT(1). Correspondingly, during period P88, the light-emitting circuit 214' performs a light-emitting operation according to the light-emitting signal EM(1) corresponding to the (N+1)th data bit BT(N+1).

[0140] In some embodiments, the period corresponding to each of the (N+1)th to (N+M)th data bits BT(N+1)-BT(N+M) further includes a disable period. The light-emitting circuit 214' does not emit light during the disable period. For example, the periods P89 and P812 correspond to the disable periods of the data bits BT(N+1) and BT(N+2), respectively. During the periods P89 and P812, the light-emitting circuit 214' does not emit light.

[0141] In some embodiments, the time lengths of the writing period and the light emitting period corresponding to each of the Nth to (N+M)th data bits BT(N)-BT(N+M) are arranged in descending order.

[0142] For example, the time lengths of the write period P85 and the light-emitting period P86 corresponding to the Nth data bit BT(N) are twice the time lengths of the write period P87 and the light-emitting period P88 corresponding to the (N+1)th data bit BT(N+1), and the time lengths of the periods P87-P88 are twice the time lengths of the write period P810 and the light-emitting period P811 corresponding to the (N+2)th data bit BT(3). Similarly, in frame time F8, the time lengths of the write period and the light-emitting period corresponding to the (N+L)th data bit BT(N+L) are half the time lengths of the write period and the light-emitting period corresponding to the (N+L-1)th data bit BT(N+L-1), where L is a positive integer less than or equal to M. In some embodiments, the time lengths of the periods P85-P86 are twice the time lengths of the write period and the light-emitting period in the period P813 corresponding to the (N+M)th data bit BT(N+M). M times.

[0143] In some embodiments, the time lengths of the periods corresponding to each of the data bits BT(1) to BT(N+M) are the same as each other, wherein the period corresponding to each of the data bits BT(1) to BT(N) includes a writing period and a light-emitting period, and the period corresponding to each of the data bits BT(N+1) to BT(N+M) includes a writing period, a light-emitting period, and a disable period.

[0144] For example, the time lengths of the write period P85 and the light-emitting period P86 corresponding to the data bit BT(N), the time lengths of the write period P87, the light-emitting period P88 and the disable period P89 corresponding to the data bit BT(N+1), and the time lengths of the write period P810, the light-emitting period P811 and the disable period P812 corresponding to the data bit BT(N+2) are the same as each other.

[0145] In some embodiments, the time length of the frame time F8 is N+M times the time length of a period corresponding to one of the data bits BT(1) to BT(N+M). For example, the time length of the frame time F8 is equal to N+M times the time length of the period P81 corresponding to the data bit BT(1), and is also equal to N+M times the time length of the periods P87 to P89 corresponding to the data bit BT(N+1).

[0146] In summary, in the embodiment of the present invention, one frame time is divided into a plurality of sub-periods. The light-emitting mode of the light-emitting circuit 214' can be updated in each sub-period, so that the operation of the light-emitting circuit 214' has high flexibility. In addition, in the embodiment of the present invention, a plurality of light-emitting circuits in the display 200B emit light at the same time, for example, the light-emitting circuits 214' and 224' emit light at the same time during periods P46 and P49. In this way, the current required for light emission is lower, the problem of flicker is less likely to occur, and the picture quality is better.

[0147] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person having ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope defined in the attached claims.

Claims

1. A display, characterized in that: A plurality of pixel devices coupled in series are included, the plurality of pixel devices comprising: A first pixel device, comprising: a first control circuit for generating a first light emitting signal according to a first clock signal and a data signal during a first period; and a first light-emitting circuit coupled to the first control circuit and configured to emit light during a second period and a third period according to the first light-emitting signal; and A second pixel device, comprising: a second control circuit for generating a second light emitting signal according to a second clock signal and the data signal during the second period; and a second light emitting circuit, coupled to the second control circuit, and configured to emit light during the third period according to the second light emitting signal; The first period to the third period are arranged sequentially and continuously.

2. The display according to claim 1, characterized in that The first control circuit is further used to generate the first light emitting signal according to the first clock signal and the data signal during a fourth period. The first light-emitting circuit is further configured to emit light during a fifth period according to the first light-emitting signal. The second light emitting circuit is further configured to emit light during the fourth period according to the second light emitting signal, and The first period to the fifth period are arranged sequentially and continuously.

3. The display according to claim 2, characterized in that: The light-emitting operation of the first light-emitting circuit in the second period and the third period corresponds to a first bit of the data signal, and the light-emitting operation of the first light-emitting circuit in the fifth period corresponds to a second bit of the data signal.

4. The display according to claim 2, characterized in that: The second control circuit is further used to generate the second light emitting signal according to the second clock signal and the data signal during the fifth period. The second light emitting circuit is further configured to emit light during a sixth period according to the second light emitting signal, and The first period to the sixth period are arranged sequentially and continuously.

5. The display according to claim 4, characterized in that: The light-emitting operation of the first light-emitting circuit and the second light-emitting circuit in the third period corresponds to a first bit of the data signal, and the light-emitting operation of the first light-emitting circuit and the second light-emitting circuit in the sixth period corresponds to a second bit of the data signal.

6. The display according to claim 2, characterized in that: The first light-emitting circuit does not emit light during the fourth period.

7. The display according to claim 2, characterized in that: The first light emitting circuit is further configured to emit light during the fourth period according to the first light emitting signal, and The light emitting operation of the first light emitting circuit during the second period to the fourth period corresponds to a first bit of the data signal.

8. The display according to claim 1, characterized in that: The first control circuit is further used to generate the first light emitting signal according to the first clock signal and the data signal during a fourth period. The first light-emitting circuit is further configured to emit light during a fifth period according to the first light-emitting signal. The first period to the fifth period are arranged sequentially and continuously, and The time length from the first period to the third period is twice the time length from the fourth period to the fifth period.

9. The display according to claim 1, characterized in that: The first control circuit is also used to control the first light emitting circuit according to the first bit to the Nth bit of the data signal during the first writing period to the Nth writing period in a frame time. The first light emitting circuit is further used to emit light during a first light emitting period to an Nth light emitting period in the frame time according to the first bit to the Nth bit, respectively. The first writing period to the Nth writing period and the first light emitting period to the Nth light emitting period are alternately arranged in the frame time, The time length of the Mth writing period and the Mth luminous period is equal to twice the time length of the (M+1)th writing period and the (M+1)th luminous period, wherein N is an integer greater than or equal to 2, M is a positive integer less than N, and The first period corresponds to the Mth writing period, and the second period to the third period correspond to the Mth light emitting period.

10. The display according to claim 1, characterized in that The first control circuit is also used to control the first light emitting circuit according to the first bit to the Nth bit of the data signal during the first writing period to the Nth writing period in a frame time. The first light emitting circuit is further used to emit light during a first light emitting period to an Nth light emitting period in the frame time according to the first bit to the Nth bit, respectively. The first writing period to the Nth writing period and the first light emitting period to the Nth light emitting period are alternately arranged in the frame time, The time length of each writing period and each luminous period from the first writing period to the Nth writing period and from the first luminous period to the Nth luminous period is equal to one Nth of the time length of the frame time, wherein N is a positive integer greater than or equal to 2, and The first period corresponds to one of the first writing period to the Nth writing period, and the second period to the third period corresponds to one of the first light emitting period to the Nth light emitting period.

11. The display according to claim 1, characterized in that: The first control circuit is further used to generate the first light emitting signal according to the first clock signal and the data signal during a fourth period and a fifth period. The first light-emitting circuit is further used to emit light during a sixth period and a seventh period according to the first light-emitting signal. The first period to the fourth period, the sixth period, the fifth period and the seventh period are arranged in sequence and continuously, the length of time from the first period to the third period is equal to the length of time from the fourth period to the sixth period, and The duration of the fourth period and the sixth period is twice as long as the duration of the fifth period and the seventh period.

12. The display according to claim 11, characterized in that: The first control circuit is further used to generate the first light emitting signal according to the first clock signal and the data signal during an eighth period. The first light-emitting circuit is further configured to emit light during a ninth period according to the first light-emitting signal, and not emit light during a tenth period. The seventh period, the tenth period, the eighth period, and the ninth period are arranged sequentially and continuously, and The duration of the fourth period and the sixth period is equal to the duration of the fifth period, the seventh period and the tenth period.

13. The display according to claim 1, characterized in that: The first control circuit is also used to control the first light emitting circuit according to the first bit to the (N+M)th bit of the data signal during the first writing period to the Nth writing period and the (N+1)th writing period to the (N+M)th writing period in a frame time. The first light emitting circuit is further used to emit light during the first light emitting period to the Nth light emitting period and the (N+1)th light emitting period to the (N+M)th light emitting period in the frame time respectively according to the first bit to the (N+M)th bit. The first writing period to the (N+M)th writing period and the first light emitting period to the (N+M)th light emitting period are alternately arranged in the frame time. The time length of each writing period and each luminous period from the first writing period to the Nth writing period and from the first luminous period to the Nth luminous period is equal to one (N+M)th of the time length of the frame time, and The time length of the (N+L)th writing period and the (N+L)th light-emitting period is half the time length of the (N+L-1)th writing period and the (N+L-1)th light-emitting period, where N and M are positive integers, and L is a positive integer less than or equal to M.

14. The display according to claim 13, characterized in that: The first light-emitting circuit does not emit light during the first disable period to the Mth disable period in the frame time. The Lth disable period is arranged continuously after the (N+L)th light emitting period, and The time lengths of the Lth disable period, the (N+L)th write period, and the (N+L)th light emitting period are equal to one (N+M)th of the time length of the frame time.

15. A display, characterized in that: A plurality of pixel devices coupled in series are included, the plurality of pixel devices comprising: A first pixel device, comprising: a first control circuit for outputting a first bit of a data signal according to a first clock signal during a first period; and a first light-emitting circuit, coupled to the first control circuit, and configured to emit light during a second period and a third period according to the first bit; and A second pixel device, comprising: a second control circuit for outputting the first bit according to a second clock signal during the second period; and a second light emitting circuit, coupled to the second control circuit, and configured to emit light during the third period and a fourth period according to the first bit, The first control circuit is further used to output a second bit of the data signal according to the first clock signal during the fourth period, and The first period to the fourth period are arranged sequentially and continuously.

16. The display according to claim 15, characterized in that The first light emitting circuit is further used to emit light in a fifth period and a sixth period according to the second bit. The second control circuit is further used to output the second bit according to the second clock signal during the fifth period. The second light emitting circuit is further configured to emit light during the sixth period according to the second bit, and The first period to the sixth period are arranged sequentially and continuously.

17. The display according to claim 16, characterized in that The first light emitting circuit is further configured to emit light during the fourth period according to the first bit, and The second light emitting circuit is further configured to emit light during the fifth period according to the first bit.

18. The display according to claim 15, characterized in that The first control circuit is further used to output the first bit, the second bit, and the third bit to the Nth bit of the data signal according to the first clock signal during the first writing period to the Nth writing period in a frame time, wherein N is an integer greater than or equal to three. The first light emitting circuit is further used to emit light during a first light emitting period to an Nth light emitting period in the frame time according to the first bit to the Nth bit, respectively. The first writing period to the Nth writing period and the first light emitting period to the Nth light emitting period are alternately arranged in the frame time, and The first period and the fourth period correspond to the Mth writing period and the (M+1)th writing period respectively, and the second period to the third period correspond to the Mth light emitting period, wherein M is a positive integer less than N.

19. The display according to claim 18, characterized in that The time lengths of the Mth writing period and the Mth light emitting period are equal to twice the time lengths of the (M+1)th writing period and the (M+1)th light emitting period.

20. The display according to claim 18, characterized in that The time lengths of the Mth writing period and the Mth luminous period are equal to the time lengths of the (M+1)th writing period and the (M+1)th luminous period. The time lengths of the (M+1)th writing period and the (M+1)th luminous period are equal to twice the time lengths of the (M+2)th writing period and the (M+2)th luminous period, and M is a positive integer less than (N-1).

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