A memory writing method and writing device

Abstract

The present disclosure provides a memory writing method and writing device. The memory writing method includes: detecting whether a write operation of a first memory cell among a plurality of memory cells of the memory is completed, wherein the plurality of memory cells are respectively used to perform writing of a plurality of write bits of write data in parallel; in response to detecting that the write operation of the first memory cell is completed, independently generating write completion information for the first memory cell; and in response to receiving the write completion information, stopping the write operation of the first memory cell. The memory writing method can detect whether the write operation of the memory cells performing the write operation in parallel is completed, and independently stop the write operation of the memory cell after the write operation of the memory cell is completed, thereby stopping the write driver circuit from continuing to drive the memory cell, reducing the power consumption of the write driver circuit and / or increasing the write speed of the write data.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a memory, and more particularly, to a method and apparatus for writing into a memory. Background Art

[0002] Memory can be used to store various data and is widely used in various electronic devices. The process of storing data in memory is called memory writing process.

[0003] The process of writing to a memory cell essentially involves converting the storage state of a memory cell. For example, for a typical memory, converting the storage state of a memory cell involves converting a high-level state of the memory cell to a low-level state, or vice versa. This conversion of the storage state of a memory cell is typically achieved through a write driver circuit external to the memory. Summary of the Invention

[0004] At least one embodiment of the present disclosure provides a method for writing to a memory, comprising: detecting whether a write operation of a first memory cell among a plurality of memory cells of the memory is completed, wherein the plurality of memory cells are respectively used to execute the writing of a plurality of write bits of write data in parallel; in response to detecting that the write operation of the first memory cell is completed, independently generating write completion information for the first memory cell; and in response to receiving the write completion information, stopping the write operation of the first memory cell.

[0005] At least one embodiment of the present disclosure provides a writing device for a memory, comprising: a writing module and a storage status detection module, wherein the writing module is configured to perform writing operations of multiple writing bits of write data in parallel on multiple storage cells of the memory; the storage status detection module is configured to detect whether the writing operation of a first storage cell among the multiple storage cells of the memory is completed, and in response to detecting that the writing operation of the first storage cell is completed, independently generates writing completion information for the first storage cell; the writing module is also configured to stop the writing operation of the first storage cell in response to receiving the writing completion information.

[0006] At least one embodiment of the present disclosure provides a memory writing device, comprising: a processor; a memory, comprising one or more computer program modules; wherein the one or more computer program modules are stored in the memory and configured to be executed by the processor, and the one or more computer program modules include instructions for executing the memory writing method provided according to at least one embodiment as described above.

[0007] At least one embodiment of the present disclosure provides an electronic device including the memory writing device provided according to at least one embodiment described above.

[0008] At least one embodiment of the present disclosure provides a non-transitory readable storage medium having instructions stored thereon, wherein when the instructions are read by a processor, the processor executes the memory writing method provided according to at least one embodiment as described above.

[0009] In this way, the memory writing method, storage writing device, electronic device and storage medium provided by at least one embodiment of the present disclosure can detect whether the writing operation of the storage unit that performs the writing operation in parallel is completed, and independently stop the writing operation of the storage unit after the writing operation of the storage unit is completed, thereby stopping the write driving circuit from continuing to drive the storage unit, reducing the power consumption of the write driving circuit and / or increasing the writing speed of the write data. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings of the embodiments of the present disclosure. Obviously, the drawings described below only relate to some embodiments of the present disclosure, and are not intended to limit the present disclosure.

[0011] Figure 1 A timing diagram of an exemplary write process is shown.

[0012] Figure 2 A flowchart of a method for writing to a memory according to at least one embodiment of the present disclosure is shown.

[0013] Figure 3 A timing diagram of a write process according to at least one embodiment of the present disclosure is shown.

[0014] Figure 4 A schematic diagram of a memory writing device according to at least one embodiment of the present disclosure is shown.

[0015] Figure 5 A schematic diagram of a memory writing device in an example application scenario according to at least one embodiment of the present disclosure is shown.

[0016] Figure 6 A schematic diagram of a bit address generation module and a bit address storage module according to at least one embodiment of the present disclosure is shown.

[0017] Figure 7 A schematic diagram showing a bit address decoding module according to at least one embodiment of the present disclosure

[0018] Figure 8 A schematic diagram of a storage status detection module according to at least one embodiment of the present disclosure is shown;

[0019] Figure 9 A schematic diagram illustrating a writing device of another memory according to at least one embodiment of the present disclosure is shown;

[0020] Figure 10 A schematic diagram illustrating an electronic device according to at least one embodiment of the present disclosure is shown;

[0021] Figure 11 A schematic diagram of a non-transitory readable storage medium according to at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0022] Reference will now be made in detail to specific embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Although the present disclosure will be described in conjunction with specific embodiments, it will be understood that the disclosure is not intended to be limited to the described embodiments. On the contrary, it is intended to cover variations, modifications, and equivalents within the spirit and scope of the present disclosure as defined by the appended claims. It should be noted that the method operations described herein can be implemented by any functional block or functional arrangement, and any functional block or functional arrangement can be implemented as a physical entity or a logical entity, or a combination of the two.

[0023] In order to enable those skilled in the art to better understand the present disclosure, the present disclosure is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0024] Note that the examples described below are merely specific examples and are not intended to limit the embodiments of the present disclosure to the specific configurations, hardware, connections, operations, values, conditions, data, sequences, etc. shown and described. Those skilled in the art can apply the concepts of the present disclosure to construct further embodiments not described herein by reading this specification.

[0025] The terms used in this disclosure are those commonly used in the art currently in consideration of the functions of the present disclosure, but these terms may vary according to the intentions of those skilled in the art, precedents, or new technologies in the art. In addition, specific terms may be selected by the applicant, and in such cases, their detailed meanings will be described in the detailed description of the present disclosure. Therefore, the terms used in the specification should not be understood as simple names, but rather as a general description based on the meaning of the terms and the present disclosure.

[0026] Flowcharts are used in this disclosure to illustrate the operations performed by the systems according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, the various steps may be processed in reverse order or simultaneously, as needed. Furthermore, other operations may be added to these processes, or one or more operations may be removed from these processes.

[0027] The write process in memory essentially involves switching the storage state of a memory cell. For nonvolatile memory cells, for example, this switching requires a large write current, necessitating a strong drive capability in the write driver circuit. Improving the drive capability of the write driver circuit often comes at the expense of circuit area. Therefore, blindly increasing the drive capability of the write driver circuit is unacceptable for memory chips that require high storage density.

[0028] To address the limitations of insufficient memory drive capability, when writing to the memory, it is necessary to group the memory into multiple memory cell groups, writing to only one memory cell group at a time, thereby reducing the number of memory cells that need to be written in parallel. When writing to a specific memory address, all memory cell groups containing the data to be written (write data) are written serially.

[0029] For example, due to the limitation of the driving capability of the write drive circuit of the memory, it is impossible to write to too many memory cells in parallel at the same time. One solution is to group the memory into a plurality of memory cell groups, and before writing the data to be written to the memory (referred to as "write data" in this article), the write data will first be grouped into a plurality of write bit groups. Among them, each write bit group is written serially to each memory cell group, and each write bit within the write bit group is written in parallel to each memory cell within the memory cell group. The sign that a write bit group completes the write operation is that all memory cells in the corresponding memory cell group have been written to the target state.

[0030] The method for verifying whether a memory cell has been written to a target state is to apply a write voltage to a group of memory cells to be written for a certain period of time at regular clock cycles, then perform a read operation, and then determine whether each memory cell in the memory cell group has been written to the target state. Only after all memory cells in the memory cell group corresponding to a write bit group have been written to the target state will the writing of the next write bit group begin. However, due to the influence of process factors, usage environment, etc. of the memory device, the time required for the storage state conversion during the writing process of different memory cells varies greatly. For example, some memory cells can complete the storage state conversion within a shorter write time, while the storage state conversion of other memory cells often takes longer.

[0031] Therefore, in some aspects of this solution, verification of whether a memory cell has been written to a target state is performed on the memory cell group as a whole, on which write operations are performed in parallel. Furthermore, because write operations to the memory cells are stopped during the verification operation, the verification operation cannot be performed in real time or frequently. This can result in some memory cells in the memory cell group having already been written to the target state when the verification operation is performed after a certain clock cycle. However, at this time, the write driver circuit still applies a drive current or drive voltage to these memory cells, resulting in wasteful power consumption of the write driver circuit.

[0032] In other aspects of the solution, the duration of the write process of a write bit group is determined by the memory cell with the slowest conversion speed. Waiting for the memory cell with the slow conversion speed increases the write time, and it often happens that only individual cells in the memory cell group need to be written under the drive of the write drive circuit, that is, the write drive circuit is often in a state where its performance is not "fully utilized".

[0033] The following combination Figure 1 The above-mentioned solution is described exemplarily.

[0034] Figure 1 A timing diagram 100 of an exemplary write process is shown. Figure 1 The memory's write driver circuit has four ports that can drive write / read operations on four memory cells respectively. Under the control of the clock signal CLK and the write voltage, the four memory cells (memory cell 1, memory cell 2, memory cell 3, and memory cell 4) in the first memory cell group begin writing simultaneously at time t1.

[0035] At time t2, the state of storage cell 1 changes, and the write to storage cell 1 is successful. At time t3, the state of storage cell 2 changes, and the write to storage cell 2 is successful. At time t4, the state of storage cell 3 changes, and the write to storage cell 3 is successful.

[0036] In this example, after each five-clock cycle write process, all memory cells within the memory cell group are verified to have been successfully written. As shown in the figure, at time t5, the four memory cells (memory cell 1, memory cell 2, memory cell 3, and memory cell 4) within the first memory cell group are verified to have been successfully written. Since memory cell 4 has not yet been successfully written, a verification failure occurs, and the write process for memory cell 4 is then continued at time t5' when the verification ends.

[0037] At time t6, the state of storage cell 4 changes, and storage cell 4 is written successfully. Subsequently, at time t7, verification is continued to verify whether the four storage cells (storage cell 1, storage cell 2, storage cell 3, and storage cell 4) in the first storage cell group are written successfully. At this time, storage cell 4 has been written successfully. Therefore, all four storage cells in the first storage cell group are written successfully, and the verification is passed. At time t7' when this verification ends, writing to the second storage cell group can be continued. The second storage cell group will perform the write operation of each storage cell in its group in a similar manner to the first storage cell group.

[0038] according to Figure 1 It can be seen that, in some aspects, taking the first memory cell group as an example, verification of whether each memory cell within the first memory cell group has been written to the target state is performed on all memory cell groups as a whole at the same time (t5 to t5'). In addition, when the verification operation begins at time t5, memory cells 1, 2, and 3 in the memory cell group have already been written to the target state. However, since memory cell 4 in the memory cell group has not yet been written to the target state, the write driver circuit still applies a drive current or a drive voltage to memory cells 1, 2, and 3, resulting in wasteful power consumption of the write driver circuit.

[0039] In other aspects, taking the first storage cell group as an example, the duration of the write process of the first storage cell group is determined by the storage cell 4 with the slowest conversion speed. Waiting for the storage cell 4 with the slow conversion speed increases the write time, and for example, from time t4 to t5 and from t5' to t6, only storage cell 4 needs to be driven by the write drive circuit, which wastes the performance of the write drive circuit.

[0040] In addition, for storage cell 2, before its write operation is completed, the storage state of storage cell 1 may already be the target state to be written (write completed). In this case, the drive resources in the write driver circuit used to drive the write of storage cell 1 enter an idle state. In addition, for storage cell 3, before its write operation is completed, the storage states of storage cells 1 and storage cells 2 may already be the target state to be written. In this case, the drive resources of the write driver circuit used to drive the write of storage cells 1 and 2 enter an idle state. In addition, for storage cell 4, before its write operation is completed, the storage states of storage cells 1, storage cells 2, and storage cells 3 may already be the target state to be written. In this case, the drive resources of the write driver circuit used to drive the write of storage cells 1, storage cells 2, and storage cells 3 enter an idle state. In these cases, even if the write data has not been written yet, that is, when the write operation needs to be performed on subsequent storage cells, only individual cells in the storage cell group need to be written under the drive of the write driver circuit. In other words, the write driver circuit is often in a state where the performance is not "fully utilized", which also wastes the performance of the write driver circuit.

[0041] The inventors of the present application have realized that, on one hand, when a plurality of memory cells are written in parallel, it would be beneficial to independently stop the write driving circuit from driving the memory cells written to the target state.

[0042] On the other hand, when there are limitations on the driving capability of the write drive circuit, it would be beneficial to improve the driving efficiency of the drive circuit. For example, during the design process, it would be beneficial to make the write drive circuit meet the highest possible driving performance requirements or even the highest driving performance requirements (that is, when every storage cell in the storage cell group needs to be written).

[0043] In view of the above-described aspect, at least some embodiments of the present disclosure provide a memory writing method and a writing device, so as to reduce the power consumption of a write driving circuit when a plurality of memory cells perform write operations in parallel.

[0044] The following describes in detail the memory writing method and writing device according to the embodiments of the present disclosure with reference to the accompanying drawings.

[0045] First, a memory writing method according to an embodiment of the present disclosure is introduced below. The memory writing method can be applied to a memory writing device, an electronic device, other suitable software or hardware, or a combination of hardware and software as further described below.

[0046] Figure 2FIG2 is a flowchart of a method 200 for writing into a memory according to at least one embodiment of the present disclosure. The flowchart of the method for writing into a memory in this embodiment may include steps S202 to S206.

[0047] In step S202 , it is detected whether a write operation of a first memory cell among a plurality of memory cells of a memory is completed, wherein the plurality of memory cells are used to execute writing of a plurality of write bits of write data in parallel.

[0048] Here, the first storage unit may be any one of a plurality of storage units to be described and used to perform writing of a plurality of write bits of write data in parallel.

[0049] The write data may be any data to be written to the memory. The write bit of the write data may be a data bit in the write data that needs to be written to the memory cell. For example, the write data may be "01", and the write bit of the write data may be "0" or "1".

[0050] In step S204 , in response to detecting that the write operation to the first memory cell is completed, write completion information is independently generated for the first memory cell.

[0051] In this manner, the write completion information can indicate that the write operation to the first storage unit is complete. For example, when the write operation to the first storage unit is complete, the write completion information can be a high level, a low level, a clock signal, or any other information that can indicate that the write operation to the first storage unit is complete. Thus, the write completion information can be obtained by other software or hardware for subsequent processing.

[0052] In step S206 , in response to receiving the write completion information, the write operation of the first storage unit is stopped.

[0053] For example, see Figure 1 At time t2, the drive of the write drive circuit to the memory cell 1 can be stopped in response to the receipt of the write completion information generated for the memory cell 1. Similarly, at time t3, the drive of the write drive circuit to the memory cell 2 can be stopped in response to the receipt of the write completion information generated for the memory cell 2. Similarly, at time t4, the drive of the write drive circuit to the memory cell 3 can be stopped in response to the receipt of the write completion information generated for the memory cell 3. And so on. In addition, in this case, it is also possible to avoid the failure of the write drive circuit due to the execution of Figure 1 The verification operation shown takes additional time (t5 to t5') to operate, thereby increasing the writing speed of writing data.

[0054] In this way, the memory writing method according to at least one embodiment of the present disclosure can detect whether the writing operation of the storage unit that performs the writing operation in parallel is completed, and independently stop the writing operation of the storage unit after the writing operation of the storage unit is completed, thereby stopping the write driving circuit from continuing to drive the storage unit, reducing the power consumption of the write driving circuit and / or increasing the writing speed of the write data.

[0055] With respect to another aspect described above, at least some embodiments of the present disclosure provide another memory writing method to improve the writing speed and / or improve the driving efficiency of the drive circuit under, for example, limited driving capability of the write drive circuit.

[0056] Another memory writing method may also include referring to Figure 2 Steps S202 and S204 described above. Figure 2 In some embodiments, in response to receiving the write completion information, a write operation is performed on a next storage unit, wherein the next storage unit is used to perform writing of a next write bit out of a plurality of write bits of the write data.

[0057] Thus, according to at least one embodiment of the present disclosure, another memory writing method can execute the writing operation of the next memory cell after the writing operation of the first memory cell among the multiple memory cells that perform writing operations in parallel is completed. According to at least one embodiment of the present disclosure, another memory writing method can execute the writing operation of the next memory cell without waiting for all the writing operations of the multiple memory cells that perform writing operations in parallel to be completed, thereby avoiding the following problems: Figure 1 The storage unit with the slowest storage state conversion in the storage unit group limits the writing time of the storage unit group, thereby improving the writing speed of the writing data.

[0058] In addition, according to at least one embodiment of the present disclosure, another memory writing method allows the writing operation of the next memory cell to be performed after the writing of the first memory cell is completed, thereby allowing the writing driving circuit for driving the writing operation of the memory cell to be in a state of driving as many memory cells as possible in parallel for a longer time, thereby avoiding the following problems: Figure 1 When some memory cell states in a memory cell group are already in the target state (i.e., writing is completed) and there are still write bits of write data that need to be written, part of the performance of the drive circuit is in an "idle" state, resulting in waste or low efficiency of the write drive circuit performance.

[0059] Therefore, according to at least one embodiment of the present disclosure, another memory writing method can improve the writing speed and / or improve the driving efficiency of the driving circuit under, for example, limited driving capability of the write driving circuit.

[0060] The following combination Figure 3 Another memory writing method according to at least one embodiment of the present disclosure is exemplarily described. Figure 3 A timing diagram 300 is shown of a write process according to at least one embodiment of the present disclosure.

[0061] and Figure 1 Similarly, see Figure 3 , the write drive circuit of the memory has four ports, which can also drive the parallel writing (or reading) of 4 memory cells; of course, the 4 ports are just examples, and the embodiments of the present disclosure do not limit the number of ports of the write drive circuit. Under the control of the clock signal CLK and the write voltage, the 4 memory cells (memory cell 1, memory cell 2, memory cell 3 and memory cell 4) start writing at the same time at time t1. Subsequently, at time t2, the state of memory cell 1 changes, and at this time, the writing of memory cell 1 is successful. At time t3, the state of memory cell 2 changes, and at this time, the writing of memory cell 2 is successful. At time t4, the state of memory cell 3 changes, and at this time, the writing of memory cell 3 is successful.

[0062] The following describes the embodiment of the present disclosure and Figure 1 different aspects of the situation.

[0063] See also Figure 3 At time t2, the state of memory cell 1 changes, so the completion / success of the write operation to memory cell 1 can be detected, and information indicating the completion of the write operation to memory cell 1 can be generated. Subsequently, the write operation to memory cell 1 can be stopped, and the write operation to the next memory cell (i.e., memory cell 5) can be performed.

[0064] Similarly, at time t3, the state of memory cell 2 changes, so that the completion / success of the write operation to memory cell 2 can be detected, and information indicating the completion of the write operation to memory cell 2 can be generated. Subsequently, the write operation to memory cell 2 can be stopped, and the write operation to the next memory cell (i.e., memory cell 6) can be performed.

[0065] Similarly, at time t4, the state of memory cell 3 changes, so that the completion / success of the write operation to memory cell 3 can be detected, and information indicating the completion of the write operation to memory cell 3 can be generated. Subsequently, the write operation to memory cell 3 can be stopped, and the write operation to the next memory cell (i.e., memory cell 7) can be executed.

[0066] Similarly, at time t6, the state of memory cell 4 changes, so that the completion / success of the write operation to memory cell 4 can be detected, and information indicating the completion of the write operation to memory cell 4 can be generated. Subsequently, the write operation to memory cell 4 can be stopped, and the write operation to the next memory cell (i.e., memory cell 8) can be performed, and so on.

[0067] It is understood that the storage unit herein is a storage unit for performing a write operation on a corresponding write bit of write data. Exemplarily, the writing of write data can be completed by performing a write operation on 8 storage units. Therefore, after performing the write operation on the 8 storage units, the write data is written to the memory.

[0068] from Figure 3 As can be seen from the example, the write operation to storage cell 5 is executed after the write operation to storage cell 1 is completed, the write operation to storage cell 6 is executed after the write operation to storage cell 2 is completed, the write operation to storage cell 7 is executed after the write operation to storage cell 3 is completed, and the write operation to storage cell 8 is executed after the write operation to storage cell 4 is completed. In this case, at time t1, the write operation to storage cell 1 is completed, and the write operation to the next storage cell (i.e., storage cell 5) can be executed without waiting for the write operations to storage cells 2, 3, and 4 to complete. At this point, four storage cells are being executed in parallel. Similarly, at time t2, the write operation to storage cell 1 is completed, and the write operation to the next storage cell (i.e., storage cell 6) can be executed without waiting for the write operations to storage cells 5, 3, and 4 to complete. Similarly, at time t3, the write operation to storage cell 3 is completed, and the write operation to the next storage cell (i.e., storage cell 7) can be executed without waiting for the write operations to storage cells 5, 6, and 4 to complete. Similarly, at time t6, the write operation of storage unit 4 is completed, and the write operation of the next storage unit (ie, storage unit 8) can be performed without waiting for the completion of the write operations of storage units 5, 6, and 7.

[0069] Therefore, the time it takes to write data into the memory is shortened, and the driving circuit can drive the write operations of as many memory cells as possible for a longer time, thereby improving the writing speed of the write data and / or improving the driving efficiency of the driving circuit.

[0070] In this way, according to Figure 3 In the embodiment, the writing speed of writing data and / or the driving efficiency of the driving circuit are improved by performing the writing operation on the next storage unit after the writing is completed on the first storage unit among the multiple storage units that perform the writing operation in parallel.

[0071] The "parallel" execution of storage units described in this article does not specifically refer to the first storage unit group, that is, it can include not only parallel storage units that start writing operations at the same time, but also multiple storage units that start at different times subsequently but execute writing operations in parallel at a certain time.

[0072] Additional aspects of a method for writing to a memory according to at least one embodiment of the present disclosure are described below.

[0073] In some embodiments, the write operation to the next memory cell can correspond to the same port of the memory's write driver circuit as the write operation to the first memory cell. In this way, the write operation to the next memory cell can replace the driver resources of the first memory cell that has already completed the write operation without affecting or changing the execution of the write driver circuit's write operations on the remaining cells in the multiple memory cells. This reduces computational overhead compared to reallocating the ports of the write driver circuit for multiple memory cells executed in parallel.

[0074] In some embodiments, in response to receiving write completion information, executing the write operation of the next storage unit may include starting to execute the write operation of the next storage unit within the same operation cycle (e.g., clock cycle) or the next operation cycle (e.g., clock cycle) in which the write completion information is received. Typically, the operation cycle is based on the system's clock cycle, such as a single clock cycle or multiple clock cycles. For example, the write operation of the next storage unit may be started immediately after receiving the write completion information. In this way, the write operation of the next storage unit may be executed immediately after the write completion of a certain storage unit, thereby improving the driving efficiency of the driving circuit and increasing the speed at which the write data is written to the memory as a whole. In other embodiments, the write operation of the next storage unit may be started within N clock cycles after receiving the write completion information, where N may be determined based on the performance of the memory (e.g., the difference or difference distribution in the time required for the conversion of the storage states of the various storage units in the memory). For example, N may be 1, 2, 3, etc. In this way, as with reference to Figure 1 Compared with the above method in which writing to the next memory cell group can be performed only after writing to all memory cells in one memory cell group is completed, the driving efficiency of the driving circuit can be improved and the speed at which the write data is written to the memory as a whole can be increased.

[0075] In some embodiments, detecting whether a write operation to a first memory cell among a plurality of memory cells of a memory is complete may include: detecting a write current of the first memory cell among the plurality of memory cells of the memory; and detecting that the write operation to the first memory cell is complete in response to the write current being below a threshold current. It will be appreciated that as the write operation is performed, the write current will gradually decrease or fall, and the decrease in the write current of a memory cell to the threshold current can well indicate that the memory cell has been written to the target state, i.e., the write operation to the memory cell is complete. In this way, it is possible to reliably detect whether the write operation to the memory cell is complete. However, other methods may be used to detect whether the write operation to the memory cell is complete.

[0076] In some embodiments, the number of storage cells in the plurality of storage cells is less than or equal to the maximum number of storage cells that the write driver circuit of the memory can support to perform write operations in parallel. For example, when the drive capability of the write driver circuit can support driving parallel writing of 4 storage cells at most, the number of storage cells in the plurality of storage cells can be 2-4. In this way, the write driver circuit can drive multiple storage cells in parallel, so that the write driver circuit operates efficiently. For example, in combination with Figure 1 and Figure 3 , it is foreseeable that even if Figure 3 Using 2 or 3 storage units to write in parallel may also be faster than Figure 1 The writing method using the memory cell group including four memory cells completes writing of the write data more quickly.

[0077] However, in some cases, in order to complete the writing of the write data more quickly, it would be advantageous to fully utilize the performance of the write driver circuit. In some embodiments, the number of storage cells in the plurality of storage cells is the maximum number of storage cells that the write driver circuit of the memory can support to perform write operations in parallel. For example, when the drive capability of the write driver circuit can drive the parallel writing of up to 4 storage cells, the number of storage cells in the plurality of storage cells is 4. In this way, the write driver circuit can drive as many storage cells as possible in parallel, so that the performance of the write driver circuit is fully utilized.

[0078] In some embodiments, the writing method of the memory according to at least one embodiment of the present disclosure further includes obtaining the write bit address of the next write bit in response to receiving write completion information; decoding the write bit address of the next write bit to generate a switch selection signal; wherein, stopping the write operation of the first storage unit includes: disconnecting the drive connection to the first storage unit based on the switch selection signal; and wherein, performing the write operation of the next storage unit includes: connecting the drive connection to the next storage unit based on the switch selection signal; and applying a write voltage or a write current to the next storage unit.

[0079] Alternatively, in some embodiments, performing a write operation on the next memory cell includes: obtaining a write bit address of the next write bit in response to receiving write completion information; decoding the write bit address of the next write bit to generate a switch selection signal; connecting a drive connection to the next memory cell based on the switch selection signal; and applying a write voltage or a write current to the next memory cell; and wherein stopping the write operation on the first memory cell includes: disconnecting the drive connection to the first memory cell based on the switch selection signal.

[0080] In this way, after receiving the completion of the write operation representing the storage unit, the write bit address of the next write bit can be obtained, and then the write bit address can be decoded to obtain the position of the next storage unit for writing the next write bit. The write bit address of the write bit in this article can indicate the address or position of the storage unit to which the write bit is to be written, so the address or position of the storage unit to be written can be determined based on the write bit address of the write bit. For example, based on the write bit address, the drive connection to the storage unit where the write operation is completed can be disconnected by controlling the drive connection between the write drive circuit and the storage unit and the drive connection to the next storage unit can be connected, so that the write drive circuit applies a write voltage or a write current to the next storage unit to achieve drive. In this way, the drive of the next storage unit can be achieved based on the write completion information.

[0081] In some embodiments, in response to receiving write completion information, obtaining the write bit address of the next write bit includes: generating the write bit address of the next write bit in response to receiving the write completion information; and storing the write bit address of the next write bit to replace the write bit address of the write bit corresponding to the first storage unit.

[0082] It is understood that before the write bit address of the next write bit is saved, the write bit address of the write bit saved and output may include the write bit addresses of the write bits of the multiple storage cells initially written in parallel to the memory. After the write bit address of the next write bit is saved, the write bit output may include the write bit addresses of the write bits of the storage cells initially written in parallel to the multiple storage cells of the memory for which the write operation has not yet been completed, as well as the write bit address of the next write bit. In addition, as time passes, when the write operations of the multiple storage cells initially written in parallel to the memory are all completed, the write bit address of the write bit output may only include the write bit addresses of the multiple next write bits. Therefore, in some embodiments, the number of write bit addresses saved and output may be less than or equal to the maximum number of storage cells that the write driver circuit of the memory can support for parallel write operations. In other embodiments, the number of write bit addresses saved and output may be equal to the maximum number of storage cells that the write driver circuit of the memory can support for parallel write operations. For example, if the maximum drive capability of the write driver circuit can support parallel write operations of 4 storage cells, the number of write bit addresses saved and output is 4.

[0083] As described above, when the write completion information is received, the write bit address of the next write bit is generated. That is, the write completion information can be a control signal that controls the generation of the write bit address of the next write bit. Therefore, in some examples, the write completion information can be, for example, a clock control signal of a register, and when the clock control signal is received, the clock control signal can control the register to output the write bit address of the next write bit.

[0084] However, the embodiments are not limited thereto. In other embodiments, the write bit address of the next write bit is pre-generated based on the write data, and when the write completion information is received, the write bit address of the next write bit can be selected. For example, the write bit address of the next write bit can be randomly selected or selected based on the level of the write bit. In other words, the write completion information can be information for indicating the selection of the write bit address of the next write bit. Therefore, in some examples, multiple write bit addresses of multiple write bits can be pre-generated based on the write data. Multiple write bit addresses can be stored in a memory, for example, and when the write completion information is received, the write bit address of the next write bit is selected from the multiple write bit addresses by, for example, a processor.

[0085] In some embodiments, in response to receiving write completion information, generating a write bit address for the next write bit includes: in response to receiving write completion information, generating a write bit address for the next write bit based on a mask input of the write data. The mask input for the write data can be produced based on a masking technique, and the mask input can indicate which bits of the write data need to be written. In other words, each bit of the mask input indicates whether the value of each write bit of the write data is the same as the value stored in the storage cell corresponding to each write bit. In one example, the write data can be "01". Through the masking technique, it can be determined that the storage cell to which "0" is to be written is already "0", while the storage cell to which "1" is to be written is already "0". In this case, there is no need to write "0" and only "1" needs to be written. Therefore, the mask input for writing the data "01" is the value 01, where the value 0 indicates that the write bit does not need to be written, and the value 1 indicates that the write bit needs to be written. In this way, the number of write bits of the write data can be reduced, and the writing efficiency of the write data can be improved.

[0086] In some embodiments, the memory writing method provided by at least one embodiment of the present disclosure may further include obtaining a mask input of the write data to facilitate reducing the number of write bits of the write data and improving the write efficiency of the write data.

[0087] In some embodiments, obtaining a mask input for write data includes: before writing the write data into a memory, performing the following operations for each write bit of the write data: reading the value of a memory cell corresponding to the write bit; comparing the value of the write bit to the value of the corresponding memory cell to determine whether they are the same; in response to the value of the write bit being the same as the value of the corresponding memory cell, setting a first value for the write bit; in response to the value of the write bit being different from the value of the corresponding memory cell, setting a second value for the write bit; and outputting the value obtained by setting each write bit of the write data as the mask input for the write data. For example, this can be accomplished by performing a bit-by-bit XOR operation on the read value (e.g., binary) and the value to be written (binary), with the result of the operation being the desired mask input. The output here can include outputting the value obtained by setting a write bit each time, or can include outputting the values ​​obtained by setting all write bits together after obtaining them.

[0088] Continuing with the above example, before writing the write data "01" into the memory, the values ​​currently stored in the storage cells corresponding to the write bits "0" and "1" of the write data "01" can be read out as "0" and "0". Then, the write bit "0" can be compared with the value "0" stored in the corresponding storage cell. At this time, the two are the same and can be identified by the first numerical value D1. Similarly, the write bit "1" can be compared with the value "0" stored in the corresponding storage cell. At this time, the two are different and can be identified by the second numerical value D2. Therefore, D1D2 can be output as the mask input of the write data. In this way, the mask input of the write data can be obtained. For example, the read value 00 is subjected to a bit-by-bit XOR operation with the value 01 to be written. The result of the operation is 01, which can be used as the mask input, where the position of 0 indicates the same and the position of 1 indicates different. However, the embodiment is not limited to this, and the mask input of the write data can also be obtained in other ways.

[0089] In some embodiments, the first value is 0, and the second value is 1. Continuing with the above example, the mask input for the write data is 01, where 0 indicates that the corresponding memory cell does not need to be written, and 1 indicates that the corresponding memory cell needs to be written. In this way, the position of the write bit in the write data that requires a write operation to the corresponding memory cell can be simply represented, facilitating subsequent determination of the position of the corresponding memory cell based on this.

[0090] Corresponding to the memory writing method provided by at least one embodiment of the present disclosure, at least one embodiment of the present disclosure further provides a memory writing device.

[0091] Figure 4 FIG. 4 is a schematic diagram of a memory writing device 400 according to at least one embodiment of the present disclosure.

[0092] Reference Figure 4 According to at least one embodiment of the present disclosure, a memory writing device includes a storage status detection module 402 and a writing module 404 .

[0093] The write module 404 is configured to execute write operations of writing a plurality of write bits of write data in parallel on a plurality of storage cells of the memory.

[0094] The storage status detection module 402 is configured to detect whether a write operation to a first storage unit among a plurality of storage units of the memory is completed, and in response to detecting that the write operation to the first storage unit is completed, independently generate write completion information for the first storage unit.

[0095] The write module 404 is further configured to stop the write operation of the first storage unit in response to receiving the write completion information.

[0096] In this way, the write device of the memory according to at least one embodiment of the present disclosure can detect whether the write operation of the storage unit that performs the write operation in parallel is completed, and independently stop the write operation of the storage unit after the write operation of the storage unit is completed, thereby stopping the write drive circuit from continuing to drive the storage unit, reducing the power consumption of the write drive circuit and / or increasing the writing speed of the write data.

[0097] Additionally or alternatively, in some embodiments, the write module 404 is configured to perform a write operation on a next storage unit in response to receiving write completion information, wherein the next storage unit is used to perform writing of a next write bit out of multiple write bits of write data.

[0098] In this way, the writing speed can be increased and / or the driving efficiency of the driving circuit can be improved under, for example, limited driving capability of the writing driving circuit.

[0099] Other aspects of the memory writing device according to at least one embodiment of the present disclosure are described below.

[0100] In some embodiments, the write operation of the next memory cell and the write operation of the first memory cell may correspond to the same port of the write driving circuit of the memory.

[0101] In some embodiments, in response to receiving write completion information, performing a write operation on the next storage unit may include starting to perform the write operation on the next storage unit within the same operation cycle (e.g., clock cycle) as receiving the write completion information or within the next operation cycle (e.g., clock cycle).

[0102] In some embodiments, the storage state detection module 402 may include a write current detection module configured to detect a change in a write current of a first memory cell among a plurality of memory cells of the memory, and detect completion of a write operation of the first memory cell in response to the write current decreasing to a threshold current.

[0103] In some embodiments, the write module 404 may include a bit address acquisition module, a bit address decoding module, and a write driver circuit. The bit address acquisition module is configured to acquire the write bit address of the next write bit in response to receiving the write completion information. The bit address decoding module is configured to decode the write bit address of the next write bit to generate a switch selection signal; disconnect the drive connection to the first storage unit based on the switch selection signal; and connect the drive connection to the next storage unit based on the switch selection signal. The write driver circuit is configured to apply a write voltage or a write current to the next storage unit. In some embodiments, part or all of the bit address acquisition module, the bit address decoding module, and the write driver circuit may also be outside the write module 404.

[0104] In some embodiments, the bit address acquisition module may include a bit address generation module and a bit address storage module. The bit address generation module is configured to generate a write bit address for the next write bit in response to receiving write completion information. The bit address storage module is configured to store the write bit address for the next write bit to replace the write bit address for the write bit corresponding to the first storage unit.

[0105] In some embodiments, the bit address generation module may include a mask bit address generation module configured to generate a write bit address of a next write bit according to a mask input of write data in response to receiving write information.

[0106] In some embodiments, the mask bit address generation module may include a value setting device module and an output module. The value setting device module is configured to, before writing the write data into the memory, perform the following operations for each write bit of the write data: read the value of the storage cell corresponding to the write bit; compare the value of the write bit with the value of the corresponding storage cell to see if they are the same; in response to the value of the write bit being the same as the value of the corresponding storage cell, set a first value for the write bit; and in response to the value of the write bit being different from the value of the corresponding storage cell, set a second value for the write bit. The output module is configured to output the value obtained by setting each write bit of the write data as a mask input for the write data.

[0107] In some embodiments, the number of memory cells in the plurality of memory cells is the maximum number of memory cells that a write driver circuit of the memory can support to perform write operations in parallel.

[0108] The above is only combined with Figure 4 A portion of a memory writing device according to at least one embodiment of the present disclosure is described, and the remaining portion of the memory writing device may be combined with the present disclosure. Figure 2 The various aspects of the memory writing method described are referenced and cited, and according to the combination of the present disclosure Figure 2The effects of various aspects of the memory writing method described can also be mapped to the combination of the present disclosure Figure 4 The writing device of the memory described above will not be described in detail here.

[0109] Below through Figures 5 to 8 To describe the implementation of the memory writing method or memory writing device provided by at least one embodiment of the present disclosure in an example application scenario. For example, Figures 5 to 8 In the example application scenario described, the write data is 32 bits, and the write drive circuit supports parallel write operations of 4 storage units. In order to facilitate understanding, detailed modules / units and specific circuits are shown in the example application scenario. However, it can be understood that these Figures 5 to 8 The various methods described are merely exemplary or optional specific implementations, and the present disclosure is not limited thereto.

[0110] It is understandable that, combined with Figure 5 Aspects and combinations of descriptions Figure 2 and Figure 4 The various aspects described may be referenced from one another without departing from the scope of the present disclosure.

[0111] Figure 5 A schematic diagram of a memory writing device 500 in an exemplary application scenario according to at least one embodiment of the present disclosure is shown.

[0112] See also Figure 5 The writing device 500 includes a bit address generating module 502 , a bit address storing module 504 , a bit address decoding module 506 , a storage unit 508 , a writing driving circuit 510 and a storage status detecting module 512 .

[0113] In some embodiments, the bit address generating module 502, the bit address storing module 504, the bit address decoding module 506, and the write driving circuit 510 can be, for example, Figure 4 The storage status detection module 512 can be used with, for example, Figure 4 The storage status detection module 410 described is the same or similar.

[0114] In some embodiments, the storage unit 508 can be implemented as a memory. Therefore, the storage unit 508 and the memory can be used interchangeably. In some embodiments, the storage unit 508 can be external to the writing device 500.

[0115] The respective modules of the writing device 500 are described below.

[0116] Figure 6Schematic diagram of a bit address generation module 502 and a bit address storage module 504 according to at least one embodiment of the present disclosure is shown.

[0117] See also Figure 6 The bit address generation module 502 includes a MASK register and register update module 602 , a CLZ instruction logic module 604 , an inverting output module 606 , and an address decoding module 608 .

[0118] The main function of the bit address generation module 502 is to generate the address of the write bit in the data based on the write data mask input. For example, if the write data mask input is 32'h0000001f, five of the 32-bit write data mask input bits are 1. The bit address generation module 502 generates these five "1" bits as 5'b00000, 5'b00001, 5'b00010, 5'b00011, and 5'b00100. These five addresses are sequentially output to the bit address storage module 504 on the rising edge of the clock CLK.

[0119] The bit address generation module 502 can be implemented based on a Count Leading Zero (CLZ) instruction logic module 604. The CLZ instruction logic module 604 determines the number of zeros preceding the first "1" in the input data starting from the highest digit. For example, if the 32-bit input data is 32'h0000001f, and there are 27 zeros preceding the first "1," the CLZ instruction logic module 604 will output 6'b011011. If the 32-bit input data is 32'h00000000, the CLZ instruction logic module 604 will output 6'b100000.

[0120] Specifically, at the initial moment, the mask input of the write data is first written into a 32-bit register, namely the MASK register and register update module 602. The MASK register and register update module 602 then transmits the mask input to the input of the CLZ instruction logic module 604. The CLZ instruction logic module 604 outputs the number of "0"s preceding the first bit with a value of "1" in the MASK register and register update module 602. This value is inverted by the inverting output module 606 to obtain the address of the bit with the first "1" in the high-order bit (i.e., the write bit address of the write bit).

[0121] It can be understood that the bit address generation module generates the address of the write bit based on the mask input of the write data. Therefore, the address of the bit where "1" is located here represents the write bit address that needs to convert the state of the corresponding storage unit, and the address of the bit where "0" is located represents the write bit address that does not need to convert the state of the corresponding storage unit.

[0122] The address of this bit is connected to the bit address storage module 504 so that it can be written into the bit address storage module when the next clock rising edge arrives. At the same time, when the clock rising edge arrives, the address of the bit where "1" is located (i.e., the write bit address of the current write bit) will first be decoded and fed back to the MASK register and register update module 602 through the address decoding module 608 to write the data "1" in the address to "0". Therefore, the address corresponding to the second "1" from the high-order bit is output (i.e., the write bit address of the next write bit). Similarly, this address will be written into the bit address storage module 504 when the next clock rising edge arrives and the second "1" in the MASK register and register update module 602 is written to "0", thereby outputting the address of the third "1". Therefore, every time a clock rising edge arrives, the bit address generation module 502 will input the address of the bit where "1" is located in the MASK input of the write data to the bit address storage module 504, that is, the write bit address that represents the state of the corresponding storage unit that needs to be converted. Therefore, the write bit address of the next write bit may be generated according to the mask input of the write data and the write bit address of the current write bit, but the embodiment is not limited thereto.

[0123] After all the addresses of the bits to be written are sent to the MASK register and register update module 602, when another clock arrives, the highest bit output of the CLZ instruction logic module 604 will output "1", indicating that the addresses of all the write bits of the write data have been transmitted to the bit address storage module 504. At this time, the number of storage cells performing the write operation is 4 (the number of storage cells is 4, which corresponds to the drive capability of the write driver circuit supporting parallel write operations of up to 4 storage cells). Therefore, at this time, a counter starts to record the number of clock arrivals. When the counter output is 4, it indicates that the write operation of the last 4 storage cells is complete, that is, the write data has been written into the memory, and a write stop signal can be given.

[0124] It should be noted that when write data begins to be written, the MASK register and register update module 602 needs to transmit the write bit addresses of the four write bits to be written to the storage unit in parallel to the bit address storage module 504. Therefore, the MASK register and register update module 602 needs to receive four clock control signals (CLK) in advance. Subsequently, the clock control signal of the MASK register and register update module 602 is generated by the signal provided by the storage status detection module 512. In other words, the MASK register and register update module 602 pre-generates the write bit addresses corresponding to the number of storage units supported in parallel by the write driver circuit (4 in this example). Subsequently, the clock control signal of the MASK register and register update module 602 is generated by the signal provided by the storage status detection module 512.

[0125] Continue to see Figure 6 The main function of the bit address storage module 504 is to store and simultaneously input multiple bit addresses to the bit address decoding module. If the drive capability of the write driver circuit 510 is sufficient to drive four memory cells in parallel, the bit address storage module 504 can store and output four write bit addresses. For example, after the write operation of a certain memory cell is completed, the bit address storage module 504 can receive the write bit address of the next write bit from the bit address generation module 502 to replace the write bit address of the write bit corresponding to the certain memory cell, thereby maintaining the output of the write bit addresses of the four memory cells.

[0126] The bit address storage module 504 can be directly implemented using registers. For example, for mask input of 32-bit input data, a 5-bit address is required to select each bit, so the shift register in the bit address storage module 504 requires five bits. Furthermore, if the drive capability of the write driver circuit 510 is sufficient to drive four memory cells in parallel, four five-bit registers are required. These four five-bit registers can simultaneously provide four write bit addresses to the bit address decoding module 506, thereby enabling the parallel opening of four memory cells to be written.

[0127] Figure 7 FIG. 5 is a schematic diagram illustrating a bit address decoding module 506 according to at least one embodiment of the present disclosure.

[0128] See also Figure 7 The bit address decoding module 506 includes four decoders 702 , 704 , 706 , and 708 . The bit address decoding module 506 also includes an OR gate logic 710 and an array switch 712 .

[0129] The function of the bit address decoding module 506 is to decode the four write bit addresses provided by the bit address storage module 504 so as to control the switches of the corresponding four storage units to open and connect to the write driving circuit to perform the writing process.

[0130] Because there are four write bit address outputs and four switches are simultaneously enabled, four decoders are required. In this embodiment, the four decoders 702, 704, 706, and 708 are 5-32 decoders. The outputs of the four decoders can be ORed together via an OR logic gate 710 to generate a 32-bit switch selection signal, which simultaneously turns on the write switches of the four memory cells in the array switch 712. This connects the write driver circuit 510 to these four memory cells for a write operation.

[0131] Figure 8 FIG. 5 is a schematic diagram illustrating a storage status detection module 512 according to at least one embodiment of the present disclosure.

[0132] The main function of the storage state detection module 512 is to detect changes in the memory cell write current Vwrite in real time or at other frequencies. When the write current decreases or drops to a certain current threshold, it generates a signal to the bit address generation module 502. This signal serves as a clock control signal for the MASK register and register update module 602 in the bit address generation module 502. When this signal is "1", it controls the output of the next bit address where the MASK register and register update module 602 will be located.

[0133] See also Figure 8 The storage state detection module 512 may include a current mirror structure 804 and an inverter 806 connected to the storage cell 802. The write current is mirrored to the other side of the current mirror 804 via the current mirror 804. As the state of the storage cell 802 changes, that is, the magnitude of the write current changes, the voltage divider on the other side of the current mirror changes, thereby causing the input voltage of the inverter 806 to change and the output voltage to reverse. The output voltage of the inverter 806 can be provided as a signal to the bit address generation module 502 to generate the write bit address of the next write bit.

[0134] return Figure 5 The main function of the write driver circuit 510 is to provide a write drive voltage or a write drive current to the memory cell 508. In some cases, the drive capability of the write driver circuit 510 is positively correlated with the area and power consumption. In some cases, the write driver circuit 510 can be composed of a linear voltage regulator to ensure that there is still sufficient write drive voltage to the load, that is, the memory cell to be written, under a large drive current.

[0135] Based on the above combination Figures 5 to 8 The example writing device 500 described can also be implemented, for example, Figures 1 to 3 The memory writing method and corresponding technical effects described in at least one embodiment of the present disclosure are not repeated here.

[0136] Therefore, combined Figures 5 to 8The described example writing device 500 may not need to group the 32-bit data to be written. First, the 4 bits to be written are selected and written under the drive of the write driver circuit. When the storage state of any storage cell is successfully changed, the storage state detection module will give a signal to stop the write operation of the storage cell, and then start the write operation on the next storage cell. In this way, the power consumption of the write driver circuit can be reduced and / or the writing speed of the written data can be increased. It can avoid the need to group the storage cells of the memory and the limitation of the write time of each storage cell group by the storage cell with the slowest storage state conversion in each storage cell group. It can also avoid the waste of driver performance that occurs when the states of some storage cells in each storage cell group are already in the target state.

[0137] It is understood that the Figures 5 to 8 The number of bits of written data and the number of storage cells supported in parallel by the write driver circuit in the described example writing device 500 can be changed, and the writing device and each module in the writing device can be adaptively modified.

[0138] The various modules / units of the writing device in the above embodiments of the present disclosure may be implemented, for example, by appropriate circuits (eg, analog circuits and / or digital circuits), and the embodiments of the present disclosure are not limited thereto.

[0139] Figure 9 FIG. 1 shows a schematic diagram of a memory writing device 900 according to at least one embodiment of the present disclosure. Figure 9 As shown, the writing device 900 includes a processor 910 and a memory 920. The memory 920 includes one or more computer program modules 921. The one or more computer program modules 921 are stored in the memory 920 and are configured to be executed by the processor 910. The one or more computer program modules 921 include instructions for executing the memory writing method according to at least one embodiment of the present disclosure. When executed by the processor 910, one or more steps of the instruction operation method according to at least one embodiment of the present disclosure and its additional aspects can be performed. The memory 920 and the processor 910 can be interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0140] For example, the processor 910 can be a central processing unit (CPU), a digital signal processor (DSP), or other processing units with data processing capabilities and / or program execution capabilities, such as a field programmable gate array (FPGA). For example, the central processing unit (CPU) can be an X86 or ARM architecture, a RISC-V architecture, etc., and the embodiments of the present disclosure are not limited thereto. The processor 910 can be a general-purpose processor or a dedicated processor, and can control other components in the writing device 900 to perform desired functions.

[0141] For example, the memory 920 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, a flash memory, etc. One or more computer program modules 921 may be stored on the computer-readable storage medium, and the processor 910 may execute one or more computer program modules 921 to implement the various functions of the writing device 900. Various applications and various data, as well as various data used and / or generated by the applications, may also be stored in the computer-readable storage medium. The specific functions and effects of the writing device 900 can be referred to the above description of the memory writing method and its additional aspects according to at least one embodiment of the present disclosure, and will not be repeated here.

[0142] Figure 10 FIG2 is a schematic diagram showing an electronic device 1000 according to at least one embodiment of the present disclosure.

[0143] like Figure 10 As shown, the electronic device 1000 according to at least one embodiment of the present disclosure includes a memory writing device 1010. The writing device 1010 can be a combination of the above Figure 4 The writing device 400 described, combined with Figure 5 The writing device 500 described above or the combination thereof Figure 9 The writing device 900 is described.

[0144] Therefore, for the writing devices of various embodiments of the present disclosure, such as the above-mentioned writing device 500, writing device 800 and writing device 900, various aspects thereof can also be mapped to the combination of Figure 10 The electronic device 1000 described is not described in detail here.

[0145] For example, the electronic device may be a memory controller, or an intermediate or terminal product including the memory controller, such as various types of computers, mobile terminals, televisions, vehicle-mounted terminals, etc., and the embodiments of the present disclosure are not limited to this.

[0146] Figure 11 FIG. 1 shows a schematic diagram of a non-transitory readable storage medium 1100 according to at least one embodiment of the present disclosure. Figure 11 As shown, a non-transitory readable storage medium 1100 stores computer instructions 1110 , which, when executed by a processor, perform one or more steps of the instruction operation method and additional aspects thereof as described above.

[0147] For example, the non-transitory readable storage medium 1100 may be any combination of one or more computer-readable storage media, for example, a computer-readable storage medium containing program code for executing step S202, program code for executing step S204, and program code for executing step S206.

[0148] For example, when the program code is read by a computer, the computer may execute the program code stored in the computer storage medium, and perform, for example, the memory writing method and additional aspects thereof according to at least one embodiment of the present disclosure.

[0149] For example, the storage medium may include a memory card of a smart phone, a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a flash memory, or any combination of the above storage media, or other applicable storage media.

[0150] In the detailed description above, specific details have been set forth for the purpose of explanation rather than limitation, so as to provide a thorough understanding of the various aspects and embodiments described in this disclosure. In some cases, detailed descriptions of well-known devices, components, circuits, and methods have been omitted to avoid obscuring the description of the embodiments disclosed herein with unnecessary details. All statements of the principles, aspects, and embodiments disclosed herein, as well as specific examples thereof, are listed herein, and are intended to cover both their structural equivalents and functional equivalents. In addition, such equivalents are intended to include currently known equivalents and equivalents developed in the future, that is, any elements developed that perform the same function, regardless of the structure. Therefore, for example, it will be understood that the block diagrams herein may represent conceptual diagrams of illustrative circuit systems or other functional units that embody the principles of the described embodiments. Such functions and the functional blocks shown will be understood to be hardware-implemented and / or computer-implemented.

[0151] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0152] It should be noted that, in this article, relational terms such as first, second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also further includes other elements not explicitly listed, or further includes elements that are inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise..." do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.

[0153] The above descriptions are merely preferred embodiments of the present disclosure and are not intended to limit the present disclosure; the scope of the present disclosure is determined by the claims.

Claims

1. A method for writing to a memory, comprising: detecting whether a write operation of a first memory cell among a plurality of memory cells of the memory is completed, wherein any memory cell among the plurality of memory cells is a memory cell for performing a write operation on a corresponding write bit of write data, and the plurality of memory cells are respectively used to perform writing of a plurality of write bits of write data in parallel; In response to detecting completion of the write operation to the first storage unit, independently generating write completion information for the first storage unit; In response to receiving the write completion information, the write operation of the first storage unit is independently stopped.

2. The writing method according to claim 1, further comprising: In response to receiving the write completion information, a write operation of a next storage unit is performed, wherein the next storage unit is used to perform writing of a next write bit out of the plurality of write bits of the write data.

3. The writing method according to claim 2, wherein: The write operation of the next storage unit and the write operation of the first storage unit correspond to the same port of the write driving circuit of the memory.

4. The writing method according to claim 2, wherein: In response to receiving the write completion information, executing the write operation of the next storage unit includes: starting to execute the write operation of the next storage unit within the same operation cycle as receiving the write completion information or within the next operation cycle immediately following the receiving of the write completion information.

5. The writing method according to claim 2, further comprising: In response to receiving the write completion information, acquiring a write bit address of the next write bit; decoding a write bit address of the next write bit to generate a switch selection signal; Wherein, stopping the write operation of the first storage unit includes: disconnecting the drive connection to the first storage unit based on the switch selection signal; Performing a write operation on the next memory cell includes: connecting a drive connection to the next memory cell based on the switch selection signal, and applying a write voltage or a write current to the next memory cell. The writing method according to claim 5 , wherein: In response to receiving the write completion information, obtaining the write bit address of the next write bit includes: In response to receiving the write completion information, generating a write bit address of the next write bit; The write bit address of the next write bit is stored to replace the write bit address of the write bit corresponding to the first storage unit.

7. The writing method according to claim 6, wherein: In response to receiving the write completion information, generating the write bit address of the next write bit includes: In response to receiving the write completion information, a write bit address of the next write bit is generated according to the mask input of the write data.

8. The writing method according to claim 7, further comprising: Obtain a mask input for the write data.

9. The writing method according to claim 8, wherein: Obtaining the mask input of the write data includes: Before writing the write data into the memory, performing the following operations on each write bit of the write data: Reading the value of the memory cell corresponding to the written bit; Comparing whether the value of the written bit is the same as the value of the corresponding storage unit; In response to the value of the write bit being the same as the value of the corresponding storage unit, setting a first value for the write bit; In response to the value of the write bit being different from the value of the corresponding memory cell, setting a second value for the write bit; and A value obtained by setting each write bit of the write data is output as a mask input of the write data.

10. The writing method according to any one of claims 1 to 9, wherein: Detecting whether a write operation of a first storage unit among a plurality of storage units of the memory is completed includes: detecting a write current of a first memory cell among a plurality of memory cells of the memory; and In response to the write current being below a threshold current, completion of the write operation of the first memory cell is detected.

11. A memory writing device, comprising: Writing module and storage status detection module, wherein, The write module is configured to perform write operations of a plurality of write bits of write data in parallel on a plurality of storage units of the memory; The storage status detection module is configured to detect whether a write operation of a first storage unit among a plurality of storage units of the memory is completed, and in response to detecting that the write operation of the first storage unit is completed, independently generate write completion information for the first storage unit, wherein any storage unit among the plurality of storage units is a storage unit for performing a write operation on a corresponding write bit of write data; The write module is further configured to independently stop the write operation of the first storage unit in response to receiving the write completion information.

12. The writing device according to claim 11, wherein The write module is further configured to execute a write operation of the next storage unit in response to receiving the write completion information. The next storage unit is used to write the next write bit outside the multiple write bits of the write data.

13. The writing device according to claim 12, wherein: The write operation of the next storage unit and the write operation of the first storage unit correspond to the same port of the write driving circuit of the memory.

14. The writing device according to claim 12, wherein The write operation of the next storage unit is started to be executed within the same operation cycle or the next operation cycle after the write completion information is received.

15. The writing device according to claim 12, wherein The writing module includes: A bit address acquisition module is configured to acquire a write bit address of the next write bit in response to receiving the write completion information; a bit address decoding module configured to decode the write bit address of the next write bit to generate a switch selection signal, disconnect the driving connection to the first storage unit based on the switch selection signal; and connect the driving connection to the next storage unit based on the switch selection signal; and The write driving circuit is configured to apply a write voltage or a write current to the next memory cell.

16. The writing device according to claim 15, wherein The bit address acquisition module includes: A bit address generating module configured to generate a write bit address of the next write bit in response to receiving the write completion information; and The bit address storage module is configured to store the write bit address of the next write bit to replace the write bit address of the write bit corresponding to the first storage unit.

17. The writing device according to claim 16, wherein: The bit address generation module includes: The mask bit address generation module is configured to generate a write bit address of the next write bit according to the mask input of the write data in response to receiving the write completion information.

18. The writing device according to any one of claims 11 to 17, wherein: The storage status detection module includes: The write current detection module is configured to detect a write current of a first memory cell among the plurality of memory cells of the memory, and detect completion of a write operation of the first memory cell in response to the write current being below a threshold current.

19. A memory writing device, comprising: processor; a memory comprising one or more computer program modules; The one or more computer program modules are stored in the memory and configured to be executed by the processor, and the one or more computer program modules include instructions for executing the memory writing method according to any one of claims 1 to 10.

20. An electronic device comprising the memory writing device according to any one of claims 11 to 18 or claim 19.

21. A non-transitory readable storage medium having stored thereon instructions, in, When the instructions are read by a processor, the processor is caused to execute the method according to any one of claims 1 to 10.

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