Shift register, display panel and driving method of shift register

Abstract

The application discloses a shift register, a display panel and a driving method of the shift register. The shift register comprises an output module, which is used for alternately outputting high and low level signals under the control of a first node and a second node; a first control module, which is used for controlling the potential of the first node; a second control module, which is used for controlling the potential of the second node; a third control module, a first leakage suppression module and a second leakage suppression module connected in series, which are used for controlling the potential of the first node; wherein the first leakage suppression module and the second leakage suppression module are further used for suppressing the leakage of non-effective potential signals to the first node. The shift register can suppress the leakage of non-effective potential to the first node when the potential of the first node is an effective potential, ensure the stability of the potential of the first node, ensure the output module to output accurate level signals, and improve the display effect of the display panel at low frequency.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to shift registers, display panels, and driving methods for shift registers. Background Technology

[0002] With the advancement of display technology, Active Matrix Organic Light Emitting Diode (AMOLED) display panels have become the mainstream of display panel development as a new generation of display technology. AMOLED display panels use gate driving circuits to control data signals to be written line by line into the pixel circuits, thereby enabling the screen to light up.

[0003] However, in low-frequency mode, the output signal of the current gate drive circuit has the problem that the effective potential signal cannot reach the target value, which affects the normal operation of the pixel circuit and the display effect of the display panel. Summary of the Invention

[0004] This invention provides a shift register, a display panel, and a driving method for the shift register, which improves the stability of the gate drive circuit output signal in low-frequency mode and enhances the display effect of the display panel.

[0005] According to one aspect of the present invention, a shift register is provided, including an output module for alternately outputting high and low level signals under the control of a first node and a second node; and a first control module for controlling the potential of the first node;

[0006] The second control module is used to control the potential of the second node;

[0007] The third control module, the first leakage current suppression module, and the second leakage current suppression module, which are connected in series, are used to control the potential of the first node; wherein, the first leakage current suppression module and the second leakage current suppression module are also used to suppress the leakage of ineffective potential signals to the first node.

[0008] Optionally, the output module is further connected to a first potential signal and a first timing signal. The output module responds to the first node to control whether the first timing signal is output, and responds to the second node to control whether the first potential signal is output.

[0009] The first leakage current suppression module is controlled by the first timing signal;

[0010] Both the second leakage current suppression module and the first control module are controlled by input signals;

[0011] The third control module is controlled by the second node;

[0012] Preferably, the second control module is controlled by the first node and the second timing signal.

[0013] Optionally, the second leakage current suppression module includes a control terminal, a first terminal, and a second terminal. The control terminal of the second leakage current suppression module is connected to the input signal, the first terminal of the second leakage current suppression module is connected to a first potential signal, and the second terminal of the second leakage current suppression module is electrically connected to the first leakage current suppression module.

[0014] Optionally, the second leakage current suppression module includes a first transistor, the first terminal of the first transistor is connected to the first potential signal, the second terminal of the first transistor is electrically connected to the first leakage current suppression module, and the gate of the first transistor is connected to the input signal;

[0015] Optionally, the first transistor is a metal-oxide transistor; alternatively, the first transistor is an indium gallium zinc oxide transistor.

[0016] Optionally, the first leakage current suppression module includes a control terminal, a first terminal, and a second terminal. The control terminal of the first leakage current suppression module is connected to the first timing signal. The first terminal of the first leakage current suppression module is electrically connected to the second leakage current suppression module, and the second terminal of the first leakage current suppression module is electrically connected to the third control module.

[0017] Optionally, the first leakage current suppression module includes a second transistor, the first terminal of the second transistor is electrically connected to the second leakage current suppression module, the second terminal of the second transistor is electrically connected to the third control module, and the gate of the second transistor is connected to the first timing signal;

[0018] Optionally, the second transistor is a metal-oxide transistor; alternatively, the second transistor is an indium gallium zinc oxide transistor.

[0019] Optionally, the third control module includes a control terminal, a first terminal, and a second terminal. The control terminal of the third control module is electrically connected to the second node, the first terminal of the third control module is electrically connected to the first leakage current suppression module, and the second terminal of the third control module is electrically connected to the first node.

[0020] Optionally, the third control module includes a third transistor, the first terminal of which is electrically connected to the first leakage current suppression module, the second terminal of which is electrically connected to the first node, and the gate of which is electrically connected to the second node.

[0021] Optionally, the first control module includes a control terminal, a first terminal, and a second terminal. The control terminal of the first control module is connected to the input signal, the first terminal of the first control module is connected to a second potential signal, and the second terminal of the first control module is electrically connected to the first node.

[0022] The second control module includes a first control terminal, a second control terminal, a first terminal, a second terminal, and a third terminal. The first control terminal of the second control module is connected to a second timing signal. The second control terminal of the second control module is electrically connected to the first node. The first terminal of the second control module is connected to a second potential signal. The second terminal of the second control module is connected to a first potential signal. The third terminal of the second control module is electrically connected to the second node.

[0023] Optionally, the first control module includes a fourth transistor, the first terminal of the fourth transistor is connected to the second potential signal, the second terminal of the fourth transistor is electrically connected to the first node, and the gate of the fourth transistor is connected to the input signal;

[0024] Optionally, the second control module includes a fifth transistor and a sixth transistor. The first terminal of the fifth transistor is connected to the second potential signal, the second terminal of the fifth transistor is electrically connected to the second node, and the gate of the fifth transistor is connected to the second timing signal. The first terminal of the sixth transistor is connected to the first potential signal, the second terminal of the sixth transistor is electrically connected to the second node, and the gate of the sixth transistor is electrically connected to the first node.

[0025] Optionally, the output module includes a first control terminal, a second control terminal, a first terminal, a second terminal, and a third terminal. The first control terminal of the output module is electrically connected to the first node, the second control terminal of the output module is electrically connected to the second node, the first terminal of the output module is connected to a first timing signal, the second terminal of the output module is connected to a first potential signal, and the third terminal of the output module serves as the output terminal of the shift register.

[0026] Optionally, the output module includes a seventh transistor, an eighth transistor, a first capacitor, and a second capacitor;

[0027] The first terminal of the seventh transistor is connected to the first timing signal, the second terminal of the seventh transistor is electrically connected to the output terminal of the shift register, the gate of the seventh transistor is electrically connected to the first node, the first terminal of the first capacitor is electrically connected to the second terminal of the seventh transistor, the second terminal of the first capacitor is electrically connected to the gate of the seventh transistor, and the first capacitor is used to couple the potential of the gate of the seventh transistor according to the jump of the first timing signal or the signal at the output terminal of the shift register.

[0028] The first terminal of the eighth transistor is connected to the first potential signal, the second terminal of the eighth transistor is electrically connected to the output terminal of the shift register, the gate of the eighth transistor is electrically connected to the second node, the first terminal of the second capacitor is electrically connected to the first terminal of the eighth transistor, and the second terminal of the second capacitor is electrically connected to the gate of the eighth transistor.

[0029] Optionally, the output module further includes a ninth transistor, the first node being electrically connected to the gate of the seventh transistor via the ninth transistor, and the gate of the ninth transistor being connected to the second potential signal.

[0030] According to another aspect of the present invention, a display panel is provided, including the shift register described in any of the preceding claims.

[0031] Optionally, the shift register of the display panel includes a first timing signal terminal, a second timing signal terminal, an input signal terminal, a first potential signal terminal, a second potential signal terminal, and an output terminal. The output module is electrically connected to the first timing signal terminal and the first potential signal terminal, respectively. The first control module is electrically connected to the input signal terminal and the second potential signal terminal, respectively. The second control module is electrically connected to the second timing signal terminal and the second potential signal terminal, respectively. The second leakage current suppression module is electrically connected to the input signal terminal IN of the next-stage shift register.

[0032] In this case, the first timing signal terminal of the shift register of the 4K+1 stage is connected to the second clock signal, and its second timing signal terminal is connected to the fourth clock signal.

[0033] The first timing signal terminal of the shift register in stage 4K+2 is connected to the third clock signal, and the second timing signal terminal is connected to the first clock signal.

[0034] The first timing signal terminal of the shift register in stage 4K+3 is connected to the fourth clock signal, and the second timing signal terminal is connected to the second clock signal.

[0035] The first timing signal terminal of the shift register of stage 4K+4 is connected to the first clock signal, and the second timing signal terminal is connected to the third clock signal; wherein, K is an integer greater than or equal to zero;

[0036] The first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are shifted sequentially.

[0037] According to another aspect of the present invention, a method for driving a shift register is provided for driving the shift register described in any of the preceding claims; the driving method includes a first setting stage and a second setting stage;

[0038] At the initial moment of the first setting phase, the first control module controls the potential of the first node to switch to an effective potential; the first node controls the output module to output the first level signal; at subsequent moments of the first setting phase, the output module maintains the potential of the first node as effective; the first node controls the output module to output the second level signal and the first level signal sequentially.

[0039] In the first setting stage, the second control module controls the potential of the second node to be an ineffective potential, and the first leakage suppression module and the second leakage suppression module suppress the leakage of ineffective potential signals to the first node.

[0040] In the second setting stage, the second control module controls the potential of the second node to be an effective potential, and the third control module, the first leakage current suppression module and the second leakage current suppression module control the potential of the first node to be an ineffective potential. Under the control of the second node, the output module outputs the first level signal.

[0041] The shift register provided in this embodiment of the invention includes a third control module, a first leakage current suppression module, and a second leakage current suppression module connected in series. This configuration increases the resistance to the transmission of ineffective potential to the first node, reduces leakage current from ineffective potential to the first node, and thus reduces the impact of ineffective potential on the effective potential of the first node. This helps prevent changes to the effective potential of the first node, ensuring the stability of the first node's potential, and consequently ensuring that the output module outputs accurate level signals, improving the display effect of the display panel at low frequencies.

[0042] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a schematic diagram of the structure of a shift register in the prior art;

[0045] Figure 2 This is a schematic diagram of the structure of a shift register provided in an embodiment of the present invention;

[0046] Figure 3 This is a timing diagram of a shift register driver provided in an embodiment of the present invention;

[0047] Figure 4 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0048] Figure 5 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0049] Figure 6 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0050] Figure 7 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0051] Figure 8 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0052] Figure 9 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0053] Figure 10 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention.

[0054] Figure 11 This is a timing diagram of another shift register provided in an embodiment of the present invention;

[0055] Figures 12-19 This is a diagram showing the working state of the shift register in each sub-stage according to an embodiment of the present invention;

[0056] Figure 20 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0057] Figure 21 This is a driving timing diagram of a display panel provided in an embodiment of the present invention;

[0058] Figure 22 This is a simulation waveform diagram of a display panel provided in an embodiment of the present invention;

[0059] Figure 23 This is a flowchart of a shift register driving method provided in an embodiment of the present invention. Detailed Implementation

[0060] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0061] It should be noted that the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or device.

[0062] As described in the background section, existing gate drive circuits suffer from a problem where the output effective potential signal fails to reach the target value, thus affecting the normal operation of the pixel circuit and the display effect of the display panel. The gate drive circuit is composed of cascaded shift registers, and the problem with the output signal of the gate drive circuit is equivalent to the problem with the output signal of the shift registers. The inventors have discovered that the cause of this problem lies in leakage current in some transistors, which will be explained in detail below with reference to the accompanying drawings.

[0063] Figure 1 This is a schematic diagram of the structure of a shift register in the prior art, wherein... Figure 1 The diagram only schematically illustrates the structure of the transistors in the shift register where leakage occurs. (See reference...) Figure 1The shift register includes a first output transistor T11, a second output transistor T12, and a first control transistor T13. The first output transistor T11 and the second output transistor T12 constitute the output module 10. The first output transistor T11 is electrically connected to the second node N2, and the second output transistor T12 is electrically connected to the first node N1. The first output transistor T11 outputs a first potential signal VGH at its output terminal OUT, which is high, based on the conduction of the second node N2. The second output transistor T12 is turned on under the control of the potential of the first node N1, causing the output terminal OUT to output a first timing signal K1. The first control transistor T13 controls the potential of the first node N1. When the first output transistor T11 is off and the second output transistor T12 is on, the shift register output terminal OUT outputs the first timing signal K1. At this time, the first control transistor T13 is turned off, so that the first potential signal VGH is no longer transmitted to the first node N1. However, when the first control transistor T13 is turned off, the leakage current is relatively large. For example, when the effective potential signal of the driving pixel circuit output by the output terminal OUT of the shift register is low, and the signal on the first timing signal K1 is low, in low-frequency mode, the output terminal OUT of the shift register outputs a low level for a long time. This results in a long leakage time of the first control transistor T13, which causes the potential of the first potential signal VGH to rise to the potential of the first node N1, affecting the conduction state of the second output transistor T12. This, in turn, affects the output of the effective potential signal of the driving pixel circuit output by the output terminal OUT of the shift register. As a result, the effective potential signal of the driving pixel circuit may not reach the target value, and the light-emitting module connected to the pixel circuit of the corresponding row driven by the shift register cannot be lit, affecting the display effect.

[0064] To address the aforementioned technical problems, this invention provides a shift register. Figure 2 This is a schematic diagram of a shift register provided in an embodiment of the present invention. (Reference) Figure 2 The shift register includes:

[0065] Output module 10 is used to alternately output a first level signal and a second level signal under the control of the first node N1 and the second node N2;

[0066] The first control module 11 is used to control the potential of the first section N1;

[0067] The second control module 12 is used to control the potential of the second node N2;

[0068] The third control module 13, the first leakage current suppression module 14, and the second leakage current suppression module 15, which are connected in series, are used to control the potential of the first node N1; wherein, the first leakage current suppression module 14 and the second leakage current suppression module 15 are also used to suppress the leakage of ineffective potential signals to the first node N1.

[0069] For example, the first level signal can be a high level, and the second level signal can be a low level. Specifically, a valid potential for the first node N1 means that the first node N1 can control the corresponding transistor in the output module 10 to be turned on; a invalid potential for the first node N1 means that the first node N1 controls the corresponding transistor in the output module 10 to be turned off. A valid potential for the second node N2 means that the second node N2 can control the corresponding transistor in the output module 10 to be turned on; a invalid potential for the second node N2 means that the second node N2 controls the corresponding transistor in the output module 10 to be turned off.

[0070] To illustrate the beneficial effects achieved by the embodiments of the present invention, the working process of the shift register provided by the embodiments of the present invention will be described below in conjunction with specific timing.

[0071] Figure 3 This invention provides a timing diagram for driving a shift register according to an embodiment of the present invention. Figure 3 The timing diagram shown is applicable to Figure 2 In the shift register shown, exemplary in this embodiment, the effective potentials of both the first node N1 and the second node N2 are low. (See reference...) Figure 2 and Figure 3 The shift register's operation includes alternating first setting stage t01 and second setting stage t02. The first setting stage t01 is when the potential of the first node N1 is an effective potential, and the second setting stage t02 is when the potential of the second node N2 is an effective potential.

[0072] Specifically, the first setting stage t01 includes an initial time t011 and a subsequent time t012. At the initial time t011 of the first setting stage t01, the input signal SIN is at a low level. The first control module 11 responds to the low level of the input signal SIN by controlling the potential of the first node N1 to be low. At the same time, the second control module 12 controls the potential of the second node N2 to be high. Under the control of the first node N1 being at an effective potential and the second node N2 being at an ineffective potential, the output module 10 outputs a high level.

[0073] At a subsequent time t012 after the first setting phase t01, the input signal SIN is high, and the potential of the first node N1 is no longer controlled by the input signal SIN, but instead controlled by the output module 10. The output module 10 maintains the potential of the first node N1 at a low level. Similarly, the second control module 12 controls the potential of the second node N2 to be high, and at this time, under the control of the first node N1 and the second node N2, the output module 10 outputs low and high levels successively.

[0074] In the second setting stage t02, the input signal SIN is high, and the potential of the first node N1 is no longer controlled by the input signal SIN. The second control module 12 controls the potential of the second node N2 to be low. Furthermore, the third control module 13, the first leakage suppression module 14, and the second leakage suppression module 15 control the potential of the first node N1 to switch to high, and the output module 10 outputs a high level under the control of the first node N1 and the second node N2. From the above analysis, it can be seen that the shift register implements the process of shifting the low level output of the input signal SIN before outputting it.

[0075] In the first setting stage, the series connection of the third control module, the first leakage current suppression module 14, and the second leakage current suppression module 15 can suppress leakage current from ineffective potential signals to the first node N1, maintaining the potential stability of the first node N1. Specifically, the first leakage current suppression module 14 and the second leakage current suppression module 15 are equipped with corresponding components, which have internal resistance to increase the transmission resistance of ineffective potential signals. For example, the first leakage current suppression module 14 and the second leakage current suppression module 15 may include resistive devices such as N-type transistors, P-type transistors, diodes, or resistors. These devices can all increase the resistance when ineffective potential is transmitted to the first node N1, thereby reducing the leakage current of the third control module 13.

[0076] In summary, this invention provides a shift register, a gate driving circuit, and a display panel. The shift register includes a third control module, a first leakage current suppression module, and a second leakage current suppression module connected in series. This configuration increases the resistance to the transmission of ineffective potential to the first node, reduces leakage current from ineffective potential to the first node, and thus reduces the impact of ineffective potential on the effective potential of the first node. This helps to prevent changes in the effective potential of the first node, ensures the stability of the first node's potential, and consequently ensures that the output module outputs accurate level signals, improving the display effect of the display panel at low frequencies.

[0077] In the above embodiments, there are various ways to configure the third control module 13, the first leakage current suppression module 14, and the second leakage current suppression module 15. For example, at least two of the third control module 13, the first leakage current suppression module 14, and the second leakage current suppression module 15 may be controlled by the second node N2.

[0078] Figure 4 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention, with reference to... Figure 4 In one embodiment of the present invention, optionally, the output module 10 is also connected to a first potential signal VGH and a first timing signal K1. The output module 10 responds to the first node N1 to control whether the first timing signal K1 is output, and responds to the second node N2 to control whether the first potential signal VGH is output.

[0079] The first leakage current suppression module 14 is controlled by the first timing signal K1.

[0080] The third control module 13 is controlled by the second node N2. For example, the output module 10 responds to the valid potential of the first node N1 by outputting the first timing signal K1, and responds to the invalid potential of the first node N1 by controlling the first timing signal to no longer be output. The invalid potential of the first node N1 is the first potential signal VGH, which can be transmitted to the first node N1 through the conducting second leakage current suppression module 15, the first leakage current suppression module 14, and the third control module 13, controlling the potential of the first node N1 to be an invalid potential. At this time, the second leakage current suppression module 15 is also connected to the first potential signal VGH. Specifically, when the input signal SIN is a valid potential, that is, when the input signal SIN can control the second leakage current suppression module 15 to conduct, the second leakage current suppression module 15 transmits the first potential signal VGH to the first leakage current suppression module 14. When the first timing signal K1 is an effective potential, i.e., when the first timing signal K1 can control the first leakage current suppression module 14 to conduct, the first leakage current suppression module 14 transmits the first potential signal VGH transmitted by the second leakage current suppression module 15 to the third control module 13. When the second node N2 is an effective potential, i.e., when the potential of the second node N2 can control the third control module 13 to conduct, the third control module 13 transmits the first potential signal VGH transmitted by the first leakage current suppression module 14 and the second leakage current suppression module 15 to the first node N1.

[0081] In the second setting phase, the input signal SIN, the first timing signal K1, and the second node N2 are simultaneously valid, causing the second leakage current suppression module 15, the first leakage current suppression module 14, and the third control module 13 to turn on in response to their respective control signals, transmitting the first potential signal VGH to the first node N1 to control the potential of the first node N1 to be an ineffective potential. In the first setting phase, at least one of the input signal SIN, the first timing signal K1, and the second node N2 is an ineffective potential, causing at least one of the second leakage current suppression module 15, the first leakage current suppression module 14, and the third control module 13 to turn off in response to its own control signal, preventing the first potential signal VGH from being transmitted to the first node N1.

[0082] Therefore, it can be seen that by setting the third control module 13 to be controlled by the second node N2, the first leakage current suppression module 14 to be controlled by the first timing signal K1, and the second leakage current suppression module 15 to be controlled by the input signal SIN, the present invention can both control the potential of the first node N1 to switch to an ineffective potential in the second setting stage and suppress leakage of ineffective potential signals to the first node N1 in the first setting stage.

[0083] Continue to refer to Figure 4 Optionally, the second control module 12 is controlled by the first node N1 and the second timing signal K2. For example, in the first setting phase, the second control module 12 responds to the potential of the first node N1 and the potential of the second timing signal K2, controlling the potential of the second node N2 to be an inactive potential. In the second setting phase, the second control module 12 responds to the potential of the first node N1 and the potential of the second timing signal K2, controlling the potential of the second node N2 to be an active potential.

[0084] Continue to refer to Figure 4 Optionally, the second leakage current suppression module 15 includes a control terminal, a first terminal, and a second terminal. The control terminal of the second leakage current suppression module 15 is connected to the input signal SIN, the first terminal of the second leakage current suppression module 15 is connected to the first potential signal VGH, and the second terminal of the second leakage current suppression module 15 is electrically connected to the first leakage current suppression module 14.

[0085] Continue to refer to Figure 4 Optionally, the second leakage current suppression module 15 includes a first transistor T1. The first terminal of the first transistor T1 is connected to a first potential signal VGH, the second terminal of the first transistor T1 is electrically connected to the first leakage current suppression module 14, and the gate of the first transistor T1 is connected to an input signal SIN. In this embodiment of the invention, the second leakage current suppression module 15 includes only the first transistor T1, which has a simple structure and is easy to implement.

[0086] The first transistor T1 is turned on or off according to the input signal SIN. When the input signal SIN is an effective potential for the first transistor T1, the input signal SIN controls the first transistor T1 to turn on. The turned-on first transistor T1 transmits the first potential signal VGH to the first leakage current suppression module 14. So that when the first leakage current suppression module 14 and the third control module 13 are turned on, the first potential signal VGH can be transmitted to the first node N1 through the turned-on first transistor T1, the first leakage current suppression module 14, and the third control module 13, switching the potential of the first node N1 to an ineffective potential. The first transistor T1 has internal resistance, which can increase the resistance to the transmission of the ineffective potential signal to the first node N1, suppress the leakage current of the ineffective potential signal to the first node N1, thereby reducing the leakage current of the third control module 13.

[0087] Optionally, the first transistor T1 is a metal-oxide-semiconductor (MODS) transistor. A MODS transistor is a transistor that uses a metal oxide as its semiconductor material. The metal oxide can be zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), etc. Optionally, the first transistor T1 is an indium gallium zinc oxide (IGZO) transistor. IGZO transistors are typically fabricated as N-type transistors, meaning they conduct under high voltage levels and turn off under low voltage levels. Further, the first transistor T1 is controlled by the input signal SIN. When the input signal SIN is high, the first transistor T1 is turned on; when the input signal SIN is low, the first transistor T1 is turned off.

[0088] Among them, the indium gallium zinc oxide transistor has the advantage of low leakage current. Therefore, when the first node N1 is at an effective potential, the leakage current of the first transistor T1 in the off state is small, which can suppress the leakage current of the first potential signal VGH to the first node N1, reduce the impact on the effective potential of the first node N1, and ensure the stability of the potential of the first node N1.

[0089] Figure 5 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention, with reference to... Figure 5 In one embodiment of the present invention, optionally, the first transistor T1 is a P-type transistor. Since a P-type transistor has a large turn-off internal resistance when off, by placing a P-type transistor between the first potential signal VGH and the first node N1, the resistance between the transmission path of the first potential signal VGH and the first node N1 can be increased when the first node N1 is at an effective potential. This increases the resistance to the transmission of the first potential signal VGH to the first node N1, reducing leakage current to the first node N1 from ineffective potentials.

[0090] Figure 6 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention, with reference to... Figure 6 In one embodiment of the present invention, optionally, the first leakage current suppression module 14 includes a control terminal, a first terminal and a second terminal. The control terminal of the first leakage current suppression module 14 is connected to a first timing signal. The first terminal of the first leakage current suppression module 14 is electrically connected to the second leakage current suppression module 15, and the second terminal of the first leakage current suppression module 14 is electrically connected to the third control module 13.

[0091] Continue to refer to Figure 6Optionally, the first leakage current suppression module 14 includes a second transistor T2. The first terminal of the second transistor T2 is electrically connected to the second leakage current suppression module 15, and the second terminal of the second transistor T2 is electrically connected to the third control module 13. The gate of the second transistor T2 is connected to the first timing signal K1. In this embodiment of the invention, the first leakage current suppression module 14 includes only the second transistor T2, which has a simple structure and is easy to implement.

[0092] The second transistor T2 is turned on or off according to the first timing signal K1. When the first timing signal K1 is an effective potential for the second transistor T2, the first timing signal K1 controls the second transistor T2 to turn on. The turned-on second transistor T2 transmits the first potential signal VGH, which is transmitted to the first terminal of the second transistor T2, to the third control module 13. So that in the second setting stage, when the second leakage current suppression module 15 and the third control module 13 are turned on, the first potential signal VGH is transmitted to the first node N1 through the turned-on second leakage current suppression module 15, the second transistor T2, and the third control module 13, switching the potential of the first node N1 to an ineffective potential. The second transistor T2 has internal resistance, which can increase the resistance to the transmission of the ineffective potential signal to the first node N1, suppress the leakage current of the ineffective potential signal to the first node N1, thereby reducing the leakage current of the third control module 13.

[0093] Optionally, the second transistor T2 is a metal-oxide-semiconductor transistor. Optionally, the second transistor T2 is an indium gallium zinc oxide transistor.

[0094] Among them, the indium gallium zinc oxide (IGaZ) transistor has the advantage of low leakage current. Therefore, when the first node N1 is at an effective potential, the leakage current of the second transistor T2 in the off state is small, which can suppress the leakage current of the first potential signal VGH to the first node N1, reduce the impact on the effective potential of the first node N1, and ensure the stability of the potential of the first node N1. Furthermore, the second transistor T2 is controlled by the first timing signal K1. When the first timing signal K1 is high, the second transistor T2 is turned on; when the first timing signal K1 is low, the second transistor T2 is turned off.

[0095] In other embodiments, the second transistor T2 can also be a P-type transistor. Compared with not setting the second transistor T2, when the second transistor T2 is turned off, it is equivalent to a large resistance, thus increasing the resistance of the transmission path between the first potential signal VGH and the first node N1, and thus reducing the leakage current of the first potential signal VGH to the first node N1.

[0096] Figure 7 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention, with reference to... Figure 7In one embodiment of the present invention, optionally, the third control module 13 includes a control terminal, a first terminal and a second terminal. The control terminal of the third control module 13 is electrically connected to the second node N2, the first terminal of the third control module 13 is electrically connected to the first leakage current suppression module 14, and the second terminal of the third control module 13 is electrically connected to the first node N1.

[0097] Optionally, the third control module 13 includes a third transistor T3. The first terminal of the third transistor T3 is electrically connected to the first leakage current suppression module 14, the second terminal of the third transistor T3 is electrically connected to the first node N1, and the gate of the third transistor T3 is electrically connected to the second node N2. In this embodiment of the invention, the third control module 13 includes only the third transistor T3, which has a simple structure and is easy to implement.

[0098] The third transistor T3 is turned on or off according to the control of the second node N2. For example, when the third transistor T3 is a P-type transistor, it is turned on when the second node N2 is at an effective potential. At the same time, both the second leakage current suppression module 15 and the first leakage current suppression module 14 are turned on, and the first potential signal VGH can be transmitted to the first node N1 through the turned-on second leakage current suppression module 15, first leakage current suppression module 14 and third control module 13, making the first node N1 an ineffective potential.

[0099] Figure 8 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention, with reference to... Figure 8 Based on the above embodiments, optionally, the first control module 11 includes a control terminal, a first terminal and a second terminal. The control terminal of the first control module 11 is connected to the input signal SIN, the first terminal of the first control module 11 is connected to the second potential signal VGL, and the second terminal of the first control module 11 is electrically connected to the first node N1.

[0100] The second control module 12 includes a first control terminal, a second control terminal, a first terminal, a second terminal, and a third terminal. The first control terminal of the second control module 12 is connected to a second timing signal K2. The second control terminal of the second control module 12 is electrically connected to a first node N1. The first terminal of the second control module 12 is connected to a second potential signal VGL. The second terminal of the second control module 12 is connected to a first potential signal VGH. The third terminal of the second control module 12 is electrically connected to a second node N2.

[0101] For example, the second potential signal VGL is the effective potential of the first node N1 and the second node N2, and the first potential signal VGH is the ineffective potential of the first node N1 and the second node N2. In the first setting stage, the first control module 11 is turned on under the control of the input signal SIN, transmitting the second potential signal VGL to the first node N1. Simultaneously, under the control of the first node N1, the second control module 12 transmits the first potential signal VGH through its second terminal to its third terminal, thereby controlling the second node N2 to be an ineffective potential. In the second setting stage, the second control module 12 is turned on under the control of the second timing signal K2, transmitting the second potential signal VGL through its first terminal to its third terminal, thereby controlling the second node N2 to be an effective potential. Simultaneously, under the control of the first node N1, the second control module 12 disconnects the connection between its second terminal and its third terminal to prevent the first potential signal VGH from being written into the second node N2.

[0102] Continue to refer to Figure 8 Optionally, the first control module 11 includes a fourth transistor T4. The first terminal of the fourth transistor T4 is connected to a second potential signal VGL, the second terminal of the fourth transistor T4 is electrically connected to a first node N1, and the gate of the fourth transistor T4 is connected to an input signal SIN. In this embodiment of the invention, the first control module 11 includes only the fourth transistor T4, which has a simple structure and is easy to implement.

[0103] The fourth transistor T4 is turned on or off according to the input signal SIN. When the input signal SIN is an effective potential for the fourth transistor T4, the input signal SIN controls the fourth transistor T4 to turn on, and the turned-on fourth transistor T4 transmits the second potential signal VGL to the first node N1.

[0104] The second control module 12 includes a fifth transistor T5 and a sixth transistor T6. The first terminal of the fifth transistor T5 is connected to a second potential signal VGL, the second terminal of the fifth transistor T5 is electrically connected to a second node N2, and the gate of the fifth transistor T5 is connected to a second timing signal K2. The first terminal of the sixth transistor T6 is connected to a first potential signal VGH, the second terminal of the sixth transistor T6 is electrically connected to a second node N2, and the gate of the sixth transistor T6 is electrically connected to a first node N1. In this embodiment of the invention, the second control module 12 includes only the fifth transistor T5 and the sixth transistor T6, resulting in a simple structure that is easy to implement.

[0105] Specifically, the fifth transistor T5 is turned on or off according to the second timing signal K2. When the second timing signal K2 is a valid potential for the fifth transistor T5, the second timing signal K2 controls the fifth transistor T5 to turn on, and the turned-on fifth transistor T5 transmits the second potential signal VGL to the second node N2. The sixth transistor T6 is turned on or off according to the potential of the first node N1. When the potential of the first node N1 is a valid potential for the sixth transistor T6, the valid potential of the first node N1 controls the sixth transistor T6 to turn on, and the turned-on sixth transistor T6 transmits the first potential signal VGH to the second node N2.

[0106] Figure 9 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention, with reference to... Figure 9 Based on the above embodiments, optionally, the output module 10 includes a first control terminal, a second control terminal, a first terminal, a second terminal, and a third terminal. The first control terminal of the output module 10 is electrically connected to the first node N1, and the second control terminal of the output module 10 is electrically connected to the second node N2. The first terminal of the output module 10 is connected to a first timing signal K1, the second terminal of the output module 10 is connected to a first potential signal VGH, and the third terminal of the output module 10 serves as the output terminal OUT of the shift register. When the potential of the first node N1 is an effective potential, the output module 10 outputs the first timing signal K1 to the third terminal of the output module 10, and when the potential of the second node N2 is an effective potential, it outputs the first potential signal VGH to the third terminal of the output module 10.

[0107] In this embodiment, the electrical connection between the first control terminal of the output module 10 and the first node N1 can be a direct electrical connection or an indirect electrical connection (that is, a switching element, such as a transistor, can be connected between the first control terminal of the output module 10 and the first node N1, and the switching element can be normally open).

[0108] Continue to refer to Figure 9 Optionally, the output module 10 includes a seventh transistor T7, an eighth transistor T8, a first capacitor C1, and a second capacitor C2.

[0109] The first terminal of the seventh transistor T7 is connected to the first timing signal K1, the second terminal of the seventh transistor T7 is electrically connected to the output terminal OUT of the shift register, the gate of the seventh transistor T7 is electrically connected to the first node N1, the first terminal of the first capacitor C1 is electrically connected to the second terminal of the seventh transistor T7, and the second terminal of the first capacitor C1 is electrically connected to the gate of the seventh transistor T7.

[0110] The first terminal of the eighth transistor T8 is connected to the first potential signal VGH, the second terminal of the eighth transistor T8 is electrically connected to the output terminal OUT of the shift register, the gate of the eighth transistor T8 is electrically connected to the second node N2, the first terminal of the second capacitor C2 is electrically connected to the first terminal of the eighth transistor T8, and the second terminal of the second capacitor C2 is electrically connected to the gate of the eighth transistor T8.

[0111] The seventh transistor T7 is turned on or off according to the potential of its gate. When its gate potential is at an effective level, the seventh transistor T7 is turned on, transmitting the first timing signal K1 to the output terminal OUT of the shift register. The first capacitor C1 is used to maintain the potential of the gate of the seventh transistor T7. Simultaneously, the seventh transistor T7 and the first capacitor C1 form a bootstrap circuit, ensuring that the gate reaches an ultra-low potential in subsequent moments of the first setting phase. This prevents the first timing signal K1 output from the shift register from being affected by the threshold voltage of the seventh transistor T7 and thus failing to decrease to the target value.

[0112] The eighth transistor T8 is turned on or off according to the potential of its gate. When its gate potential is at an effective potential, the eighth transistor T8 is turned on and transmits the first potential signal VGH to the output terminal OUT of the shift register. The second capacitor C2 can store the gate potential of the eighth transistor T8.

[0113] Figure 10 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention, with reference to... Figure 10 Based on the above embodiments, optionally, the second leakage current suppression module 15 includes a first transistor T1, the first leakage current suppression module 14 includes a second transistor T2, the third control module 13 includes a third transistor T3, the first control module 11 includes a fourth transistor T4, the second control module 12 includes a fifth transistor T5 and a sixth transistor T6, and the output module 10 includes a seventh transistor T7, an eighth transistor T8, a first capacitor C1 and a second capacitor C2.

[0114] Optionally, the output module 10 further includes a ninth transistor T9. The first node N1 is electrically connected to the gate of the seventh transistor T7 through the ninth transistor T9, and the gate of the ninth transistor T9 is connected to the second potential signal VGL. Placing the ninth transistor T9 between the first node N1 and the gate of the seventh transistor T7 can suppress the transmission of an ultra-low potential from the gate of the seventh transistor T7 to the first node N1 due to the bootstrap effect of the first capacitor C1, reduce the probability of the gate insulation layer of the fourth transistor T4 being broken down, and improve the stability of the shift register.

[0115] Figure 11 This invention provides a timing diagram for driving a shift register according to an embodiment of the present invention. Figure 11The timing diagram shown can be applied to Figure 10 The aforementioned shift register, refer to Figure 10 and Figure 11 In this embodiment, the first transistor T1 and the second transistor T2 are N-type transistors, while the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are all P-type transistors. The effective potentials of the first node N1 and the second node N2 are both low. The third transistor T3 is controlled by the second node N2, and its effective potential for conduction is low. The effective potentials for conduction of the first transistor T1 and the second transistor T2 are high. Therefore, the conduction levels of the first transistor T1 and the second transistor T2 are different from those of the third transistor T3. In this embodiment, the first transistor T1 is controlled by the input signal SIN, and the second transistor T2 is controlled by the first timing signal K1. This allows the first transistor T1 and the second transistor T2 to be alternately or simultaneously turned off when the third transistor T3 is turned off, thereby suppressing the leakage current of the third transistor T3.

[0116] Specifically, the first setting stage t01 includes the second sub-stage t12, the third sub-stage t13 and the fourth sub-stage t14, and the second setting stage t02 includes the first sub-stage t11, the fifth sub-stage t15, the sixth sub-stage t16, the seventh sub-stage t17 and the eighth sub-stage t18. Figures 12-19 The following are the working state diagrams of the shift register provided in the embodiments of the present invention from the first sub-stage to the eighth sub-stage, for reference. Figure 12-19 The operation of the shift register described above is as follows:

[0117] In the first sub-stage t11, such as Figure 12As shown, when the first timing signal K1 is high, it controls the second transistor T2 to turn on; when the input signal SIN is high, it controls the first transistor T1 to turn on and the fourth transistor T4 to turn off; when the second timing signal K2 is low, it controls the fifth transistor T5 to turn on, and the second potential signal VGL is written to the second node N2 through the turned-on fifth transistor T5, so that the potential of the second node N2 is low; the eighth transistor T8 turns on in response to the low level of the second node N2, transmitting the first potential signal VGH to the output terminal OUT of the shift register. When the second node N2 is low, it controls the third transistor T3 to turn on. Therefore, the turned-on first transistor T1, second transistor T2, and third transistor T3 transmit the first potential signal VGH to the first node N1. The first potential signal VGH transmitted to the first node N1 is then transmitted to the gate of the seventh transistor T7 through the normally open ninth transistor T9. The seventh transistor T7 turns off in response to the high level of the first potential signal VGH. When the first node N1 is high, it controls the sixth transistor T6 to turn off, preventing the first potential signal VGH from being mistakenly written to the second node N2 via the sixth transistor T6. Therefore, in the first sub-stage t11, the shift register outputs the first potential signal VGH.

[0118] Therefore, in the first sub-stage t11, the first transistor T1, the second transistor T2, and the third transistor T3 are all turned on to transmit the first potential signal VGH to the first node N1.

[0119] In the second sub-stage t12, such as Figure 13 As shown, when the second timing signal K2 is high, it controls the fifth transistor T5 to turn off, and the second potential signal VGL cannot continue to be transmitted to the second node N2 through the fifth transistor T5; when the input signal SIN is low, it controls the first transistor T1 to turn off and the fourth transistor T4 to turn on, and the second potential signal VGL is transmitted to the gate of the seventh transistor T7 through the turned-on fourth transistor T4 and the normally open ninth transistor T9. The seventh transistor T7 turns on in response to the low level of the gate, and the output terminal OUT of the shift register outputs the first timing signal K1. When the potential of the first node N1 is low, it controls the sixth transistor T6 to turn on. The first potential signal VGH is transmitted to the second node N2 via the sixth transistor T6. The eighth transistor T8 turns off in response to the high level of the second node. When the second node N2 is high, it controls the third transistor T3 to turn off. Although the first timing signal K1 is high, controlling the second transistor T2 to turn on, the first transistor T1 and the third transistor T3 are turned off to prevent the first potential signal VGH from being transmitted to the gate of the seventh transistor T7 via the first transistor T1, the second transistor T2, and the third transistor T3, thus affecting the low level of the gate of the seventh transistor T7. In the second sub-stage t12, the seventh transistor T7 turns on and the eighth transistor T8 turns off, preparing for the output of the low level of the first timing signal K1 in the next stage.

[0120] Therefore, in the second sub-stage t12, the first transistor T1 and the third transistor T3 are turned off. The first transistor T1 is an indium gallium zinc oxide transistor, which has a small leakage current when turned off, reducing the leakage current from the first potential signal VGH to the gate of the seventh transistor T7, reducing the rise of the low potential of the gate of the seventh transistor T7, and ensuring that the seventh transistor T7 is stably turned on to output the first timing signal K1.

[0121] In the third sub-stage t13, such as Figure 14 As shown, when the second timing signal K2 is high, it controls the fifth transistor T5 to turn off; when the input signal SIN is high, it controls the first transistor T1 to turn on and the fourth transistor T4 to turn off; when the first timing signal K1 is low, it controls the second transistor T2 to turn off, and the first potential signal VGH cannot be transmitted to the first node N1 through the first transistor T1, the second transistor T2, and the third transistor T3. The first node N1 maintains a low level in the second sub-stage t12 due to the storage effect of the first capacitor C1, and the seventh transistor T7 turns on in response to the low level of the first node N1; when the first node N1 is low, it controls the sixth transistor T6 to turn on, and the potential of the second node N2 maintains a high level in the second sub-stage t12, and the eighth transistor T8 turns off in response to the high level of the second node N2. After the seventh transistor T7 turns on, the signal output by the shift register's output terminal OUT is the first timing signal K1. When the second sub-stage t12 ends and the third sub-stage t13 begins, the first timing signal K1 changes from a high potential to a low potential. The first capacitor C1 has a bootstrap function. When the potential of the first terminal of the first capacitor C1 changes from high level to low level, it can pull down the potential of the second terminal of the first capacitor C1, so that the potential of the gate of the seventh transistor T7 is lower than the second potential signal VGL. This ensures that the low level on the first timing signal K1 will not fail to pull down the low level of the output terminal OUT of the shift register from high level due to the influence of the threshold voltage of the seventh transistor T7, thus preventing the output terminal OUT of the shift register from failing to pull down to a level that can turn on the transistor in the pixel circuit. This ensures that the output terminal OUT of the shift register can output a low-level signal that drives the transistor in the pixel circuit to turn on.

[0122] Therefore, in the third sub-stage t13, the second transistor T2 and the third transistor T3 are turned off. The second transistor T2 is an indium gallium zinc oxide transistor, which has a small leakage current when turned off, reducing the leakage current from the first potential signal VGH to the gate of the seventh transistor T7, reducing the rise of the low level of the gate of the seventh transistor T7, and ensuring that the seventh transistor T7 is stably turned on, so as to ensure the stable output of the low level of the first timing signal K1.

[0123] In the fourth sub-stage t14, such as Figure 15As shown, the input signal SIN, the first timing signal K1, and the second timing signal K2 are all high, controlling the first transistor T1 and the second transistor T2 to turn on and the fourth transistor T4 to turn off. The gate of the seventh transistor T7 is kept at a low potential due to the storage effect of the first capacitor C1, thus controlling the seventh transistor T7 to turn on. The first node N1 is at a low potential, controlling the sixth transistor T6 to turn on. The first potential signal VGH is transmitted to the second node N2 via the sixth transistor T6. The potential at the second node N2 is high, controlling the eighth transistor T8 and the third transistor T3 to turn off. After the third transistor T3 turns off, it prevents the first potential signal VGH from being transmitted to the first node N1 via the first transistor T1, the second transistor T2, and the third transistor T3. During this stage, the signal output by the shift register's output terminal OUT is the first timing signal K1.

[0124] Therefore, in the fourth sub-stage t14, the third transistor T3 is turned off to prevent the first potential signal VGH from being transmitted to the first node N1.

[0125] In the fifth sub-stage t15, such as Figure 16 As shown, when the second timing signal K2 is low, it controls the fifth transistor T5 to turn on. The second potential signal VGL is written to the second node N2 via the fifth transistor T5. The eighth transistor T8 turns on in response to the low level of the second node N2. When the input signal SIN is high, it controls the fourth transistor T4 to turn off and the first transistor T1 to turn on. When the first timing signal K1 is high, it controls the second transistor T2 to turn on. The turned-on first transistor T1, second transistor T2, and third transistor T3 transmit the first potential signal VGH to the first node N1, charging the first capacitor C1. At the same time, the high level of the first node N1 controls the seventh transistor T7 to turn off. The high level of the first node N1 controls the sixth transistor T6 to turn off, preventing the first potential signal VGH from being mistakenly written to the second node N2 via the sixth transistor T6. During this stage, the eighth transistor T8 turns on, and the signal output by the shift register's output terminal OUT is the first potential signal VGH.

[0126] Therefore, in the fifth sub-stage t15, the first transistor T1, the second transistor T2, and the third transistor T3 are all turned on to transmit the first potential signal VGH to the first node N1.

[0127] In the sixth sub-stage t16, such as Figure 17As shown, the first timing signal K1, the second timing signal K2, and the input signal SIN are all high, controlling the fourth transistor T4, the sixth transistor T6, and the fifth transistor T5 to turn off. The first node N1 maintains the high level of the previous stage, and the second node N2 maintains the low level of the previous stage. The low level of the second node N2 controls the third transistor T3 to turn on. The turned-on first transistor T1, second transistor T2, and third transistor T3 write the first potential signal VGH into the gate of the seventh transistor T7, charging the first capacitor C1. During this stage, the potential of the second node N2 is low, controlling the eighth transistor T8 to turn on. Therefore, the potential output at the output terminal OUT of the shift register is the first potential signal VGH.

[0128] Therefore, in the sixth sub-stage t16, the first transistor T1, the second transistor T2, and the third transistor T3 are all turned on to transmit the first potential signal VGH to the first node N1.

[0129] In the seventh sub-phase t17, such as Figure 18 As shown, when the second timing signal K2 is high, it controls the fifth transistor T5 to turn off. Due to the storage effect of the second capacitor C2, the gate of the eighth transistor T8 maintains the low level of the previous stage. The eighth transistor T8 and the third transistor T3 turn on in response to the low level of the second node N2. When the first timing signal K1 is low, it controls the second transistor T2 to turn off. Although the input signal SIN is high, controlling the first transistor T1 to turn on, the second transistor T2 is off. Therefore, the first potential signal VGH cannot be written to the first node N1 through the series-connected first transistor T1, second transistor T2, and third transistor T3. The gate of the seventh transistor T7 maintains the high level of the previous stage due to the storage effect of the first capacitor C1. The seventh transistor T7 turns off in response to the high level of its gate. When the first node N1 is high, it controls the sixth transistor T6 to turn off, preventing the first potential signal VGH from being written to the second node N2 through the sixth transistor T6. During this stage, the potential of the second node N2 is low, controlling the eighth transistor T8 to turn on. The signal output by the shift register's output terminal OUT is the first potential signal VGH.

[0130] Therefore, in the seventh sub-stage t17, the second transistor T2 turns off in response to the first timing signal K1.

[0131] In the eighth sub-stage t18, such as Figure 19As shown, when the second timing signal K2 is high, it controls the fifth transistor M5 to turn off. Due to the storage effect of the second capacitor C2, the gate of the eighth transistor T8 continues to maintain the low level of the previous stage. The eighth transistor T8 and the third transistor T3 turn on in response to the low level of the second node N2. When the input signal SIN and the first timing signal K1 are high, they control the first transistor T1 and the second transistor T2 to turn on. The first potential signal VGH is written to the first node N1 through the turned-on first transistor T1, second transistor T2, and third transistor T3. The fourth transistor T4 turns off in response to the high level of the input signal SIN, preventing the second potential signal VGL from being written to the first node N1 through the fourth transistor. When the first node N1 is high, it controls the seventh transistor T7 to turn off. When the first node N1 is high, it controls the sixth transistor T6 to turn off, preventing the first potential signal VGH from being written to the second node N2 through the sixth transistor T6. During this stage, the potential of the second node N2 is low, controlling the eighth transistor T8 to turn on. The signal output by the shift register's output terminal OUT is the first potential signal VGH.

[0132] Therefore, in the eighth sub-stage t18, the first transistor T1, the second transistor T2, and the third transistor T3 are all turned on to transmit the first potential signal VGH to the first node N1.

[0133] Within a frame, after the eighth sub-stage ends, the fifth sub-stage t15, the sixth sub-stage t16, the seventh sub-stage t17, and the eighth sub-stage t18 are repeated continuously until the end of a frame.

[0134] In summary, this invention provides a shift register, a gate driving circuit, and a display panel. The shift register includes a third control module, a first leakage current suppression module, and a second leakage current suppression module connected in series. This configuration increases the resistance to the transmission of ineffective potential to the first node, reduces leakage current from ineffective potential to the first node, and thus reduces the impact of ineffective potential on the effective potential of the first node. This helps to prevent changes in the effective potential of the first node, ensures the stability of the first node's potential, and consequently ensures that the output module outputs accurate level signals, improving the display effect of the display panel at low frequencies.

[0135] This invention also provides a display panel, which includes the shift register described in any of the above embodiments. The beneficial effects of the display panel are the same as those of the shift register, and will not be repeated here.

[0136] Figure 20 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, with reference to... Figure 2 and 20Optionally, the shift register includes a first timing signal terminal L1, a second timing signal terminal L2, an input signal terminal IN, a first potential signal terminal VH, a second potential signal terminal VL, and an output terminal OUT. Combined with... Figures 2-11 and Figure 20 The output module 10 is electrically connected to the first timing signal terminal L1 and the first potential signal terminal VH, respectively. The first control module 11 is electrically connected to the input signal terminal IN and the second potential signal terminal VL, respectively. The second control module 12 is electrically connected to the second timing signal terminal L2 and the second potential signal terminal VL, respectively. The second leakage current suppression module 15 is electrically connected to the input signal terminal IN and the first potential signal terminal VH, respectively. The first leakage current suppression module 14 is electrically connected to the first timing signal terminal L1. The output terminal OU1 is electrically connected to the input signal terminal IN of the next stage shift register.

[0137] Among them, the first timing signal terminal L1 of the 4K+1 level shift register 01 is connected to the second clock signal SCK2, and the second timing signal terminal L2 is connected to the fourth clock signal SCK4.

[0138] The first timing signal terminal L1 of the 4K+2 level shift register 01 is connected to the third clock signal SCK3, and the second timing signal terminal L2 is connected to the first clock signal SCK1.

[0139] The first timing signal terminal L1 of the 4K+3 level shift register 01 is connected to the fourth clock signal SCK4, and the second timing signal terminal L2 is connected to the second clock signal SCK2.

[0140] The first timing signal terminal L1 of the 4K+4 stage shift register 01 is connected to the first clock signal SCK1, and the second timing signal terminal L2 is connected to the third clock signal SCK3; where K is an integer greater than or equal to zero;

[0141] The first clock signal SCK1, the second clock signal SCK2, the third clock signal SCK3, and the fourth clock signal SCK4 are shifted sequentially.

[0142] The first potential signal terminal VH is used to provide the first potential signal VGH, and the second potential signal terminal VL is used to provide the second potential signal VGL. The display panel uses a series of cascaded shift registers 01 to shift the output signal, enabling the line-by-line writing of the scan signal when the screen is lit. This embodiment of the invention achieves the step-by-step shifting of the output signals of each shift register.

[0143] The display panel 02 includes a shift register as described in any of the above embodiments. The shift register drives the pixel units of the display panel 02. For example, the pixel unit includes a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. Each stage of the shift register in the gate driving circuit outputs a scan signal to drive each row of pixel units to light up. For example, the first-stage shift register 011 outputs a first scan signal S1 to drive the pixel unit 031 in the first row, the second-stage shift register 012 outputs a second scan signal S2 to drive the pixel unit 032 in the second row, the third-stage shift register 013 outputs a third scan signal S3 to drive the pixel unit 033 in the third row, and the fourth-stage shift register 014 outputs a fourth scan signal S4 to drive the pixel unit 034 in the fourth row. In other embodiments, a row of pixel units can also be driven by two, three, or more scan signals. These scan signals can be generated by the same set of gate driving circuits 03 composed of shift registers, or they can be generated by different gate driving circuits; this invention does not limit the scope of the invention.

[0144] See also Figure 20 Optionally, the gate driving circuit 03 is configured as a dual-sided driving circuit, where two sets of gate driving circuits simultaneously drive each row of pixel units to ensure that the line loss of the scan signals received by the pixel units on both the left and right sides is the same. This is not a limitation of the present invention; in other embodiments, the gate driving circuit of the display panel may also be configured as a single-sided driving circuit, etc.

[0145] Figure 21 This is a driving timing diagram of a display panel provided in an embodiment of the present invention, with reference to... Figure 20 , Figure 21 The first-stage shift register 011 receives the input signal SIN at its input terminal IN. Based on the second clock signal SCK2 and the fourth clock signal SCK4, the first-stage shift register 011 shifts the input signal SIN to generate the first scan signal S1. The first scan signal S1 is transmitted to the pixel unit 031 of the first row and the input signal terminal IN of the second-stage shift register 012. The second-stage shift register 012 shifts the first scan signal S1 based on the third clock signal SCK3 and the first clock signal SCK1 to generate the second scan signal S2. The second scan signal S2 is transmitted to the pixel unit 032 of the second row and the input signal terminal IN of the third-stage shift register 013, and so on, thus realizing the sequential writing of scan signals when the screen is lit.

[0146] The inventor Figure 20 The display panel shown was simulated and verified. The structure of the shift register included in the display panel is as follows: Figure 10 As shown, Figure 22 This is a simulation waveform diagram of a gate driving circuit provided in an embodiment of the present invention. (Reference) Figure 20 and 22 It can be clearly seen that the waveforms of the first scan signal S1, the second scan signal S2, the third scan signal S3, and the fourth scan signal S4 are shifted sequentially, and the waveform effect is good. The simulation results show that the display panel achieves the shifted output of the input signal SIN, and the stability and reliability of the output signal are good.

[0147] This invention also provides a method for driving a shift register, used to drive any of the shift registers mentioned above. Figure 23 A flowchart illustrating a shift register driving method provided in an embodiment of the present invention is shown below. Figure 23 The driving method includes a first setting stage and a second setting stage:

[0148] S101: At the initial moment of the first setting phase, the first control module controls the potential of the first node to switch to an effective potential; the first node controls the output module to output a first level signal; at a subsequent moment of the first setting phase, the output module maintains the potential of the first node as effective; the first node controls the output module to output a second level signal and a first level signal sequentially.

[0149] In the first setting stage, the second control module controls the potential of the second node to be an ineffective potential, and the first leakage current suppression module and the second leakage current suppression module suppress the leakage of the ineffective potential signal to the first node.

[0150] S102: In the second setting stage, the second control module controls the potential of the second node to be an effective potential, the third control module, the first leakage current suppression module and the second leakage current suppression module control the potential of the first node to be an ineffective potential, and the output module outputs a first level signal under the control of the second node.

[0151] The beneficial effects of the shift register driving method in this embodiment are the same as those of the shift register itself, and will not be repeated here.

[0152] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0153] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A shift register, characterized by, The application relates to a signal outputting circuit, comprising: an output module for alternately outputting a first level signal and a second level signal under the control of a first node and a second node; a first control module for controlling the potential of the first node; a second control module for controlling the potential of the second node; a third control module, a first leakage suppression module and a second leakage suppression module connected in series for controlling the potential of the first node; wherein the first leakage suppression module and the second leakage suppression module are also used for suppressing the leakage of an ineffective potential signal to the first node; the output module is also connected to a first potential signal and a first timing signal, and the output module responds to the first node to control whether the first timing signal is outputted, and responds to the second node to control whether the first potential signal is outputted; the first leakage suppression module is controlled by the first timing signal; the second leakage suppression module and the first control module are both controlled by an input signal; the third control module is controlled by the second node; the second control module is controlled by the first node and a second timing signal; the first control module comprises a fourth transistor, the first pole of the fourth transistor is connected to a second potential signal, the second pole of the fourth transistor is electrically connected to the first node, and the gate of the fourth transistor is connected to an input signal; the second control module comprises a fifth transistor and a sixth transistor, the first pole of the fifth transistor is connected to the second potential signal, the second pole of the fifth transistor is electrically connected to the second node, the gate of the fifth transistor is connected to the second timing signal, the first pole of the sixth transistor is connected to the first potential signal, the second pole of the sixth transistor is electrically connected to the second node, and the gate of the sixth transistor is electrically connected to the first node; the second leakage suppression module comprises a first transistor, the first pole of the first transistor is connected to the first potential signal, the second pole of the first transistor is electrically connected to the first leakage suppression module, and the gate of the first transistor is connected to the input signal; the first leakage suppression module comprises a second transistor, the first pole of the second transistor is electrically connected to the second leakage suppression module, the second pole of the second transistor is electrically connected to the third control module, and the gate of the second transistor is connected to the first timing signal; the third control module comprises a third transistor, the first pole of the third transistor is electrically connected to the first leakage suppression module, the second pole of the third transistor is electrically connected to the first node, and the gate of the third transistor is electrically connected to the second node.

2. The shift register of claim 1, wherein, The second leakage suppression module comprises a control end, a first end and a second end, the control end of the second leakage suppression module is connected to the input signal, the first end of the second leakage suppression module is connected to the first potential signal, and the second end of the second leakage suppression module is electrically connected to the first leakage suppression module.

3. The shift register of claim 1, wherein, The first transistor is a metal oxide transistor.

4. The shift register of claim 1, wherein, The first transistor is an indium gallium zinc oxide transistor.

5. The shift register of claim 1, wherein, The first leakage suppression module comprises a control end, a first end and a second end, the control end of the first leakage suppression module is connected to the first timing signal, the first end of the first leakage suppression module is electrically connected to the second leakage suppression module, and the second end of the first leakage suppression module is electrically connected to the third control module.

6. The shift register of claim 1, wherein, The second transistor is a metal oxide transistor.

7. The shift register of claim 1, wherein, The second transistor is an indium gallium zinc oxide transistor.

8. The shift register of claim 1, wherein, The third control module comprises a control end, a first end and a second end, the control end of the third control module is electrically connected to the second node, the first end of the third control module is electrically connected to the first leakage suppression module, and the second end of the third control module is electrically connected to the first node.

9. The shift register of claim 1, wherein, The first control module comprises a control end, a first end and a second end, the control end of the first control module is connected to the input signal, the first end of the first control module is connected to a second potential signal, and the second end of the first control module is electrically connected to the first node. The second control module comprises a first control end, a second control end, a first end, a second end and a third end, the first control end of the second control module is connected to a second timing signal, the second control end of the second control module is electrically connected to the first node, the first end of the second control module is connected to the second potential signal, the second end of the second control module is connected to a first potential signal, and the third end of the second control module is electrically connected to the second node.

10. The shift register of claim 1, wherein, The output module comprises a first control end, a second control end, a first end, a second end and a third end, the first control end of the output module is electrically connected to the first node, the second control end of the output module is electrically connected to the second node, the first end of the output module is connected to a first timing signal, the second end of the output module is connected to a first potential signal, and the third end of the output module serves as an output end of the shift register.

11. The shift register of claim 10, wherein, The output module comprises a seventh transistor, an eighth transistor, a first capacitor and a second capacitor. The first pole of the seventh transistor is connected to the first timing signal, the second pole of the seventh transistor is electrically connected to the output end of the shift register, the gate of the seventh transistor is electrically connected to the first node, the first end of the first capacitor is electrically connected to the second pole of the seventh transistor, and the second end of the first capacitor is electrically connected to the gate of the seventh transistor. The first pole of the eighth transistor is connected to the first potential signal, the second pole of the eighth transistor is electrically connected to the output end of the shift register, the gate of the eighth transistor is electrically connected to the second node, the first end of the second capacitor is electrically connected to the first pole of the eighth transistor, and the second end of the second capacitor is electrically connected to the gate of the eighth transistor.

12. The shift register of claim 11, wherein, The output module further comprises a ninth transistor, the first node is electrically connected to the gate of the seventh transistor through the ninth transistor, and the gate of the ninth transistor is connected to a second potential signal.

13. A display panel, characterized by The shift register comprises any one of claims 1-12.

14. The display panel of claim 13, wherein, The shift register comprises a first timing signal end, a second timing signal end, an input signal end, a first potential signal end, a second potential signal end and an output end, the output module is electrically connected with the first timing signal end and the first potential signal end respectively, the first control module is electrically connected with the input signal end and the second potential signal end respectively, the second control module is electrically connected with the second timing signal end and the second potential signal end respectively, the second leakage suppression module is electrically connected with the input signal end and the first potential signal end respectively, and the first leakage suppression module is electrically connected with the first timing signal end; the output end is electrically connected with the input signal end IN of the next stage shift register; The first timing signal end of the 4K+1 stage shift register is connected with the second clock signal, and the second timing signal end is connected with the fourth clock signal; The first timing signal end of the 4K+2 stage shift register is connected with the third clock signal, and the second timing signal end is connected with the first clock signal; The first timing signal end of the 4K+3 stage shift register is connected with the fourth clock signal, and the second timing signal end is connected with the second clock signal; The first timing signal end of the 4K+4 stage shift register is connected with the first clock signal, and the second timing signal end is connected with the third clock signal; wherein K is an integer greater than or equal to zero; The first clock signal, the second clock signal, the third clock signal and the fourth clock signal are sequentially shifted.

15. A driving method of a shift register, characterized by, The driving method comprises a first setting stage and a second setting stage; At the initial moment of the first setting stage, the first control module controls the potential of the first node to switch to an effective potential; The first node controls the output module to output the first level signal; At the subsequent moment of the first setting stage, the output module maintains the effective potential of the first node; The first node controls the output module to output the second level signal and the first level signal in turn; In the first setting stage, the second control module controls the potential of the second node to be a non-effective potential, and the first leakage suppression module and the second leakage suppression module suppress the leakage of the non-effective potential signal to the first node; In the second setting stage, the second control module controls the potential of the second node to be an effective potential, the third control module, the first leakage suppression module and the second leakage suppression module control the potential of the first node to be a non-effective potential, and the output module outputs the first level signal under the control of the second node.

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