A multi-channel high-precision coherent signal generation system based on digital synchronous control

Abstract

The present invention discloses a multi-channel high-precision coherent signal generation system based on digital synchronous control, which includes an FPGA chip, a multi-channel intermediate frequency signal module, and a frequency conversion channel; a plurality of DDS signal generators are provided in the FPGA chip, and a plurality of DAC digital-to-analog converters are provided in the multi-channel intermediate frequency signal module. The FPGA can control the DDS to generate digital signals with a set phase according to the received signal parameter control command, and form an intermediate frequency signal data stream when receiving a synchronous trigger signal. The data stream is sent to the DAC digital-to-analog converters of each channel for digital-to-analog conversion to generate an intermediate frequency analog signal, and then transmitted to each frequency conversion channel to complete the up-conversion process to obtain a coherent signal. This coherent signal generation system realizes the multi-channel coherent intermediate frequency signal generation technology based on the high-precision synchronous control of multiple digital-to-analog converters, and uses a common local oscillator to up-convert the signal to achieve the purpose of realizing multi-channel coherent radio frequency signals.

Description

Technical Field

[0001] The present invention belongs to the field of direction finding signal simulation devices, and particularly relates to a multi-channel high-precision coherent signal generation system based on digital synchronous control. Background Art

[0002] In order to accurately and quickly obtain the position information of a target, in existing electronic equipment, a direction finding technology based on an interferometer system is often used to achieve the positioning of the target. Its principle is to receive spatial electromagnetic signals through multiple receiving channels, and then perform data processing and fusion in a processor, and calculate the azimuth information of the target by using the phase difference and amplitude difference between channels. Therefore, it is very necessary to construct a multi-channel high-precision coherent electromagnetic signal environment to realize the function and performance testing of the positioning of these equipment.

[0003] When existing signal simulation devices such as radars and communications realize the generation of multi-channel radio frequency (RF) level coherent signals, they mainly use a signal simulation source to generate the required single-channel RF signal, then split the single-channel signal into multiple channels, and then use an IQ vector modulator to perform phase shift control on the signals of each channel, so as to realize the simulation of coherent signals of multiple channels. There are three disadvantages in the products adopting this type of technical system:

[0004] a) Closed-loop calibration control cannot be realized during power-on initialization, and the IQ vector modulator is sensitive to factors such as ambient temperature. Under different environmental conditions, the consistency of the multi-channel coherent characteristics of the system is poor. Therefore, during use, it is often necessary to use instruments to carry out complex phase calibration work.

[0005] b) High-precision IQ vector modulators basically rely on imports and face problems such as high costs.

[0006] c) When the IQ vector modulator performs phase control, its phase is related to the current signal frequency. If it is a broadband signal, accurate control of the signal phase cannot be achieved. Summary of the Invention

[0007] The purpose of the present invention is to provide a multi-channel high-precision coherent signal generation system based on digital synchronous control to overcome the defects of the prior art. This coherent signal generation system is based on high-precision synchronous control of multiple digital-to-analog converters to realize the technology of generating multi-channel coherent intermediate frequency signals, and uses a common local oscillator to perform up-conversion on the signals, so as to achieve the purpose of generating multi-channel coherent RF signals.

[0008] The purpose of the present invention is achieved through the following technical solutions:

[0009] A multi-channel high-precision coherent signal generation system based on digital synchronous control, the coherent signal generation system includes an FPGA chip, a multi-channel intermediate frequency signal module, and a frequency conversion channel;

[0010] There are several DDS signal generators in the FPGA chip, and there are several DAC digital-to-analog converters in the multi-channel intermediate frequency signal module.

[0011] There are several DDS signal generators in the FPGA chip, and there are several DAC digital-to-analog converters in the multi-channel intermediate frequency signal module. The FPGA can control the DDS to generate digital signals with set phases according to the received signal parameter control commands, and form an intermediate frequency signal data stream when receiving a synchronous trigger signal; the data stream is sent to the DAC digital-to-analog converters of each channel for digital-to-analog conversion to generate intermediate frequency analog signals, and then transmitted to each frequency conversion channel to complete up-conversion processing to obtain coherent signals.

[0012] Among them, the working clocks of each DAC digital-to-analog converter use the same reference clock source; the data streams of each DDS signal generator use synchronous clock logic, and clock constraints are performed on the wiring paths of the data streams generated by the DDS signal generators in the FPGA chip; and the data lines from each DDS signal generator to the corresponding DAC digital-to-analog converter are set to be of equal length.

[0013] According to a preferred embodiment, each DAC digital-to-analog converter has a synchronous control function pin, and each function pin is interconnected or connected to the control pin of the FPGA to complete the synchronous control of each DAC digital-to-analog converter.

[0014] According to a preferred embodiment, the synchronous control of each DAC digital-to-analog converter includes: setting parameters for the synchronous control function register of each DAC digital-to-analog converter. After the configuration is completed, the status value of the synchronous control function register of each DAC digital-to-analog converter is read to ensure the working state and synchronous locking of each DAC digital-to-analog converter; when the read status value is abnormal, secondary configuration is performed until it is normal.

[0015] According to a preferred embodiment, when the number of multi-channel intermediate frequency signal modules in the coherent signal generation system is greater than 1, the working clocks of the DAC digital-to-analog converters in each multi-channel intermediate frequency signal module are provided by the same external reference clock source, and the clock delays of the external reference clock source reaching each multi-channel intermediate frequency signal module are the same.

[0016] According to a preferred embodiment, the path delays of the external reference clock source input to the clock pins of the DAC digital-to-analog converters in each multi-channel intermediate frequency signal module are the same.

[0017] According to a preferred embodiment, when there are more than one multi-channel intermediate frequency signal modules in the coherent signal generation system, an external synchronous trigger signal unit is further provided between the multi-channel intermediate frequency signal modules. Each intermediate frequency signal module latches the received external signal control command and starts to calculate and generate the DAC data stream only after receiving the synchronous trigger signal from the external synchronous trigger signal unit.

[0018] According to a preferred embodiment, the paths of the traces for the external synchronous trigger signal unit to transmit the synchronous trigger signal to each multi-channel intermediate frequency signal module are set to be of equal length.

[0019] According to a preferred embodiment, the parameter characteristics of the sine signal generated by the DDS signal generator are determined by the initial phase, the phase accumulation value, and the phase accumulation step parameter.

[0020] According to a preferred embodiment, the local oscillator sources for up-conversion processing in each frequency conversion channel are the same-source signals.

[0021] The foregoing main solution of the present invention and its various further alternative solutions can be freely combined to form multiple solutions, all of which are solutions that can be adopted and claimed by the present invention. Those skilled in the art can understand that there are various combinations according to the prior art and common general knowledge after understanding the solution of the present invention, and all of them are the technical solutions to be protected by the present invention, and will not be enumerated here.

[0022] Advantages of the present invention: The multi-channel high-precision coherent signal generation system based on digital synchronous control of the present invention adopts multiple multi-channel intermediate frequency signal modules and the same-source local oscillator frequency conversion design, and combines the high-precision inter-board synchronization technology to realize the simulation of multi-channel coherent signals. It can ensure the high-quality coherence characteristics between the output signals of each channel and realize the high-precision control of the signal phase. The inter-channel coherence control accuracy is better than 1.5° and the phase adjustment resolution is less than 0.5° in the frequency band of 0.1 GHz to 18 GHz.

[0023] Compared with the traditional solution, the above solution can obtain a solution with higher integration and smaller hardware scale. Taking the generation of 16-channel coherent signals as an example, after statistics, the hardware scale (divided according to the functional modules in the conventional VPX structure form) can be reduced by about 25%, and the cost can be saved by about 55.5%, with excellent cost-effectiveness. Brief Description of the Drawings

[0024] Figure 1 is the architecture diagram of the multi-channel high-precision coherent signal generation system based on digital synchronous control of the present invention;

[0025] Figure 2 is the combined architecture diagram of digital synchronous control and multi-channel coherent signal generation of the multi-channel high-precision coherent signal generation system based on digital synchronous control of the present invention;

[0026] Figure 3 It is the control flow chart of multi-channel coherent signal generation of the system of the present invention;

[0027] Figure 4 It is the implementation structure diagram of an embodiment of the present invention. Detailed implementation manners

[0028] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0029] It should be noted that, for the purpose of making the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention are described clearly and completely below. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments.

[0030] To achieve high-precision synchronization control, the system should reasonably plan the control resources and the number of single-board channels in combination with the requirements during the control architecture and hardware design process.

[0031] In view of the limited resources of a single functional module, for the requirement of a large number of output channels, multiple intermediate-frequency signal modules are used for integrated design in the signal simulation device. Therefore, the multi-channel coherent signal generation technology not only needs to consider the signal synchronization generation control of multiple high-speed digital-to-analog converters (DAC devices) on a single board, but also needs to implement the synchronization control between multiple modules.

[0032] For the requirement of a small number of signal channels, a solution of using a single intermediate-frequency signal module to design the signal simulation device can be adopted, and it can be trimmed based on the control technology proposed in this article.

[0033] The technical architecture of the present invention is as shown in the reference Figures 1 to 3 As shown, the present invention discloses a multi-channel high-precision coherent signal generation system based on digital synchronization control. The coherent signal generation system includes an FPGA chip, a multi-channel intermediate-frequency signal module, and a frequency conversion channel.

[0034] Preferably, several DDS signal generators are provided inside the FPGA chip, and several DAC digital-to-analog converters are provided inside the multi-channel intermediate frequency signal module. The FPGA can control the DDS to generate digital signals with set phases according to the received signal parameter control commands, and form an intermediate frequency signal data stream when receiving a synchronous trigger signal. The data stream is sent to the DAC digital-to-analog converters of each channel for digital-to-analog conversion to generate intermediate frequency analog signals, which are then transmitted to each frequency conversion channel to complete up-conversion processing to obtain coherent signals.

[0035] Among them, the working clocks of the DAC digital-to-analog converters all adopt the same reference clock source.

[0036] Preferably, each DAC digital-to-analog converter has a synchronous control function pin, and each function pin is interconnected or connected to the control pin of the FPGA to complete the synchronous control of each DAC digital-to-analog converter.

[0037] The synchronous control of each DAC digital-to-analog converter includes: setting parameters for the synchronous control function register of each DAC digital-to-analog converter. After the configuration is completed, the status value of the synchronous control function register of each DAC digital-to-analog converter is read to ensure the working status and synchronous locking of each DAC digital-to-analog converter; when the read status value is abnormal, secondary configuration is performed until it is normal.

[0038] When the number of multi-channel intermediate frequency signal modules in the coherent signal generation system is greater than 1, the working clocks of the DAC digital-to-analog converters in each multi-channel intermediate frequency signal module are provided by the same external reference clock source. To achieve the synchronous of DAC channels between multiple boards, it is necessary to ensure that the clock delay of the reference clock source reaching each multi-channel intermediate frequency signal module is the same in terms of hardware.

[0039] The path delays of the external reference clock source input to the clock pins of the DAC digital-to-analog converters in each multi-channel intermediate frequency signal module are the same or a fixed value. And, in order to ensure the stability and reliability of the input clock, it is recommended to use phase-stabilized cables to transmit the clock in the signal analog device.

[0040] The data streams of each DDS signal generator use synchronous clock logic, and clock constraints are imposed on the wiring paths of the data streams generated by the DDS signal generators inside the FPGA chip. And the data lines from each DDS signal generator to the corresponding DAC digital-to-analog converter are set to be of equal length.

[0041] Specifically, the high-speed data streams for digital-to-analog conversion of each DAC device are all generated by the FPGA chip (programmable logic device). The data streams use synchronous clock logic, and clock constraints need to be imposed on the key wiring paths of these data streams inside the FPGA. Combining the equal-length control of all data lines in the hardware design, it is ensured that the time of all control data streams reaching the data ports of each DAC device is highly synchronized.

[0042] Preferably, when there are more than one multi-channel intermediate frequency signal modules in the coherent signal generation system, an external synchronous trigger signal unit is further provided between the multi-channel intermediate frequency signal modules. Each multi-channel intermediate frequency signal module latches the received external signal control command and starts the calculation and generation of the DAC data stream only after receiving the synchronous trigger signal from the external synchronous trigger signal unit. Otherwise, the synchronous control between multiple boards will be disordered.

[0043] The synchronous trigger signal is generally generated by an external control module after the signal control parameters are transmitted. In the hardware design, the paths of the wires transmitting the synchronous trigger signal of the external synchronous trigger signal unit to each multi-channel intermediate frequency signal module are set to be of equal length.

[0044] Preferably, to generate the radio frequency signal, the intermediate frequency signal needs to be up-converted. To ensure that the coherent intermediate frequency signals maintain a strict phase relationship after frequency conversion, the local oscillator sources for frequency conversion need to be of the same source signal.

[0045] Taking the radar signal as an example, the high-speed DAC digital-to-analog converter models the basic information model of the radar signal according to the received signal parameters, and generates a pulse data stream through operations. The basic information model of the radar signal mainly includes the carrier frequency f of the pulse RF , arrival time t TOA , pulse width τ PW , pulse power P A , in-pulse modulation information F, etc. The above parameters f RF , t TOA , τ PW , P A , F constitute the pulse data stream. The carrier frequency f RF , arrival time t TOA , pulse width τ PW , pulse power P A and other data models are as follows respectively:

[0046] 1) Carrier frequency model

[0047] The carrier frequency of the radar pulse can be divided into two categories: single carrier frequency and multi-carrier frequency. Among them, the multi-carrier frequency includes frequency agility and frequency diversity.

[0048] The RF model of the single carrier frequency is:

[0049]

[0050] The RF model of the multi-carrier frequency is calculated according to the following iterative formula.

[0051]

[0052] Where:

[0053] j(n)——Carrier frequency number of the current pulse;

[0054] j(n - 1)——Carrier frequency number of the previous pulse;

[0055] LF(n)——Remaining number of pulses with the same carrier frequency number as the current pulse;

[0056] LF(n - 1)——Remaining number of pulses with the same carrier frequency number as the previous pulse;

[0057] NF[j(n)]——Total number of pulses with the same carrier frequency number as the current pulse;

[0058] NRF——Total number of carrier frequencies;

[0059] NF(1)——Total number of pulses of the first carrier frequency number.

[0060]

[0061] 2) Pulse width model

[0062] The pulse width mainly includes single pulse and variable pulse width. The model of single pulse width is:

[0063]

[0064] The model of variable pulse width is calculated by an iterative formula:

[0065]

[0066] Where:

[0067] k(n)——Pulse width number of the current pulse;

[0068] k(n - 1)——Pulse width number of the previous pulse;

[0069] LW(n)——Remaining number of pulses with the same pulse width number as the current pulse;

[0070] LW(n - 1)——Remaining number of pulses with the same pulse width number as the previous pulse;

[0071] NW[k(n)]——Total number of pulses with the same pulse width number as the current pulse;

[0072] NPW——Total number of pulse widths;

[0073] NW(1)——Total number of pulses of the first pulse width number.

[0074]

[0075] 3) TOA model

[0076] The arrival time of the pulse front is mainly related to the pulse emission time, its propagation distance and propagation speed in the atmosphere. The pulse emission time is related to the pulse repetition interval (PRI) of the radar. The PRI is related to the specific radar signal type. For example, if the emission time of the previous pulse is t(n - 1), then the emission time t(n) of the current pulse is:

[0077] t(n) = t(n - 1) + t PRI (7)

[0078] As can be seen from the above, based on the signal mathematical model, the desired signal can be generated after programming on the hardware platform.

[0079] Next, the specific technical solution for generating signals within the hardware platform is described. According to the basic theory of digital signal processing, the mathematical expression of any periodic signal S(t) can be represented as:

[0080]

[0081] In the formula, A0 is the DC component and ω1 is the fundamental frequency. For aperiodic signals, after performing periodic extension in the time domain, the above expression is also applicable.

[0082] As can be seen from the above, any signal can be decomposed into the superposition of multiple sine / cosine signals. Therefore, in engineering practice, to ensure the flexibility and generality of the design, a technology system based on DDS can be used to realize signal generation.

[0083] FPGA devices have IP cores designed based on DDS. By using these IP cores, the set sine signal can be generated. The parameter characteristics of this signal are determined by parameters such as the initial phase, phase accumulation value, and phase accumulation step.

[0084] Therefore, when these digital control signals are strictly synchronized, the generated signals are also strictly synchronized. That is, through the control of the phase parameters, it can be ensured that all signals are coherent.

[0085] The multi-channel high-precision coherent signal generation system based on digital synchronous control of the present invention adopts multiple multi-channel intermediate-frequency signal modules and a homologous local oscillator frequency conversion design, combined with high-precision inter-board synchronization technology, to realize the simulation of multi-channel coherent signals. It can ensure the high-quality coherent characteristics between the output signals of each channel and achieve high-precision control of the signal phase. In the frequency band of 0.1 GHz to 18 GHz, the inter-channel coherent control accuracy is better than 1.5°, and the phase adjustment resolution is less than 0.5°.

[0086] Compared with traditional solutions, the above solution can achieve a solution with higher integration and smaller hardware scale. Taking the generation of 16-channel coherent signals as an example, after statistics, the hardware scale (divided according to the functional modules of the conventional VPX structure form) can be reduced by about 25%, and the cost can be saved by about 55.5%, with excellent cost-effectiveness.

[0087] Embodiment 1

[0088] Now, in combination with this embodiment and the attached drawings, the present invention will be further described: Generate 16-channel coherent signals, with a phase adjustment range of 0 to 360°, a phase accuracy of better than 1.5°, and a phase adjustment resolution of less than 0.5°.

[0089] According to the present invention, the specific implementation process is as follows:

[0090] The system uses multiple multi-channel intermediate frequency signal modules, and the structure form adopts the VPX structure standard. A single multi-channel intermediate frequency signal module can generate 4-channel intermediate frequency signals, and a total of 4 intermediate frequency signal modules are used to generate 16-channel signals.

[0091] Select a certain model of DAC device to design the corresponding intermediate frequency signal module. The synchronous configuration of multiple high-speed DAC chips is as Figure 4 shown.

[0092] First, in terms of hardware design, select one of the DACs as the main configuration chip, and all other DAC chips as slave configuration chips, and use the same high-precision temperature-compensated clock source to ensure the quality of clock skew and jitter. Secondly, the control signal interface and data lines from the FPGA to the DAC chips are designed to be of equal length, and the equal length accuracy is controlled within 1 mil. The DAC clock of the intermediate frequency signal module is provided by the backplane, and the clocks between all backplanes and the intermediate frequency signal modules are transmitted through phase-stabilized cables via the VXP radio frequency interface.

[0093] The control process is as follows:

[0094] A. Power on the device, and complete the initialization of the program after power on.

[0095] B. The real-time calculation control module sends the configuration parameters of each DAC channel to the corresponding intermediate frequency signal module. The FPGA in the intermediate frequency signal module starts to synchronously configure the DAC device, and reads the status flag value in the synchronous status register and returns it to the real-time calculation control module. The real-time calculation control module judges whether the status flag values of the DAC devices configured in 16 channels meet the design requirements. If they meet, the synchronous configuration ends; otherwise, reconfiguration is performed.

[0096] C. The upper computer sends the signal parameters of each channel to the real-time calculation control module, and the real-time calculation control module analyzes and forwards the external control parameters to the intermediate frequency signal module;

[0097] D. Ensure that after the signal parameters are sent, the real-time calculation control module generates a synchronous trigger signal. After each intermediate frequency signal module is effectively triggered, corresponding coherent signals are generated according to the received signal frequency information, phase information, and modulation information.

[0098] E. Determine whether there is new signal parameter input. If so, stop signal generation and wait for a new synchronous trigger signal to arrive; otherwise, maintain the current state.

[0099] Channels 1 and 8 in the multi-channel coherent signal simulation device are selected for testing. The signal type is conventional pulse modulation without intrapulse modulation, and the radio frequency is 600 MHz. The test results show that after implementing 155° phase modulation control on the phases of the two channels, the control accuracy is approximately 0.24°.

[0100] The implementation example verifies the correctness and engineering feasibility of the multi-channel high-precision coherent signal generation technology based on digital synchronous control.

[0101] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A multi-channel high-precision coherent signal generation system based on digital synchronous control, characterized in that, The coherent signal generation system includes an FPGA chip, a multi-channel intermediate frequency signal module, and a frequency conversion channel; Several DDS signal generators are provided inside the FPGA chip, and several DAC digital-to-analog converters are provided inside the multi-channel intermediate frequency signal module. Several DDS signal generators are provided inside the FPGA chip, and several DAC digital-to-analog converters are provided inside the multi-channel intermediate frequency signal module. The FPGA can control the DDS to generate digital signals with set phases according to the received signal parameter control commands, and form an intermediate frequency signal data stream when receiving a synchronous trigger signal; The data stream is sent to the DAC digital-to-analog converters of each channel for digital-to-analog conversion to generate intermediate frequency analog signals, and then transmitted to each frequency conversion channel to complete up-conversion processing to obtain coherent signals; Among them, the working clocks of each DAC digital-to-analog converter use the same reference clock source; the data streams of each DDS signal generator use synchronous clock logic, and clock constraints are performed on the wiring paths of the data streams generated by the DDS signal generators inside the FPGA chip; and the data lines from each DDS signal generator to the corresponding DAC digital-to-analog converter are set to be of equal length; Each DAC digital-to-analog converter has a synchronous control function pin, and each function pin is interconnected or connected to the control pin of the FPGA to complete the synchronous control of each DAC digital-to-analog converter; The synchronous control of each DAC digital-to-analog converter includes: Parameters are set for the synchronous control function registers of each DAC digital-to-analog converter. After the configuration is completed, the status values of the synchronous control function registers of each DAC digital-to-analog converter are read to ensure the working status and synchronous locking of each DAC digital-to-analog converter; when the read status value is abnormal, secondary configuration is performed until it is normal.

2. The coherent signal generation system according to claim 1, characterized in that When the number of multi-channel intermediate frequency signal modules in the coherent signal generation system is greater than 1, the working clocks of the DAC digital-to-analog converters in each multi-channel intermediate frequency signal module are provided by the same external reference clock source, and the clock delays of the external reference clock source reaching each multi-channel intermediate frequency signal module are the same.

3. The coherent signal generation system according to claim 2, wherein The path delays of the external reference clock source input to the clock pins of the DAC digital-to-analog converters in each multi-channel intermediate frequency signal module are the same.

4. The coherent signal generation system according to claim 2, wherein When the number of multi-channel intermediate frequency signal modules in the coherent signal generation system is greater than 1, an external source synchronous trigger signal unit is also provided between each multi-channel intermediate frequency signal module. Each intermediate frequency signal module latches the received external signal control command and starts the calculation and generation of the DAC data stream only after receiving the synchronous trigger signal from the external source synchronous trigger signal unit.

5. The coherent signal generation system according to claim 4, wherein The paths of the wires for the external source synchronous trigger signal unit to transmit the synchronous trigger signal to each multi-channel intermediate frequency signal module are set to be of equal length.

6. The coherent signal generation system according to claim 1, wherein The parameter characteristics of the sine signal generated by the DDS signal generator are determined by the initial phase, the phase accumulation value, and the phase accumulation step parameter.

7. The coherent signal generation system according to claim 1, wherein The local oscillator sources for up-conversion processing in each frequency conversion channel are homologous signals.

Images