Display device

Abstract

Provided is a display device including a base layer, a circuit layer, a light-emitting device layer, a thin film encapsulation layer, and a touch sensing unit that are sequentially arranged. The base layer includes a display area and a non-display area. The light-emitting device layer includes an organic light-emitting diode, a pixel defining layer, a connection electrode including a plurality of holes, and a plurality of insulating patterns that overlap with the plurality of holes and include first insulating patterns spaced apart from each other. The touch sensing unit includes at least one touch insulating layer, a plurality of touch electrodes, and a plurality of touch signal lines connected to the plurality of touch electrodes. The plurality of touch electrodes include a first touch electrode in a first direction and a second touch electrode in a second direction intersecting the first direction. The plurality of touch signal lines include a first touch signal line connected to the first touch electrode and a second touch signal line connected to the second touch electrode. At least a part of the first touch signal line extends in the first direction, and the part of the first touch signal line overlaps with the first insulating pattern.

Description

[0001] This application is a divisional application of the patent application No. 201710623671.7, with the invention title of "display device", which was filed with the State Intellectual Property Office on July 27, 2017. Technical Field

[0002] Exemplary embodiments of the present disclosure relate to a display device, and more particularly, to a display device integrated with a touch sensing unit. Background Art

[0003] Currently, various display devices are being developed for multimedia devices such as televisions, mobile phones, tablet computers, navigation devices, and game consoles. A keyboard or a mouse is included as an input device of the display device. In addition, recent display devices include a touch panel as an input device.

[0004] The above information disclosed in this background art section is only for enhancing the understanding of the background of the inventive concept, and thus, it may include information that does not form the prior art already known to those of ordinary skill in the art in the country. Summary of the Invention

[0005] Exemplary embodiments of the present disclosure provide a touch sensing unit integrated display device with reduced noise.

[0006] Additional aspects will be set forth in the detailed description below, and in part, will be apparent from the disclosure, or may be learned by practice of the inventive concept.

[0007] Exemplary embodiments of the inventive concept disclose a display device, the display device including: a base layer including a display area and a non-display area; a circuit layer including at least one intermediate insulating layer and a power supply electrode stacked on the non-display area, the circuit layer being disposed on the base layer; a light emitting device layer including an organic light emitting diode including a first electrode, a light emitting layer, and a second electrode disposed on the circuit layer, a pixel defining layer including an opening exposing the first electrode, a connection electrode connecting the second electrode to the power supply electrode and including a plurality of holes, and a plurality of insulating patterns stacked on the plurality of holes; a thin film encapsulation layer including an organic layer stacked on the plurality of insulating patterns and the organic light emitting diode and disposed on the light emitting device layer; and a touch sensing unit including at least one touch insulating layer, a plurality of touch electrodes, and a plurality of touch signal lines connected to the plurality of touch electrodes and disposed on the thin film encapsulation layer. At least a part of the plurality of touch signal lines is stacked on the plurality of insulating patterns.

[0008] Exemplary embodiments of the inventive concept also disclose a display device, the display device including: a base layer including a display area and a non-display area; a circuit layer disposed on the base layer; a light-emitting device layer including light-emitting diodes disposed on the circuit layer, a pixel defining layer including a first electrode exposing the light-emitting diodes, and a plurality of insulating patterns stacked with the non-display area; an organic layer disposed on the light-emitting device layer and stacked with the plurality of insulating patterns and the light-emitting diodes; and a touch sensing unit including a plurality of touch electrodes and a plurality of touch signal lines connected to the plurality of touch electrodes and disposed on the organic layer. At least a part of the plurality of touch signal lines is stacked with the plurality of insulating patterns.

[0009] The foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The drawings, which are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the inventive concept and, together with the specification, serve to explain the principles of the inventive concept.

[0011] Figure 1A is a perspective view of a display device according to a first operation of an exemplary embodiment of the inventive concept.

[0012] Figure 1B is a perspective view of a display device according to a second operation of an exemplary embodiment of the inventive concept.

[0013] Figure 1C is a perspective view of a display device according to a third operation of an exemplary embodiment of the inventive concept.

[0014] Figure 2 is a cross-sectional view of a display device according to an exemplary embodiment of the inventive concept.

[0015] Figure 3A and Figure 3B is a perspective view of a display device according to an exemplary embodiment of the inventive concept.

[0016] Figure 4 is a perspective view of a display device according to an exemplary embodiment of the inventive concept.

[0017] Figure 5A is a cross-sectional view of a display module according to an exemplary embodiment of the inventive concept.

[0018] Figure 5B is a plan view of an organic light-emitting display panel according to an exemplary embodiment of the inventive concept.

[0019] Figure 6AIt is an equivalent circuit diagram of a pixel according to an exemplary embodiment of the inventive concept.

[0020] Figure 6B and Figure 6C It is a partial cross-sectional view of an organic light-emitting display panel according to an exemplary embodiment of the inventive concept.

[0021] Figure 7A 、 Figure 7B and Figure 7C It is a cross-sectional view of a thin film encapsulation layer according to an exemplary embodiment of the inventive concept.

[0022] Figure 8A It is a cross-sectional view of a touch sensing unit according to an exemplary embodiment of the inventive concept.

[0023] Figure 8B 、 Figure 8C 、 Figure 8D 、 Figure 8E and Figure 8F It is a plan view of a touch sensing unit according to an exemplary embodiment of the inventive concept.

[0024] Figure 9A It is a cross-sectional view of a display module according to an exemplary embodiment of the inventive concept.

[0025] Figure 9B It is a cross-sectional view of a display module according to a comparative example.

[0026] Figure 10 It is a plan view of a display module according to an exemplary embodiment of the inventive concept.

[0027] Figure 11A It is an enlarged plan view of a part of a display module according to an exemplary embodiment of the inventive concept.

[0028] Figure 11B is along Figure 11A A cross-sectional view of a display module according to an exemplary embodiment of the inventive concept taken along line I-I'.

[0029] Figure 11C is along Figure 11A A cross-sectional view of a display module according to a comparative example of the inventive concept taken along line I-I'.

[0030] Figure 11D is Figure 11B An enlarged cross-sectional view of a part of

[0031] Figure 12A 、 Figure 12B and Figure 12C It is an enlarged plan view of a part of a display module according to an exemplary embodiment of the inventive concept.

[0032] Figure 13A and Figure 13B are cross-sectional views of a display module according to an exemplary embodiment of the inventive concept. Detailed Description

[0033] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various exemplary embodiments. It is evident, however, that the various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various exemplary embodiments.

[0034] In the drawings, for clarity and description purposes, the dimensions and relative dimensions of layers, films, panels, regions, etc. may be exaggerated. Additionally, like reference numerals denote like elements.

[0035] When an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it may be directly on, directly connected to, or directly coupled to the other element or layer or intervening elements or layers may be present. However, when an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, no intervening elements or layers are present. For purposes of the present disclosure, “at least one of (a) X, Y, and Z” and “selected from the group consisting of at least one of (a) X, Y, and Z” may be construed to mean only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, by way of example, XYZ, XYY, YZ, and ZZ. Like reference numerals always denote like elements. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0036] Although terms such as first, second, etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, and / or section from another element, component, region, layer, and / or section. Thus, a first element, component, region, layer, and / or section discussed below may be referred to as a second element, component, region, layer, and / or section without departing from the teachings of the present disclosure.

[0037] Spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used for descriptive purposes to describe the relationship of one element or feature to another element or feature as shown in the figures. In addition to the orientation depicted in the figures, spatial relative terms are also intended to encompass different orientations of the device during use, operation, and / or manufacture. For example, if the device in the figures is flipped, an element described as "below" or "beneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary term "below" can include both an upper and a lower orientation. Additionally, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and thus, the spatial relative descriptors used herein are to be interpreted accordingly.

[0038] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. As used herein, unless the context clearly dictates otherwise, the singular forms "a", "an", and "the" are also intended to include the plural forms. Additionally, when the terms "comprises", "comprising", and their various variations are used in this specification, they specify the presence of the stated features, integers, steps, operations, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0039] Various exemplary embodiments are described herein with reference to cross-sections that are schematic illustrations of idealized exemplary embodiments and / or intermediate structures. As such, variations in shapes as a result of, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, the exemplary embodiments disclosed herein should not be construed as limiting the shape of the specifically illustrated regions, but rather include deviations in shapes resulting from, for example, manufacturing. The regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device nor are they intended to be limiting.

[0040] All terms used herein, unless otherwise defined, have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Unless specifically defined herein, terms (such as those defined in a general dictionary) should be construed to have a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense.

[0041] Figure 1A is a perspective view of a display device DD according to a first operation of an exemplary embodiment of the inventive concept. Figure 1B is a perspective view of a display device DD according to a second operation of an exemplary embodiment of the inventive concept.Figure 1C is a perspective view of a display device DD according to a third operation of an exemplary embodiment according to the inventive concept.

[0042] As Figure 1A shown, in the first operation mode, the display surface IS of the display image IM is parallel to the surface defined by the first direction axis DR1 and the second direction axis DR2. The normal direction of the display surface IS (i.e., the thickness direction of the display device DD) indicates the third direction axis DR3. The front surface (or upper surface) and the rear surface (or lower surface) of each member are divided by the third direction axis DR3. However, the directions indicated by the first direction axis to the third direction axis DR1, DR2, and DR3 can be changed to other directions as relative concepts. Hereinafter, the first direction to the third direction as the directions indicated by the first direction axis to the third direction axis DR1, DR2, and DR3 respectively are applied to the same reference numerals.

[0043] Figures 1A to 1C shows a foldable display device as an example of the flexible display device DD. However, the inventive concept may relate to a rollable display device or a bendable display device and is not specifically limited. In addition, although a flexible display device is shown in this exemplary embodiment, the inventive concept is not limited thereto. The display device DD according to this exemplary embodiment may be a planar rigid display device. In addition to large-sized electronic devices such as televisions and monitors, the flexible display device DD can also be used in small-sized and medium-sized electronic devices such as mobile phones, tablet computers, in-vehicle navigators, game consoles, and smart watches.

[0044] As Figure 1A shown, the display surface IS of the flexible display device DD may include a plurality of regions. The flexible display device DD may include a display region DD-DA for displaying the display image IM and a non-display region DD-NDA adjacent to the display region DD-DA. The non-display region DD-NDA is a region where no image is displayed. Figure 1A shows a vase as an example of the image IM. As an example, the display region DD-DA may have a rectangular shape. The non-display region DD-NDA may surround the display region DD-DA. However, the inventive concept is not limited thereto, and the shapes of the display region DD-DA and the non-display region DD-NDA can be designed relatively.

[0045] As Figures 1A to 1C shown, the display device DD may include a plurality of regions defined according to the operation form. The display device DD may include a bending region BA bent based on the bending axis BX, a first non-bending region NBA1, and a second non-bending region NBA2. As Figure 1BAs shown, the display device DD may be bent inward to allow the display surfaces IS of the first non-bent region NBA1 and the second non-bent region NBA2 to face each other. As Figure 1C As shown, the display device DD may be bent outward to allow the display surface IS to be exposed to the outside.

[0046] According to an exemplary embodiment of the inventive concept, the display device DD may include a plurality of bending regions BA. In addition, the bending regions BA may be defined according to how the user manipulates the display device DD. For example, different from Figure 1B and Figure 1C the bending regions BA may be defined to be parallel to the first direction axis DR1 or may be defined in the diagonal direction. The area of the bending regions BA is not fixed but may be determined according to the radius of curvature. According to an exemplary embodiment of the inventive concept, the display device DD may be configured to only repeat Figure 1A and Figure 1B the operation modes shown.

[0047] Figure 2 is a cross-sectional view of the display device DD according to an exemplary embodiment of the inventive concept. Figure 2 shows a cross-section defined by the second direction axis DR2 and the third direction axis DR3.

[0048] As Figure 2 shown, the display device DD may include a protective film PM, a display module DM, an optical member LM, a window WM, a first adhesive member AM1, a second adhesive member AM2, and a third adhesive member AM3. The display module DM is disposed between the protective film PM and the optical member LM. The optical member LM is disposed between the display module DM and the window WM. The first adhesive member AM1 bonds the display module DM and the protective film PM, the second adhesive member AM2 bonds the display module DM and the optical member LM, and the third adhesive member AM3 bonds the optical member LM and the window WM. Although Figure 2 shown that the lengths of the protective film PM, the display module DM, the optical member LM, the window WM, the first adhesive member AM1, the second adhesive member AM2, and the third adhesive member AM3 in the second direction DR2 are the same, the display device DD according to the inventive concept is not limited thereto.

[0049] The protective film PM protects the display module DM. The protective film PM provides a first outer surface OS-L exposed to the outside and provides an adhesive surface adhered to the first adhesive member AM1. The protective film PM may absorb external shocks and inhibit moisture from penetrating into the display module DM.

[0050] The protective film PM may include a plastic film as a base layer. The protective film PM may include a plastic film as a base substrate. The protective film PM may include a plastic film, and the plastic film includes at least one selected from the group consisting of polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), poly(arylene ether sulfone), and combinations thereof. The material constituting the protective film PM is not limited to plastic resins and may also include organic / inorganic composite materials. The protective film PM may include an organic layer and an inorganic material filled in the pores of the porous organic layer. The protective film PM may also include a functional layer formed on the plastic film. The functional layer may include a resin layer. The functional layer may be formed by a coating method. According to an exemplary embodiment of the inventive concept, the protective film PM may be omitted.

[0051] A window WM is provided, and an adhesion surface adhered to a third adhesive member AM3 is provided. Refer to Figures 1A to 1C , the window WM may protect the display module DM from external impacts and provide an input surface to the user. The display surface IS of the window WM may be a second outer surface OS-U.

[0052] The window WM may include a plastic film as a base substrate. The window WM may have a multi-layer structure. The base member of the window WM may have a multi-layer structure selected from a glass substrate, a plastic film, and a plastic substrate. The window WM may also include a border pattern. The multi-layer structure may be formed by a continuous process or an adhesion process using an adhesive layer. In addition, the window WM may also include a functional layer provided at the base member. The functional layer may include a hard coat, an anti-fingerprint layer, an anti-reflection layer, and a self-healing layer.

[0053] The optical member LM reduces the reflectivity of external light. The optical member LM may include at least one polarizing film. The optical member LM may also include a retardation film. According to an exemplary embodiment of the inventive concept, the optical member LM may be omitted.

[0054] The display module DM may include a display panel DP and a touch sensing unit TS. The display panel DP may be an organic light emitting display panel, but is not specifically limited thereto. For example, the display panel DP may be a quantum dot light emitting display panel as another type of self-luminous display panel. For the quantum dot light emitting display panel, the light emitting layer includes quantum dots and quantum rods. Hereinafter, the display panel DP will be described as an "organic light emitting display panel".

[0055] The touch sensing unit TS is directly provided on the organic light emitting display panel DP. In this specification, "directly provided" means "formed" by a continuous process and does not include "attached" by an additional adhesive layer.

[0056] The organic light emitting display panel DP generates an image IM corresponding to input image data (see Figure 1A ). The organic light emitting display panel DP provides a first display panel surface BS1-L and a second display panel surface BS1-U facing the thickness direction DR3. In this exemplary embodiment, although the organic light emitting display panel DP is described, the display panel is not limited thereto.

[0057] The touch sensing unit TS obtains coordinate information of an external input. For example, the touch sensing unit TS may detect an external input by a capacitive method. In this inventive concept, the operation method of the touch sensing unit TS is not specifically limited thereto, and according to an exemplary embodiment of the inventive concept, the touch sensing unit TS may detect an external input by an electromagnetic induction method or a pressure detection method.

[0058] Although not shown separately, the display module DM according to an exemplary embodiment of the inventive concept may further include an anti-reflection layer. The anti-reflection layer may include a color filter or a stacked structure of a conductive layer / insulating layer / conductive layer. The anti-reflection layer may reduce the external light reflectance by absorbing, destructively interfering with light incident from the outside, or polarizing light incident from the outside. The anti-reflection layer may replace the function of the optical member LM.

[0059] Each of the first adhesive member AM1, the second adhesive member AM2, and the third adhesive member AM3 may be an organic adhesive layer such as an optically clear adhesive (OCA) film, an optically clear resin (OCR), or a pressure sensitive adhesive (PSA) film. The organic adhesive layer may include an adhesive material such as polyurethane, polyacrylic acid, polyester, polyepoxy, and polyvinyl acetate. As a result, the organic adhesive layer corresponds to one of the plurality of organic layers.

[0060] Although not shown separately, the display device DD may further include a frame structure for supporting the functional layer to maintain Figures 1A to 1C the state shown in

[0061] Figure 3A and Figure 3B are perspective views of a display device DD-1 according to an exemplary embodiment of the inventive concept. Figure 3A shows the display device DD-1 in an unfolded state, Figure 3B shows the display device DD-1 in a bent state. Figure 4 is a perspective view of a display device DD-2 according to an exemplary embodiment of the inventive concept.

[0062] As Figure 3A and 3BAs shown, the display device DD-1 may include a bent area BA and a non-bent area NBA. The non-display area DD-NDA of the display device DD-1 may be bent. However, according to an exemplary embodiment of the inventive concept, the bent area of the display device DD-1 may be changed.

[0063] Different from Figures 1A to 1C the display device DD shown in Figure 3B As shown, the display device DD-1 may be a bent display device that operates in a bent state. The display device DD-1 may be fixed in a bent state at a frame, and the frame may be coupled to a housing of an electronic device.

[0064] The display device DD-1 may have the same cross-sectional structure as Figure 2 shown. However, the non-bent area NBA and the bent area BA may have different stack structures. The non-bent area NBA may have the same cross-sectional structure as Figure 2 shown, while the bent area BA may have a cross-sectional structure different from Figure 2 shown. The optical member LM and the window WM do not need to be disposed in the bent area BA. That is, the optical member LM and the window WM may be disposed only in the non-bent area NBA. The second adhesive member AM2 and the third adhesive member AM3 also do not need to be disposed in the bent area BA.

[0065] As Figure 4 shown, the display device DD-2 may include a bent area BA and a non-bent area NBA. A bent area BA may be defined along an edge of the display device DD-2 that extends in a first direction DR1. However, according to an exemplary embodiment of the inventive concept, the display device DD-2 may include two bent areas facing each other in a second direction DR2. The two bent areas may extend in the first direction DR1 and may both extend along two edges facing each other in the second direction DR2.

[0066] Figure 5A is a cross-sectional view of a display module DM according to an exemplary embodiment of the inventive concept. Figure 5B is a plan view of an organic light emitting display panel DP according to an exemplary embodiment of the inventive concept. Figure 6A is an equivalent circuit diagram of a pixel PXi according to an exemplary embodiment of the inventive concept. Figure 6B and Figure 6C are partial cross-sectional views of an organic light emitting display panel DP according to an exemplary embodiment of the inventive concept.

[0067] As Figure 5AAs shown in the figure, the organic light-emitting display panel DP includes a base layer SUB, a circuit layer DP-CL disposed on the base layer SUB, a light-emitting device layer DP-OLED, and a thin film encapsulation layer TFE. The base layer SUB may include at least one plastic film. The base layer SUB may include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite substrate as a flexible substrate.

[0068] The circuit layer DP-CL may include at least one intermediate insulating layer, a plurality of conductive layers, and a semiconductor layer. The plurality of conductive layers of the circuit layer DP-CL may constitute signal lines or a driving circuit of a pixel. The light-emitting device layer DP-OLED includes at least an organic light-emitting diode. The thin film encapsulation layer TFE seals the light-emitting device layer DP-OLED. The thin film encapsulation layer TFE includes an inorganic layer and an organic layer. The thin film encapsulation layer TFE may include at least two inorganic layers and an organic layer therebetween. The inorganic layer protects the light-emitting device layer DP-OLED from moisture / oxygen, and the organic layer protects the light-emitting device layer DP-OLED from foreign substances such as dust particles. The inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic layer may include an acrylate-based organic layer, but is not limited thereto.

[0069] The touch sensing unit TS is directly disposed on the thin film encapsulation layer TFE. The touch sensing unit TS includes touch electrodes and touch signal lines. The touch electrodes and touch signal lines may have a single-layer structure or a multi-layer structure.

[0070] The touch electrodes and touch signal lines may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowires, or graphene. The touch electrodes and touch signal lines may include a metal layer, for example, molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The touch electrodes and touch signal lines may have the same or different layer structures. The specific content of the touch sensing unit TS will be described later.

[0071] As Figure 5B shown in the figure, the organic light-emitting display panel DP includes a display area DA and a non-display area NDA on a plane. In this exemplary embodiment, the non-display area NDA may be defined along the contour of the display area DA. The display area DA and the non-display area NDA of the organic light-emitting display panel DP respectively correspond to the display area DD-DA and the non-display area DD-NDA of the display device DD. The display area DA and the non-display area NDA of the organic light-emitting display panel DP do not have to be the same as the display area DD-DA and the non-display area DD-NDA of the display device DD, but may be changed according to the structure / design of the organic light-emitting display panel DP.

[0072] The organic light emitting display panel DP includes a driving circuit, a plurality of signal lines SL-Vint, SL-VDD, EL, GL, DL, and SL-D, a power electrode E-VSS, and a plurality of pixels PX. The area where the plurality of pixels PX are provided may be defined as a display area DA.

[0073] The driving circuit may include a scan driving circuit GDC. The scan driving circuit GDC generates a plurality of scan signals and sequentially outputs the plurality of scan signals to a plurality of scan lines GL described later. In addition, the scan driving circuit GDC generates a plurality of light emission control signals and outputs the plurality of light emission control signals to a plurality of light emission control lines EL described later.

[0074] Although Figure 5B it is shown that a plurality of scan signals and a plurality of light emission control signals are output from one scan driving circuit GDC, the inventive concept is not limited thereto. According to an exemplary embodiment of the inventive concept, a plurality of scan driving circuits may split and output a plurality of scan signals and split and output a plurality of light emission control signals. In addition, according to an exemplary embodiment of the inventive concept, the driving circuit for generating and outputting a plurality of scan signals and the driving circuit for generating and outputting a plurality of light emission control signals may be separated and separated from each other. Another scan driving circuit facing the scan driving circuit GDC shown in Figure 5B may be further provided in the second direction DR2.

[0075] The scan driving circuit GDC may be included in the circuit layer DP-CL. The scan driving circuit GDC may include a plurality of thin film transistors, and the plurality of thin film transistors are formed by the same process as the driving circuit of the pixel PX.

[0076] Although not separately shown in the figure, the organic light emitting display panel DP may further include a data driving circuit bonded to the pad PD in the form of a chip on film (COF). According to an exemplary embodiment of the inventive concept, the data driving circuit may also be integrated on the circuit layer DP-CL.

[0077] The plurality of signal lines GL, DL, EL, SL-VDD, SL-Vint, and SL-D may include scan lines GL, light emission control lines EL, data lines DL, power supply lines SL-VDD, initialization voltage lines SL-Vint, and dummy signal lines SL-D. The plurality of signal lines GL, DL, EL, SL-VDD, SL-Vint, and SL-D may be included in the circuit layer DP-CL, and some lines may be omitted. The pad PD may be connected to the ends of the plurality of signal lines GL, DL, EL, SL-VDD, SL-Vint, and SL-D.

[0078] A plurality of scan lines GL are respectively connected to corresponding pixels PX among the plurality of pixels PX, and a plurality of data lines DL are respectively connected to corresponding pixels PX among the plurality of pixels PX. Each of the emission control lines EL may be arranged parallel to a corresponding one of the plurality of scan lines GL.

[0079] The power supply line SL-VDD may be connected to the plurality of pixels PX and supply a first power supply voltage to the plurality of pixels PX. The power supply line SL-VDD may include a plurality of lines extending in a first direction DR1 and a plurality of lines extending in a second direction DR2.

[0080] The initialization voltage line SL-Vint may supply an initialization voltage to the plurality of pixels PX. The initialization voltage line SL-Vint may include a plurality of lines extending in a first direction DR1 and a plurality of lines extending in a second direction DR2.

[0081] The dummy signal line SL-D may supply a control signal to the scan driving circuit GDC. The dummy signal line SL-D may supply a second power supply voltage to the power supply electrode E-VSS. The second power supply voltage has a voltage level different from that of the first power supply voltage. The second power supply voltage may have a voltage level lower than that of the first power supply voltage.

[0082] The power supply electrode E-VSS is provided in the non-display area NDA and has a shape extending along the contour of the base layer SUB. As Figure 5B shown, the power supply electrode E-VSS may have a shape facing the three-side contour. The power supply electrode E-VSS may also be included in the circuit layer DP-CL.

[0083] Figure 6A Exemplarily shown is the i-th pixel PXi connected to the k-th data line DLk among the plurality of data lines DL1 to DLm. The i-th pixel PXi is activated in response to the i-th scan signal Si applied to the i-th scan line GLi.

[0084] The i-th pixel PXi includes an organic light-emitting diode OLED and a pixel driving circuit for controlling the organic light-emitting diode OLED. The pixel driving circuit may include seven thin film transistors T1 to T7 and a capacitor Cst. Although a pixel driving circuit including seven thin film transistors T1 to T7 and a capacitor Cst is shown in the exemplary embodiment, it is sufficient that the pixel PXi includes a first transistor T1 (or driving transistor), a second transistor T2 (or switching transistor), and a capacitor Cst as a driving circuit for driving the organic light-emitting diode OLED, and the pixel driving circuit may be modified in various ways.

[0085] The driving transistor controls a driving current supplied to the organic light emitting diode OLED. An output electrode of the second transistor T2 is electrically connected to the organic light emitting diode OLED. The output electrode of the second transistor T2 may directly contact a first electrode of the organic light emitting diode OLED or may be connected to the first electrode of the organic light emitting diode OLED through another transistor (e.g., the sixth transistor T6 in this exemplary embodiment).

[0086] A control electrode of the control transistor may receive a control signal. The control signal applied to the i-th pixel PXi may include the (i - 1)-th scan signal Si - 1, the i-th scan signal Si, the (i + 1)-th scan signal Si + 1, a data signal Dk, and the i-th light emission control signal Ei. According to an exemplary embodiment of the inventive concept, the control transistor may include a first transistor T1 and third transistors T3 to T7.

[0087] The first transistor T1 includes an input electrode connected to the k-th data line DLk, a control electrode connected to the i-th scan line Gli, and an output electrode connected to an output electrode of the second transistor T2. The first transistor T1 is turned on by the scan signal Si (hereinafter, referred to as the i-th scan signal) applied to the i-th scan line Gli and provides the data signal Dk applied to the k-th data line DLk to the capacitor Cst.

[0088] Figure 6B is a cross-sectional view of a portion corresponding to the first transistor T1 of the equivalent circuit shown in Figure 6A is a cross-sectional view of a portion corresponding to the second transistor T2, the sixth transistor T6, and the organic light emitting diode OLED of the equivalent circuit shown in Figure 6C is Figure 6A in the cross-sectional view of a portion corresponding to the second transistor T2, the sixth transistor T6, and the organic light emitting diode OLED of the equivalent circuit shown in

[0089] Referring to Figure 6B and Figure 6C , a buffer layer BFL may be disposed on the base layer SUB. The buffer layer BFL improves the bonding strength between the base layer SUB and the conductive pattern or the semiconductor pattern. The buffer layer BFL may include an inorganic layer. Although not separately shown in the drawings, a barrier layer for preventing foreign substances from entering may be further disposed on an upper surface of the base layer SUB. The buffer layer BFL and the barrier layer may be selectively provided / omitted.

[0090] The semiconductor pattern OSP1 of the first transistor T1 (hereinafter referred to as the first semiconductor pattern), the semiconductor pattern OSP2 of the second transistor T2 (hereinafter referred to as the second semiconductor pattern), and the semiconductor pattern OSP6 of the sixth transistor T6 (hereinafter referred to as the sixth semiconductor pattern) are disposed on the buffer layer BFL. The first semiconductor pattern OSP1, the second semiconductor pattern OSP2, and the sixth semiconductor pattern OSP6 may be selected from amorphous silicon, polysilicon, and metal oxide semiconductor.

[0091] The first insulating layer 10 may be disposed on the first semiconductor pattern OSP1, the second semiconductor pattern OSP2, and the sixth semiconductor pattern OSP6. Although the first insulating layer 10 is shown in Figure 6B and Figure 6C as a layer shape covering the first semiconductor pattern OSP1, the second semiconductor pattern OSP2, and the sixth semiconductor pattern OSP6, the first insulating layer 10 may be disposed as a pattern corresponding to the first semiconductor pattern OSP1, the second semiconductor pattern OSP2, and the sixth semiconductor pattern OSP6.

[0092] The first insulating layer 10 may include a plurality of inorganic layers. The plurality of inorganic layers may include a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer.

[0093] The control electrode GE1 of the first transistor T1 (hereinafter referred to as the "first control electrode"), the control electrode GE2 of the second transistor T2 (hereinafter referred to as the "second control electrode"), and the control electrode GE6 of the sixth transistor T6 (hereinafter referred to as the "sixth control electrode") are disposed on the first insulating layer 10. The first control electrode GE1, the second control electrode GE2, and the sixth control electrode GE6 may be manufactured according to the same lithography process as the lithography process of the scan line GL (see Figure 5A ).

[0094] The second insulating layer 20 for covering the first control electrode GE1, the second control electrode GE2, and the sixth control electrode GE6 may be disposed on the first insulating layer 10. The second insulating layer 20 may provide a flat upper surface. The second insulating layer 20 may include an organic material and / or an inorganic material.

[0095] The input electrode SE1 (hereinafter referred to as the "first input electrode") and the output electrode DE1 (hereinafter referred to as the "first output electrode") of the first transistor T1, the input electrode SE2 (hereinafter referred to as the "second input electrode") and the output electrode DE2 (hereinafter referred to as the "second output electrode") of the second transistor T2, and the input electrode SE6 (hereinafter referred to as the "sixth input electrode") and the output electrode DE6 (hereinafter referred to as the "sixth output electrode") of the sixth transistor T6 are disposed on the second insulating layer 20.

[0096] The first input electrode SE1 and the first output electrode DE1 are respectively connected to the first semiconductor pattern OSP1 through a first through hole CH1 and a second through hole CH2 penetrating through the first insulating layer 10 and the second insulating layer 20. The second input electrode SE2 and the second output electrode DE2 are respectively connected to the second semiconductor pattern OSP2 through a third through hole CH3 and a fourth through hole CH4 penetrating through the first insulating layer 10 and the second insulating layer 20. The sixth input electrode SE6 and the sixth output electrode DE6 are respectively connected to the sixth semiconductor pattern OSP6 through a fifth through hole CH5 and a sixth through hole CH6 penetrating through the first insulating layer 10 and the second insulating layer 20. On the other hand, according to another exemplary embodiment of the inventive concept, at least one of the first transistor T1, the second transistor T2, and the sixth transistor T6 may be modified and implemented as a bottom gate structure.

[0097] A third insulating layer 30 for covering the first input electrode SE1, the second input electrode SE2, the sixth input electrode SE6, the first output electrode DE1, the second output electrode DE2, and the sixth output electrode DE6 is disposed on the second insulating layer 20. The third insulating layer 30 may include an organic layer and / or an inorganic layer. The third insulating layer 30 may further include an organic material for providing a flat surface.

[0098] The first insulating layer 10, the second insulating layer 20, and the third insulating layer 30 may be defined as "intermediate insulating layers". One of the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30 may be omitted according to the circuit structure of the pixel.

[0099] A pixel defining layer PDL and an organic light emitting diode OLED are disposed on the third insulating layer 30. A first electrode AE is disposed on the third insulating layer 30. The first electrode AE is connected to the sixth output electrode DE6 through a seventh through hole CH7 penetrating through the third insulating layer 30. An opening OP is defined in the pixel defining layer PDL. At least a portion of the first electrode AE is exposed by the opening OP of the pixel defining layer PDL.

[0100] Pixels PX can be disposed in a pixel region on a plane. The pixel region may include a light-emitting region PXA and a non-light-emitting region NPXA adjacent to the light-emitting region PXA. The non-light-emitting region NPXA may surround the light-emitting region PXA. According to this exemplary embodiment, the light-emitting region PXA is defined corresponding to a partial region of the first electrode AE exposed by the opening OP.

[0101] The hole control layer HCL can be commonly disposed in the light-emitting region PXA and the non-light-emitting region NPXA. Although not separately shown in the figure, a common layer such as the hole control layer HCL can be commonly formed in a plurality of pixels PX (see Figure 5A ).

[0102] The light-emitting layer EML is disposed on the hole control layer HCL. The light-emitting layer EML can be disposed in a region corresponding to the opening OP. That is, the light-emitting layer EML can be split and formed at each of a plurality of pixels PX. The light-emitting layer EML may include an organic material and / or an inorganic material. Although the patterned light-emitting layer EML is shown according to this exemplary embodiment, the light-emitting layer EML can be commonly disposed in a plurality of pixels PX. At this time, the light-emitting layer EML can generate white light. In addition, the light-emitting layer EML may have a multilayer structure.

[0103] The electron control layer ECL is disposed on the light-emitting layer EML. Although not separately shown in the figure, the electron control layer ECL can be commonly formed at a plurality of pixels PX (see Figure 5A ).

[0104] The second electrode CE is disposed on the electron control layer ECL. The second electrode CE is commonly disposed at a plurality of pixels PX.

[0105] The thin film encapsulation layer TFE is disposed on the second electrode CE. The thin film encapsulation layer TFE is commonly disposed at a plurality of pixels PX. According to this exemplary embodiment, the thin film encapsulation layer TFE directly covers the second electrode CE. According to an exemplary embodiment of the inventive concept, a covering layer for covering the second electrode CE may be further disposed between the thin film encapsulation layer TFE and the second electrode CE. At this time, the thin film encapsulation layer TFE can directly cover the covering layer.

[0106] Figures 7A to 7C is a cross-sectional view of the thin film encapsulation layers TFE1, TFE2, and TFE3 according to an exemplary embodiment of the inventive concept. Hereinafter, refer to Figures 7A to 7C to describe the thin film encapsulation layers TFE1, TFE2, and TFE3 according to an exemplary embodiment of the inventive concept.

[0107] As Figure 7AAs shown, the thin film encapsulation layer TFE1 may include n inorganic layers IOL1 to IOLn. The thin film encapsulation layer TFE1 may include n - 1 organic layers OL1 to OLn - 1, and the n - 1 organic layers OL1 to OLn - 1 and the n inorganic layers IOL1 to IOLn may be alternately disposed. The n - 1 organic layers OL1 to OLn - 1 may each have a thickness greater than the thickness of the n inorganic layers IOL1 to IOLn on average.

[0108] Each of the n inorganic layers IOL1 to IOLn may be a single layer including one material or multiple layers including respective different materials. Each of the n - 1 organic layers OL1 to OLn - 1 may be formed by depositing, printing, or coating an organic monomer. The organic monomer may include an acrylate monomer.

[0109] As Figure 7B and Figure 7C As shown, the inorganic layers included in each of the thin film encapsulation layers TFE2 and TFE3 may have the same or different inorganic materials and may have the same or different thicknesses. The organic layers included in each of the thin film encapsulation layers TFE2 and TFE3 may have the same or different organic materials and may have the same or different thicknesses.

[0110] As Figure 7B As shown, the thin film encapsulation layer TFE2 may include a first inorganic layer IOL1, a first organic layer OL1, a second inorganic layer IOL2, a second organic layer OL2, and a third inorganic layer IOL3 that are sequentially stacked.

[0111] The first inorganic layer IOL1 may have a two - layer structure. The first sub - layer S1 and the second sub - layer S2 may include different inorganic materials.

[0112] As Figure 7C As shown, the thin film encapsulation layer TFE3 may include a first inorganic layer IOL10, a first organic layer OL1, and a second inorganic layer IOL20 that are sequentially stacked. The first inorganic layer IOL10 may have a two - layer structure. The first sub - layer S10 and the second sub - layer S20 may include different inorganic materials. The second inorganic layer IOL20 may have a two - layer structure. The second inorganic layer IOL20 may include a first sub - layer S100 and a second sub - layer S200 deposited in different deposition environments. The first sub - layer S100 may be deposited under low - power conditions, while the second sub - layer S200 may be deposited under high - power conditions. The first sub - layer S100 and the second sub - layer S200 may include the same inorganic material.

[0113] Figure 8A is a cross - sectional view of a touch - sensing unit TS according to an exemplary embodiment of the inventive concept. Figures 8B to 8F is a plan view of a touch - sensing unit TS according to an exemplary embodiment of the inventive concept.

[0114] As shown Figure 8A Figure 8A

[0115]

[0115]

[0116]

[0116]

[0117]

[0117]

[0118] The first touch insulation layer TS-IL1 is sufficient to insulate the first conductive layer TS-CL1 from the second conductive layer TS-CL2, but its shape is not limited. The shape of the first touch insulation layer TS-IL1 may be changed according to the shapes of the first conductive pattern and the second conductive pattern. The first touch insulation layer TS-IL1 may completely cover the thin film encapsulation layer TFE or may include a plurality of insulation patterns. The plurality of insulation patterns are sufficient to overlap with the first connection part CP1 or the second connection part CP2, which will be described later.

[0119] Although a two-layer touch sensing unit is shown in this exemplary embodiment, the inventive concept is not limited thereto. A single-layer touch sensing unit includes a conductive layer and an insulation layer for covering the conductive layer. The conductive layer includes touch electrodes and touch signal lines connected to the touch electrodes. The single-layer touch sensing unit may obtain coordinate information by a self-capacitance method.

[0120] As Figure 8B shown, the touch sensing unit TS may include first touch electrodes TE1-1 to TE1-4, first touch signal lines SL1-1 to SL1-4 connected to the first touch electrodes TE1-1 to TE1-4, second touch electrodes TE2-1 to TE2-5, second touch signal lines SL2-1 to SL2-5 connected to the second touch electrodes TE2-1 to TE2-5, and a pad part PADa connected to the first touch signal lines SL1-1 to SL1-4 and the second touch signal lines SL2-1 to SL2-5. Although a touch sensing unit TS including four first touch electrodes TE1-1 to TE1-4 and five second touch electrodes TE2-1 to TE2-5 is shown in the exemplary embodiment Figure 8B shown, the inventive concept is not limited thereto.

[0121] Each of the first touch electrodes TE1-1 to TE1-4 may have a mesh shape defined with a plurality of touch openings. Each of the first touch electrodes TE1-1 to TE1-4 includes a plurality of first touch sensor parts SP1 and a plurality of first connection parts CP1. The first touch sensor parts SP1 are arranged along a first direction DR1. Each of the first connection parts CP1 connects two adjacent first touch sensor parts SP1 among the first touch sensor parts SP1. Although not separately shown in the drawing, the first touch signal lines SL1-1 to SL1-4 may also have a mesh shape.

[0122] The second touch electrodes TE2-1 to TE2-5 cross the first touch electrodes TE1-1 to TE1-4 and are insulated from the first touch electrodes TE1-1 to TE1-4. Each of the second touch electrodes TE2-1 to TE2-5 may have a mesh shape defined with a plurality of touch openings. Each of the second touch electrodes TE2-1 to TE2-5 includes a plurality of second touch sensor portions SP2 and a plurality of second connection portions CP2. The second touch sensor portions SP2 are arranged along a second direction DR2. Each of the second connection portions CP2 connects two adjacent second touch sensor portions SP2 among the second touch sensor portions SP2. The second touch signal lines SL2-1 to SL2-5 may also have a mesh shape.

[0123] The first touch electrodes TE1-1 to TE1-4 are electrostatically coupled to the second touch electrodes TE2-1 to TE2-5. When a touch detection signal is applied to the first touch electrodes TE1-1 to TE1-4, a capacitor is formed between the first touch sensor portions SP1 and the second touch sensor portions SP2.

[0124] Some of the plurality of first touch sensor portions SP1, the plurality of first connection portions CP1, the first touch signal lines SL1-1 to SL1-4, the plurality of second touch sensor portions SP2, the plurality of second connection portions CP2, and the second touch signal lines SL2-1 to SL2-5 may be formed by patterning the first conductive layer TS-CL1 shown in Figure 8A , and other portions may be formed by patterning the second conductive layer TS-CL2 shown in Figure 8A .

[0125] Although the touch sensing unit TS in which the plurality of first connection portions CP1 cross the plurality of second connection portions CP2 is shown in the exemplary embodiment, the inventive concept is not limited thereto. For example, in order not to overlap with the plurality of first connection portions CP1, each of the second connection portions CP2 may be modified to a V-shaped form. The V-shaped second connection portions CP2 may overlap with the first touch sensor portions SP1. Although the first touch sensor portions SP1 and the second touch sensor portions SP2 having a diamond shape are shown in the exemplary embodiment, the inventive concept is not limited thereto.

[0126] As Figure 8C shown, the first conductive pattern is provided on the thin film encapsulation layer TFE. The first conductive pattern may include a bridging pattern CP2. The bridging pattern CP2 may be directly provided on the thin film encapsulation layer TFE. The bridging pattern CP2 corresponds to the second connection portion CP2 shown in Figure 8B .

[0127] As Figure 8DAs shown in [Fig.], a first touch insulating layer TS-IL1 for covering the bridging pattern CP2 is disposed on the thin film encapsulation layer TFE. A contact hole CH for partially exposing the bridging pattern CP2 is defined in the first touch insulating layer TS-IL1. The contact hole CH may be formed by a photolithography process.

[0128] As Figure 8E shown in [Fig.], a second conductive pattern is disposed on the first touch insulating layer TS-IL1. The second conductive pattern may include a plurality of first touch sensor portions SP1, a plurality of first connection portions CP1, first touch signal lines SL1-1 to SL1-4, a plurality of second touch sensor portions SP2, and second touch signal lines SL2-1 to SL2-5. Although not separately shown in the figure, a second touch insulating layer TS-IL2 for covering the second conductive pattern is disposed on the first touch insulating layer TS-IL1.

[0129] According to another exemplary embodiment of the inventive concept, the first conductive pattern may include first touch electrodes TE1-1 to TE1-4 and first touch signal lines SL1-1 to SL1-4. The second conductive pattern may include second touch electrodes TE2-1 to TE2-5 and second touch signal lines SL2-1 to SL2-5. At this time, the contact hole CH is not defined in the first touch insulating layer TS-IL1.

[0130] In addition, according to an exemplary embodiment of the inventive concept, the first conductive pattern and the second conductive pattern may be interchanged. That is, the second conductive pattern may include the bridging pattern CP2.

[0131] In addition, according to an exemplary embodiment of the inventive concept, the first conductive pattern may further include dummy signal lines corresponding to the first touch signal lines SL1-1 to SL1-4 and the second touch signal lines SL2-1 to SL2-5. The corresponding dummy signal lines and touch signal lines may be connected to each other through the contact hole CH penetrating the first touch insulating layer TS-IL1. The dummy signal lines reduce the resistance of the touch signal lines.

[0132] Figure 8F is Figure 8E a partial enlarged view of the region BB of [Fig.]. As Figure 8F shown in [Fig.], the first touch sensor portion SP1 and the second touch sensor portion SP2 are superimposed on the non-light emitting region NPXA. A plurality of grid holes TS-OPR, TS-OPG, and TS-OPB are defined in the first touch sensor portion SP1 and the second touch sensor portion SP2. The plurality of grid holes TS-OPR, TS-OPG, and TS-OPB may have a one-to-one correspondence with the light emitting regions PXA-R, PXA-G, and PXA-B.

[0133] The light-emitting regions PXA-R, PXA-G, and PXA-B can be defined in the same manner as the light-emitting region PXA of Figure 6C An organic light-emitting diode OLED is disposed in each of the light-emitting regions PXA-R, PXA-G, and PXA-B. The organic light-emitting diode OLED can include a first organic light-emitting diode for generating first-color light, a second organic light-emitting diode for generating second-color light, and a third organic light-emitting diode for generating third-color light.

[0134] PXA-R, PXA-G, and PXA-B can have different areas according to the color emitted by the emission layer EML (see Figure 6C ) of the organic light-emitting diode OLED (see Figure 6C ). The sizes of the light-emitting regions PXA-R, PXA-G, and PXA-B can be determined according to the type of the organic light-emitting diode. The light-emitting regions PXA-R, PXA-G, and PXA-B can be divided into at least two groups. Figure 8F It shows that the light-emitting regions PXA-R, PXA-G, and PXA-B are divided into three groups.

[0135] A plurality of mesh holes TS-OPR, TS-OPG, and TS-OPB can be divided into several groups having different areas. They can be divided into at least two groups. Figure 8F Exemplarily shown are a first mesh hole TS-OPR having a first area, a second mesh hole TS-OPG having a second area different from the first area, and a third mesh hole TS-OPB having a third area different from the first area and the second area. The areas of the mesh holes TS-OPR, TS-OPG, and TS-OPB can be determined according to the type of the organic light-emitting diode OLED stacked therewith.

[0136] Each of the first touch sensor portion SP1 and the second touch sensor portion SP2 can include grid lines for defining a plurality of mesh holes TS-OPR, TS-OPG, and TS-OPB. The grid lines can include first grid lines extending along a fourth direction DR4 intersecting with a first direction DR1 and a second direction DR2, and second grid lines extending along a fifth direction DR5 intersecting with the fourth direction DR4. The line widths of the first grid lines and the second grid lines can be several micrometers.

[0137] Figure 8F Four grid line units M1, M2, M3, and M4 for defining one mesh hole TS-OPR are respectively shown. The grid line units form a part of the first grid lines and the second grid lines. The first grid line unit M1 and the second grid line unit M2 face each other in the fourth direction DR4, and the third grid line unit M3 and the fourth grid line unit M4 face each other in the fifth direction DR5.

[0138] Although it is shown above that the grid holes TS-OPR, TS-OPG, and TS-OPB correspond to the light-emitting regions PXA-R, PXA-G, and PXA-B on a one-to-one basis, the inventive concept is not limited thereto. One of the grid holes TS-OPR, TS-OPG, and TS-OPB may correspond to two or more of the light-emitting regions PXA-R, PXA-G, and PXA-B.

[0139] Although it is shown that the sizes of the light-emitting regions PXA-R, PXA-G, and PXA-B are different, the inventive concept is not limited thereto. The sizes of the light-emitting regions PXA-R, PXA-G, and PXA-B may be the same as each other and the sizes of the grid holes TS-OPR, TS-OPG, and TS-OPB may be the same as each other.

[0140] Figure 9A is a cross-sectional view of a display module DM according to an exemplary embodiment of the inventive concept. Figure 9B is a cross-sectional view of a display module according to a comparative example. Figure 9A and Figure 9B show Figure 5A the enlarged region AA. Figure 10 is a plan view of a display module DM according to an exemplary embodiment of the inventive concept.

[0141] Since the stacked structures of the circuit layer DP-CL, the light-emitting device layer DP-OLED, and the thin film encapsulation layer TFE provided in the display area DA are the same as the stacked structures described with reference to Figure 6B and Figure 6C the detailed description thereof is omitted. However, the hole control layer HCL and the electron control layer ECL are not shown. Since the stacked structure of the touch sensing unit TS provided in the display area DA is also the same as the structure described with reference to Figures 8A to 8F the detailed description thereof is omitted. The thin film encapsulation layer TFE including a first inorganic layer IOL1, an organic layer OL, and a second inorganic layer IOL2 is shown in the exemplary embodiment. Hereinafter, the non-display area NDA will be mainly described.

[0142] The scan driving circuit GDC of the circuit layer DP-CL is provided in the non-display area NDA. The scan driving circuit GDC includes at least one transistor GDC-T formed by the same process as the pixel transistor T6. The scan driving circuit GDC includes a signal line GDC-SL provided on the same layer as the input electrode of the pixel transistor T6. The initialization voltage line SL-Vint and the power supply electrode E-VSS are also provided on the same layer as the input electrode of the pixel transistor T6. Since the initialization voltage line SL-Vint, the power supply electrode E-VSS, and the input electrode of the pixel transistor T6 are also formed by the same process, they may include the same layer structure and the same material.

[0143] As shown Figure 10 in the figure, the power supply electrode E-VSS is disposed outside the scan driving circuit GDC. The power supply electrode E-VSS may extend along the contour of the base layer SUB. The non-display area may include a first non-display area NDA1 and a second non-display area NDA2 facing each other in a first direction DR1, and the display area DA is located between the first non-display area NDA1 and the second non-display area NDA2. The non-display area may include a third non-display area NDA3 and a fourth non-display area NDA4 facing each other in a second direction DR2, and the display area DA is located between the third non-display area NDA3 and the fourth non-display area NDA4. The power supply electrode E-VSS may be disposed in at least one of the first non-display area NDA1, the third non-display area NDA3, and the fourth non-display area NDA4. The power supply electrode E-VSS may be disposed in the first non-display area NDA1, the third non-display area NDA3, and the fourth non-display area NDA4.

[0144] Referring again to Figure 9A , the connection electrode E-CNT is disposed on the third insulating layer 30. The connection electrode E-CNT connects the power supply electrode E-VSS to the second electrode CE. The connection electrode E-CNT transmits a second power supply voltage from the power supply electrode E-VSS to the second electrode CE. Since the connection electrode E-CNT and the first electrode AE are formed by the same process, they may include the same layer structure and the same material. The connection electrode E-CNT and the first electrode AE may have the same thickness.

[0145] The connection electrode E-CNT may be disposed in at least one of the first non-display area NDA1, the third non-display area NDA3, and the fourth non-display area NDA4. The connection electrode E-CNT may be disposed in the first non-display area NDA1, the third non-display area NDA3, and the fourth non-display area NDA4.

[0146] A plurality of holes CNT-H are defined in the connection electrode E-CNT. The plurality of holes CNT-H discharge the gas generated during the process for forming the third insulating layer. A plurality of insulating patterns IP superposed on the plurality of holes CNT-H are disposed on the connection electrode E-CNT. The plurality of insulating patterns IP may correspond to the plurality of holes CNT-H one by one.

[0147] The plurality of insulating patterns IP may be single-layer and may be formed simultaneously with the pixel defining layer PDL. Since the plurality of insulating patterns IP and the pixel defining layer PDL are formed by the same process, they may have the same thickness and include the same material. The plurality of insulating patterns IP may have a thickness smaller than the thickness of the pixel defining layer PDL.

[0148] The second electrode CE is stacked on at least a part of the plurality of insulating patterns IP. The second electrode CE contacts the non-stacked portions of the plurality of insulating patterns IP that connect the electrode E-CNT.

[0149] As Figure 9A shown, the dams DM1 and DM2 can be provided in the non-display area NDA. According to this exemplary embodiment, it is shown that the first dam DM1 and the second dam DM2 are separated in the second direction DR2. Although not shown separately in the figure, the first dam DM1 and the second dam DM2 can be provided around the display area DA in a plane. The first dam DM1 and the second dam DM2 can be provided in at least one of the first non-display area NDA1, the third non-display area NDA3, and the fourth non-display area NDA4. The first dam DM1 and the second dam DM2 can be provided in the first non-display area NDA1, the third non-display area NDA3, and the fourth non-display area NDA4.

[0150] The first dam DM1 can be provided on the power supply electrode E-VSS. The first dam DM1 can be a single layer and can be formed simultaneously with the pixel defining layer PDL. Since the first dam DM1 and the pixel defining layer PDL are formed by the same process, they can have the same thickness and include the same material. The first dam DM1 can have a thickness smaller than the thickness of the pixel defining layer PDL.

[0151] The second dam DM2 can be provided outside the first dam DM1. For example, the distance between the second dam DM2 and the display area DA can be greater than the distance between the first dam DM1 and the display area DA.

[0152] The second dam DM2 can cover a part of the power supply electrode E-VSS. The second dam DM2 can have a multi-layer structure. The second dam DM2 can include an upper part and a lower part. The lower part can be formed simultaneously with the third insulating layer 30, and the upper part can be formed simultaneously with the pixel defining layer PDL.

[0153] The first inorganic layer IOL1 can cover the first dam DM1 and the second dam DM2. The edge of the first inorganic layer IOL1 can contact the second insulating layer 20. The organic layer OL can be stacked on the insulating pattern IP, and its edge is stacked on the first dam DM1 and the second dam DM2. It is desirable that the edge of the organic layer OL is not provided outside the second dam DM2. The second inorganic layer IOL2 can be stacked on the first dam DM1 and the second dam DM2. The edge of the second inorganic layer IOL2 can contact the first inorganic layer IOL1.

[0154] The first touch insulating layer TS-IL1 can be stacked on the first dam DM1 and the second dam DM2. The edge of the first touch insulating layer TS-IL1 can contact the second inorganic layer IOL2.

[0155] At least a part of the touch signal line SL2 disposed on the first touch insulation layer TS-IL1 overlaps with a plurality of insulation patterns IP. It is not necessary for the entire touch signal line SL2 to overlap with the plurality of insulation patterns IP; it is sufficient for a part of some of the touch signal lines SL2 to overlap with the insulation patterns IP.

[0156] As Figure 9A shown, the touch signal line SL2 of the touch sensing unit TS according to this exemplary embodiment is disposed on a relatively flat surface. According to Figure 9B the comparative example shown, some of the touch signal lines SL2 are disposed on an inclined surface. According to the comparative example, since the insulation pattern IP shown in Figure 9A is omitted, the thickness of the organic layer OL gradually decreases toward the edge of the base layer SUB. When comparing the lengths in the second direction DR2 of the regions where the thickness of the organic layer OL decreases according to this exemplary embodiment and the comparative example, it is known that the length of the comparative example is greater than that of this exemplary embodiment. This will be described in detail below with reference to Figure 11B and Figure 11C

[0157] When the distance from the second electrode CE changes according to the position of the touch signal line SL2 (see Figure 9B ), noise is generated. In particular, since the capacitance between the touch signal line SL2 and the second electrode CE increases at the outermost side, the noise will increase only at specific signal lines. In addition, the noise generated by the signal line GDC-SL of the scan driving circuit GDC will concentrate on the outermost touch signal line SL2. The noise will be amplified by the signal line in the signal line GDC-SL of the scan driving circuit GDC to which an AC signal is applied.

[0158] Figure 11A is an enlarged plan view of a part of a display module according to an exemplary embodiment of the inventive concept. Figure 11B is a cross-sectional view of a display module according to an exemplary embodiment of the inventive concept taken along the line I-I' of Figure 11A . Figure 11C is a cross-sectional view of a display module according to a comparative example of the inventive concept taken along the line I-I' of Figure 11A . Figure 11D is Figure 11B an enlarged cross-sectional view of a part of Figure 11A corresponding to the region CC of Figure 10 . Figure 11B and Figure 11C show the process of forming the thin film encapsulation layer.

[0159] As Figure 11A ​As shown, a plurality of insulating patterns IP may correspond one-to-one to a plurality of holes CNT-H. The plurality of holes CNT-H define a plurality of rows H-R1 to H-R8, and the plurality of rows H-R1 to H-R8 are arranged in a first direction DR1. The plurality of rows H-R1 to H-R8 may include holes arranged in a second direction DR2, and the plurality of rows H-R1 to H-R8 may include different numbers of holes. The shape of the plurality of holes CNT-H in the plane is not limited.

[0160] The holes in the first row H-R1 of the plurality of rows may be defined as first holes, and the holes in the second row H-R2 of the plurality of rows may be defined as second holes. The holes in the third row H-R3 of the plurality of rows may be defined as third holes.

[0161] The first row H-R1 and the third row H-R3 may include the same number of holes. The first hole and the third hole may be aligned. The second hole is disposed between the first hole and the third hole.

[0162] The plurality of insulating patterns IP may have the same arrangement as the plurality of holes CNT-H. The plurality of insulating patterns IP may control the flow rate of the liquid organic material.

[0163] As Figure 11B shown, a liquid organic material is disposed on the first inorganic layer IOL1 to form an organic layer OL (see Figure 9A ). The liquid organic material may be provided by an inkjet head. The liquid organic material provided to the edge portion of the display area DA (see Figure 9A ) flows toward the non-display area NDA. The plurality of insulating patterns IP may control the flow of the liquid organic material. The first dam DM1 and the second dam DM2 may prevent the liquid organic material from overflowing. Although not shown separately in the figure, in order to control the flow rate / velocity of the liquid organic material, a hydrophobic or hydrophilic plasma treatment may be performed on the first inorganic layer IOL1.

[0164] Figure 11B And Figure 11C respectively show two paths FP and FP-S. Figure 11B Shows a path according to this exemplary embodiment, Figure 11C shows a path according to a comparative example. Referring to the path FP according to this exemplary embodiment, the plurality of insulating patterns IP reduce the flow velocity of the liquid organic material. The liquid organic material slowly flows toward the edge of the base layer SUB. Additionally, since the plurality of insulating patterns IP compensate for the thickness, the organic layer OL (see Figure 9A ) has a relatively uniform thickness in the non-display area NDA (see Figure 9A ).

[0165] According to Figure 11C the path FP-S of the comparative example shown, since the flow velocity is not reduced, the organic layer OL (seeFigure 9B ) thins as it approaches the edge of the base layer SUB. Thus, the organic layer OL (see Figure 9B ) has an uneven thickness in the non-display area NDA (see Figure 9B ).

[0166] According to the path FP, when the flow rate / velocity of the liquid organic material is controlled, a uniform and flat organic layer can be formed in the non-display area NDA. As Figure 11A shown, when even-numbered insulating patterns IP are formed between odd-numbered insulating patterns IP, they can control all the paths FP1 corresponding to the odd-numbered rows (hereinafter referred to as the first paths) and the paths FP2 corresponding to the even-numbered rows (hereinafter referred to as the second paths).

[0167] The insulating pattern IP can control the flow rate / velocity of the liquid organic material and can also prevent damage to the connection electrode E-CNT. As Figure 11D shown, the connection electrode E-CNT can include a first transparent conductive layer TCO1, a metal layer ML located on the first transparent conductive layer TCO1, and a second transparent conductive layer TCO2 located on the metal layer ML. The first transparent conductive layer TCO1 and the second transparent conductive layer TCO2 can include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO). The metal layer ML can include highly conductive metals such as aluminum, copper, and silver.

[0168] The insulating pattern IP can cover the cross-section of the metal layer ML exposed by the plurality of holes CNT-H. Thus, corrosion of the metal layer ML is prevented.

[0169] Figures 12A to 12C is an enlarged plan view of a part of a display module according to an exemplary embodiment of the inventive concept. Figures 12A to 12C is a plan view corresponding to Figure 11A . Hereinafter, a detailed description of the same structure described with reference to Figures 11A to 11D is omitted.

[0170] As Figure 12A shown, the plurality of holes CNT-H can be arranged in an n×m matrix. Here, n and m are natural numbers greater than or equal to 2. A 4×6 matrix of holes CNT-H is exemplarily shown. It is not necessary for all the holes defined in the connection electrode E-CNT to be arranged in a matrix, but the holes defined in some regions can be arranged in a matrix. For example, the holes CNT-H defined in some other regions can be arranged as Figure 11A .

[0171] The insulating pattern may include a first insulating pattern IP1 superimposed on a plurality of holes CNT-H and a second insulating pattern IP2 not superimposed on the plurality of holes CNT-H. The first insulating pattern IP1 may be arranged in an n×m matrix corresponding one-to-one with the holes in the matrix.

[0172] The second insulating pattern IP2 is arranged to be separated from the first insulating pattern IP1. The second insulating pattern IP2 may define n - 1 rows between the n rows of the first insulating pattern IP1 and m - 1 columns between the m columns of the first insulating pattern IP1. The second insulating pattern IP2 may be arranged at the centers of four first insulating patterns in the first insulating pattern IP1 for defining a minimum rectangle.

[0173] The length of the second insulating pattern IP2 in the plane is greater than the interval between the second insulating pattern IP2 and the first insulating pattern IP1. For example, the length of the second insulating pattern IP2 may be twice as large as the interval between the second insulating pattern IP2 and the first insulating pattern IP1.

[0174] The first insulating pattern IP1 may control the same path FP10 as the first path FP1 shown in Figure 11A , and the second insulating pattern IP2 may control a path FP20 corresponding to the second path FP2 shown in Figure 11A .

[0175] As shown in Figure 12B , the insulating pattern may include a first insulating pattern IP10 and a second insulating pattern IP20 having different shapes.

[0176] The first insulating pattern IP10 may include a column portion IP-C and a row portion IP-R connected to the column portion IP-C. The column portion IP-C may be superimposed on the holes arranged in the column direction among the plurality of holes in the n×m matrix. The row portion IP-R may be superimposed on the holes arranged in the row direction, wherein the holes arranged in the column direction are respectively arranged in the row direction. The column portion IP-C may have a shape along the base layer SUB (see Figure 10) The shape of the edge extending in the first direction DR1. The second insulating pattern IP20 may have a shape corresponding to the hole CNT-H. The insulating pattern may further include a third insulating pattern IP30. The third insulating pattern IP30 may have the same shape as the first insulating pattern IP10. In this case, the second insulating pattern IP20 may be disposed between two first insulating patterns IP10 separated in the row direction. The third insulating pattern IP30 may have a shape different from the shape of the first insulating pattern IP10. For example, the third insulating pattern IP30 may include a column portion identical to the column portion of the first insulating pattern IP10 and a row portion different from the row portion of the first insulating pattern IP10. In this case, the second insulating pattern IP20 may be disposed between the first insulating pattern IP10 and the third insulating pattern IP30 separated in the row direction.

[0177] The row portion IP-R of the first insulating pattern IP10 and the second insulating pattern IP20 may control the same path FP100 as the first path FP1 shown in Figure 11A and the column portion IP-C of the first insulating pattern IP10 may control a path FP200 corresponding to the second path FP2 shown in Figure 11A .

[0178] Although Figure 12B shows a plurality of holes CNT-H arranged in an n×m matrix, the inventive concept is not limited thereto. For example, the holes CNT-H defined in some other regions may be arranged as shown in Figure 11A .

[0179] As shown in Figure 12C , the insulating pattern may include column insulating patterns IP-C1 and IP-C2 that overlap some of the holes arranged in the column direction among the holes CNT-H arranged in an n×m matrix. At least one of the plurality of column insulating patterns may be disposed between every k rows of the plurality of holes in the n×m matrix, where k is a natural number less than n. For example, as shown in Figure 12C , at least one of the plurality of column insulating patterns may be disposed between every 3 rows of the plurality of holes in the n×m matrix, that is, covering 3 holes arranged continuously in the column direction.

[0180] The first column insulating pattern IP-C1 and the second column insulating pattern IP-C2 are superimposed on holes in adjacent and different rows. When viewed from the second direction DR2, the first column insulating pattern IP-C1 and the second column insulating pattern IP-C2 are superimposed on each other. When the second column insulating pattern IP-C2 is moved toward the first column insulating pattern IP-C1 in the second direction DR2, the second column insulating pattern IP-C2 and the first column insulating pattern IP-C1 are partially superimposed. The first column insulating pattern IP-C1 and the second column insulating pattern IP-C2 are alternately arranged, and the end of the second column insulating pattern IP-C2 may be superimposed on the central region of the first column insulating pattern IP-C1. Here, the boundary of the central region may be defined within 10% of the length of the first column insulating pattern IP-C1 from the end of the first column insulating pattern IP-C1.

[0181] The first column insulating pattern IP-C1 and the second column insulating pattern IP-C2 complementarily control the same path FP1000 as the first path FP1 shown in Figure 11A and the path FP2000 corresponding to the second path FP2 shown in Figure 11A .

[0182] Figure 13A And Figure 13B are cross-sectional views of a display module according to an exemplary embodiment of the inventive concept. Figure 13A And Figure 13B show cross-sections corresponding to Figure 9A . Hereinafter, detailed descriptions of the same structures described with reference to Figures 9A to 12C are omitted.

[0183] As shown in Figure 13A , the holes CNT-H defined in the connection electrode E-CNT may be omitted. That is, the connection electrode E-CNT does not include the holes CNT-H. Whether there are holes CNT-H or not, the insulating pattern IP may be provided on the connection electrode E-CNT. The insulating pattern IP may have the arrangement and shape shown in Figure 11A and Figures 12A to 12C in a plane.

[0184] As shown in Figure 13B , the connection electrode E-CNT may be omitted. The insulating pattern IP may be directly provided on the third insulating layer 30. The insulating pattern IP may have the arrangement and shape shown in Figure 11A and Figures 12A to 12C in a plane.

[0185] As described above, the insulating pattern can control the flow of the monomer solution constituting the thin film encapsulation layer. By controlling the flow rate of the monomer solution flowing toward the edge region of the display panel, the flat organic layer can be formed up to the edge region. As a result, the inorganic layer provided on the organic layer can also provide a flat upper surface. The touch signal lines provided on the inorganic layer are separated from the second electrode by substantially the same distance. In addition, the separation distance can be greater than the reference distance. Signal interference between the second electrode and the touch signal lines can be prevented.

[0186] Although exemplary embodiments of the present invention have been described, it is understood that the present invention should not be limited to these exemplary embodiments, but various changes and modifications can be made by those of ordinary skill in the art within the spirit and scope claimed by the present invention.

Claims

1. A display device, the display device comprises: a base layer including a display area and a non-display area; a circuit layer including: at least one intermediate insulating layer; a power electrode stacked with the non-display area; and a driving circuit stacked with the non-display area and extending in a first direction, the circuit layer being disposed on the base layer; a light-emitting device layer including: an organic light-emitting diode including a first electrode, a light-emitting layer, and a second electrode disposed on the circuit layer; a pixel defining layer including an opening exposing the first electrode; a connection electrode connecting the second electrode and the power electrode, the connection electrode including a plurality of holes; and a plurality of insulating patterns stacked with the plurality of holes and including first insulating patterns spaced apart from each other; a thin film encapsulation layer including an organic layer stacked with the first insulating pattern and the organic light-emitting diode, the thin film encapsulation layer being disposed on the light-emitting device layer; and a touch sensing unit including at least one touch insulating layer, a plurality of touch electrodes, and a plurality of touch signal lines connected to the plurality of touch electrodes, the touch sensing unit being disposed on the thin film encapsulation layer, wherein the plurality of touch electrodes include a first touch electrode arranged in the first direction and a second touch electrode arranged in a second direction intersecting the first direction, the plurality of touch signal lines include a first touch signal line connected to the first touch electrode and a second touch signal line connected to the second touch electrode, at least a part of the first touch signal line extends in the first direction, and the part of the first touch signal line is stacked with the first insulating pattern, wherein the plurality of holes define a plurality of rows and the plurality of rows are arranged in the first direction, a first row of the plurality of rows includes a first hole arranged in the second direction intersecting the first direction, a second row of the plurality of rows includes second holes arranged in the second direction, the second holes being respectively disposed between the first holes, and a third row of the plurality of rows includes third holes arranged in the second direction, the third holes corresponding to the first holes.

2. A display device, the display device comprises: a base layer including a display area and a non-display area; a circuit layer including: at least one intermediate insulating layer; a power electrode stacked with the non-display area; and a driving circuit stacked with the non-display area and extending in a first direction, the circuit layer being disposed on the base layer; a light-emitting device layer including: an organic light-emitting diode including a first electrode, a light-emitting layer, and a second electrode disposed on the circuit layer; a pixel defining layer including an opening exposing the first electrode; a connection electrode connecting the second electrode and the power electrode, the connection electrode including a plurality of holes; and a plurality of insulating patterns stacked with the plurality of holes and including first insulating patterns spaced apart from each other; a thin film encapsulation layer including an organic layer stacked with the first insulating pattern and the organic light-emitting diode, the thin film encapsulation layer being disposed on the light-emitting device layer; and A touch sensing unit, including at least one touch insulating layer, a plurality of touch electrodes, and a plurality of touch signal lines connected to the plurality of touch electrodes, wherein the touch sensing unit is disposed on the film encapsulation layer. Wherein, the plurality of touch electrodes include first touch electrodes arranged in the first direction and second touch electrodes arranged in a second direction intersecting the first direction. The plurality of touch signal lines include first touch signal lines connected to the first touch electrodes and second touch signal lines connected to the second touch electrodes. At least a portion of the first touch signal line extends in the first direction, and The portion of the first touch signal line overlaps with the first insulating pattern. Wherein, the plurality of holes are arranged in an n×m matrix.

3. The display device according to claim 2, Wherein, The plurality of insulating patterns further include a second insulating pattern, Wherein, the first insulating pattern is arranged in an n×m matrix corresponding to the plurality of holes in the n×m matrix one by one, and The second insulating pattern is spaced apart from the first insulating pattern in the n×m matrix, and defines n - 1 rows between the n rows of the first insulating pattern and m - 1 columns between the m columns of the first insulating pattern.

4. The display device according to claim 2, Wherein, The plurality of insulating patterns further include a second insulating pattern, Wherein, the first insulating pattern is arranged in an n×m matrix corresponding to the plurality of holes in the n×m matrix one by one, and The second insulating pattern is disposed at the centers of four first insulating patterns for defining a minimum rectangle in the first insulating pattern.

5. The display device according to claim 2, Wherein, The first insulating pattern includes a column portion and a row portion connected to the column portion, and The column portion overlaps with the holes arranged in the column direction among the plurality of holes in the n×m matrix, and the row portion overlaps with the holes arranged in the row direction along the holes arranged in the column direction.

6. The display device according to claim 5, Wherein, The plurality of insulating patterns further include a second insulating pattern and a third insulating pattern, The second insulating pattern is disposed between the first insulating pattern and the third insulating pattern separated along the row direction.

7. The display device according to claim 2, Wherein, The plurality of insulating patterns include column insulating patterns, each of the column insulating patterns overlaps with the holes arranged in the column direction among the plurality of holes in the n×m matrix, and At least one of the column insulating patterns is disposed between every k rows of the plurality of holes in the n×m matrix, where k is a natural number less than n.

8. The display device according to claim 1 or 2, Wherein, The non-display area includes: A first non-display area and a second non-display area, facing each other in the first direction, and the display area is disposed between the first non-display area and the second non-display area; A third non-display region and a fourth non-display region face each other in the second direction intersecting the first direction, and the display region is disposed between the third non-display region and the fourth non-display region. Wherein, the power supply electrode is disposed at least in the first non-display region, the third non-display region, and the fourth non-display region, and the connection electrode is disposed at least in the third non-display region and the fourth non-display region.

9. The display device according to claim 8, the display device further comprises: a dam disposed at least in the first non-display region, the third non-display region, and the fourth non-display region, wherein the dam is stacked with the power supply electrode.

10. The display device according to claim 9, wherein, the at least one touch insulating layer is stacked with the dam.

11. The display device according to claim 9, wherein, the dam has the same thickness and the same material as the pixel defining layer or the at least one intermediate insulating layer.

12. The display device according to claim 1 or 2, wherein, the second electrode is stacked with at least a part of the plurality of insulating patterns.

13. The display device according to claim 1 or 2, wherein, each of the plurality of holes is covered by a corresponding insulating pattern among the plurality of insulating patterns.

14. The display device according to claim 1 or 2, wherein, the connection electrode includes a first transparent conductive layer, a metal layer disposed on the first transparent conductive layer, and a second transparent conductive layer disposed on the metal layer.

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