Asynchronous cache device, processor and computer equipment

By introducing redundant processing and consistency comparison mechanisms in the asynchronous cache device, the problem that control signals are not protected in the prior art is solved, and a higher security protection level and data transmission reliability are achieved.

CN115079994BActive Publication Date: 2025-08-22SHENZHEN JAGUAR MICROSYSTEMS CO LTD
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Patent Information

Application Number
CN202210794612.7
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2022-07-07
Publication Date
2025-08-22
Estimated Expiration
2042-07-07

AI Technical Summary

Technical Problem

The existing asynchronous FIFO only checks the data in terms of security protection, but does not protect the control signal, resulting in a low security protection level.

Method used

The first and second asynchronous cache modules are used to perform redundant processing on the data and control signals respectively, and the consistency comparison is performed through the comparison module to ensure the integrity of the data and control signals.

Benefits of technology

The security protection level of the asynchronous cache device is improved to prevent data loss and control signal abnormalities, and to ensure the reliability of data transmission.

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Abstract

The present application provides an asynchronous cache device, a processor, and a computer device. The asynchronous cache device includes: a first asynchronous cache module, a second asynchronous cache module, and a comparison module. The first asynchronous cache module is used to write the data provided by the source end according to the first control signal used by the source end, and to read out the stored data according to the second control signal used by the destination end; the second asynchronous cache module is used to write the data provided by the source end according to the first control signal, and to read out the stored data according to the third control signal output by the comparison module; the comparison module is used to compare the data read out by the first asynchronous cache module with the data read out by the second asynchronous cache module for consistency. The asynchronous cache device of the present application can provide security protection for the data writing and reading processes, thereby improving the security protection level of the asynchronous cache device.
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Description

Technical Field

[0001] The present application relates to the field of computer network technology, and in particular to an asynchronous cache device, a processor, and a computer device. Background Art

[0002] A FIFO (First In First Out) is a first-in, first-out data buffer. Asynchronous FIFOs use control signals from one clock domain to write data into the FIFO and control signals from another clock domain to read data out of the FIFO. Regarding security protection, currently asynchronous FIFOs only add checksums such as CRC (Cyclic Redundancy Check) or ECC (Error Correcting Code) to the data for error detection at the entry and exit of the asynchronous FIFO. This means that currently asynchronous FIFOs only provide security protection for data, not for control signals (such as ready and valid). Therefore, the current level of security protection for asynchronous FIFOs is low. Summary of the Invention

[0003] The present application can provide an asynchronous cache device, processor and computer equipment with a high security protection level.

[0004] In a first aspect, the present application provides an asynchronous cache device, comprising: a first asynchronous cache module, a second asynchronous cache module, and a comparison module, wherein:

[0005] The first asynchronous cache module is configured to write data provided by the source end according to a first control signal used by the source end, and read stored data according to a second control signal used by the destination end;

[0006] the second asynchronous cache module being configured to write the data provided by the source end according to the first control signal, and to read the stored data according to the third control signal output by the comparison module;

[0007] The comparison module is configured to perform consistency comparison between the data read out by the first asynchronous cache module and the data read out by the second asynchronous cache module.

[0008] In a second aspect, the present application provides a processor comprising the asynchronous cache device provided in the first aspect.

[0009] In a third aspect, the present application provides a computer device comprising the asynchronous cache apparatus provided in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1exemplarily shows a structural diagram of an asynchronous cache device provided in the first embodiment of the present application;

[0011] Figure 2 exemplarily shows a structural diagram of an asynchronous cache device provided in the second embodiment of the present application;

[0012] Figure 3 exemplarily shows a structural diagram of an asynchronous cache device provided in the third embodiment of the present application;

[0013] Figure 4 Schematic diagram of the structure of the computer device provided in the fourth embodiment of the present application is shown in FIG. DETAILED DESCRIPTION

[0014] In order to make the purpose, technical solutions and advantages of the exemplary embodiments of the present application clearer, the technical solutions in the exemplary embodiments of the present application will be clearly and completely described below in combination with the drawings in the exemplary embodiments of the present application. Obviously, the described exemplary embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0015] Based on the exemplary embodiments shown in this application, all other embodiments obtained by persons of ordinary skill in the art without inventive effort are within the scope of protection of this application. In addition, although the disclosure in this application is presented based on one or several exemplary examples, it should be understood that each aspect of the disclosure can independently constitute a complete technical solution.

[0016] As used in this application, the terms "include" and "have" and any variations thereof are intended to cover but not exclude inclusion. For example, a product or device comprising a list of components is not necessarily limited to those components expressly listed but may include other components not expressly listed or inherent to the product or device.

[0017] The term "module" as used in this application refers to any known or future developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software codes that can perform the functions associated with the module.

[0018] The present application provides an asynchronous cache device, which can write data provided by a source end according to a control signal based on a first clock signal used by the source end, and read out stored data according to a control signal based on a second clock signal used by a destination end.

[0019] The first clock signal and the second clock signal are in different clock domains. The source end may be a functional device that needs to store data in the asynchronous cache device. The destination end may be a functional device that needs to retrieve data stored in the asynchronous cache device. The functional device may refer to any known or future-developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software code that can perform the functions associated with the functional device.

[0020] The asynchronous cache device described in the present application may be an asynchronous FIFO (First In First Out) or other types of asynchronous cache devices.

[0021] See Figure 1 , Figure 1 Schematic diagram of the structure of the asynchronous cache device provided by the first embodiment of the present application is shown in FIG. The asynchronous cache device provided by the first embodiment of the present application may include: a first asynchronous cache module 10 , a second asynchronous cache module 30 , and a comparison module 50 .

[0022] The first asynchronous cache module 10 is connected to the source end 70, the destination end 90, and the comparison module 50. The second asynchronous cache module 30 is connected to the source end 70, the first asynchronous cache module 10, and the comparison module 50. The comparison module 50 is connected to the second asynchronous cache module 30, the first asynchronous cache module 10, and the destination end 90.

[0023] Specifically, the first asynchronous cache module 10 is used to write data provided by the source end 70 according to a first control signal used by the source end 70, and to read out stored data (ie, data stored in the first asynchronous cache module) according to a second control signal used by the destination end 90.

[0024] In the data writing scenario, in one case, when the first asynchronous cache module 10 is not full (i.e., not yet fully stored with data), it can write data provided by the source end 70 according to the first control signal used by the source end 70. In another case, when the first asynchronous cache module 10 is full (i.e., fully stored with data), it will output a full signal to prevent the first asynchronous cache module 10 from continuing to write data and causing data overflow.

[0025] In the data reading scenario, in one case, when the first asynchronous cache module 10 is in a non-empty state (i.e., still storing data), the stored data can be read according to the second control signal used by the destination end 90. In another case, when the first asynchronous cache module 10 is in an empty state (i.e., the data is empty), it will output an empty signal to prevent the first asynchronous cache module 10 from continuing to read data and causing invalid data to be read.

[0026] It should be noted that, in the present application, the first control signal may be a write control signal based on the first clock signal. The second control signal may be a read control signal based on the second clock signal. The full signal may be a low level or a high level. The empty signal may also be a low level or a high level. The full signal and the empty signal are opposite signals.

[0027] Specifically, the second asynchronous cache module 30 is used to write data provided by the source end 70 according to the first control signal, and read out stored data (ie, data stored in the second asynchronous cache module) according to the third control signal used by the comparison module 50 .

[0028] In the data writing scenario, in one case, when the second asynchronous cache module 30 is not full, it can write the data provided by the source end 70 according to the first control signal used by the source end 70. In another case, when the second asynchronous cache module 30 is full, it will output a full signal to prevent the write operation of the second asynchronous cache module 30 from continuing to write data and causing data overflow.

[0029] In the data reading scenario, in one case, when the second asynchronous cache module 30 is in a non-empty state, it can read the stored data based on the third control signal used by the comparison module 50. In another case, when the second asynchronous cache module 30 is in an empty state, it will output an empty signal to prevent the second asynchronous cache module 30 from continuing to read data, thereby preventing invalid data from being read. It should be noted that the third control signal can be a read control signal based on the second clock signal.

[0030] The asynchronous cache device provided in the first embodiment of the present application copies the data provided by the source end written by the first asynchronous cache module through the second asynchronous cache module, which is equivalent to not only performing redundant processing on the written data, but also performing redundant processing on the write control signal. The process of copying the stored data read out by the first asynchronous cache module through the second asynchronous cache module and the comparison module is equivalent to not only performing redundant processing on the read data, but also performing redundant processing on the read control signal, which can improve the security protection level of the asynchronous cache device.

[0031] Specifically, the comparison module 50 is used to compare the data read out by the first asynchronous cache module 10 with the data read out by the second asynchronous cache module 30 for consistency. When the data read out by the first asynchronous cache module 10 and the data read out by the second asynchronous cache module 30 are inconsistent, the comparison module 50 identifies a data cache exception and reports an interrupt to the CPU (Central Processing Unit) to start the data cache exception handler to execute the operation of rewriting the data of the source end 70 into the asynchronous cache device and reading it out to the destination end 90. When the data read out by the first asynchronous cache module 10 and the data read out by the second asynchronous cache module 30 are consistent, the comparison module 50 does not respond (that is, no additional operations other than comparison are performed). The asynchronous cache device provided in the first embodiment of the present application uses the comparison module to compare the data read out by the first asynchronous cache module and the data read out by the second asynchronous cache module for consistency, which can provide security protection for the data written from the source end and ensure that the data written from the source end will not be lost.

[0032] The asynchronous cache device provided in the first embodiment of the present application has a process of copying the data provided by the source end written by the first asynchronous cache module through the second asynchronous cache module, a process of copying the stored data read out by the first asynchronous cache module through the second asynchronous cache module and the comparison module, and a consistency comparison of the data read out by the first asynchronous cache module and the data read out by the second asynchronous cache module through the comparison module. Not only the written data and the read data are redundantly processed, but also the write control signal and the read control signal are redundantly processed, and the data read out by the first asynchronous cache module and the data read out by the second asynchronous cache module are compared for consistency. This can provide security protection for the data writing and reading processes, thereby improving the security protection level of the asynchronous cache device.

[0033] Further, see Figure 2 , Figure 2 The schematic diagram of the structure of the asynchronous cache device provided by the second embodiment of the present application is exemplified in FIG. The technical solution of the asynchronous cache device provided by the second embodiment of the present application includes all the contents of the asynchronous cache device provided by the first embodiment of the present application. The technical solution provided by the second embodiment of the present application further explains the comparison module in detail based on the technical solution provided by the first embodiment of the present application.

[0034] The comparison module 50 of the asynchronous cache device provided in the second embodiment of the present application includes a first synchronous cache module 501 and a first control module 503. The first synchronous cache module 501 is configured to write data read out by the first asynchronous cache module 10 according to a second control signal, and to read out stored data (i.e., data stored in the first synchronous cache module) according to a third control signal. The first control module 503 is configured to control the first synchronous cache module 501 and the second asynchronous cache module 30 to synchronously read out stored data (i.e., data stored in the first synchronous cache module and data stored in the second asynchronous cache module) using the third control signal.

[0035] Specifically, in order to prevent the first asynchronous cache module and the second asynchronous cache module from having a mismatch when reading data, which may lead to data loss. The asynchronous cache device provided by the second embodiment of the present application writes the data read out by the first asynchronous cache module by setting a first synchronous cache module in the comparison module, and then sets a first control module to control the first synchronous cache module and the second asynchronous cache module to synchronously read out the stored data. Since the first synchronous cache module writes data and reads data based on the same clock domain (i.e., the second clock signal), mismatches in writing data and reading data can be avoided. Moreover, the first control module is used to control the first synchronous cache module and the second asynchronous cache module to synchronously read out the stored data, so the first asynchronous cache module and the second asynchronous cache module can be prevented from having a mismatch when reading data, which may lead to data loss.

[0036] In a modified embodiment of the second embodiment, the comparison module 50 of the asynchronous cache device also includes a comparator 505. The comparator 505 is used to compare the data synchronously read out by the first synchronous cache module 501 and the data read out by the second asynchronous cache module 30 for consistency. When the data read out by the first synchronous cache module 501 and the data read out by the second asynchronous cache module 30 are inconsistent, the comparator 505 identifies a data cache exception and reports an interrupt to the CPU to start the data cache exception handler to execute the operation of rewriting the data of the source end 70 into the asynchronous cache device and reading it out to the destination end 90. When the data read out by the first synchronous cache module 501 and the data read out by the second asynchronous cache module 30 are consistent, the comparator 505 does not respond (that is, no additional operations other than comparison are performed). The asynchronous cache device provided in the modified embodiment of the second embodiment of the present application uses a comparator to compare the data read out by the first synchronous cache module and the data read out by the second asynchronous cache module for consistency, which can provide security protection for the data written from the source end and ensure that the data written from the source end will not be lost.

[0037] In a variation of the second embodiment, the first control module 503 of the comparison module 50 may include a first AND gate 5031, a first NOT gate 5033, and a second NOT gate 5035. The input of the first NOT gate 5033 is connected to the first synchronous cache module 501 to receive a null signal. The output of the first NOT gate 5033 is connected to one input of the first AND gate 5031. The input of the second NOT gate 5035 is connected to the second asynchronous cache module 30 to receive a null signal. The output of the second NOT gate 5035 is connected to the other input of the first AND gate 5031. The output of the first AND gate 5031 is connected to the first synchronous cache module 501 and the second asynchronous cache module 30, respectively, to provide a third control signal. Accordingly, the control logic of the first control module 503 is as follows: when both the first synchronous cache module 501 and the second asynchronous cache module 30 are in a non-null state, the first synchronous cache module 501 and the second asynchronous cache module 30 are controlled to synchronously read out the stored data. When the first synchronous cache module 501 or the second asynchronous cache module 30 is in an empty state, the first synchronous cache module 501 and the second asynchronous cache module 30 are prevented from reading out the stored data.

[0038] In a variation of the second embodiment, the first synchronous buffer module 501 may include a second AND gate 5011 and a first synchronous buffer 5013. One input of the second AND gate 5011 is connected to the destination terminal 90 to receive the second control signal. Another input of the second AND gate 5011 is connected to the first asynchronous buffer module 10 to receive a non-empty signal. The output of the second AND gate 5011 is connected to the write enable terminal (wen) of the first synchronous buffer 5013 to provide the second control signal. The data input terminal (data_in) of the first synchronous buffer 5013 is connected to the first asynchronous buffer module 10 to receive data read from the first asynchronous buffer module 10. The empty flag terminal (empty) of the first synchronous buffer 5013 is connected to the input terminal of the first NOT gate 5033 to provide an empty signal. The read enable terminal (ren) of the first synchronous buffer 5013 is connected to the output terminal of the first AND gate 5031 to receive the third control signal. The data output terminal (data_out) of the first synchronization buffer 5013 is connected to an input terminal of the comparator 505 to provide read data (i.e., data read by the first synchronization buffer). The data written to and read from the first synchronization buffer are based on the same clock domain (i.e., the second clock signal), which can prevent synchronization errors between the written and read data.

[0039] In a modified embodiment of the second embodiment of the present application, the full mark end (full) of the first synchronization buffer 5013 is used to report an interrupt (des_err) to the CPU to start the data cache exception handler to execute the operation of rewriting the data of the source end 70 into the asynchronous cache device and reading it out to the destination end 90 in order to prevent data loss when the first synchronization buffer 5013 is in a full state.

[0040] In the modified embodiment of the second embodiment, see Figure 2 The first asynchronous cache module 10 may include a first asynchronous cache 101, a fifth NOT gate 103, and a sixth NOT gate 105. The full flag terminal (full) of the first asynchronous cache 101 is connected to the source terminal 70 and the second asynchronous cache module 30 via the fifth NOT gate 103 connected in series to provide a non-full signal to the source terminal 70 and the second asynchronous cache module 30. The write enable terminal (wen) of the first asynchronous cache 101 is connected to the source terminal 70 to receive a first control signal. The data input terminal (data_in) of the first asynchronous cache 101 is connected to the source terminal 70 to receive data provided by the source terminal 70. The read enable terminal (ren) of the first asynchronous cache 101 is connected to the destination terminal 90 to receive a second control signal.

[0041] The empty flag terminal (empty) of the first asynchronous buffer 101 is connected to the destination terminal 90 and the first synchronous buffer module 501 of the comparison module 50 via a sixth serially connected NOT gate 105, thereby providing a non-empty signal to the destination terminal 90 and the first synchronous buffer module 501 of the comparison module 50. The data output terminal (data_out) of the first asynchronous buffer 101 is connected to the destination terminal 90 and the first synchronous buffer module 501 of the comparison module 50, thereby providing read data to the destination terminal 90 and the first synchronous buffer module 501 of the comparison module 50.

[0042] The asynchronous cache device provided in the second embodiment of the present application has a process of copying the data provided by the source end written by the first asynchronous cache module through the second asynchronous cache module, a process of copying the stored data read out by the first asynchronous cache module through the second asynchronous cache module and the first synchronous cache module of the comparison module, and a consistency comparison of the data read out by the first asynchronous cache module and the data read out by the second asynchronous cache module through the first control module and the comparator of the comparison module. Not only the written data and the read data are redundantly processed, but also the write control signal and the read control signal are redundantly processed, and the data read out by the first asynchronous cache module and the data read out by the second asynchronous cache module are compared for consistency, which can provide security protection for the data writing and reading processes and improve the security protection level of the asynchronous cache device.

[0043] Further, see Figure 3 , Figure 3The schematic diagram of the structure of the asynchronous cache device provided in the third embodiment of the present application is exemplarily shown in FIG. The technical solution of the asynchronous cache device provided in the third embodiment of the present application includes all the contents of the asynchronous cache device provided in the second embodiment of the present application. The technical solution provided in the third embodiment of the present application is based on the technical solution provided in the second embodiment of the present application, and further details the second asynchronous cache module.

[0044] The second asynchronous cache module 30 of the asynchronous cache device provided in the third embodiment of the present application may include a second asynchronous cache 305, a second control module 303, and a second synchronous cache module 301. The second synchronous cache module 301 is configured to write data provided by the source end 70 in accordance with a first control signal, and to read stored data (i.e., data stored in the second synchronous cache module) in accordance with a fourth control signal output by the second control module 303. The second control module 303 is configured to control the second synchronous cache module 301 to read stored data via the fourth control signal, and to control the second asynchronous cache 305 to write data read by the second synchronous cache module 301.

[0045] In the asynchronous cache device provided in the third embodiment of the present application, data provided by the source end 70 can flow to the comparator 505 through two paths: the first path flows through the first asynchronous cache module 10 and the first synchronous cache module 501 to the comparator 505, and the second path flows through the second synchronous cache module 301 and the second asynchronous cache 305 to the comparator 505. Because the asynchronous cache device provided in the third embodiment of the present application includes a second synchronous cache module within the second asynchronous cache module, the first path and the second path can have the same depth, further ensuring that data in the two paths can reach the comparator synchronously.

[0046] In a third embodiment of the present application, the second synchronous buffer module 301 may include a third AND gate 3011 and a second synchronous buffer 3013. One input of the third AND gate 3011 is connected to the fifth NOT gate 103 of the first asynchronous buffer module 10 to receive a not-full signal. Another input of the third AND gate 3011 is connected to the source terminal 70 to receive a first control signal. An output of the third AND gate 3011 is connected to a write enable terminal (wen) of the second synchronous buffer 3013 to provide the first control signal to the second synchronous buffer 3013. A data input terminal (data_in) of the second synchronous buffer 3013 is connected to the source terminal 70 to receive data provided by the source terminal 70. A read enable terminal (ren) of the second synchronous buffer 3013 is connected to the second control module 303 to receive a fourth control signal. An empty flag terminal (empty) of the second synchronous buffer 3013 is connected to the second control module 303 to provide an empty signal. The data output terminal (data_out) of the second synchronous buffer 3013 is connected to the data input terminal (data_in) of the second asynchronous buffer 305 to provide read data.

[0047] In a modified embodiment of the third embodiment of the present application, the full mark end (full) of the second synchronization buffer 3013 is used to report an interrupt (src_err) to the CPU to start the data cache exception handler to execute the operation of rewriting the data of the source end 70 into the asynchronous cache device and reading it out to the destination end 90 in order to prevent data loss when the second synchronization buffer 3013 is in a full state.

[0048] In a third embodiment of the present application, the second control module 303 may include a fourth AND gate 3031, a third NOT gate 3033, and a fourth NOT gate 3035. The input of the third NOT gate 3033 is connected to the empty flag terminal (empty) of the second synchronous buffer 3013 to receive an empty signal. The output of the third NOT gate 3033 is connected to one input of the fourth AND gate 3031. The input of the fourth NOT gate 3035 is connected to the full flag terminal (full) of the second asynchronous buffer 305 to receive a full signal. The output of the fourth NOT gate 3035 is connected to the other input of the fourth AND gate 3031. The output of the fourth AND gate 3031 is connected to the read enable terminal (ren) of the second synchronous buffer 3013 and the write enable terminal (wen) of the second asynchronous buffer 305, respectively, to provide a fourth control signal. For the second synchronous buffer 3013, the fourth control signal is a read control signal based on the first clock signal. For the second asynchronous buffer 305, the fourth control signal is a write control signal based on the first clock signal. Accordingly, the control logic of the second control module 303 is as follows: when the second synchronous buffer 3013 is not empty and the second asynchronous buffer 305 is not full, the second synchronous buffer 3013 is controlled to read the stored data and the second asynchronous buffer 305 is controlled to write the data read from the second synchronous buffer 3013. When the second synchronous buffer 3013 is empty or the second asynchronous buffer 305 is full, the second synchronous buffer 3013 is prevented from reading the stored data and the second asynchronous buffer 305 is prevented from writing the data read from the second synchronous buffer 3013.

[0049] The asynchronous cache device provided in the third embodiment of the present application has a process of copying the data provided by the source end written by the first asynchronous cache module through the second synchronous cache module of the second asynchronous cache module and the second asynchronous cache, a process of copying the stored data read out by the first asynchronous cache module through the second asynchronous cache and the first synchronous cache module of the comparison module, and a consistency comparison of the data read out by the first asynchronous cache module and the second asynchronous cache module through the first control module and the comparator of the comparison module. Not only the written data and the read data are redundantly processed, but also the write control signal and the read control signal are redundantly processed, and the data read out by the first asynchronous cache module and the second asynchronous cache module are compared for consistency, which can provide security protection for the data writing and reading processes and improve the security protection level of the asynchronous cache device.

[0050] Accordingly, the fourth embodiment of the present application further provides a computer device, the internal structure diagram of the computer device can be as follows: Figure 4As shown. The computer device includes a processor, a memory and a network interface connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal via a network connection. The computer device may include an asynchronous cache device as described in the first embodiment, the second embodiment or the third embodiment of the present application.

[0051] Those skilled in the art will understand that Figure 4 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0052] Accordingly, the present application also provides a processor. The processor may be a DPU (Data Processing Unit), a GPU (Graphics Processing Unit), a CPU (Central Processing Unit), or other types of processors, such as a processor for an in-vehicle system. The processor may include an asynchronous cache device as described in the first, second, or third embodiments of the present application. The processor may also be installed in the computer device described in the fourth embodiment of the present application.

[0053] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0054] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. An asynchronous cache device, characterized in that: include: A first asynchronous cache module, a second asynchronous cache module, and a comparison module, wherein: The first asynchronous cache module is configured to write data provided by the source end according to a first control signal used by the source end, and read stored data according to a second control signal used by the destination end; wherein the first control signal is a write control signal based on the first clock signal, and the second control signal is a read control signal based on the second clock signal; The second asynchronous cache module is configured to write the data provided by the source end according to the first control signal, and read the stored data according to a third control signal output by the comparison module; wherein the third control signal is a read control signal based on the second clock signal; The comparison module is configured to perform consistency comparison between the data read out by the first asynchronous cache module and the data read out by the second asynchronous cache module.

2. The asynchronous cache device according to claim 1, wherein: The comparison module includes a first synchronization cache module, a first control module, and a comparator, wherein: the first synchronous cache module being configured to write the data read out by the first asynchronous cache module according to the second control signal, and to read out the stored data according to the third control signal; The first control module is configured to control the first synchronous cache module and the second asynchronous cache module to synchronously read out stored data through the third control signal; The comparator is used to perform consistency comparison on the data synchronously read out by the first synchronous cache module and the second asynchronous cache module.

3. The asynchronous cache device according to claim 2, wherein: The first control module includes a first AND gate, a first NOT gate, and a second NOT gate, wherein: The input end of the first NOT gate is connected to the first synchronization buffer module to receive the empty signal, and the output end of the first NOT gate is connected to an input end of the first AND gate. The input end of the second NOT gate is connected to the second asynchronous buffer module to receive the empty signal, and the output end of the second NOT gate is connected to the other input end of the first AND gate. The output end of the first AND gate is respectively connected to the first synchronous cache module and the second asynchronous cache module to provide the third control signal.

4. The asynchronous cache device according to claim 3, wherein: The first synchronization buffer module includes a second AND gate and a first synchronization buffer. One input terminal of the second AND gate is connected to the destination terminal to receive the second control signal, another input terminal of the second AND gate is connected to the first asynchronous buffer module to receive a non-empty signal, and an output terminal of the second AND gate is connected to the write enable terminal of the first synchronous buffer to provide the second control signal. The data input end of the first synchronous buffer is connected to the first asynchronous buffer module to receive the data read out by the first asynchronous buffer module, the empty mark end of the first synchronous buffer is connected to the input end of the first NOT gate to provide the empty signal, the read enable end of the first synchronous buffer is connected to the output end of the first AND gate to receive the third control signal, and the data output end of the first synchronous buffer is connected to an input end of the comparator to provide the read data.

5. The asynchronous cache device according to any one of claims 2 to 4, characterized in that: The second asynchronous cache module includes a second asynchronous cache, a second control module, and a second synchronous cache module, wherein: The second synchronization cache module is configured to write the data provided by the source end according to the first control signal, and read the stored data according to the fourth control signal output by the second control module. The second control module is configured to control the second synchronous cache module to read out stored data and control the second asynchronous cache to write the data read out by the second synchronous cache module through the fourth control signal.

6. The asynchronous cache device according to claim 5, characterized in that: The second synchronization buffer module includes a third AND gate and a second synchronization buffer, wherein: One input terminal of the third AND gate is connected to the first asynchronous buffer module to receive a non-full signal, another input terminal of the third AND gate is connected to the source terminal to receive the first control signal, and an output terminal of the third AND gate is connected to the write enable terminal of the second synchronous buffer to provide the first control signal. The data input end of the second synchronous buffer is connected to the source end to receive the data provided by the source end, the read enable end of the second synchronous buffer is connected to the second control module to receive the fourth control signal, the empty mark end of the second synchronous buffer is connected to the second control module to provide an empty signal, and the data output end of the second synchronous buffer is connected to the data input end of the second asynchronous buffer to provide the read data.

7. The asynchronous cache device according to claim 6, characterized in that: The second control module includes a fourth AND gate, a third NOT gate, and a fourth NOT gate, wherein: The input end of the third NOT gate is connected to the empty mark end of the first synchronization buffer to receive the empty signal, and the output end of the third NOT gate is connected to an input end of the fourth AND gate. The input end of the fourth NOT gate is connected to the full mark end of the second asynchronous buffer to receive a full signal, and the output end of the fourth NOT gate is connected to the other input end of the fourth AND gate. The output terminal of the fourth AND gate is respectively connected to the read enable terminal of the second synchronous buffer and the write enable terminal of the second asynchronous buffer to provide the fourth control signal.

8. The asynchronous cache device according to claim 7, wherein: The empty mark end of the second asynchronous buffer is connected to the comparison module to provide an empty signal, the read enable end of the second asynchronous buffer is connected to the comparison module to receive the third control signal, and the data output end of the second asynchronous buffer is connected to the comparison module to provide read data.

9. The asynchronous cache device according to claim 1, wherein: The first asynchronous cache module includes a first asynchronous cache, a fifth NOT gate, and a sixth NOT gate, wherein: The full mark terminal of the first asynchronous buffer is connected to the source terminal and the second asynchronous buffer module via the fifth NOT gate connected in series to provide a not full signal. The write enable terminal of the first asynchronous buffer is connected to the source terminal to receive the first control signal. The data input terminal of the first asynchronous buffer is connected to the source terminal to receive data provided by the source terminal. The read enable terminal of the first asynchronous buffer is connected to the destination terminal to receive the second control signal, the empty mark terminal of the first asynchronous buffer is connected to the destination terminal and the comparison module respectively through the sixth NOT gate connected in series to provide a non-empty signal, and the data output terminal of the first asynchronous buffer is connected to the destination terminal and the comparison module to provide read data.

10. A processor, characterized in that: It comprises the asynchronous cache device according to any one of claims 1 to 9.

11. A computer device, characterized in that: It comprises the asynchronous cache device according to any one of claims 1 to 9.

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