Metal oxide thin film transistor and manufacturing method thereof, array substrate

Abstract

The present application provides a metal oxide thin film transistor, comprising: a substrate; a first insulating buffer layer on the substrate; a metal oxide layer on the first insulating buffer layer, the metal oxide layer having a first conductor region, a second conductor region and a semiconductor region; a gate insulating layer on the semiconductor region; a source, a drain and a gate formed in the same layer and spaced from each other, the gate being arranged on the gate insulating layer, the source and the drain covering the first conductor region and being in contact with the first conductor region, and the second conductor region being exposed from between the source, the drain and the gate insulating layer. The semiconductor region of the metal oxide thin film transistor of the present application is not damaged by the process, so that the performance of the metal oxide thin film transistor is excellent.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a metal oxide thin-film transistor and its fabrication method. Background Technology

[0002] In recent years, metal oxide thin film transistors (AOS TFTs) have attracted widespread attention in the industry due to their excellent electrical and optical properties. However, thin film transistors using metal oxide semiconductors as the active layer material typically employ vapor deposition methods such as sputtering, atomic layer deposition (ALD), pulsed laser deposition (PLD), and metal-organic chemical vapor deposition (MOCVD), or liquid phase deposition methods such as solution coating and inkjet printing. The metal oxide semiconductor films deposited by any of these methods contain numerous microstructural defects, such as micropores, vacancies, dislocations, and various crystallographic defects like bond length / bond angle strain. Therefore, the resulting films are usually amorphous.

[0003] Common metal-oxide thin-film transistors, such as amorphous indium gallium zinc thin-film transistors (a-IGZO TFTs), are characterized by their high electron mobility (>10 cm⁻¹). 2 With its advantages such as low power consumption, simple process, fast response speed, good large-area uniformity, and high transmittance in the visible light range, it is considered a core component of the driving circuit of Active Matrix Organic Light Emitting Diode (AMOLED) and Active Matrix Liquid Crystal Display (AMLCD). It is also considered the most competitive backplane driving technology as displays develop towards larger size, flexibility, and portability.

[0004] Existing metal-oxide-semiconductor (MOS) thin-film transistors (TFTs) are mainly classified into coplanar, etch-stop layer (ESL), and back channel etch (BCE) types. However, due to the aforementioned defects within amorphous MOS semiconductor films, these crystallographic defects provide efficient channels for the infiltration and diffusion of foreign molecules / atoms (such as H2, H2O, and etching chemicals during fabrication), thereby damaging the semiconductor layer. This leads to widespread reliability issues in MOS TFTs, necessitating stable process conditions to ensure TFT performance. Therefore, improving the fabrication process and structure of MOS TFTs is crucial. Summary of the Invention

[0005] The purpose of this invention is to provide a metal oxide thin film transistor and its fabrication method, in which the semiconductor region is not damaged by the fabrication process, resulting in excellent performance of the metal oxide thin film transistor.

[0006] This invention provides a metal oxide thin-film transistor, comprising:

[0007] Substrate;

[0008] The first insulating buffer layer is located on the substrate;

[0009] A metal oxide layer located on the first insulating buffer layer, the metal oxide layer having a first conductor region, a second conductor region and a semiconductor region;

[0010] The gate insulating layer located on the semiconductor region; and

[0011] A source, drain, and gate electrode are formed in the same layer and spaced apart from each other. The gate electrode is disposed on the gate insulating layer. The source and drain electrodes cover the first conductor region and are in contact with the first conductor region. The second conductor region is exposed between the source, drain, and gate insulating layer.

[0012] Furthermore, it also includes a shielding layer and a scan line formed in the same layer and spaced apart from each other, the shielding layer and the scan line being disposed between the substrate and the first insulating buffer layer.

[0013] Furthermore, the first insulating buffer layer and the gate insulating layer are provided with a first through hole exposing the scan line, and the gate is filled into the first through hole and in contact with the scan line.

[0014] Furthermore, it also includes a data line connected to the source, which is formed in the same layer as the source, the drain, and the gate.

[0015] The present invention also provides a method for fabricating a metal oxide thin-film transistor, comprising:

[0016] A first insulating buffer layer is formed on the substrate;

[0017] An oxide semiconductor thin film is formed on the first insulating buffer layer, and the oxide semiconductor thin film is patterned to form a metal oxide layer;

[0018] A second insulating buffer layer is formed over the metal oxide layer in the first insulating buffer layer, and a first photoresist pattern and a second photoresist pattern are formed on the second insulating buffer layer, with the thickness of the first photoresist pattern being greater than the thickness of the second photoresist pattern.

[0019] The second insulating buffer layer, the first photoresist pattern, and the second photoresist pattern are etched, while the first photoresist pattern, the exposed second insulating buffer layer, and the portion of the second insulating buffer layer located below the first photoresist pattern are removed, so that the second insulating buffer layer located below the first photoresist pattern and the second photoresist pattern forms a first insulating pattern and a second insulating pattern with different thicknesses after etching, wherein the thickness of the second insulating pattern is less than the thickness of the first insulating pattern;

[0020] Remove the first photoresist pattern located above the first insulating pattern;

[0021] Using the first insulating pattern and the second insulating pattern as a mask, the metal oxide layer is ion-doped, so that the area of ​​the metal oxide layer not covered by the first insulating pattern and the second insulating pattern is transformed from a semiconductor into a conductor and formed into a first conductor region.

[0022] A second metal layer is formed and etched and patterned to form a source, drain and gate that are spaced apart from each other. The source and drain are both in contact with the first conductor region and the gate is disposed above the first insulating pattern.

[0023] Using the source, drain, and gate as a mask, the second insulating pattern is etched away to expose a portion of the metal oxide layer below the second insulating pattern, while retaining the first insulating pattern to form the gate insulating layer; and

[0024] The exposed portion of the metal oxide layer is ion-doped to transform it into a conductor, forming a second conductor region. The portion of the unconducted metal oxide layer located below the first insulating pattern forms a semiconductor region.

[0025] Furthermore, the method for forming the first photoresist pattern and the second photoresist pattern includes:

[0026] A photoresist layer is coated on the second insulating buffer layer. The photoresist layer is exposed and developed using a halftone mask to leave the first photoresist pattern and the second photoresist pattern on the photoresist layer. The halftone mask includes an opaque area, a semi-transparent area and a fully transparent area. The opaque area, the semi-transparent area and the fully transparent area correspond to the first photoresist pattern, the second photoresist pattern and the area where no photoresist needs to be left, respectively.

[0027] Furthermore, before forming the first insulating buffer layer on the substrate, a shielding layer and scan lines are formed on the substrate at intervals, the position of the shielding layer corresponding to the position of the metal oxide layer.

[0028] Furthermore, after removing the first photoresist pattern located above the first insulating pattern, the method further includes patterning the first insulating pattern and the first insulating buffer layer to form a first via to expose the scan line. When forming the gate, the gate is filled into the first via and makes contact with the scan line.

[0029] Furthermore, data lines are formed during the etching patterning of the second metal layer, and these data lines are connected to the source electrode.

[0030] The present invention also provides an array substrate comprising the above-described metal oxide thin-film transistor, the array substrate further comprising:

[0031] A first passivation layer covering the source, the drain, and the gate;

[0032] A planar layer covering the first passivation layer;

[0033] The common electrode is located on this planar layer;

[0034] A second passivation layer covers the common electrode;

[0035] The pixel electrode is located on the second passivation layer. A contact hole is formed in the second passivation layer, the planarization layer and the first passivation layer at a position corresponding to the drain electrode. The pixel electrode is filled into the contact hole and makes contact with the drain electrode.

[0036] The metal oxide thin-film transistor, its fabrication method, and array substrate provided by this invention have the following beneficial effects:

[0037] 1. The semiconductor region in the metal oxide layer used to form the active layer is protected by the first and second insulating buffer layers throughout the fabrication process. The semiconductor region is not damaged by the process, resulting in excellent performance of the metal oxide thin film transistor.

[0038] 2. The metal oxide layer is divided into two conductive sections, which allows for flexible adjustment of the characteristics of the metal oxide thin film transistor, making it more suitable for different applications.

[0039] 3. By cleverly using halftone masks to make the metal oxide structure conductive, a top-gate metal oxide thin-film transistor is formed, and the gate, source and drain are fabricated on the same layer, resulting in higher efficiency.

[0040] 4. The process of this invention is simple, can be integrated with existing processes, is highly implementable, and is easy to achieve mass production.

[0041] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the other objects, features and advantages of the above-mentioned metal oxide thin film transistor and its fabrication method and array substrate of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0042] Figures 1a to 1j This is a cross-sectional structural diagram illustrating the fabrication process of a metal oxide thin-film transistor according to a preferred embodiment of the present invention.

[0043] Figure 2 This is a partial structural planar schematic diagram of the array substrate according to a preferred embodiment of the present invention.

[0044] Figure 3 for Figure 2 A schematic diagram of the cross-section along line AA.

[0045] Figure 4 for Figure 2 A cross-sectional diagram along line BB. Detailed Implementation

[0046] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and preferred embodiments, provides a detailed explanation of the specific implementation methods, structures, features, and effects of the metal oxide thin-film transistor and its fabrication method, as well as the array substrate, proposed according to the present invention:

[0047] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of preferred embodiments with reference to the accompanying drawings. Through the description of the specific embodiments, a more in-depth and specific understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the present invention.

[0048] Figures 1a to 1j This is a cross-sectional structural diagram illustrating the fabrication process of a metal-oxide-slim thin-film transistor according to a preferred embodiment of the present invention. The fabrication method of the metal-oxide-slim thin-film transistor provided in this embodiment includes:

[0049] like Figure 1a As shown, a shielding layer 21 is formed on the substrate 10.

[0050] Specifically, a substrate 10 is provided, which may be, for example, a transparent hard or soft substrate, and the material is not limited thereto. A first metal layer 20 is formed on the substrate 10, and the first metal layer 20 is patterned by photolithography to form a masking layer 21. The photolithography process mainly includes film deposition, photoresist coating, exposure, development, etching, and photoresist removal, which are well known to those skilled in the art and will not be described in detail here. The masking layer 21 may include one or more of molybdenum, aluminum, copper, and titanium, or may include an alloy composed of at least two of the above metals.

[0051] Furthermore, during the etching of the first metal layer 20 to form the shielding layer 21, scan lines 22 are also formed simultaneously. (See scan lines 22 for details.) Figure 2 ) and the shielding layer 21 are spaced apart.

[0052] like Figure 1b As shown, a first insulating buffer layer 30 is formed on the substrate 10, and the first insulating buffer layer 30 covers the shielding layer 21.

[0053] The material of the first insulating buffer layer 30 can be silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ), aluminum oxide (AlO) x ) etc., or silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ), aluminum oxide (AlO) x ) and silicon nitride (SiN) x Multilayer composite materials formed by multiple combinations of elements.

[0054] like Figure 1c As shown, an oxide semiconductor thin film is formed on the first insulating buffer layer 30, and the oxide semiconductor thin film is patterned by photolithography to form a metal oxide layer 40.

[0055] A metal oxide layer 40 is formed above the shielding layer 21, with the shielding layer 21 positioned corresponding to the metal oxide layer 40. The projection of the metal oxide layer 40 onto the substrate 10 falls within the projection range of the shielding layer 21 onto the substrate 10. The shielding layer 21 can effectively reduce the negative threshold voltage bias of the metal oxide thin-film transistor caused by light irradiation, thereby effectively improving the stability of the device.

[0056] The metal oxide layer 40 is an oxide containing at least one or more elements selected from zinc, indium, gallium, tin, aluminum, silicon, scandium, titanium, vanadium, yttrium, zirconium, niobium, molybdenum, hafnium, tantalum, tungsten, and lanthanides. Typical oxide semiconductor materials include indium zinc oxide (IZO), lanthanide rare earth doped indium zinc oxide (Ln-IZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), and indium gallium zinc tin oxide (IGZTO). Preferably, the material of the metal oxide layer 40 is amorphous indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), or lanthanide rare earth doped indium zinc oxide (Ln-IZO).

[0057] like Figure 1d As shown, a second insulating buffer layer 50 covering the metal oxide layer 40 is formed in the first insulating buffer layer 30, and a first photoresist pattern 210 and a second photoresist pattern 220 are formed on the second insulating buffer layer 50. The first photoresist pattern 210 and the second photoresist pattern 220 are respectively located on the metal oxide layer 40, and the thickness of the first photoresist pattern 210 is greater than the thickness of the second photoresist pattern 220.

[0058] Specifically, the method for forming the first photoresist pattern 210 and the second photoresist pattern 220 includes: coating a photoresist layer on the second insulating buffer layer 50, exposing and developing the photoresist layer using a half-tone mask 300, so that the photoresist layer leaves the first photoresist pattern 210 and the second photoresist pattern 220, while other areas where no photoresist is left expose the second insulating buffer layer 50.

[0059] The halftone mask 300 includes an opaque area 310, a semi-transparent area 320, and a fully transparent area 330, wherein the opaque area 310, the semi-transparent area 320, and the fully transparent area 330 correspond to the first photoresist pattern 210, the second photoresist pattern 220, and the area where no photoresist is required, respectively. After exposure and development, only the first photoresist pattern 210 and the second photoresist pattern 220 remain in the photoresist layer, and the thickness of the first photoresist pattern 210 is greater than the thickness of the second photoresist pattern 220.

[0060] The material of the second insulating buffer layer 50 can be silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ), aluminum oxide (AlO) x ) etc., or silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ), aluminum oxide (AlO) x ) and silicon nitride (SiN) x Multilayer composite materials formed by multiple combinations of elements.

[0061] like Figure 1e As shown, the second insulating buffer layer 50, the first photoresist pattern 210, and the second photoresist pattern 220 are etched, while the first photoresist pattern 210, the exposed second insulating buffer layer 50 (i.e. the portion not covered by the first photoresist pattern 210 and the second photoresist pattern 220), and the portion of the second insulating buffer layer 50 located below the first photoresist pattern 210 are removed. This results in the second insulating buffer layer 50 located below the first photoresist pattern 210 and the second photoresist pattern 220 forming a first insulating pattern 51 and a second insulating pattern 52 with different thicknesses after etching, wherein the thickness of the second insulating pattern 52 is less than the thickness of the first insulating pattern 51.

[0062] Since the thickness of the first photoresist pattern 210 is greater than that of the second photoresist pattern 220, the first photoresist pattern 210 will be thinned during the etching process. The first insulating pattern 51 retains its original thickness under the protection of the first photoresist pattern 210. The second insulating buffer layer 50 located below the second photoresist pattern 220 will continue to be etched thinner after the second photoresist pattern 220 is completely etched, so that the thickness of the second insulating pattern 52 is less than that of the first insulating pattern 51.

[0063] like Figure 1f As shown, the first photoresist pattern 210 located above the first insulating pattern 51 is removed.

[0064] like Figure 1g As shown, the metal oxide layer 40 is ion-doped using the first insulating pattern 51 and the second insulating pattern 52 as a mask, so that the area of ​​the metal oxide layer 40 not covered by the first insulating pattern 51 and the second insulating pattern 52 is transformed from a semiconductor into a conductor and formed into the first conductor region 41.

[0065] like Figure 1h As shown, a second metal layer is formed and etched to pattern the second metal layer, so that the second metal layer forms a source 61, a drain 62 and a gate 63 spaced apart from each other, wherein the source 61 and the drain 62 are both in contact with the first conductor region 41 of the metal oxide layer 40, and the gate 63 is disposed above the first insulating pattern 51.

[0066] Furthermore, when the second metal layer is etched and patterned, a data line 64 is also formed, which is electrically connected to the source electrode 61.

[0067] In this embodiment, a halftone mask 300 is used to pattern a first insulating pattern 51 and a second insulating pattern 52 with different thicknesses. The first insulating pattern 51 and the second insulating pattern 52 with different thicknesses are used to ion-dopate the metal oxide layer 40 and to protect the metal oxide layer 40 when forming the source 61, drain 62 and gate 63. The whole process does not require the use of multiple masks, saving process steps, reducing manufacturing costs and improving production efficiency.

[0068] like Figure 1i As shown, the second insulating pattern 52 is etched away using the source 61, drain 62, and gate 63 as a mask, exposing a portion of the metal oxide layer 40 located below the second insulating pattern 52, while retaining the first insulating pattern 51 to form the gate insulating layer 53.

[0069] like Figure 1j As shown, the exposed portion of the metal oxide layer 40 is ion-doped to become a conductor, forming a second conductor region 42. The portion of the unconducted metal oxide layer 40 located below the first insulating pattern 51 forms the semiconductor region 43 (i.e., the active layer) of the metal oxide thin film transistor.

[0070] The first conductor region 41 and the second conductor region 42 formed by the conductor of the metal oxide layer 4 have a function similar to a lightly doped drain region (LDD). That is, a lightly doped drain region is set near the drain electrode in the active layer channel, so that the lightly doped drain region also bears part of the voltage to weaken the drain region electric field and prevent the hot electron degradation effect.

[0071] A preferred embodiment of the present invention also provides a metal oxide thin-film transistor, which is fabricated by the above-described method for fabricating metal oxide thin-film transistors, such as... Figure 1j As shown, the metal oxide thin-film transistor includes:

[0072] Substrate 10;

[0073] The first insulating buffer layer 30 is located on the substrate 10;

[0074] A metal oxide layer 40 is located on the first insulating buffer layer 30, and the metal oxide layer 40 has a first conductor region 41, a second conductor region 42 and a semiconductor region 43.

[0075] The gate insulating layer 53 located on the semiconductor region 43; and

[0076] A source 61, a drain 62, and a gate 63 are formed in the same layer and spaced apart from each other. The gate 63 is disposed on the gate insulating layer 53. The source 61 and the drain 62 cover the first conductor region 41 and are in contact with the first conductor region 41. The second conductor region 42 is exposed between the source 61, the drain 62, and the gate insulating layer 53 (gate 63).

[0077] Furthermore, the metal oxide thin film transistor also includes a shielding layer 21 and a scan line 22 formed in the same layer and spaced apart from each other. The shielding layer 21 and the scan line 22 are disposed on the substrate 10 and located below the first insulating buffer layer 30, that is, between the substrate 10 and the first insulating buffer layer 30.

[0078] like Figure 4 As shown, in the above-described method for fabricating a metal oxide thin-film transistor, after removing the first photoresist pattern 210 located above the first insulating pattern 51, the method further includes patterning the first insulating pattern 51 and the first insulating buffer layer 30 to form a first through-hole 501 to expose the scan line 22. When forming the gate 63, the gate 63 fills into the first through-hole 501 and contacts and connects with the scan line 22. That is, the first insulating buffer layer 30 and the gate insulating layer 53 of the metal oxide thin-film transistor are provided with a first through-hole 501 exposing the scan line 22, and the gate 63 fills into the first through-hole 501 and contacts and connects with the scan line 22.

[0079] Furthermore, the metal oxide thin film transistor also includes a data line 64 connected to the source 61, which is formed in the same layer as the source 61, drain 62 and gate 63.

[0080] The metal oxide thin film transistors fabricated by the above-described method can be used as array substrates in liquid crystal display (LCD) panels or as array substrates in organic light-emitting diode (OLED) panels.

[0081] The present invention also provides an array substrate on which a plurality of the above-mentioned metal oxide thin film transistors are arranged in an array. Figure 2 This is a partial planar schematic diagram of the array substrate according to a preferred embodiment of the present invention; Figure 3 for Figure 2 A schematic diagram of the cross-section along line AA. Figure 4 for Figure 2 A cross-sectional diagram along line BB. Please refer to the attached diagram. Figure 2 , Figure 3 and Figure 4 When the aforementioned array substrate is applied to a liquid crystal display panel, the array substrate further includes:

[0082] A first passivation layer 70 covering the source 61, drain 62, gate 63 and data line 64;

[0083] A planarization layer 80 covering the first passivation layer 70;

[0084] A common electrode 91 is located on the planarization layer 80 and is formed by etching patterning of the first transparent conductive layer;

[0085] A second passivation layer 100 covering the common electrode 91;

[0086] The pixel electrode 110 is located on the second passivation layer 100 and is formed by etching the second transparent conductive layer. A contact hole 101 is formed in the second passivation layer 100, the planarization layer 80 and the first passivation layer 70 at a position corresponding to the drain 62. The pixel electrode 110 is filled in the contact hole 101 and is electrically connected to the drain 62.

[0087] It is understood that when the aforementioned metal-oxide-slim thin-film transistor is applied to the array substrate in an organic light-emitting diode (OLED) panel, the pixel electrode 110 becomes the anode of the OLED. The shielding layer 21 allows for more stable electrical signals, and since the signal is connected to the source 61, the driving current is more easily saturated, making it more suitable for driving the OLED.

[0088] The array substrate with the aforementioned metal oxide thin film transistors can be paired with active driving devices for various displays, thus diversifying the products and increasing their added value.

[0089] The metal oxide thin-film transistor and its fabrication method, as well as the array substrate provided in the embodiments of the present invention, have the following beneficial effects:

[0090] 1. The semiconductor region 43 in the metal oxide layer 40 used to form the active layer is protected by the first insulating buffer layer 30 and the second insulating buffer layer 50 during the fabrication process. The semiconductor region 43 is not damaged by the process, which makes the metal oxide thin film transistor perform well.

[0091] 2. The metal oxide layer is divided into two conductive segments, which allows for flexible adjustment of the characteristics of the metal oxide thin film transistor and makes it more suitable for different applications.

[0092] 3. By cleverly using a halftone mask 300, the metal oxide structure is made conductive, forming a top-gate metal oxide thin-film transistor. Furthermore, the gate 63, source 61, and drain 62 are fabricated on the same layer, resulting in higher efficiency.

[0093] 4. The process of this invention is simple, can be integrated with existing processes, is highly implementable, and is easy to achieve mass production.

[0094] The metal oxide thin-film transistor and its fabrication method and array substrate provided by the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for fabricating a metal oxide thin-film transistor, characterized in that, include: A first insulating buffer layer (30) is formed on the substrate (10); An oxide semiconductor thin film is formed on the first insulating buffer layer (30), and the oxide semiconductor thin film is patterned to form a metal oxide layer (40); A second insulating buffer layer (50) is formed on the first insulating buffer layer (30) to cover the metal oxide layer (40), and a first photoresist pattern (210) and a second photoresist pattern (220) are formed on the second insulating buffer layer (50), and the thickness of the first photoresist pattern (210) is greater than the thickness of the second photoresist pattern (220). The second insulating buffer layer (50), the first photoresist pattern (210) and the second photoresist pattern (220) are etched, and the first photoresist pattern (210), the exposed second insulating buffer layer (50) and the portion of the second insulating buffer layer (50) located below the first photoresist pattern (210) are removed, so that the second insulating buffer layer (50) located below the first photoresist pattern (210) and the second photoresist pattern (220) forms a first insulating pattern (51) and a second insulating pattern (52) with different thicknesses after etching, wherein the thickness of the second insulating pattern (52) is less than the thickness of the first insulating pattern (51); Remove the first photoresist pattern (210) located above the first insulating pattern (51); Using the first insulating pattern (51) and the second insulating pattern (52) as a mask, the metal oxide layer (40) is ion-doped, so that the area of ​​the metal oxide layer (40) not covered by the first insulating pattern (51) and the second insulating pattern (52) is transformed from a semiconductor into a conductor and formed as a first conductor region (41). A second metal layer is formed and etched and patterned to form a source (61), a drain (62) and a gate (63) spaced apart from each other. The source (61) and the drain (62) are both in contact with the first conductor region (41), and the gate (63) is disposed above the first insulating pattern (51). Using the source (61), drain (62), and gate (63) as a mask, the second insulating pattern (52) is etched away, exposing a portion of the metal oxide layer (40) below the second insulating pattern (52), while retaining the first insulating pattern (51) to form the gate insulating layer (53); and The exposed portion of the metal oxide layer (40) is ion-doped to become a conductor, forming a second conductor region (42), while the portion of the unconducted metal oxide layer (40) located below the first insulating pattern (51) forms a semiconductor region (43).

2. The method for fabricating a metal oxide thin-film transistor as described in claim 1, characterized in that, The method for forming the first photoresist pattern (210) and the second photoresist pattern (220) includes: A photoresist layer is coated on the second insulating buffer layer (50), and the photoresist layer is exposed and developed using a halftone mask (300) to leave the first photoresist pattern (210) and the second photoresist pattern (220) on the photoresist layer; the halftone mask (300) includes an opaque area (310), a semi-transparent area (320) and a fully transparent area (330), and the opaque area (310), the semi-transparent area (320) and the fully transparent area (330) respectively correspond to the first photoresist pattern (210), the second photoresist pattern (220) and the area where no photoresist needs to be left.

3. The method for fabricating a metal oxide thin-film transistor as described in claim 1, characterized in that, Before forming the first insulating buffer layer (30) on the substrate (10), a shielding layer (21) and a scan line (22) are formed on the substrate (10) at intervals, the position of the shielding layer (21) corresponding to the position of the metal oxide layer (40).

4. The method for fabricating a metal oxide thin-film transistor as described in claim 3, characterized in that, After removing the first photoresist pattern (210) located above the first insulating pattern (51), the process further includes patterning the first insulating pattern (51) and the first insulating buffer layer (30) to form a first via (501) to expose the scan line (22). When forming the gate (63), the gate (63) is filled into the first via (501) and contacts the scan line (22).

5. The method for fabricating a metal oxide thin-film transistor as described in claim 1, characterized in that, When the second metal layer is etched and patterned, a data line (64) is also formed, which is connected to the source electrode (61).

6. A metal oxide thin-film transistor, characterized in that, Fabricated by the method of fabricating a metal oxide thin-film transistor according to any one of claims 1 to 5, comprising: Substrate (10); A first insulating buffer layer (30) is located on the substrate (10); A metal oxide layer (40) is located on the first insulating buffer layer (30), the metal oxide layer (40) having a first conductor region (41), a second conductor region (42) and a semiconductor region (43); The gate insulating layer (53) located on the semiconductor region (43); and A source (61), a drain (62), and a gate (63) are formed in the same layer and spaced apart from each other. The gate (63) is disposed on the gate insulating layer (53). The source (61) and the drain (62) cover the first conductor region (41) and are in contact with the first conductor region (41). The second conductor region (42) is exposed between the source (61), the drain (62), and the gate insulating layer (53).

7. The metal oxide thin-film transistor as claimed in claim 6, characterized in that, It also includes a shielding layer (21) and a scan line (22) formed in the same layer and spaced apart from each other, the shielding layer (21) and the scan line (22) being disposed between the substrate (10) and the first insulating buffer layer (30).

8. The metal oxide thin-film transistor as claimed in claim 7, characterized in that, The first insulating buffer layer (30) and the gate insulating layer (53) are provided with a first through hole (501) exposing the scan line (22), and the gate (63) is filled into the first through hole (501) and in contact with the scan line (22).

9. The metal oxide thin-film transistor as claimed in claim 6, characterized in that, It also includes a data line (64) connected to the source (61), which is formed on the same layer as the source (61), the drain (62) and the gate (63).

10. An array substrate comprising a metal-oxide-slim thin-film transistor as described in any one of claims 6 to 9, wherein the array substrate further comprises: A first passivation layer (70) covering the source (61), the drain (62) and the gate (63); A planarization layer (80) covering the first passivation layer (70); The common electrode (91) is located on the planar layer (80); A second passivation layer (100) covering the common electrode (91); A pixel electrode (110) is located on the second passivation layer (100). A contact hole (101) is formed in the second passivation layer (100), the planarization layer (80) and the first passivation layer (70) at a position corresponding to the drain electrode (62). The pixel electrode (110) is filled into the contact hole (101) and makes contact with the drain electrode (62).

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