Display substrate and manufacturing method thereof, and display device

Abstract

A display substrate and a manufacturing method thereof, and a display device. The display substrate comprises: a base substrate, and a shift register unit, a first clock signal line, and a second clock signal line arranged on a peripheral area of ​​the base substrate; the first clock signal line and the second clock signal line extend along a first direction; the shift register unit comprises a first control transistor, a second control transistor, and a third control transistor, the active layer of the first control transistor, the active layer of the second control transistor, and the active layer of the third control transistor extend along a second direction respectively, the active layer of the first control transistor, the active layer of the second control transistor, and the active layer of the third control transistor are located on a side of the first clock signal line and the second clock signal line close to the display area, and the active layer of the first control transistor, the active layer of the second control transistor, and the active layer of the third control transistor are arranged side by side in the first direction. The display substrate is conducive to realizing a narrow frame design.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate and a manufacturing method thereof, and a display device. Background Art

[0002] In the field of display technology, for example, the pixel array of a liquid crystal display panel or an organic light emitting diode (OLED) display panel usually includes multiple rows of gate lines and multiple columns of data lines interlaced with the gate lines. The driving of the gate lines can be achieved by a bound integrated drive circuit. In recent years, with the continuous improvement of the preparation process of amorphous silicon thin film transistors or oxide thin film transistors, the gate line drive circuit can also be directly integrated on the thin film transistor array substrate to form a GOA (Gate driver On Array) to drive the gate lines. For example, a GOA including multiple cascaded shift register units can be used to provide a switching state voltage signal (scanning signal) for multiple rows of gate lines of a pixel array, so as to control multiple rows of gate lines to open in sequence, and at the same time, the data line provides a data signal to the pixel unit of the corresponding row in the pixel array, so as to form the grayscale voltage required for each grayscale of the display image in each pixel unit, thereby displaying a frame of image. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a display substrate, which includes: a base substrate, a shift register unit, a first clock signal line and a second clock signal line; the base substrate includes a display area and a peripheral area located at least on one side of the display area, and the shift register unit, the first clock signal line and the second clock signal line are arranged on the peripheral area of ​​the base substrate; the first clock signal line and the second clock signal line extend along a first direction on the base substrate, and the first clock signal line and the second clock signal line are configured to provide a first clock signal or a second clock signal to the shift register unit respectively; the shift register unit includes a first control transistor, a second control transistor and a third control transistor, the active layer of the first control transistor, the active layer of the second control transistor and the active layer of the third control transistor respectively extend along a second direction different from the first direction, the orthographic projection of the active layer of the first control transistor on the base substrate, the orthographic projection of the active layer of the second control transistor on the base substrate and the orthographic projection of the active layer of the third control transistor on the base substrate are located on a side of the orthographic projection of the first clock signal line and the second clock signal line on the base substrate close to the display area, and the orthographic projection of the active layer of the first control transistor on the base substrate is parallel to the orthographic projection of the active layer of the third control transistor on the base substrate. The minimum distance between the orthographic projections of the first clock signal line and the second clock signal line on the substrate in the second direction is a first distance, the minimum distance between the orthographic projection of the active layer of the second control transistor on the substrate and the orthographic projections of the first clock signal line and the second clock signal line on the substrate in the second direction is a second distance, the minimum distance between the orthographic projection of the active layer of the third control transistor on the substrate and the orthographic projections of the first clock signal line and the second clock signal line on the substrate in the second direction is a third distance, the difference between the first distance and the second distance is greater than or equal to 0 and less than or equal to the size of the active layer of the first control transistor in the second direction or the size of the active layer of the second control transistor in the second direction, the difference between the first distance and the third distance is greater than or equal to 0 and less than or equal to 2 times the size of the active layer of the first control transistor in the second direction or 2 times the size of the active layer of the third control transistor in the second direction, and the difference between the second distance and the third distance is greater than or equal to 0 and less than or equal to 2 times the size of the active layer of the second control transistor in the second direction or 2 times the size of the active layer of the third control transistor in the second direction.

[0004] For example, in a display substrate provided in an embodiment of the present disclosure, the first distance ranges from 40 μm to 55 μm, and the second distance ranges from 40 μm to 55 μm.

[0005] For example, in a display substrate provided in an embodiment of the present disclosure, the first distance is 40 μm, 42 μm, 44 μm, 45 μm or 50 μm, and the second distance is 40 μm, 42 μm, 44 μm, 45 μm or 50 μm.

[0006] For example, in a display substrate provided by an embodiment of the present disclosure, the gate of the first control transistor, the gate of the second control transistor, and the gate of the third control transistor are parallel to each other in the first direction.

[0007] For example, in a display substrate provided in one embodiment of the present disclosure, the gate of the first control transistor includes a main portion extending along the second direction and two sub-gates extending from the main portion of the gate of the first control transistor and parallel to each other, and the gate of the second control transistor includes a main portion extending along the second direction and two sub-gates extending from the main portion of the gate of the second control transistor and parallel to each other.

[0008] For example, in a display substrate provided in an embodiment of the present disclosure, the orthographic projection of the active layer of the third control transistor on the base substrate is located on a side of the orthographic projection of the active layer of the second control transistor on the base substrate away from the orthographic projection of the active layer of the first control transistor on the base substrate.

[0009] For example, in a display substrate provided in an embodiment of the present disclosure, the shift register unit includes an input circuit, a first node control circuit, a second node control circuit, a second node noise reduction circuit, a third node control circuit, an output control circuit and an output circuit; the first node control circuit is configured to input a first voltage to a first node under the control of an input signal and a second clock signal; the second node control circuit is configured to input the first clock signal to a second node in response to a level of the first node; the output control circuit is configured to output the first voltage to the output end in response to a level of the second node; the input circuit is configured to input an input signal to a fourth node in response to the first clock signal; the second node noise reduction circuit is configured to input the first voltage to the second node in response to a level of the fourth node to perform noise reduction on the second node; the third node control circuit is configured to control the level of the third node under the control of a second voltage; the output circuit is configured to output the second voltage to the output end in response to a level of the third node; the first node control circuit includes the first control transistor and the second control transistor, and the second node control circuit includes the third control transistor.

[0010] For example, the display substrate provided by an embodiment of the present disclosure also includes a first connecting trace, which extends along the second direction, and the orthographic projection of the first connecting trace on the base substrate is located on the side of the orthographic projection of the gate of the second control transistor on the base substrate away from the display area, and the first end of the first connecting trace is connected to the gate of the second control transistor, and the second end of the first connecting trace is connected to the second clock signal line through a via penetrating the insulating layer, and the first connecting trace is integrated with the gate of the second control transistor.

[0011] For example, a display substrate provided by an embodiment of the present disclosure also includes a first transfer electrode, which includes a first sub-portion extending along the first direction, a first end of the first sub-portion of the first transfer electrode is connected to the second electrode of the first control transistor, and a second end of the first sub-portion of the first transfer electrode is connected to the second electrode of the second control transistor.

[0012] For example, a display substrate provided by an embodiment of the present disclosure also includes a first power line and a first power line transition electrode for providing the first voltage, the first power line extends along the first direction, the orthographic projection of the first power line on the base substrate is located on a side where the orthographic projection of the active layer of the first control transistor on the base substrate and the orthographic projection of the active layer of the second control transistor on the base substrate are close to the display area, the first power line transition electrode is connected to the first power line and is formed as an integral whole, and the first electrode of the first control transistor and the first electrode of the second control transistor are respectively connected to the first power line through the first power line transition electrode.

[0013] For example, in a display substrate provided in an embodiment of the present disclosure, the ratio of the width of the first power line in the second direction to the width of the first clock signal line in the second direction is greater than or equal to 1.2 and less than or equal to 3, and the ratio of the width of the first power line in the second direction to the width of the second clock signal line in the second direction is greater than or equal to 1.2 and less than or equal to 3.

[0014] For example, the display substrate provided by an embodiment of the present disclosure also includes a second transfer electrode, the orthographic projection of the second transfer electrode on the base substrate is located on a side away from the orthographic projection of the active layer of the first control transistor on the base substrate and the orthographic projection of the active layer of the second control transistor on the base substrate, the second transfer electrode extends along the first direction and is connected to the gate of the first control transistor through a via hole penetrating the insulating layer, and the second transfer electrode is connected to the trigger signal line or the output end of the previous stage shift register unit to receive the input signal.

[0015] For example, in a display substrate provided in an embodiment of the present disclosure, the output circuit includes an output transistor, the output control circuit includes an output control transistor, the orthographic projection of the active layer of the output transistor on the substrate substrate and the orthographic projection of the active layer of the output control transistor on the substrate substrate are located on a side where the orthographic projection of the active layer of the first control transistor on the substrate substrate and the orthographic projection of the active layer of the second control transistor on the substrate substrate are close to the display area, and are located on a side where the orthographic projection of the first power line on the substrate substrate is away from the display area.

[0016] For example, the display substrate provided by an embodiment of the present disclosure further includes at least one common semiconductor pattern, and the active layer of the output transistor and the active layer of the output control transistor are respectively different parts of the at least one common semiconductor pattern.

[0017] For example, in a display substrate provided by an embodiment of the present disclosure, the at least one common semiconductor pattern includes a plurality of common semiconductor patterns, and the plurality of common semiconductor patterns are spaced apart from each other and arranged in parallel in the second direction.

[0018] For example, in a display substrate provided in an embodiment of the present disclosure, the gate of the output transistor includes multiple sub-gates connected in parallel, the multiple sub-gates of the output transistor are parallel to each other in the first direction, and the gate of the output control transistor includes multiple sub-gates connected in parallel, the multiple sub-gates of the output control transistor are parallel to each other in the first direction.

[0019] For example, a display substrate provided by an embodiment of the present disclosure also includes a second power line for providing the second voltage, a second power line switching electrode and a third switching electrode, the second power line extends along the first direction, the orthographic projection of the second power line on the base substrate is located on a side away from the orthographic projection of the active layer of the first control transistor on the base substrate and the orthographic projection of the active layer of the second control transistor on the base substrate, the second power line switching electrode is connected to the second power line and is formed as an integral whole, the first electrode of the output transistor is connected to the second power line through the second power line switching electrode, the second electrode of the output transistor is connected to the third switching electrode, the first electrode of the output control transistor is connected to the first power line through the first power line switching electrode, the second electrode of the output control transistor is connected to the third switching electrode, and the output end includes the third switching electrode.

[0020] For example, in a display substrate provided in an embodiment of the present disclosure, the ratio of the width of the second power line in the second direction to the width of the first clock signal line in the second direction is greater than or equal to 1.2 and less than or equal to 3, and the ratio of the width of the second power line in the second direction to the width of the second clock signal line in the second direction is greater than or equal to 1.2 and less than or equal to 3.

[0021] For example, in a display substrate provided in an embodiment of the present disclosure, the orthographic projection of the second power line on the base substrate is located on a side of the orthographic projections of the first clock signal line and the second clock signal line on the base substrate close to the display area.

[0022] For example, in a display substrate provided in an embodiment of the present disclosure, the output circuit further includes a first capacitor, and the output control circuit further includes a second capacitor, the orthographic projection of the first capacitor on the substrate substrate is located between the orthographic projection of the active layer of the output transistor on the substrate substrate and the orthographic projection of the first power line on the substrate substrate, and is arranged side by side with the orthographic projection of the active layer of the output transistor on the substrate substrate in the second direction, the orthographic projection of the second capacitor on the substrate substrate is located between the orthographic projection of the active layer of the output control transistor on the substrate substrate and the orthographic projection of the first power line on the substrate substrate, and is arranged side by side with the orthographic projection of the active layer of the output control transistor on the substrate substrate in the second direction, and the orthographic projection of the first capacitor on the substrate substrate and the orthographic projection of the second capacitor on the substrate substrate are arranged side by side in the first direction.

[0023] For example, in a display substrate provided in an embodiment of the present disclosure, the first electrode of the first capacitor is connected to the gate of the output transistor and is formed as an integral whole, the second electrode of the first capacitor is connected to the third transfer electrode through a via hole penetrating the insulating layer, the first electrode of the second capacitor is connected to the gate of the output control transistor and is formed as an integral whole, and the second electrode of the second capacitor is connected to the first power line through a via hole penetrating the insulating layer.

[0024] For example, in a display substrate provided in an embodiment of the present disclosure, the second node control circuit also includes a third capacitor, and the orthographic projection of the third capacitor on the base substrate is located between the orthographic projection of the active layer of the third control transistor on the base substrate and the orthographic projection of the active layer of the second control transistor on the base substrate in the first direction.

[0025] For example, a display substrate provided by an embodiment of the present disclosure further includes an electrode connecting trace and a fourth switching electrode, the first switching electrode further including a second sub-portion extending along the second direction, the end of the second sub-portion of the first switching electrode is connected to the first pole of the third capacitor through a via hole penetrating the insulating layer, the first pole of the third capacitor is connected to the gate of the third control transistor and is formed as an integrated whole, the second pole of the third capacitor is connected to the electrode connecting trace and is formed as an integrated whole, the electrode connecting trace extends along the second direction, the first end of the electrode connecting trace is connected to the first clock signal line through a via hole penetrating the insulating layer, the second end of the electrode connecting trace is connected to the second pole of the third capacitor, the fourth switching electrode extends along the first direction, the first end of the fourth switching electrode is connected to the second end of the electrode connecting trace through a via hole penetrating the insulating layer, and the second end of the fourth switching electrode is connected to the first pole of the third control transistor.

[0026] For example, in a display substrate provided in an embodiment of the present disclosure, the second node noise reduction circuit includes a fourth control transistor, the active layer of the fourth control transistor extends along the second direction, and the orthographic projection of the active layer of the fourth control transistor on the base substrate is located in the first direction on a side away from the orthographic projection of the active layer of the third control transistor on the base substrate and away from the orthographic projection of the active layer of the second control transistor on the base substrate.

[0027] For example, in the display substrate provided in an embodiment of the present disclosure, the minimum distance in the second direction between the orthographic projection of the active layer of the fourth control transistor on the base substrate and the orthographic projections of the first clock signal line and the second clock signal line on the base substrate is a fourth distance, and the difference between the third distance and the fourth distance is greater than or equal to 0 and less than or equal to the size of the active layer of the third control transistor in the second direction or the size of the active layer of the fourth control transistor in the second direction.

[0028] For example, the display substrate provided by an embodiment of the present disclosure also includes a fifth transfer electrode and a second connecting wire, the fifth transfer electrode extends along the second direction, the first end of the fifth transfer electrode is connected to the second electrode of the third control transistor, the second end of the fifth transfer electrode is connected to the first electrode of the fourth control transistor, the first end of the second connecting wire is connected to the fifth transfer electrode through a via hole penetrating the insulating layer, the second end of the second connecting wire is connected to the gate of the output control transistor, the second connecting wire is integrated with the gate of the output control transistor, and the second electrode of the fourth control transistor is connected to the first power line transfer electrode.

[0029] For example, in a display substrate provided in an embodiment of the present disclosure, the input circuit includes an input transistor, the third node control circuit includes a fifth control transistor, the active layer of the input transistor and the active layer of the fifth control transistor extend respectively along the first direction and are arranged side by side in the second direction, and the orthographic projection of the active layer of the input transistor on the base substrate and the orthographic projection of the active layer of the fifth control transistor on the base substrate are located on a side of the orthographic projection of the active layer of the fourth control transistor on the base substrate away from the orthographic projection of the active layer of the third control transistor on the base substrate.

[0030] For example, in the display substrate provided in an embodiment of the present disclosure, the minimum distance in the second direction between the orthographic projection of the active layer of the input transistor on the base substrate and the orthographic projections of the first clock signal line and the second clock signal line on the base substrate is the fifth distance, and the difference between the fourth distance and the fifth distance is greater than or equal to 0 and less than or equal to 1.5 times the size of the active layer of the fourth control transistor in the second direction.

[0031] For example, in the display substrate provided in an embodiment of the present disclosure, the minimum distance between the orthographic projection of the active layer of the input transistor on the base substrate and the orthographic projection of the active layer of the fourth control transistor on the base substrate in the first direction is the sixth distance, the minimum distance between the orthographic projection of the active layer of the fifth control transistor on the base substrate and the orthographic projection of the active layer of the fourth control transistor on the base substrate in the first direction is the seventh distance, and the difference between the sixth distance and the seventh distance is greater than or equal to 0 and less than or equal to the size of the active layer of the input transistor in the first direction or the size of the active layer of the fifth control transistor in the first direction.

[0032] For example, the display substrate provided in an embodiment of the present disclosure further includes a third connecting wire, a fourth connecting wire, a sixth switching electrode and a seventh switching electrode, the first electrode of the input transistor is connected to the first end of the sixth switching electrode, the second electrode of the input transistor is connected to the second switching electrode, the third connecting wire extends along the second direction, the first end of the third connecting wire is connected to the first clock signal line through a via hole penetrating the insulating layer, the second end of the third connecting wire is connected to the gate of the input transistor, the third connecting wire is integrated with the gate of the input transistor, the gate of the fifth control transistor is connected to the second power line switching electrode through a via hole penetrating the insulating layer, the first electrode of the fifth control transistor is connected to the second end of the sixth switching electrode, the second electrode of the fifth control transistor is connected to the first end of the seventh switching electrode, the second end of the seventh switching electrode is connected to the first end of the fourth connecting wire through a via hole penetrating the insulating layer, the second end of the fourth connecting wire is connected to the gate of the output transistor, and the fourth connecting wire is integrated with the gate of the output transistor.

[0033] For example, in a display substrate provided in an embodiment of the present disclosure, the sixth switching electrode extends along the second direction.

[0034] For example, a display substrate provided by an embodiment of the present disclosure also includes a trigger signal line and a gate driving circuit, the gate driving circuit includes a plurality of cascaded shift register units, the trigger signal line is configured to provide a trigger signal to the gate driving circuit, the orthographic projection of the trigger signal line on the base substrate is located on a side away from the orthographic projection of the first clock signal line on the base substrate and the orthographic projection of the second clock signal line on the base substrate, and the trigger signal line is connected to the input circuit of the first-stage shift register unit of the gate driving circuit to provide the trigger signal as the input signal of the first-stage shift register unit.

[0035] At least one embodiment of the present disclosure further provides a display device, which includes the display substrate described in any embodiment of the present disclosure.

[0036] For example, in a display device provided in an embodiment of the present disclosure, the display device is an organic light emitting diode display device.

[0037] For example, the display device provided by an embodiment of the present disclosure further includes pixel units arranged in an array, and the output signal output by the output circuit of the shift register unit of the display substrate is output to the pixel units as a reset control signal.

[0038] At least one embodiment of the present disclosure further provides a method for manufacturing the display substrate described in any embodiment of the present disclosure, the manufacturing method comprising: providing the base substrate, and forming the shift register unit, the first power line providing the first voltage, the second power line providing the second voltage, the first clock signal line and the second clock signal line on the base substrate; forming the shift register unit comprises: sequentially forming a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer and a third conductive layer in a direction perpendicular to the base substrate; the active layer of each transistor is located in the semiconductor layer, the gate of each transistor and the first electrode of each capacitor are located in the first conductive layer, the second electrode of each capacitor is located in the second conductive layer, the first power line, the second power line, the first clock signal line, the second clock signal line and the first electrode and the second electrode of each transistor are located in the third conductive layer; the each transistor and the each capacitor are connected to each other and to the first power line, the second power line, the first clock signal line and the second clock signal line through vias penetrating the first insulating layer, the second insulating layer or the third insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0040] Figure 1A A schematic diagram of an overall circuit structure of a display panel;

[0041] Figure 1B A circuit diagram of a reset control shift register unit;

[0042] Figure 1C for Figure 1B The signal timing diagram of the reset control shift register unit when it is working;

[0043] Figure 2A and Figure 2B A schematic diagram of the layout of a display substrate provided for at least one embodiment of the present disclosure;

[0044] Figure 3A and Figure 3B A plan view of a semiconductor layer of a display substrate provided for at least one embodiment of the present disclosure;

[0045] Figure 4 A plan view of a first conductive layer of a display substrate provided for at least one embodiment of the present disclosure;

[0046] Figure 5A plan view of a second conductive layer of a display substrate provided for at least one embodiment of the present disclosure;

[0047] Figure 6 A distribution diagram of via holes of a display substrate provided in at least one embodiment of the present disclosure;

[0048] Figure 7 A plan view of a third conductive layer of a display substrate provided for at least one embodiment of the present disclosure;

[0049] Figure 8 for Figure 2A Some examples of cross-sectional views of the display substrate along the AA' direction are shown;

[0050] Fig. 9 A schematic diagram of a display device provided for at least one embodiment of the present disclosure; and

[0051] Fig.10 A flow chart of a method for manufacturing a display substrate provided in at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0053] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0054] The present disclosure is described below by several specific embodiments. In order to keep the following description of the embodiments of the present invention clear and concise, the detailed description of known functions and known components may be omitted. When any component of the embodiments of the present invention appears in more than one accompanying drawings, the component is represented by the same reference numeral in each of the accompanying drawings.

[0055] Figure 1A is a schematic diagram of the overall circuit structure of a display panel. Figure 1A As shown, 101 represents the overall outer frame of the display panel. The display panel includes a display area (i.e., a pixel array area) 102 and a peripheral area 106 located around the display area 102; the display area 102 includes a plurality of pixel units 103 arranged in an array; the peripheral area 106 includes a scan drive shift register unit 104, and a plurality of cascaded scan drive shift register units 104 form a gate drive circuit (Gate The peripheral area 106 further includes a reset control shift register unit 105, and a plurality of cascaded reset control shift register units 105 constitute a reset control drive circuit array, which is used to provide, for example, a reset control signal that is shifted row by row to the pixel units 103 arranged in an array in the display area 102 of the display panel 101, that is, a gate drive circuit for outputting a reset control signal; the peripheral area 106 further includes a light emitting control shift register unit (not shown), and a plurality of cascaded light emitting control shift register units constitute a light emitting control drive circuit array, which is used to provide, for example, a light emitting control signal that is shifted row by row to the pixel units 103 arranged in an array in the display area 102 of the display panel 101, that is, a gate drive circuit for outputting a light emitting control signal.

[0056] In some embodiments, an output signal (ie, a reset control signal) output by an output circuit of a reset control shift register unit 105 is correspondingly output to a row of pixel units 103 .

[0057] For example, in some embodiments, the reset control shift register unit 105 may be as follows: Figure 1A As shown, it is located on the side of the scan drive shift register unit 104 close to the display area 102; in some embodiments, the reset control shift register unit 105 can also be located on the side of the scan drive shift register unit 104 away from the display area 102, and the embodiments of the present disclosure are not limited to this.

[0058] like Figure 1AAs shown, a plurality of data lines DL1 to DLN (N is an integer greater than 1) connected to the data driver chip IC vertically pass through the display area 102 to provide data signals for the pixel units 103 arranged in an array; a plurality of groups of gate lines GL1 to GLM (M is an integer greater than 1) connected to the scan drive shift register unit 104, the reset control shift register unit 105, and the light emitting control shift register unit horizontally pass through the display area 102 to provide the pixel units 103 arranged in an array with gate scanning signals, reset control signals, and light emitting control signals. For example, each pixel unit 103 may include a pixel circuit and a light emitting element having a circuit structure such as 7T1C, 8T2C, or 4T1C in the art, and the pixel circuit operates under the control of the data signal transmitted through the data line and the gate scanning signal, reset control signal, and light emitting control signal transmitted through the gate line to drive the light emitting element to emit light to achieve display and other operations. The light emitting element may be, for example, an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED).

[0059] Figure 1B The invention is a circuit diagram of a reset control shift register unit. Figure 1C for Figure 1B The signal timing diagram of the reset control shift register unit when it is working is shown below. Figure 1B and Figure 1C The working process of the reset control shift register unit is briefly introduced.

[0060] like Figure 1B As shown, the reset control shift register unit 105 includes 8 transistors (a first control transistor T1, a second control transistor T2, a third control transistor T3, a fourth control transistor T4, a fifth control transistor T5, an input transistor T6, an output transistor T7 and an output control transistor T8) and 3 capacitors (a first capacitor C1, a second capacitor C2 and a third capacitor C3). For example, when multiple reset control shift register units 105 are cascaded, the second electrode of the input transistor T6 in the first-stage reset control shift register unit 105 is connected to the input terminal EI, and the input terminal EI is configured to be connected to the trigger signal line to receive the trigger signal as an input signal, while the second electrode of the input transistor T6 in the reset control shift register units 105 at other stages is electrically connected to the output terminal EOUT of the previous stage reset control shift register unit 105 to receive the output signal output by the output terminal EOUT of the previous stage reset control shift register unit 105 as an input signal, thereby realizing shifted output to provide, for example, a reset control signal shifted row by row to the array-arranged pixel units 103 in the display area 102 of the display panel 101.

[0061] In addition, if Figure 1BAs shown, the reset control shift register unit also includes a first clock signal terminal CK and a second clock signal terminal CB. For example, the first clock signal terminal CK is connected to the first clock signal line or the second clock signal line to receive the first clock signal. For example, when the first clock signal terminal CK is connected to the first clock signal line, the first clock signal line provides the first clock signal; when the first clock signal terminal CK is connected to the second clock signal line, the second clock signal line provides the first clock signal; it depends on the actual situation, and the embodiments of the present disclosure are not limited to this. Similarly, the second clock signal terminal CB is connected to the second clock signal line or the first clock signal line to receive the second clock signal. The following is an introduction to the example that the first clock signal terminal CK is connected to the first clock signal line to receive the first clock signal, and the second clock signal terminal CB is connected to the second clock signal line to receive the second clock signal. The embodiments of the present disclosure are not limited to this. For example, the first clock signal and the second clock signal can use pulse signals with a duty cycle greater than 50%, and the two can differ by half a cycle, for example. For example, VGH represents a first power line and a first voltage provided by the first power line, VGL represents a second power line and a second voltage provided by the second power line, and the first voltage is greater than the second voltage. For example, the first voltage is a DC high level, and the second voltage is a DC low level. For example, N1, N2, N3, and N4 represent a first node, a second node, a third node, and a fourth node in the circuit diagram, respectively.

[0062] like Figure 1B As shown, the gate of the input transistor T6 is connected to the first clock signal terminal CK to receive the first clock signal, the second electrode of the input transistor T6 is connected to the input terminal EI, and the first electrode of the input transistor T6 is connected to the fourth node N4. For example, when the reset control shift register unit is a first-stage reset control shift register unit, the input terminal EI is connected to the trigger signal line to receive the trigger signal; when the reset control shift register unit is a reset control shift register unit of other stages except the first-stage reset control shift register unit, the input terminal EI is connected to the output terminal EOUT of the reset control shift register unit of the previous stage.

[0063] A gate electrode of the fifth control transistor T5 is connected to the second power line VGL to receive the second voltage, a first electrode of the fifth control transistor T5 is connected to the fourth node N4, and a second electrode of the fifth control transistor T5 is connected to the third node N3.

[0064] A gate of the output transistor T7 is connected to the third node N3 , a first electrode of the output transistor T7 is connected to the second power line VGL to receive the second voltage, and a second electrode of the output transistor T7 is connected to the output terminal EOUT.

[0065] A first electrode of the first capacitor C1 is connected to the third node N3 , and a second electrode of the first capacitor C1 is connected to the output terminal EOUT.

[0066] The gate of the first control transistor T1 is connected to the input terminal EI, the first electrode of the first control transistor T1 is connected to the first power line VGH to receive the first voltage, and the second electrode of the first control transistor T1 is connected to the first node N1. For example, when the reset control shift register unit is a first-stage reset control shift register unit, the input terminal EI is connected to the trigger signal line to receive the trigger signal; when the reset control shift register unit is a reset control shift register unit of other stages except the first-stage reset control shift register unit, the input terminal EI is connected to the output terminal EOUT of the reset control shift register unit of the previous stage.

[0067] A gate of the second control transistor T2 is connected to the second clock signal terminal CB to receive the second clock signal, a first electrode of the second control transistor T2 is connected to the first power line VGH to receive the first voltage, and a second electrode of the second control transistor T2 is connected to the first node N1.

[0068] A gate of the third control transistor T3 is connected to the first node N1, a first electrode of the third control transistor T3 is connected to the first clock signal terminal CK to receive the first clock signal, and a second electrode of the third control transistor T3 is connected to the second node N2.

[0069] A first electrode of the third capacitor C3 is connected to the first node N1, and a second electrode of the third capacitor C3 is connected to the first clock signal terminal CK to receive the first clock signal.

[0070] A gate of the fourth control transistor T4 is connected to the fourth node N4 , a first electrode of the fourth control transistor T4 is connected to the second node N2 , and a second electrode of the fourth control transistor T4 is connected to the first power line VGH to receive the first voltage.

[0071] A gate of the output control transistor T8 is connected to the second node N2 , a first electrode of the output control transistor T8 is connected to the first power line VGH to receive a first voltage, and a second electrode of the output control transistor T8 is connected to the output terminal EOUT.

[0072] A first electrode of the second capacitor C2 is connected to the second node N2 , and a second electrode of the second capacitor C2 is connected to the first power line VGH to receive the first voltage.

[0073] Figure 1BThe transistors in the reset control shift register unit 105 shown in the figure are all described by taking P-type transistors as examples, that is, each transistor is turned on when the gate is connected to a low level (on level), and is turned off when the gate is connected to a high level (off level). At this time, the first electrode of the transistor can be a source electrode, and the second electrode of the transistor can be a drain electrode.

[0074] The reset control shift register unit includes but is not limited to Figure 1B Configuration method, for example, each transistor in the reset control shift register unit 105 can also use N-type transistors or a mixture of P-type transistors and N-type transistors, and it is only necessary to simultaneously connect the port polarities of the selected type of transistors according to the port polarities of the corresponding transistors in the embodiments of the present disclosure.

[0075] It should be noted that the transistors used in the reset control shift register unit can be thin film transistors or field effect transistors or other switching devices with the same characteristics. Here, thin film transistors are used as examples for explanation. For example, the active layer (channel region) of the transistor is made of semiconductor materials, such as polycrystalline silicon (such as low-temperature polycrystalline silicon or high-temperature polycrystalline silicon), amorphous silicon, indium gallium tin oxide (IGZO), etc., while the gate, source, drain, etc. are made of metal materials, such as metal aluminum or aluminum alloy. The source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be indistinguishable in structure. In the embodiment of the present disclosure, in order to distinguish the two poles of the transistor except the gate, one of the poles is directly described as the first pole and the other pole is the second pole. In addition, in the embodiment of the present disclosure, the electrodes of the capacitor can be metal electrodes or one of the electrodes can be made of semiconductor materials (such as doped polycrystalline silicon).

[0076] Figure 1C for Figure 1B The signal timing diagram of the reset control shift register unit 105 when it is working is shown below. Figure 1B and Figure 1C The working process of the reset control shift register unit is described in detail. For example, the working principle of the first-stage reset control shift register unit 105 is described, and the working principles of the other stages of the reset control shift register unit 105 are similar to it and will not be described in detail. Figure 1C As shown, the working process of the reset control shift register unit 105 includes 6 stages, namely, the first stage P1, the second stage P2, the third stage P3, the fourth stage P4, the fifth stage P5 and the sixth stage P6. Figure 1C The timing waveforms of each signal in each stage are shown.

[0077] In the first stage P1, if Figure 1CAs shown, the first clock signal line provides a high level, so the first clock signal terminal CK connected to the first clock signal line receives the first clock signal of the high level, and the input transistor T6 is turned off. Due to the storage effect of the first capacitor C1, the level of the third node N3 can be kept at a high level, so that the output transistor T7 is turned off. The fifth control transistor T5 is turned on in response to the second voltage of the low level, so that the level of the fourth node N4 becomes a high level, and the fourth control transistor T4 is turned off. The trigger signal line provides a low level, so the input terminal EI connected to the trigger signal line receives a low-level trigger signal, and the first control transistor T1 is turned on. The second clock signal line provides a low level, so the second clock signal terminal CB connected to the second clock signal line receives a low-level second clock signal, and the second control transistor T2 is turned on. The high-level first voltage is transmitted to the first node N1 through the turned-on first control transistor T1 and the second control transistor T2, so that the level of the first node N1 becomes a high level, and the third control transistor T3 is turned off. Due to the storage function of the second capacitor C2, the level of the second node N2 can be kept at a low level, so that the output control transistor T8 is turned on. The high-level first voltage is transmitted to the output terminal EOUT through the turned-on output control transistor T8, so in the first stage P1, the output signal output by the output terminal EOUT of the reset control shift register unit 105 is a high level.

[0078] In the second stage P2, if Figure 1C As shown, the input terminal EI receives a low-level trigger signal provided by the trigger signal line, and the first control transistor T1 is turned on. The second clock signal terminal CB receives a high-level second clock signal provided by the second clock signal line, and the second control transistor T2 is turned off. The high-level first voltage is transmitted to the first node N1 through the turned-on first control transistor T1, so that the level of the first node N1 becomes high, and the third control transistor T3 is turned off. The first clock signal terminal CK receives a low-level first clock signal provided by the first clock signal line, and the input transistor T6 is turned on. Since the input terminal EI receives a low-level trigger signal provided by the trigger signal line, the level of the fourth node N4 becomes low, so that the fourth control transistor T4 is turned on. The high-level first voltage is transmitted to the second node N2 through the turned-on fourth control transistor T4, so that the output control transistor T8 is turned off. The fifth control transistor T5 is turned on in response to the low-level second voltage, so that the level of the third node N3 becomes low, so that the output transistor T7 is turned on, and the low-level second voltage is transmitted to the output terminal EOUT through the turned-on output transistor T7. Therefore, in the second phase P2, the output signal outputted from the output terminal EOUT of the reset control shift register unit 105 is at a low level.

[0079] In the third stage P3, if Figure 1C As shown, the input terminal EI receives the low-level trigger signal provided by the trigger signal line, and the first control transistor T1 is turned on. The second clock signal terminal CB receives the low-level second clock signal provided by the second clock signal line, and the second control transistor T2 is turned on. The high-level first voltage is transmitted to the first node N1 through the turned-on first control transistor T1 and the second control transistor T2, so that the level of the first node N1 becomes high, and the third control transistor T3 is turned off. Due to the storage effect of the second capacitor C2, the level of the second node N2 can be kept at a high level, so that the output control transistor T8 is turned off. The first clock signal terminal CK receives the high-level first clock signal provided by the first clock signal line, and the input transistor T6 is turned off. Due to the storage effect of the first capacitor C1, the level of the third node N3 can be kept at a low level, so that the output transistor T7 is turned on, and the low-level second voltage is transmitted to the output terminal EOUT through the turned-on output transistor T7. At the same time, the level of the third node N3 is further pulled down to be lower than the second voltage, so that the fifth control transistor T5 is turned off. Therefore, in the third phase P3, the output signal outputted from the output terminal EOUT of the reset control shift register unit 105 is at a low level.

[0080] In the fourth stage P4, if Figure 1C As shown, the input terminal EI receives a low-level trigger signal provided by the trigger signal line, and the first control transistor T1 is turned on. The second clock signal terminal CB receives a high-level second clock signal provided by the second clock signal line, and the second control transistor T2 is turned off. The high-level first voltage is transmitted to the first node N1 through the turned-on first control transistor T1, so that the level of the first node N1 becomes high, and the third control transistor T3 is turned off. The first clock signal terminal CK receives a low-level first clock signal provided by the first clock signal line, and the input transistor T6 is turned on. Since the input terminal EI receives a low-level trigger signal provided by the trigger signal line, the level of the fourth node N4 becomes low, so that the fourth control transistor T4 is turned on. The high-level first voltage is transmitted to the second node N2 through the turned-on fourth control transistor T4, so that the output control transistor T8 is turned off. Due to the storage effect of the first capacitor C1, the level of the third node N3 can be kept at a low level, so that the output transistor T7 is turned on, and the low-level second voltage is transmitted to the output terminal EOUT through the turned-on output transistor T7. At the same time, the level of the third node N3 is further pulled down to be lower than the second voltage, so that the fifth control transistor T5 is turned off. Therefore, in the fourth phase P4, the output signal outputted by the output terminal EOUT of the reset control shift register unit 105 is at a low level.

[0081] In the fifth stage P5, if Figure 1CAs shown, the input terminal EI receives the high-level trigger signal provided by the trigger signal line, and the first control transistor T1 is turned off. The second clock signal terminal CB receives the low-level second clock signal provided by the second clock signal line, and the second control transistor T2 is turned on. The high-level first voltage is transmitted to the first node N1 through the turned-on second control transistor T2, so that the level of the first node N1 becomes high, and the third control transistor T3 is turned off. Due to the storage effect of the second capacitor C2, the level of the second node N2 can be kept at a high level, so that the output control transistor T8 is turned off. The first clock signal terminal CK receives the high-level first clock signal provided by the first clock signal line, and the input transistor T6 is turned off. Due to the storage effect of the first capacitor C1, the level of the third node N3 can be kept at a low level, so that the output transistor T7 is turned on, and the low-level second voltage is transmitted to the output terminal EOUT through the turned-on output transistor T7. At the same time, the level of the third node N3 is further pulled down to be lower than the second voltage, so that the fifth control transistor T5 is turned off. Therefore, in the fifth phase P5, the output signal outputted from the output terminal EOUT of the reset control shift register unit 105 is at a low level.

[0082] In the sixth stage P6, if Figure 1C As shown, the first clock signal terminal CK receives the low-level first clock signal provided by the first clock signal line, and the input transistor T6 is turned on. Since the input terminal EI receives the high-level trigger signal provided by the trigger signal line, the level of the fourth node N4 becomes high, so that the fourth control transistor T4 is turned off. The fifth control transistor T5 is turned on in response to the low-level second voltage, so that the level of the third node N3 becomes high, and therefore, the output transistor T7 is turned off. The input terminal EI receives the high-level trigger signal provided by the trigger signal line, and the first control transistor T1 is turned off. The second clock signal terminal CB receives the high-level second clock signal provided by the second clock signal line, and the second control transistor T2 is turned off. Due to the storage function of the third capacitor C3, under the action of the low-level first clock signal received by the first clock signal terminal CK, the level of the first node N1 becomes low, so that the third control transistor T3 is turned on. The low level received by the first clock signal terminal CK is transmitted to the second node N2 through the turned-on third control transistor T3, so that the output control transistor T8 is turned on. The high-level first voltage is transmitted to the output terminal EOUT through the turned-on output control transistor T8 . Therefore, in the sixth phase P6 , the output signal outputted by the output terminal EOUT of the reset control shift register unit 105 is at a high level.

[0083] With the maturity of AMOLED (Active-matrix organic light-emitting diode) technology, more and more mobile terminals use AMOLED as display panels. At present, for the market, AMOLED products with narrow borders have more competitive advantages and are favored by more consumers. In addition to being affected by packaging technology, the size of the border is also largely limited by the overall size of GOA (for example, gate drive circuit, reset control drive circuit array, and light control drive circuit array, etc.). The larger the size of GOA, the larger the size of the left and right borders of the panel will be, and conversely, the smaller the size of GOA, the narrower the border will become. However, at present, taking the reset control drive circuit array as an example, the arrangement design between the transistors and capacitors in GOA occupies a large space in the direction from the left border of the panel to the right border, resulting in a waste of layout space of the display substrate, which is not conducive to the realization of a narrow border of the display substrate.

[0084] At least one embodiment of the present disclosure provides a display substrate, which includes: a base substrate including a display area and a peripheral area located on at least one side of the display area; and a shift register unit, a first clock signal line, and a second clock signal line arranged on the peripheral area of ​​the base substrate. The first clock signal line and the second clock signal line extend along a first direction on the substrate, and the first clock signal line and the second clock signal line are configured to provide a first clock signal or a second clock signal to the shift register unit respectively; the shift register unit comprises a first control transistor, a second control transistor and a third control transistor, the active layer of the first control transistor, the active layer of the second control transistor and the active layer of the third control transistor respectively extend along a second direction different from the first direction, the orthographic projection of the active layer of the first control transistor on the substrate, the orthographic projection of the active layer of the second control transistor on the substrate and the orthographic projection of the active layer of the third control transistor on the substrate are located on a side of the orthographic projection of the first clock signal line and the second clock signal line on the substrate close to the display area; the minimum distance in the second direction between the orthographic projection of the active layer of the first control transistor on the substrate and the orthographic projection of the first clock signal line and the second clock signal line on the substrate is a first distance, and the orthographic projection of the second control transistor on the substrate is a first distance. The minimum distance in the second direction between the orthographic projection of the active layer on the substrate and the orthographic projections of the first clock signal line and the second clock signal line on the substrate is the second distance, the minimum distance in the second direction between the orthographic projection of the active layer of the third control transistor on the substrate and the orthographic projections of the first clock signal line and the second clock signal line on the substrate is the third distance, the difference between the first distance and the second distance is greater than or equal to 0 and less than or equal to the size of the active layer of the first control transistor in the second direction or the size of the active layer of the second control transistor in the second direction, the difference between the first distance and the third distance is greater than or equal to 0 and less than or equal to 2 times the size of the active layer of the first control transistor in the second direction or 2 times the size of the active layer of the third control transistor in the second direction, and the difference between the second distance and the third distance is greater than or equal to 0 and less than or equal to 2 times the size of the active layer of the second control transistor in the second direction or 2 times the size of the active layer of the third control transistor in the second direction.

[0085] At least one embodiment of the present disclosure further provides a display device corresponding to the above-mentioned display substrate and a method for manufacturing the display substrate.

[0086] The display substrate provided in the above-mentioned embodiments of the present disclosure optimizes the line connection and structural layout of the shift register unit, compresses the size of the shift register unit in the second direction to a certain extent, and reduces the space required to be occupied by the shift register unit in the peripheral area of ​​the display substrate, which is conducive to realizing the narrow frame design of the display substrate while ensuring the display quality of the display substrate.

[0087] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals in different drawings will be used to refer to the same elements that have been described.

[0088] Figure 2A A schematic layout diagram of a display substrate provided for at least one embodiment of the present disclosure.

[0089] For example, Figure 2A As shown, the display substrate includes a base substrate 10 and a shift register unit 105 disposed on the base substrate 10, a first power line VGH, a second power line VGL and a plurality of clock signal lines. For example, the plurality of clock signal lines may include Figure 2A , the first clock signal line ECK, the second clock signal line ECB and the trigger signal line ESTV shown in FIG. For example, in an embodiment of the present disclosure, the shift register unit 105 may be Figure 1B The reset control shift register unit 105 shown in FIG. For the sake of convenience and brevity, the reset control shift register unit 105 is referred to as a shift register unit for the following description.

[0090] For example, a first power line VGH, a second power line VGL, and a plurality of clock signal lines (for example, a first clock signal line ECK, a second clock signal line ECB, and a trigger signal line ESTV) extend along a first direction Y on the substrate 10, and are configured to provide a first voltage, a second voltage, and a plurality of clock signals (for example, a first clock signal, a second clock signal, or a trigger signal, etc.) to the shift register unit 105, respectively. For example, the first power line VGH is configured to provide a first voltage to the shift register unit 105, and the second power line VGL is configured to provide a second voltage to the shift register unit 105; the first clock signal line ECK and the second clock signal line ECB are configured to provide a first clock signal or a second clock signal to the shift register unit 105, respectively. For example, the second voltage is less than the first voltage, for example, the first voltage is a DC high level, and the second voltage is a DC low level. The specific connection relationship between the first power line VGH, the second power line VGL, and the plurality of clock signal lines and the shift register unit 105 can be referred to the following description.

[0091] It should be noted that in the embodiment of the present disclosure, the first clock signal line ECK provides the first clock signal to the shift register unit 105, and the second clock signal line ECB provides the second clock signal to the shift register unit 105 is used as an example for explanation, and the embodiments of the present disclosure include but are not limited to this; in some other embodiments of the present disclosure, the first clock signal line ECK may provide the second clock signal to the shift register unit 105, and the second clock signal line ECB may provide the first clock signal to the shift register unit 105, and the embodiments of the present disclosure are not limited to this.

[0092] It should be noted that the first power line VGH, the second power line VGL and the multiple clock signal lines can extend along the first direction Y and be arranged parallel to each other, or they can cross at a certain angle (for example, less than or equal to 20°), which is not limited in the embodiments of the present disclosure.

[0093] For example, the base substrate 10 may be made of glass, plastic, quartz or other suitable materials, which is not limited in the embodiments of the present disclosure.

[0094] For example, refer to Figure 1A and Figure 2A As shown, the display substrate provided by the embodiment of the present disclosure includes a display area 102 (for example, the display area 102 can also be called a pixel array area) and a peripheral area 106 located at least on one side of the pixel array area. For example, the first power line VGH, the second power line VGL, the plurality of clock signal lines and the shift register unit 105 are located on the peripheral area 106 of the base substrate 10 and on one side of the base substrate 10 (for example, Figure 1A As shown, it is located between the display area 102 and the side of the base substrate 10), for example, Figure 1A As shown, it can be located on both the left and right sides of the base substrate 10, and of course it can also be located on the left or right side of the base substrate 10, and the embodiments of the present disclosure are not limited to this.

[0095] For example, the positive projection of the second power line VGL on the base substrate 10 and the positive projection of the plurality of clock signal lines on the base substrate 10 are both located on the side of the positive projection of the shift register unit 105 on the base substrate 10 away from the display area 102, for example, in the second direction X, both are located Figure 2A The orthographic projection of the first power line VGH on the substrate 10 partially overlaps with the orthographic projection of the shift register unit 105 on the substrate 10, and is located on the side of the orthographic projection of the shift register unit 105 on the substrate 10 close to the display area 102. For example, in the second direction X, the first power line VGH is located Figure 2A The right side of the shift register unit 105 is located between the orthographic projection of the shift register unit 105 on the substrate 10 and the display area 102. That is, the orthographic projection of the shift register unit 105 on the substrate 10 is located between the orthographic projection of the first power line VGH on the substrate 10 and the orthographic projection of the second power line VGL on the substrate 10.

[0096] For example, Figure 2AAs shown, the orthographic projection of the second power line VGL on the substrate substrate 10 is located between the orthographic projections of the first clock signal line ECK and the second clock signal line ECB on the substrate substrate 10 and the orthographic projection of the shift register unit 105 on the substrate substrate 10. For example, the first clock signal line ECK and the second clock signal line ECB are sequentially arranged from right to left along the second direction X on the substrate substrate 10, that is, the orthographic projection of the second clock signal line ECB on the substrate substrate 10 is located on the side of the orthographic projection of the first clock signal line ECK on the substrate substrate 10 away from the orthographic projection of the second power line VGL on the substrate substrate 10.

[0097] It should be noted that the above-mentioned multiple clock signal lines may also include a trigger signal line ESTV that provides a trigger signal. For example, the positive projection of the trigger signal line ESTV on the substrate substrate 10 may be located on a side where the positive projections of the first clock signal line ECK and the second clock signal line ECB on the substrate substrate 10 are away from the positive projection of the shift register unit 105 on the substrate substrate 10, that is, the first clock signal line ECK, the second clock signal line ECB and the trigger signal line ESTV are sequentially arranged from right to left along the second direction X on the substrate substrate 10.

[0098] It should be noted that the above wiring positions are merely exemplary, and as long as the wiring arrangement can facilitate connection with the shift register unit, the embodiments of the present disclosure do not impose any limitation on this.

[0099] For example, the angle between the first direction Y and the second direction X is between 70° and 90°, including 70° and 90°. For example, the angle between the first direction Y and the second direction X can be 70°, 75°, 80°, 85° or 90°, etc. The specific value of the angle can be set according to actual conditions, and the embodiments of the present disclosure are not limited to this.

[0100] For example, the display area 102 includes a plurality of pixel units 103 arranged in an array. For example, each of the plurality of pixel units 103 includes a pixel circuit, and may further include a light emitting element (not shown in the figure).

[0101] For example, a plurality of cascaded shift register units 105 (i.e., reset control shift register units 105) form a reset control driving circuit array. For example, the output terminals EOUT of the plurality of shift register units 105 are respectively connected to the reset control signal terminals of the pixel circuits of each row located in the pixel array area to provide output signals (e.g., reset control signals) to the pixel circuits of each row, thereby driving the light-emitting elements to emit light. For example, the pixel circuit can be a pixel circuit in the art, such as a circuit structure including 7T1C, 2T1C, 4T2C, 8T2C, etc., which will not be described in detail here.

[0102] It should be noted that Figure 2A Only the Kth (K is an odd number greater than 1) stage shift register unit 105 in the gate driving circuit is shown. For example, the first clock signal terminal CK of the first stage shift register unit (not shown in the figure) is connected to the first clock signal line ECK to receive the first clock signal, the second clock signal terminal CB of the first stage shift register unit is connected to the second clock signal line ECB to receive the second clock signal, the first clock signal terminal CK of the second stage shift register unit (not shown in the figure) is connected to the second clock signal line ECB to receive the first clock signal, the second clock signal terminal CB of the second stage shift register unit is connected to the first clock signal line ECK to receive the second clock signal; and so on. Figure 2A As shown, the first clock signal terminal CK of the Kth (K is an odd number greater than 1) shift register unit 105 is connected to the first clock signal line ECK to receive the first clock signal, the second clock signal terminal CB of the Kth shift register unit 105 is connected to the second clock signal line ECB to receive the second clock signal, the first clock signal terminal CK of the K+1th shift register unit is connected to the second clock signal line ECB to receive the first clock signal, and the second clock signal terminal CB of the K+1th shift register unit is connected to the first clock signal line ECK to receive the second clock signal. It should be noted that the connection method of the shift register units at each level and the clock signal line can also adopt other connection methods in the art, and the embodiments of the present disclosure are not limited to this. For example, the input terminal EI of the first-stage shift register unit is connected to the trigger signal line ESTV to receive the trigger signal as the input signal, the input terminal EI of the second-stage shift register unit is connected to the output terminal EOUT of the previous-stage shift register unit (i.e., the first-stage shift register unit), and the connection methods of the remaining shift register units at each level are similar. The structure of the K-th stage shift register unit 105 is taken as an example for description below, and the embodiments of the present disclosure are not limited to this.

[0103] For example, Figure 1B As shown, in some examples, the shift register unit 105 includes a first node control circuit 1041, a second node control circuit 1042, a third node control circuit 1043, a second node noise reduction circuit 1044, an input circuit 1045, an output circuit 1046 and an output control circuit 1047.

[0104] The first node control circuit 1041 is configured to input the first voltage to the first node N1 under the control of the input signal and the second clock signal, thereby controlling the level of the first node N1. For example, the first node control circuit 1041 is connected to the first power line VGH, the input terminal EI, the second clock signal terminal CB (the second clock signal terminal CB of the K-th stage shift register unit 105 is connected to the second clock signal line ECB to receive the second clock signal, and the second clock signal terminal CB of the K+1-th stage shift register unit is connected to the first clock signal line ECK to receive the second clock signal) and the first node N1, and is configured to be turned on under the control of the input signal received by the input terminal EI and the second clock signal received by the second clock signal terminal CB, so that the first power line VGH is connected to the first node N1 to input the first voltage provided by the first power line VGH to the first node N1, thereby controlling the level of the first node N1. For example, the first node control circuit 1041 can be implemented as the first control transistor T1 and the second control transistor T2 described above. The connection method of the first control transistor T1 and the second control transistor T2 can refer to the corresponding description above and will not be repeated here.

[0105] The second node control circuit 1042 is configured to input the first clock signal to the second node N2 in response to the level of the first node N1, thereby controlling the level of the second node N2. For example, the second node control circuit 1042 is connected to the first clock signal terminal CK (the first clock signal terminal CK of the K-th stage shift register unit 105 is connected to the first clock signal line ECK to receive the first clock signal, and the first clock signal terminal CK of the K+1-th stage shift register unit is connected to the second clock signal line ECB to receive the first clock signal), the first node N1, and the second node N2, and is configured to be turned on under the control of the level of the first node N1, and input the first clock signal to the second node N2 to control the level of the second node N2. For example, the second node control circuit 1042 can be implemented as the third control transistor T3 and the third capacitor C3 described above, and the connection method of the third control transistor T3 and the third capacitor C3 can refer to the corresponding description above, which will not be repeated here. It should be noted that the second node control circuit 1042 is not limited to being connected to the first node N1, and can also be connected to other independent voltage terminals (providing the same voltage as the first node N1) or a separately set circuit that is the same as the first node control circuit 1041, and the embodiments of the present disclosure are not limited to this. The connections of other circuits of the shift register unit are similar to this, and will not be repeated here.

[0106] The output control circuit 1047 is configured to output the first voltage to the output terminal EOUT in response to the level of the second node N2. For example, the output control circuit 1047 is connected to the second node N2, the first power line VGH and the output terminal EOUT, and is configured to be turned on under the control of the level of the second node N2, so that the first power line VGH is connected to the output terminal EOUT, thereby outputting the first voltage as an output signal at the output terminal EOUT. For example, the output control circuit 1047 can be implemented as the output control transistor T8 and the second capacitor C2 described above, and the connection mode of the output control transistor T8 and the second capacitor C2 can refer to the corresponding description above, which is not repeated here. It should be noted that the output control circuit 1047 is not limited to being connected to the second node N2, and can also be connected to other independent voltage terminals (providing the same voltage as the voltage of the second node N2) or to a separately set circuit that is the same as the second node control circuit 1042, and the embodiments of the present disclosure are not limited to this.

[0107] The input circuit 1045 is configured to input the input signal to the fourth node N4 in response to the first clock signal. For example, the input circuit 1045 is connected to the input terminal EI, the fourth node N4, and the first clock signal terminal CK, and is configured to be turned on under the control of the first clock signal received by the first clock signal terminal CK, and connect the input terminal EI to the fourth node N4, so as to input the input signal received by the input terminal EI to the fourth node N4. For example, the input circuit 1045 can be implemented as the input transistor T6 described above, and the connection method of the input transistor T6 can refer to the corresponding description above, which will not be repeated here.

[0108] The second node noise reduction circuit 1044 is configured to input the first voltage to the second node N2 in response to the level of the fourth node N4, so as to reduce the noise of the second node N2. For example, the second node noise reduction circuit 1044 is connected to the first power line VGH, the second node N2 and the fourth node N4, and is configured to be turned on under the control of the level of the fourth node N4, so that the second node N2 is connected to the first power line VGH, thereby maintaining the voltage of the second node N2 at a high level to reduce the noise of the second node N2. For example, the second node noise reduction circuit 1044 can be implemented as the fourth control transistor T4 described above, and the connection method of the fourth control transistor T4 can refer to the corresponding description above, which is not repeated here. It should be noted that the second node noise reduction circuit 1044 is not limited to being connected to the fourth node N4, and can also be connected to other independent voltage terminals (providing the same voltage as the voltage of the fourth node N4) or to a separately set circuit that is the same as the input circuit 1045, and the embodiments of the present disclosure are not limited to this.

[0109] The third node control circuit 1043 is configured to control the level of the third node N3 under the control of the second voltage. For example, the third node control circuit 1043 is connected to the second power line VGL, the third node N3 and the fourth node N4, and is configured to be turned on under the control of the second voltage provided by the second power line VGL, and the level of the fourth node N4 is input to the third node N3. For example, the third node control circuit 1043 can be implemented as the fifth control transistor T5 described above, and the connection method of the fifth control transistor T5 can refer to the corresponding description above, which is not repeated here. It should be noted that the third node control circuit 1043 is not limited to being connected to the fourth node N4, and can also be connected to other independent voltage terminals (providing the same voltage as the fourth node N4) or to a separately set circuit that is the same as the input circuit 1045, and the embodiments of the present disclosure are not limited to this.

[0110] The output circuit 1046 is configured to output the second voltage to the output terminal EOUT in response to the level of the third node N3. For example, the output circuit 1046 is connected to the third node N3, the output terminal EOUT and the second power line VGL, and is configured to be turned on under the control of the level of the third node N3, so that the second power line VGL and the output terminal EOUT are connected, thereby outputting the second voltage as an output signal at the output terminal EOUT. For example, the output circuit 1046 can be implemented as the output transistor T7 and the first capacitor C1 described above, and the connection mode of the output transistor T7 and the first capacitor C1 can refer to the corresponding description above, which is not repeated here. It should be noted that the output circuit 1046 is not limited to being connected to the third node N3, and can also be connected to other independent voltage terminals (providing the same voltage as the voltage of the third node N3) or to a separately set circuit that is the same as the third node control circuit 1043, and the embodiments of the present disclosure are not limited to this.

[0111] It should be noted that the embodiment of the present disclosure only schematically shows two clock signal lines (a first clock signal line ECK and a second clock signal line ECB), and the display substrate provided by the embodiment of the present disclosure may also include 4, 6 or 8 or more clock signal lines, and the embodiment of the present disclosure is not limited to this. Correspondingly, when the number of clock signal lines changes, the connection relationship between the shift register unit 105 in the display substrate and the clock signal lines also changes accordingly. The specific content can refer to the conventional design in the art, and will not be repeated here.

[0112] Figure 3A , Figure 4 , Figure 5 and Figure 7 They are shown respectively Figure 2A The figure shows a plan view of the wiring of each layer of the display substrate. Figure 3AA plan view of a semiconductor layer of a display substrate provided in at least one embodiment of the present disclosure, Figure 4 A plan view of a first conductive layer of a display substrate provided in at least one embodiment of the present disclosure, Figure 5 A plan view of a second conductive layer of a display substrate provided in at least one embodiment of the present disclosure, Figure 6 A distribution diagram of via holes of a display substrate provided in at least one embodiment of the present disclosure, Figure 7 A plan view of a third conductive layer of a display substrate provided for at least one embodiment of the present disclosure. Figure 8 for Figure 2A The cross-sectional views of some examples of the display substrate along the AA' direction are shown. For example, the AA' direction can be understood as: along the first electrode SD11 of the first control transistor T1→the second electrode SD12 of the first control transistor T1→the second electrode SD22 of the second control transistor T2→the first electrode SD21 of the second control transistor T2, or along the first electrode SD21 of the second control transistor T2→the second electrode SD22 of the second control transistor T2→the second electrode SD12 of the first control transistor T1→the first electrode SD11 of the first control transistor T1. For example, Figure 8 The cross-sectional view shown may correspond to the structure of the first control transistor T1 and the second control transistor T2. Figure 2A-Figure 8 The stacked structure of a display substrate provided in at least one embodiment of the present disclosure is introduced in detail.

[0113] For example, the interlayer insulating layer of the display substrate (eg, including a first insulating layer, a second insulating layer, a third insulating layer, etc.) may be located at FIG. 3A to FIG. 7 For example, the first insulating layer 350 (eg Figure 8 shown) is located at Figure 3A The semiconductor layer 310 and Figure 4 The first conductive layer 320 is shown between the second insulating layer 360 (such as Figure 8 shown) is located at Figure 4 The first conductive layer 320 and Figure 5 The third insulating layer 370 (such as Figure 8 shown) is located at Figure 5 The second conductive layer 330 and Figure 7 Between the third conductive layers 340 shown. Figure 6 The via hole shown is a via hole that penetrates one or more layers among the first insulating layer 350 , the second insulating layer 360 and the third insulating layer 370 .

[0114] For example, Figure 8As shown, the display substrate further includes a fourth insulating layer 380 , which is located on the third conductive layer 340 , that is, located on a side of the third conductive layer 340 away from the base substrate 10 , for protecting the third conductive layer 340 .

[0115] For example, the materials of the first insulating layer 350, the second insulating layer 360, the third insulating layer 370 and the fourth insulating layer 380 may include inorganic insulating materials such as SiNx, SiOx, SiNxOy, organic insulating materials such as organic resins, or may also include other suitable materials, which is not limited to the embodiments of the present disclosure.

[0116] It should be noted that Figure 2A The display substrate shown in the figure takes the layout design of the K-th shift register unit in the reset control driving circuit array and the first power line, the second power line and the clock signal line connected thereto as an example for explanation. The layout implementation methods of the remaining shift register units at various levels can refer to Figure 2A The layout shown in FIG. 1 is not described in detail here. Of course, other suitable layouts can also be used, and the embodiments of the present disclosure are not limited to this. Of course, the shift register units of each level of the reset control drive circuit array can also refer to FIG. Figure 2A The layout shown in , or other suitable layouts may also be adopted, and the embodiments of the present disclosure are not limited to this.

[0117] Combine the following Figure 2A-Figure 8 A display substrate provided in at least one embodiment of the present disclosure is introduced in detail.

[0118] For example, Figure 2A The active layers A1 to A8 of the first control transistor T1, the second control transistor T2, the third control transistor T3, the fourth control transistor T4, the fifth control transistor T5, the input transistor T6, the output transistor T7, and the output control transistor T8 of the shift register unit 105 shown in FIG. 1 may be formed on Figure 3A The semiconductor layer 310 is shown in FIG. The semiconductor layer 310 may be formed by patterning a semiconductor material. Figure 3AAs shown, according to different actual needs, the semiconductor layer 310 may include a short rod-shaped portion or a portion having a curved or bent shape, so as to be used to make the active layers A1 to A8 of the above-mentioned transistors T1 to T8. The active layer of each transistor may include a source region, a drain region, and a channel region located between the source region and the drain region. For example, the channel region has semiconductor characteristics; the source region and the drain region are on both sides of the channel region, and may be doped with impurities and thus have conductivity. For example, the source region is a part of the active layer, and the metal electrode in contact with the source region (for example, located in the third conductive layer 340) corresponds to the source (or first electrode) of the transistor; the drain region is a part of the active layer, and the metal electrode in contact with the drain region (for example, located in the third conductive layer 340) corresponds to the drain (or second electrode) of the transistor. For example, the source region is connected to its corresponding metal electrode (source) through a via that penetrates the first insulating layer 350, the second insulating layer 360 and the third insulating layer 370, and the drain region is connected to its corresponding metal electrode (drain) through a via that penetrates the first insulating layer 350, the second insulating layer 360 and the third insulating layer 370.

[0119] For example, taking the first control transistor T1 and the second control transistor T2 as an example, Figure 8 As shown, the first electrode SD11 of the first control transistor T1 is connected to the source region of the active layer A1 of the first control transistor T1 through a via hole H1 penetrating the third insulating layer 370, the second insulating layer 360 and the first insulating layer 350, and the second electrode SD12 of the first control transistor T1 is connected to the drain region of the active layer A1 of the first control transistor T1 through a via hole H2 penetrating the third insulating layer 370, the second insulating layer 360 and the first insulating layer 350; the second electrode SD22 of the second control transistor T2 is connected to the drain region of the active layer A2 of the second control transistor T2 through a via hole H3 penetrating the third insulating layer 370, the second insulating layer 360 and the first insulating layer 350, and the first electrode SD21 of the second control transistor T2 is connected to the source region of the active layer A2 of the second control transistor T2 through a via hole H4 penetrating the third insulating layer 370, the second insulating layer 360 and the first insulating layer 350.

[0120] For example, the material of the semiconductor layer 310 may include an oxide semiconductor, an organic semiconductor or amorphous silicon, polycrystalline silicon, etc. For example, the oxide semiconductor includes a metal oxide semiconductor (such as indium gallium zinc oxide (IGZO)), and the polycrystalline silicon includes low-temperature polycrystalline silicon or high-temperature polycrystalline silicon, etc., which is not limited in the embodiments of the present disclosure. It should be noted that the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities, which is not limited in the embodiments of the present disclosure.

[0121] It should be noted that in some other examples, the first electrode and the second electrode of each transistor may also be located in other conductive layers, and connected to the corresponding active layer through vias in the insulating layer between it and the semiconductor layer, and the embodiments of the present disclosure are not limited to this.

[0122] Figure 4 The first conductive layer 320 of the display substrate is shown, and the first conductive layer 320 is disposed on the first insulating layer 350, so as to be insulated from the semiconductor layer 310. For example, the first conductive layer 320 may include first electrodes CE11, CE12, and CE13 of the first capacitor C1 to the third capacitor C3, and gates G1-G8 of the transistors T1-T8 and various wirings directly connected to the gates G1-G8 (for example, the first connecting wiring L1, the second connecting wiring L2, the third connecting wiring L3, and the fourth connecting wiring L4), and accordingly, the first insulating layer 350 may also serve as a gate insulating layer. Figure 4 As shown, the gates G1 - G8 of the transistors T1 - T8 are the parts enclosed by circular or elliptical dotted circles, ie, the parts where the semiconductor layer structures of the respective transistors overlap with the electrodes or traces on the first conductive layer 320 .

[0123] Figure 5 The second conductive layer 330 of the display substrate is shown, and the second conductive layer 330 includes second electrodes CE21, CE22, and CE23 of the first capacitor C1 to the third capacitor C3 and a wiring (for example, an electrode connection wiring M1) for connecting with a signal line or a transfer electrode on the third conductive layer 340. For example, the second electrode CE21 at least partially overlaps with the first electrode CE11 to form the first capacitor C1, the second electrode CE22 at least partially overlaps with the first electrode CE12 to form the second capacitor C2, and the second electrode CE23 at least partially overlaps with the first electrode CE13 to form the third capacitor C3.

[0124] Figure 7 The third conductive layer 340 of the display substrate is shown, and the third conductive layer 340 includes a plurality of signal lines (for example, a first clock signal line ECK, a second clock signal line ECB, and a trigger signal line ESTV), a first power line VGH, and a second power line VGL, etc. It should be noted that the third conductive layer 340 also includes a first switching electrode 110, a second switching electrode 120, a third switching electrode 130, a fourth switching electrode 140, a fifth switching electrode 150, a sixth switching electrode 160, a seventh switching electrode 170, a first power line switching electrode 180, and a second power line switching electrode 190, etc., which are connected between various transistors, capacitors, and signal lines. For example, the second switching electrode 120 includes an input terminal EI, and the third switching electrode 130 includes an output terminal EOUT.

[0125] It should be noted that, in the embodiment of the present disclosure, the second switching electrode 120 located in the third conductive layer 340 can be used to receive an input signal; and in some other embodiments of the present disclosure, the input signal of the input terminal EI of the shift register unit 105 can also be received by electrodes located in other layers, that is, the input terminal EI can also be set in other layers different from the third conductive layer 340, for example, it can be set in the first conductive layer 320 or the second conductive layer 330, and the embodiments of the present disclosure are not limited to this.

[0126] It should be noted that, in the embodiments of the present disclosure, the third switching electrode 130 located in the third conductive layer 340 can be used to provide an output signal; and in some other embodiments of the present disclosure, the output signal of the output terminal EOUT of the shift register unit 105 can also be provided by electrodes located in other layers, that is, the output terminal EOUT can also be set in other layers different from the third conductive layer 340, for example, it can be set in the first conductive layer 320 or the second conductive layer 330, and the embodiments of the present disclosure are not limited to this.

[0127] It should be noted that, in the embodiment of the present disclosure, the second transfer electrode 120 and the third transfer electrode 130 are both located in the third conductive layer 340. Therefore, except for the last-stage shift register unit 105, the third transfer electrode 130 for providing an output signal can be connected to and integrated with the second transfer electrode 120 in the next-stage shift register unit 105, thereby providing an input signal to the input terminal EI of the next-stage shift register unit 105; except for the first-stage shift register unit 105, the second transfer electrode 120 for receiving an input signal can be connected to and integrated with the third transfer electrode 130 in the previous-stage shift register unit 105, thereby receiving the output signal of the output terminal EOUT of the previous-stage shift register unit 105 as the input signal of the input terminal EI of the current-stage shift register unit 105.

[0128] like Figures 2A to 7 As shown, a plurality of signal lines, a first power line VGH and a second power line VGL are connected through Figure 6 The at least one via shown is connected to the transistors and capacitors in the remaining layers that need to be connected thereto. Each transistor and capacitor may also be connected through at least one via, or bridged through a switching electrode, which will not be described in detail here.

[0129] For example, the material of the third conductive layer 340 may include titanium, titanium alloy, aluminum, aluminum alloy, copper, copper alloy or any other suitable composite material, which is not limited in the embodiments of the present disclosure. For example, the material of the first conductive layer 320 and the second conductive layer 330 may be the same as the material of the third conductive layer 340, which will not be described in detail herein.

[0130] Figure 2A For the above Figure 3A The semiconductor layer 310 shown Figure 4 The first conductive layer 320 shown, Figure 5 The second conductive layer 330 and Figure 7 The schematic diagram of the stacking position relationship of the third conductive layer 340 is shown below. Figure 2A-Figure 8 A display substrate provided in at least one embodiment of the present disclosure is introduced in detail.

[0131] For example, Figure 2A and Figure 3A As shown, the active layer A1 of the first control transistor T1 and the active layer A2 of the second control transistor T2 extend respectively along a second direction X different from the first direction Y. The orthographic projection of the active layer A1 of the first control transistor T1 and the orthographic projection of the active layer A2 of the second control transistor T2 on the substrate 10 are located on a side of the orthographic projection of the first clock signal line ECK and the second clock signal line ECB on the substrate 10 close to the display area 102, that is, in the second direction X, the active layer A1 of the first control transistor T1 and the active layer A2 of the second control transistor T2 are located on the right side of the first clock signal line ECK and the second clock signal line ECB.

[0132] For example, combined with Figure 2A , Figure 2B and Figure 3AAs shown, the minimum distance between the orthographic projection of the active layer A1 of the first control transistor T1 on the substrate 10 and the orthographic projections of the first clock signal line ECK and the second clock signal line ECB on the substrate 10 in the second direction X is the first distance D1, and the minimum distance between the orthographic projection of the active layer A2 of the second control transistor T2 on the substrate 10 and the orthographic projections of the first clock signal line ECK and the second clock signal line ECB on the substrate 10 in the second direction X is the second distance D2. For example, the first distance D1 is the distance between the orthographic projection of the active layer A1 of the first control transistor T1 on the substrate 10 and the edge of the first clock signal line ECK on the side close to the display area 102 in the second direction X, and the second distance D2 is the distance between the orthographic projection of the active layer A2 of the second control transistor T2 on the substrate 10 and the edge of the first clock signal line ECK on the side close to the display area 102 in the second direction X. The difference between the first distance D1 and the second distance D2 is greater than or equal to 0 and less than or equal to the size AL1 of the active layer A1 of the first control transistor T1 in the second direction X or the size AL2 of the active layer A2 of the second control transistor T2 in the second direction X, that is, 0≤|D1-D2|≤AL1 or 0≤|D1-D2|≤AL2. For example, AL1 is the length of the active layer A1 of the first control transistor T1 in the second direction X, and AL2 is the length of the active layer A2 of the second control transistor T2 in the second direction X. Thus, the active layer A1 of the first control transistor T1 and the active layer A2 of the second control transistor T2 are arranged side by side in the first direction Y.

[0133] Thus, by making the difference between the first distance D1 and the second distance D2 greater than or equal to 0 and less than or equal to the size AL1 of the active layer A1 of the first control transistor T1 in the second direction X or the size AL2 of the active layer A2 of the second control transistor T2 in the second direction X, the active layer A1 of the first control transistor T1 and the active layer A2 of the second control transistor T2 can be arranged side by side in the first direction Y, thereby reducing the size occupied by the first control transistor T1 and the second control transistor T2 in the second direction X, and optimizing the layout design of the first control transistor T1 and the second control transistor T2 in the shift register unit 105. Furthermore, the size occupied by the shift register unit 105 in the second direction X is reduced to a certain extent, and the space required to be occupied by the shift register unit 105 in the peripheral area 106 of the display substrate is reduced, which is conducive to realizing the narrow frame design of the display substrate and ensuring the display quality of the display substrate. In addition, more sufficient space can be reserved for other transistors, capacitors, wiring, etc. in the shift register unit 105, so that the line connection and structural layout of the shift register unit 105 can be further optimized.

[0134] For example, the first distance D1 may range from 30 μm to 60 μm, such as 40 μm to 55 μm; the second distance D2 may range from 30 μm to 60 μm, such as 40 μm to 55 μm. Thus, the layout of the first control transistor T1 and the second control transistor T2 in the first direction Y and the second direction X is further optimized.

[0135] For example, the first distance D1 may be 40μm, 42μm, 44μm, 45μm, 47μm, 49μm, 50μm, 52μm or 55μm, and the second distance D2 may be 40μm, 42μm, 44μm, 45μm, 47μm, 49μm, 50μm, 52μm or 55μm, etc.

[0136] For example, the size AL1 of the active layer A1 of the first control transistor T1 in the second direction X can be set to be similar to the size AL2 of the active layer A2 of the second control transistor T2 in the second direction X, thereby further optimizing the layout structure of the first control transistor T1 and the second control transistor T2 in the display substrate.

[0137] For example, Figure 2A and Figure 4 As shown, the gate G1 of the first control transistor T1 and the gate G2 of the second control transistor T2 are parallel to each other in the first direction Y, that is, the gate G1 of the first control transistor T1 and the gate G2 of the second control transistor T2 are arranged side by side in the first direction Y. Thus, the size occupied by the first control transistor T1 and the second control transistor T2 in the second direction X is further reduced, and the layout design of the first control transistor T1 and the second control transistor T2 in the shift register unit 105 is optimized.

[0138] For example, Figure 2A , Figure 4 and Figure 8 As shown, the gate G1 of the first control transistor T1 includes a main body G11 extending along the second direction X and two sub-gates G12 extending from the main body G11 of the gate G1 of the first control transistor T1 and parallel to each other, that is, the first control transistor T1 is a dual-gate structure. For example, the two sub-gates G12 extending along the first direction Y are respectively extended. The gate G2 of the second control transistor T2 includes a main body G21 extending along the second direction X and two sub-gates G22 extending from the main body G21 of the gate G2 of the second control transistor T2 and parallel to each other, that is, the second control transistor T2 is a dual-gate structure. For example, the two sub-gates G22 extending along the first direction Y are respectively extended.

[0139] Therefore, by making the gate G1 of the first control transistor T1 and the gate G2 of the second control transistor T2 form a "U"-shaped structure respectively, the stability of the first control transistor T1 and the second control transistor T2 can be improved, thereby improving the performance of the first control transistor T1 and the second control transistor T2.

[0140] It should be noted that in some other embodiments of the present disclosure, taking the first control transistor T1 as an example, the active layer of the first control transistor T1 may be a "U"-shaped structure, and the gate of the first control transistor T1 may be a "I"-shaped structure overlapping the "U"-shaped active layer, thereby forming a double-gate structure, as long as it does not affect the arrangement of other structures and does not increase the width of the shift register unit too much, the embodiments of the present disclosure are not limited to this. It should be noted that a single gate may also overlap with the active layer of the first control transistor T1, and the embodiments of the present disclosure are not limited to this.

[0141] For example, Figure 2A , Figure 4 and Figure 7 As shown, the display substrate further includes a first connecting wire L1. The first connecting wire L1 extends along the second direction X, and the positive projection of the first connecting wire L1 on the substrate 10 is located on the side of the positive projection of the gate G2 of the second control transistor T2 on the substrate 10 away from the display area 102. For example, in the second direction X, the first connecting wire L1 is located on the left side of the gate G2 of the second control transistor T2. The first end L11 of the first connecting wire L1 is connected to the gate G2 of the second control transistor T2, for example, connected to the main body G21 of the gate G2 of the second control transistor T2, thereby simplifying the layout structure of the first connecting wire L1. The second end L12 of the first connecting wire L1 is connected to the second clock signal line ECB through a via hole penetrating the second insulating layer 360 and the third insulating layer 370 to receive the second clock signal provided by the second clock signal line ECB. As a result, the second clock signal provided by the second clock signal line ECB can be transmitted to the gate G2 of the second control transistor T2 through the first connecting wire L1. The first connection line L1 and the gate G2 of the second control transistor T2 can be formed in one piece, thereby simplifying the manufacturing process of the display substrate and reducing the manufacturing cost.

[0142] For example, Figure 2A , Figure 7 and Figure 8As shown, the display substrate further includes a first switching electrode 110. The first switching electrode 110 includes a first sub-portion 111 extending along the first direction Y, a first end 111A of the first sub-portion 111 of the first switching electrode 110 is connected to the second electrode SD12 of the first control transistor T1, preferably, for example, formed in one piece, and a second end 111B of the first sub-portion 111 of the first switching electrode 110 is connected to the second electrode SD22 of the second control transistor T2, preferably, for example, formed in one piece, thereby realizing connection between the second electrode SD12 of the first control transistor T1 and the second electrode SD22 of the second control transistor T2 through the first switching electrode 110.

[0143] For example, the first switching electrode 110 can serve as Figure 1B The first node N1 in the circuit structure shown.

[0144] For example, Figure 2A , Figure 3A , Figure 7 and Figure 8 As shown, the first power line VGH extends along the first direction Y, and the orthographic projection of the first power line VGH on the base substrate 10 is located on the side of the orthographic projection of the active layer A1 of the first control transistor T1 on the base substrate 10 and the orthographic projection of the active layer A2 of the second control transistor T2 on the base substrate 10 close to the display area 102, that is, in the second direction X, the first power line VGH is located on the right side of the active layer A1 of the first control transistor T1 and the active layer A2 of the second control transistor T2. The display substrate further includes a first power line switching electrode 180, which is connected to the first power line VGH and is formed integrally to transmit the first voltage provided by the first power line VGH. The first electrode SD11 of the first control transistor T1 and the first electrode SD21 of the second control transistor T2 are respectively connected to the first power line switching electrode 180, and are preferably formed integrally with the first power line switching electrode 180, so that the first electrode SD11 of the first control transistor T1 and the first electrode SD21 of the second control transistor T2 are respectively connected to the first power line VGH through the first power line switching electrode 180 to receive the first voltage.

[0145] For example, the ratio between the width of the first power line VGH in the second direction X and the width of the first clock signal line ECK in the second direction X is greater than or equal to 1.2 and less than or equal to 3, that is, the width of the first power line VGH in the second direction X can be 1.2 to 3 times the width of the first clock signal line ECK in the second direction X; the ratio between the width of the first power line VGH in the second direction X and the width of the second clock signal line ECB in the second direction X is greater than or equal to 1.2 and less than or equal to 3, that is, the width of the first power line VGH in the second direction X can be 1.2 to 3 times the width of the second clock signal line ECB in the second direction X. Thus, the stability of the signal transmitted on the first power line VGH is improved and the charging time is reduced.

[0146] For example, the width of the first power line VGH in the second direction X may be 1.1 times, 1.2 times, 1.33 times, 1.5 times, 1.8 times, 2 times, 2.2 times, 2.5 times, 2.7 times, or 3 times, etc., of the width of the first clock signal line ECK in the second direction X, and the width of the first power line VGH in the second direction X may be 1.1 times, 1.2 times, 1.33 times, 1.5 times, 1.8 times, 2 times, 2.2 times, 2.5 times, 2.7 times, or 3 times, etc., of the width of the second clock signal line ECB in the second direction X.

[0147] For example, Figure 2A , Figure 3A and Figure 7 As shown, the display substrate further includes a second switching electrode 120. The orthographic projection of the second switching electrode 120 on the base substrate 10 is located on a side away from the orthographic projection of the active layer A1 of the first control transistor T1 and the orthographic projection of the active layer A2 of the second control transistor T2 on the base substrate 10, that is, in the second direction X, the second switching electrode 120 is located on the left side of the active layer A1 of the first control transistor T1 and the active layer A2 of the second control transistor T2. The second switching electrode 120 extends along the first direction Y and is connected to the gate G1 of the first control transistor T1 through a via hole penetrating the second insulating layer 360 and the third insulating layer 370, for example, connected to the main part G11 of the gate G1 of the first control transistor T1.

[0148] For example, in the K-th stage shift register unit 105, the second switching electrode 120 is connected to the output terminal EOUT of the previous stage shift register unit to receive the input signal.

[0149] For example, when the shift register unit 105 is a first-stage shift register unit, the second switching electrode 120 is connected to the trigger signal line ESTV, so that the trigger signal provided by the trigger signal line ESTV is used as the input signal of the shift register unit of this stage.

[0150] For example, Figure 2A and Figure 3A As shown, the orthographic projection of the active layer A7 of the output transistor T7 on the substrate 10 and the orthographic projection of the active layer A8 of the output control transistor T8 on the substrate 10 are located on the side where the orthographic projection of the active layer A1 of the first control transistor T1 and the orthographic projection of the active layer A2 of the second control transistor T2 on the substrate 10 are close to the display area 102, and are located on the side where the orthographic projection of the first power line VGH on the substrate 10 is away from the display area 102. That is, in the second direction X, the active layer A7 of the output transistor T7 and the active layer A8 of the output control transistor T8 are located between the first power line VGH and the active layer A1 of the first control transistor T1 and the active layer A2 of the second control transistor T2.

[0151] For example, Figure 2A and Figure 3A As shown, the display substrate includes at least one common semiconductor pattern, for example, the at least one common semiconductor pattern includes a plurality of common semiconductor patterns CSP. The active layer A7 of the output transistor T7 and the active layer A8 of the output control transistor T8 are respectively different parts of the plurality of common semiconductor patterns CSP, thereby improving the stability of the output transistor T7 and the output control transistor T8.

[0152] For example, the plurality of common semiconductor patterns CSP are spaced apart from each other and arranged in parallel in the second direction X. Alternatively, in some other embodiments of the present disclosure, the plurality of common semiconductor patterns CSP may also be arranged continuously in the second direction X to form a common semiconductor pattern, which is not limited in the embodiments of the present disclosure.

[0153] For example, in the first direction Y, the active layer A7 of the output transistor T7 is located below the active layer A8 of the output control transistor T8, so that the active layer A7 of the output transistor T7 and the active layer A8 of the output control transistor T8 are arranged side by side in the first direction Y, thereby reducing the size occupied by the active layer A7 of the output transistor T7 and the active layer A8 of the output control transistor T8 in the second direction X.

[0154] For example, Figure 2A and Figure 4As shown, the gate G7 of the output transistor T7 includes a plurality of sub-gates G71 connected in parallel, and the plurality of sub-gates G71 of the output transistor T7 are parallel to each other in the first direction Y. For example, each sub-gate G71 of the output transistor T7 extends along the second direction X, so that the gate G7 of the output transistor T7 is comb-shaped in the first direction Y, thereby improving the stability of the output transistor T7. The gate G8 of the output control transistor T8 includes a plurality of sub-gates G81 connected in parallel, and the plurality of sub-gates G81 of the output control transistor T8 are parallel to each other in the first direction Y. For example, each sub-gate G81 of the output control transistor T8 extends along the second direction X, so that the gate G8 of the output control transistor T8 is comb-shaped in the first direction Y, thereby improving the stability of the output control transistor T8.

[0155] For example, Figure 2A and Figure 3A , Figure 7 As shown, the display substrate further includes a third switching electrode 130 and a second power line switching electrode 190. The second power line VGL extends along the first direction Y, and the orthographic projection of the second power line VGL on the substrate substrate 10 is located on the side away from the orthographic projection of the active layer A1 of the first control transistor T1 on the substrate substrate 10 and the orthographic projection of the active layer A2 of the second control transistor T2 on the substrate substrate 10. The display substrate 100 further includes a third switching electrode 130 and a second power line switching electrode 190. The second power line VGL extends along the first direction Y, and the orthographic projection of the second power line VGL on the substrate substrate 10 is located on the side away from the display area 102, that is, in the second direction X, the second power line VGL is located on the left side of the active layer A1 of the first control transistor T1 and the active layer A2 of the second control transistor T2. The second power line switching electrode 190 is connected to the second power line VGL and formed integrally, thereby transmitting the second voltage provided by the second power line VGL. The first electrode of the output transistor T7 is connected to the second power line VGL through the second power line switching electrode 190 to receive the second voltage. The first electrode of the output control transistor T8 is connected to the first power line switching electrode 180, preferably, for example, integrated with the first power line switching electrode 180, so that the first electrode of the output control transistor T8 is connected to the first power line VGH through the first power line switching electrode 180 to receive the first voltage. The second electrode of the output transistor T7 is connected to the third switching electrode 130, preferably, for example, integrated, and the second electrode of the output control transistor T8 is connected to the third switching electrode 130, preferably, for example, integrated, and the output terminal EOUT includes the third switching electrode 130, that is, through the third switching electrode 130, the second electrode of the output transistor T7 and the second electrode of the output control transistor T8 are respectively connected to the output terminal EOUT to provide an output signal.

[0156] For example, the ratio of the width of the second power line VGL in the second direction X to the width of the first clock signal line ECK in the second direction X is greater than or equal to 1.2 and less than or equal to 3, that is, the width of the second power line VGL in the second direction X can be 1.2 to 3 times the width of the first clock signal line ECK in the second direction X; the ratio of the width of the second power line VGL in the second direction X to the width of the second clock signal line ECB in the second direction X is greater than or equal to 1.2 and less than or equal to 3, that is, the width of the second power line VGL in the second direction X can be 1.2 to 3 times the width of the second clock signal line ECB in the second direction X. Thus, the stability of the signal transmitted on the second power line VGL is improved and the charging time is reduced.

[0157] For example, the width of the second power line VGL in the second direction X may be 1.1 times, 1.2 times, 1.33 times, 1.5 times, 1.8 times, 2 times, 2.2 times, 2.5 times, 2.7 times or 3 times, etc., of the width of the first clock signal line ECK in the second direction X, and the width of the second power line VGL in the second direction X may be 1.1 times, 1.2 times, 1.33 times, 1.5 times, 1.8 times, 2 times, 2.2 times, 2.5 times, 2.7 times or 3 times, etc., of the width of the second clock signal line ECB in the second direction X.

[0158] For example, Figure 2A and Figure 3A , Figure 7 As shown, the orthogonal projection of the first capacitor C1 on the substrate substrate 10 is located between the orthogonal projection of the active layer A7 of the output transistor T7 on the substrate substrate 10 and the orthogonal projection of the first power line VGH on the substrate substrate 10, and is arranged side by side with the orthogonal projection of the active layer A7 of the output transistor T7 on the substrate substrate 10 in the second direction X, that is, in the second direction X, the first capacitor C1 is located between the active layer A7 of the output transistor T7 and the first power line VGH. The orthogonal projection of the second capacitor C2 on the substrate substrate 10 is located between the orthogonal projection of the active layer A8 of the output control transistor T8 on the substrate substrate 10 and the orthogonal projection of the first power line VGH on the substrate substrate 10, and is arranged side by side with the orthogonal projection of the active layer of the output control transistor T8 on the substrate substrate 10 in the second direction X, that is, in the second direction X, the second capacitor C2 is located between the active layer A8 of the output control transistor T8 and the first power line VGH. For example, the first capacitor C1 and the second capacitor C2 may overlap partially with the first power line VGH, respectively. The orthographic projection of the first capacitor C1 on the base substrate 10 and the orthographic projection of the second capacitor C2 on the base substrate 10 are arranged side by side in the first direction Y, that is, the first capacitor C1 and the second capacitor C2 are arranged along the first direction Y. For example, in the first direction Y, the second capacitor C2 is located above the first capacitor C1.

[0159] Therefore, by arranging the first capacitor C1 and the second capacitor C2 side by side in the first direction Y, the number of devices arranged side by side in the second direction X can be further reduced, thereby reducing the space occupied by the first capacitor C1 and the second capacitor C2 in the second direction X, thereby compressing the size occupied by the shift register unit 105 in the second direction X to a certain extent, which is conducive to realizing a narrow frame design of the display substrate while ensuring the display quality of the display substrate.

[0160] For example, Figure 2A , Figure 4 and Figure 5 As shown, the first electrode CE11 of the first capacitor C1 is connected to the gate G7 of the output transistor T7 and is formed in an integrated manner to form, for example, a comb-shaped structure. The second electrode CE21 of the first capacitor C1 is connected to the third transfer electrode 130 through a via hole penetrating the third insulating layer 370. The first electrode CE12 of the second capacitor C2 is connected to the gate G8 of the output control transistor T8 and is formed in an integrated manner to form, for example, a comb-shaped structure. The second electrode CE22 of the second capacitor C2 is connected to the first power line VGH through a via hole penetrating the third insulating layer 370 to receive the first voltage.

[0161] For example, Figure 2A and Figure 3A As shown, the active layer A3 of the third control transistor T3 extends along the second direction X. For example, in combination Figure 2A , Figure 2B and Figure 3AAs shown, the minimum distance between the positive projection of the active layer A3 of the third control transistor T3 on the substrate 10 and the positive projections of the first clock signal line ECK and the second clock signal line ECB on the substrate 10 in the second direction X is the third distance D3. For example, the third distance D3 is the distance between the positive projection of the active layer A3 of the third control transistor T3 on the substrate 10 and the edge of the first clock signal line ECK on the side close to the display area 102 in the second direction X. The difference between the first distance D1 and the third distance D3 is greater than or equal to 0 and less than or equal to 2 times the size AL1 of the active layer A1 of the first control transistor T1 in the second direction X or 2 times the size AL3 of the active layer A3 of the third control transistor T3 in the second direction X, that is, 0≤|D1-D3|≤2AL1 or 0≤|D1-D3|≤2AL3. The difference between the second distance D2 and the third distance D3 is greater than or equal to 0 and less than or equal to twice the size AL2 of the active layer A2 of the second control transistor T2 in the second direction X or twice the size AL3 of the active layer A3 of the third control transistor T3 in the second direction X, that is, 0≤|D2-D3|≤2AL2 or 0≤|D2-D3|≤2AL3. For example, AL3 is the length of the active layer A3 of the third control transistor T3 in the second direction X. Thus, the active layer A1 of the first control transistor T1, the active layer A2 of the second control transistor T2, and the active layer A3 of the third control transistor T3 are arranged side by side in the first direction Y.

[0162] For example, the positive projection of the active layer A3 of the third control transistor T3 on the substrate 10 is located on the side where the positive projections of the first clock signal line ECK and the second clock signal line ECB on the substrate 10 are close to the display area 102. For example, the positive projection of the active layer A3 of the third control transistor T3 on the substrate 10 is located on the side where the positive projection of the active layer A2 of the second control transistor T2 on the substrate 10 is away from the positive projection of the active layer A1 of the first control transistor T1 on the substrate 10. That is, the active layer A1 of the first control transistor T1, the active layer A2 of the second control transistor T2, and the active layer A3 of the third control transistor T3 are arranged in sequence from top to bottom in the first direction Y.

[0163] Thus, by arranging the active layer A1 of the first control transistor T1, the active layer A2 of the second control transistor T2, and the active layer A3 of the third control transistor T3 side by side in the first direction Y, the size occupied by the active layer A1 of the first control transistor T1, the active layer A2 of the second control transistor T2, and the active layer A3 of the third control transistor T3 in the second direction X can be reduced, thereby optimizing the layout design of the first control transistor T1, the second control transistor T2, and the third control transistor T3 in the shift register unit 105. Furthermore, the size occupied by the shift register unit 105 in the second direction X is reduced to a certain extent, and the space required to be occupied by the shift register unit 105 in the peripheral area 106 of the display substrate is reduced, which is conducive to realizing the narrow frame design of the display substrate and ensuring the display quality of the display substrate. In addition, more sufficient space can be reserved for other transistors, capacitors, wiring, etc. in the shift register unit 105, so that the line connection and structural layout of the shift register unit 105 can be further optimized.

[0164] For example, Figure 2A and Figure 4 As shown, the gate G1 of the first control transistor T1, the gate G2 of the second control transistor T2, and the gate G3 of the third control transistor T3 are parallel to each other in the first direction Y. That is, the gate G1 of the first control transistor T1, the gate G2 of the second control transistor T2, and the gate G3 of the third control transistor T3 are arranged in sequence from top to bottom in the first direction Y. Thus, the size occupied by the first control transistor T1, the second control transistor T2, and the third control transistor T3 in the second direction X is further reduced, and the layout design of the first control transistor T1, the second control transistor T2, and the third control transistor T3 in the shift register unit 105 is optimized.

[0165] For example, Figure 2A and Figure 4 As shown, the orthographic projection of the third capacitor C3 on the base substrate 10 is located between the orthographic projection of the active layer A3 of the third control transistor T3 on the base substrate 10 and the orthographic projection of the active layer A2 of the second control transistor T2 on the base substrate 10 in the first direction Y. That is, in the first direction Y, the third capacitor C3 is located between the active layer A3 of the third control transistor T3 and the active layer A2 of the second control transistor T2, thereby further reducing the size of the shift register unit 105 in the second direction X to a certain extent.

[0166] For example, Figure 2A , Figure 4 , Figure 5 and Figure 7As shown, the first transfer electrode 110 also includes a second sub-portion 112 extending along the second direction X, and the end of the second sub-portion 112 of the first transfer electrode 110 is connected to the first electrode CE13 of the third capacitor C3 through a via hole penetrating the second insulating layer 360 and the third insulating layer 370. The first electrode CE13 of the third capacitor C3 is connected to the gate G3 of the third control transistor T3 and is formed in an integrated manner, and the second electrode CE23 of the third capacitor C3 is connected to the electrode connection line M1 and is formed in an integrated manner, thereby simplifying the preparation process of the display substrate and reducing the preparation cost. The electrode connection line M1 extends along the second direction X. The first end M11 of the electrode connection line M1 is connected to the first clock signal line ECK through a via hole penetrating the third insulating layer 370 to receive the first clock signal; the second end M12 of the electrode connection line M1 is connected to the second electrode CE23 of the third capacitor C3 to transmit the first clock signal provided by the first clock signal line ECK. The display substrate further includes a fourth transfer electrode 140, which extends along the first direction Y to reduce the size occupied in the second direction X. The first end 141 of the fourth transfer electrode 140 is connected to the second end M12 of the electrode connection wiring M1 through a via hole penetrating the third insulating layer 370, and the second end 142 of the fourth transfer electrode 140 is connected to the first electrode of the third control transistor T3, preferably, for example, formed in an integrated manner. Thus, the first clock signal provided by the first clock signal line ECK is transmitted through the fourth transfer electrode 140 and the electrode connection wiring M1.

[0167] For example, Figure 2A and Figure 3A As shown, the active layer A4 of the fourth control transistor T4 extends along the second direction X, and the positive projection of the active layer A4 of the fourth control transistor T4 on the substrate 10 is located in the first direction Y on the side of the positive projection of the active layer A3 of the third control transistor T3 on the substrate 10 away from the positive projection of the active layer A2 of the second control transistor T2 on the substrate 10.

[0168] For example, combined with Figure 2A , Figure 2B and Figure 3AAs shown, the minimum distance between the positive projection of the active layer A4 of the fourth control transistor T4 on the substrate 10 and the positive projections of the first clock signal line ECK and the second clock signal line ECB on the substrate 10 in the second direction X is the fourth distance D4. For example, the fourth distance D4 is the distance between the positive projection of the active layer A4 of the fourth control transistor T4 on the substrate 10 and the edge of the first clock signal line ECK on the side close to the display area 102 in the second direction X. The difference between the third distance D3 and the fourth distance D4 is greater than or equal to 0 and less than or equal to the size AL3 of the active layer A3 of the third control transistor T3 in the second direction X or the size AL4 of the active layer A4 of the fourth control transistor T4 in the second direction X, that is, 0≤|D3-D4|≤AL3 or 0≤|D3-D4|≤AL4. For example, AL4 is the length of the active layer A4 of the fourth control transistor T4 in the second direction X. Therefore, the active layer A2 of the second control transistor T2, the active layer A3 of the third control transistor T3 and the active layer A4 of the fourth control transistor T4 are arranged in sequence from top to bottom in the first direction Y, thereby further optimizing the layout structure of the second control transistor T2, the third control transistor T3 and the fourth control transistor T4 in the display substrate, and reducing the size of the shift register unit 105 in the second direction X to a certain extent.

[0169] For example, Figure 2A , Figure 4 and Figure 7 As shown, the display substrate also includes a fifth switching electrode 150 and a second connecting wire L2. The fifth switching electrode 150 extends along the second direction X, and the first end 151 of the fifth switching electrode 150 is connected to the second electrode of the third control transistor T3, preferably, for example, formed in an integrated manner, and the second end 152 of the fifth switching electrode 150 is connected to the first electrode of the fourth control transistor T4, preferably, for example, formed in an integrated manner. The first end L21 of the second connecting wire L2 is connected to the fifth switching electrode 150 through a via hole penetrating the second insulating layer 360 and the third insulating layer 370, and the second end L22 of the second connecting wire L2 is connected to the gate G8 of the output control transistor T8. The second connecting wire L2 can be formed in an integrated manner with the gate G8 of the output control transistor T8 to simplify the manufacturing process of the display substrate. The second electrode of the fourth control transistor T4 is connected to the first power line switching electrode 180, preferably, for example, formed in an integrated manner to receive the first voltage.

[0170] For example, Figure 2A and Figure 3AAs shown, the active layer A6 of the input transistor T6 and the active layer A5 of the fifth control transistor T5 extend along the first direction Y and are arranged side by side in the second direction X, respectively, so as to reduce the size occupied by the active layer A6 of the input transistor T6 and the active layer A5 of the fifth control transistor T5 in the second direction X. The orthographic projection of the active layer A6 of the input transistor T6 on the substrate 10 and the orthographic projection of the active layer A5 of the fifth control transistor T5 on the substrate 10 are located on the side of the orthographic projection of the active layer A4 of the fourth control transistor T4 on the substrate 10 away from the orthographic projection of the active layer A3 of the third control transistor T3 on the substrate 10. That is, the active layer A6 of the input transistor T6 and the active layer A5 of the fifth control transistor T5 are located below the active layer A4 of the fourth control transistor T4 in the first direction Y.

[0171] For example, combined with Figure 2A , Figure 2B and Figure 3A As shown, the minimum distance between the positive projection of the active layer A6 of the input transistor T6 on the substrate 10 and the positive projection of the first clock signal line ECK and the second clock signal line ECB on the substrate 10 in the second direction X is the fifth distance D5. For example, the fifth distance D5 is the distance between the positive projection of the active layer A6 of the input transistor T6 on the substrate 10 and the edge of the first clock signal line ECK on the side close to the display area 102 in the second direction X. The difference between the fourth distance D4 and the fifth distance D5 is greater than or equal to 0 and less than or equal to 1.5 times the size of the active layer A4 of the fourth control transistor T4 in the second direction X, that is, 0≤|D4-D5|≤1.5AL4. Thus, the layout setting of the input transistor T6 in the first direction Y and the second direction X is further optimized.

[0172] For example, combined with Figure 2A , Figure 2B and Figure 3AAs shown, the minimum distance between the orthographic projection of the active layer A6 of the input transistor T6 on the substrate 10 and the orthographic projection of the active layer A4 of the fourth control transistor T4 on the substrate 10 in the first direction Y is the sixth distance D6, and the minimum distance between the orthographic projection of the active layer A5 of the fifth control transistor T5 on the substrate 10 and the active layer A4 of the fourth control transistor T4 on the substrate 10 in the first direction Y is the seventh distance D7. The difference between the sixth distance D6 and the seventh distance D7 is greater than or equal to 0 and less than or equal to the size AL6 of the active layer A6 of the input transistor T6 in the first direction Y or the size AL5 of the active layer A5 of the fifth control transistor T5 in the first direction Y, that is, 0≤|D6-D7|≤AL5 or 0≤|D6-D7|≤AL6. For example, AL5 is the length of the active layer A5 of the fifth control transistor T5 in the first direction Y, and AL6 is the length of the active layer A6 of the input transistor T6 in the first direction Y. Thus, the layout of the fifth control transistor T5 and the input transistor T6 in the first direction Y is further optimized.

[0173] For example, in some other embodiments of the present disclosure, Figure 3B As shown, the active layer A6 of the input transistor T6 and the active layer A5 of the fifth control transistor T5 may also extend along the second direction X and be arranged side by side in the first direction Y, respectively, so that the active layer A1 of the first control transistor T1, the active layer A2 of the second control transistor T2, the active layer A3 of the third control transistor T3, the active layer A4 of the fourth control transistor T4, the active layer A6 of the input transistor T6 and the active layer A5 of the fifth control transistor T5 in the shift register unit 105 all extend along the second direction X and are arranged in sequence in the first direction Y, respectively, thereby simplifying the preparation process of the display substrate, for example, simplifying the preparation process of the active layer of the display substrate and reducing the preparation cost.

[0174] For example, in the case where the active layer A6 of the input transistor T6 and the active layer A5 of the fifth control transistor T5 extend along the second direction X respectively, the active layer A6 of the input transistor T6 may be as follows: Figure 3BAs shown, it is located above the active layer A5 of the fifth control transistor T5, that is, the orthogonal projection of the active layer A5 of the fifth control transistor T5 on the substrate substrate 10 is located on the side of the orthogonal projection of the active layer A6 of the input transistor T6 on the substrate substrate 10, which is away from the orthogonal projection of the active layer A4 of the fourth control transistor T4 on the substrate substrate 10; alternatively, the active layer A6 of the input transistor T6 may also be located below the active layer A5 of the fifth control transistor T5, that is, the orthogonal projection of the active layer A5 of the fifth control transistor T5 on the substrate substrate 10 is located on the side of the orthogonal projection of the active layer A6 of the input transistor T6 on the substrate substrate 10, which is close to the orthogonal projection of the active layer A4 of the fourth control transistor T4 on the substrate substrate 10, and the embodiments of the present disclosure are not limited to this.

[0175] For example, Figure 2A , Figure 4 and Figure 7 As shown, the display substrate further includes a sixth transfer electrode 160, a seventh transfer electrode 170, a third connection line L3 and a fourth connection line L4. The first electrode of the input transistor T6 is connected to the first end 161 of the sixth transfer electrode 160, preferably, for example, formed in an integrated manner, and the second electrode of the input transistor T6 is connected to the second transfer electrode 120, preferably, for example, formed in an integrated manner. The third connection line L3 extends along the second direction X, and the first end L31 of the third connection line L3 is connected to the first clock signal line ECK through a via penetrating the second insulating layer 360 and the third insulating layer 370 to receive the first clock signal provided by the first clock signal line ECK. The second end L32 of the third connection line L3 is connected to the gate G6 of the input transistor T6 to transmit the first clock signal. The third connection line L3 is formed in an integrated manner with the gate G6 of the input transistor T6, thereby simplifying the preparation process of the display substrate and reducing the preparation cost. The gate G5 of the fifth control transistor T5 is connected to the second power line switching electrode 190 through a via hole penetrating the second insulating layer 360 and the third insulating layer 370 to receive the second voltage. The first electrode of the fifth control transistor T5 is connected to the second end 162 of the sixth switching electrode 160, preferably, for example, formed in an integrated manner, the second electrode of the fifth control transistor T5 is connected to the first end 171 of the seventh switching electrode 170, preferably, for example, formed in an integrated manner, the second end 172 of the seventh switching electrode 170 is connected to the first end L41 of the fourth connection line L4 through a via hole penetrating the second insulating layer 360 and the third insulating layer 370, and the second end L42 of the fourth connection line L4 is connected to the gate G7 of the output transistor T7. For example, the fourth connection line L4 can be formed in an integrated manner with the gate G7 of the output transistor T7 to simplify the manufacturing process.

[0176] For example, Figure 7As shown, the sixth switching electrode 160 extends along the second direction X, thereby optimizing the layout design between the first electrode of the fifth control transistor T5 and the first electrode of the input transistor T6 .

[0177] For example, in some embodiments of the present disclosure, the display substrate further includes a gate drive circuit (not shown in the figure). The gate drive circuit includes a plurality of cascaded shift register units. For example, the gate drive circuit is the reset control drive circuit array described above, which includes a plurality of cascaded shift register units 105, so that the reset control signal can be output row by row.

[0178] For example, the trigger signal line ESTV is configured to provide a trigger signal to the gate drive circuit, and the positive projection of the trigger signal line ESTV on the substrate substrate 10 is located on the side away from the positive projection of the first clock signal line ECK on the substrate substrate 10 and the positive projection of the second clock signal line ECB on the substrate substrate 10. The display area 102, that is, in the second direction X, the trigger signal line ESTV is located on the left side of the first clock signal line ECK and the second clock signal line ECB. The trigger signal line ESTV is connected to the input circuit of the first-stage shift register unit of the gate drive circuit to provide a trigger signal as an input signal of the first-stage shift register unit. For a specific introduction, please refer to the previous description, which will not be repeated here.

[0179] For example, in some embodiments of the present disclosure, the line width of each layer of wiring is generally 3 microns, and the spacing between wirings on the same layer is, for example, greater than 3 microns. For example, the wiring spacing is related to the accuracy of the exposure machine. The higher the accuracy of the exposure machine, the smaller the spacing can be. The specific spacing can be determined according to actual conditions, and the embodiments of the present disclosure are not limited to this. In the embodiments of the present disclosure, necessary spacing must be left between wirings on the same layer to avoid wiring adhesion, signal short circuit, etc. in actual processes.

[0180] The spacing between the orthographic projections of each wiring of the first conductive layer 320 on the substrate 10 and the orthographic projections of each wiring of the second conductive layer 330 on the substrate 10 is generally 1.5 microns, for example, the gate of the transistor in the first conductive layer 320 should extend beyond its active layer on the semiconductor layer 310 by more than 2 microns. Figure 2A , Figure 3A and Figure 4 As shown, the "U"-shaped double gate of the first control transistor T1 exceeds the active layer of the first control transistor T1 on both sides of the active layer of the first control transistor T1 in the first direction Y, for example, by more than 2 microns. For example, the length of the portion that does not overlap with the active layer of the first control transistor T1 in the first direction Y is more than 2 microns, and the embodiments of the present disclosure are not limited to this.

[0181] For example, the spacing between the orthographic projection of the active layer of each transistor on the semiconductor layer 310 on the substrate 10 and the orthographic projection of each gate wiring on the first conductive layer 320 on the substrate 10 is more than 1.5 microns, so as to avoid the generation of a channel effect between the gate wiring and the active layer of each transistor on the semiconductor layer 310. For example, the spacing between the orthographic projection of the semiconductor layer 310 on the substrate 10 and the orthographic projection of the second conductive layer 330 on the substrate 10 can be unlimited, for example, they can be overlapped. For example, in some embodiments of the present disclosure, a certain spacing is maintained between wirings of different layers as much as possible (this spacing is smaller than the spacing between wirings of the same layer), thereby reducing unnecessary overlaps to reduce or avoid crosstalk caused by excessive parasitic capacitance.

[0182] For example, the width of each routing line of the third conductive layer 340 should cover (e.g., completely cover) the corresponding via hole, for example, it can exceed the size of the via hole (e.g., the diameter of the via hole) by more than 1 micron, for example, the size of the via hole is 2.0 microns to 2.5 microns, and the width of each routing line of the third conductive layer 340 covering the via hole is 4 microns to 5 microns. For example, the width of the routing line corresponding to the output transistor T7 and the output control transistor T8 that exceeds the via hole by 1 micron, for example, 4.0 microns to 4.5 microns. Because there are more via holes corresponding to the output transistor T7 and the output control transistor T8, the width of the routing line located in the third conductive layer 340 that connects other transistors only needs to meet the requirement of covering the via hole by more than 1 micron at the via hole position, for example, the routing width between the via holes can be relatively narrow.

[0183] For example, the spacing between the first clock signal line ECK, the second clock signal line ECB, the first power line VGH, the second power line VGL and the like located in the third conductive layer 340 is more than 3 microns, the line width of the first clock signal line ECK and the second clock signal line ECB is set to be more than 9 microns to meet the driving capability requirements, and the line width of the first power line VGH and the second power line VGL can be, for example, 6 microns, 9 microns or 10 microns, etc. The second voltage provided by the second power line VGL can be, for example, -7V.

[0184] For example, in some examples, the thickness of the first conductive layer 320 and the second conductive layer 330 is 2000 angstroms to 3000 angstroms, and the thickness of the third conductive layer 340 is 5000 angstroms to 8000 angstroms, which is not limited in the embodiments of the present disclosure.

[0185] For example, by providing the above-mentioned transfer electrodes, connecting wires, electrode connecting wires, etc., the problems of wire adhesion, signal short circuit, etc. caused by dense wires on the same layer can be reduced or avoided. For example, the above-mentioned transfer electrodes, connecting wires, electrode connecting wires, etc. can play the role of connection or jumper connection.

[0186] The display substrate provided in the above-mentioned embodiments of the present disclosure optimizes the line connection and structural layout of the shift register unit, compresses the size of the shift register unit in the second direction to a certain extent, and reduces the space required to be occupied by the shift register unit in the peripheral area of ​​the display substrate, which is conducive to using the display substrate to achieve a narrow frame design, while ensuring the display quality achieved by using the display substrate.

[0187] At least one embodiment of the present disclosure further provides a display device. Fig. 9 Schematic diagram of a display device provided by at least one embodiment of the present disclosure. Fig. 9 As shown, the display device 2 includes a display substrate 1, and the display substrate 1 can be a display substrate provided by any embodiment of the present disclosure, for example, the display substrate Figure 2A The display substrate shown in .

[0188] It should be noted that the display device 2 can be any product or component with a display function, such as an OLED panel, an OLED TV, a QLED panel, a QLED TV, a mobile phone, a tablet computer, a laptop computer, a digital photo frame, a navigator, etc. The display device 2 can also include other components, such as a data drive circuit, a timing controller, etc., which are not limited in the embodiments of the present disclosure.

[0189] It should be noted that, for the sake of clarity and simplicity, the embodiments of the present disclosure do not provide all the components of the display device 2. To achieve the basic functions of the display device 2, those skilled in the art can provide and set other structures not shown according to specific needs, and the embodiments of the present disclosure are not limited to this.

[0190] The technical effects of the display device 2 provided in the above embodiment can refer to the display substrate provided in the embodiment of the present disclosure (for example, the above Figure 2A The technical effects of the display substrate shown in FIG. 1 are not described in detail here.

[0191] At least one embodiment of the present disclosure further provides a method for manufacturing a display substrate, such as the method for manufacturing a display substrate provided by any embodiment of the present disclosure. Fig.10 A flowchart of a method for manufacturing a display substrate provided in at least one embodiment of the present disclosure. For example, the method can be used to manufacture a display substrate provided in any embodiment of the present disclosure, for example, it can be used to manufacture the above-mentioned Figure 2A The display substrate shown in .

[0192] like Fig.10 As shown, the manufacturing method of the display substrate includes the following steps S10 to S20.

[0193] Step S10: providing a substrate.

[0194] Step S20: forming a shift register unit, a first power line for providing a first voltage, a second power line for providing a second voltage, a first clock signal line, and a second clock signal line on a base substrate.

[0195] For example, forming a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, and a third conductive layer respectively includes forming corresponding material layers (e.g., semiconductor material layers, insulating material layers, or conductive material layers), and then using a patterning process to form corresponding pattern structures (e.g., active layers, electrode patterns, traces, vias, etc.). The patterning process is, for example, a photolithography process, for example, including: coating a photoresist layer on the material layer to be patterned, exposing the photoresist layer using a mask, developing the exposed photoresist layer to obtain a photoresist pattern, etching the structural layer using the photoresist pattern, and then optionally removing the photoresist pattern.

[0196] For example, to make the above Figure 2A Taking the display substrate shown in as an example, for step S10, the base substrate 10 can be made of, for example, glass, plastic, quartz or other suitable materials, which is not limited in the embodiments of the present disclosure.

[0197] For example, the shift register unit 105 , a first power line VGH, a second power line VGL, a first clock signal line ECK, and a second clock signal line ECB are formed on the base substrate 10 .

[0198] For step S20, for example, forming the shift register unit 105 includes: sequentially forming a semiconductor layer 310, a first insulating layer 350, a first conductive layer 320, a second insulating layer 360, a second conductive layer 330, a third insulating layer 370, and a third conductive layer 340 in a direction perpendicular to the base substrate 10. The active layer of each transistor is located in the semiconductor layer 310, the gate of each transistor and the first electrode of each capacitor are located in the first conductive layer 320, the second electrode of each capacitor is located in the second conductive layer 330, and the first power line VGH, the second power line VGL, the first clock signal line ECK, the second clock signal line ECB, and the first electrode and the second electrode of each transistor are located in the third conductive layer 340.

[0199] For example, the transistors and capacitors are connected to each other and to the first power line VGH, the second power line VGL, the first clock signal line ECK and the second clock signal line ECB through vias penetrating the first insulating layer 350, the second insulating layer 360 or the third insulating layer 370.

[0200] For the configuration of each transistor and capacitor of the shift register unit 105 and the first power line VGH, the second power line VGL, a plurality of clock signal lines, and each connection structure, please refer to the relevant Figure 2A-Figure 8The corresponding description in the illustrated embodiment will not be repeated here.

[0201] It should be noted that in multiple embodiments of the present disclosure, the process of the method for manufacturing the display substrate may include more or fewer operations, and these operations may be performed sequentially or in parallel. Although the process of the manufacturing method described above includes multiple operations that appear in a specific order, it should be clearly understood that the order of the multiple operations is not limited. The manufacturing method described above can be performed once or multiple times according to predetermined conditions.

[0202] The technical effects of the method for manufacturing the display substrate provided in the above embodiment can be referred to the display substrate provided in the embodiment of the present disclosure (for example, the above Figure 2A The technical effects of the display substrate shown in FIG. 1 are not described in detail here.

[0203] There are a few points to note:

[0204] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0205] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0206] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A display substrate, comprising: A base substrate, comprising a display area and a peripheral area located on at least one side of the display area; as well as A shift register unit, a first clock signal line and a second clock signal line are arranged on the peripheral area of ​​the base substrate, The first clock signal line and the second clock signal line extend along a first direction on the substrate, and the first clock signal line and the second clock signal line are configured to provide a first clock signal or a second clock signal to the shift register unit, respectively; The shift register unit includes a first control transistor, a second control transistor and a third control transistor. The active layer of the first control transistor, the active layer of the second control transistor, and the active layer of the third control transistor extend respectively along a second direction different from the first direction, The orthographic projection of the active layer of the first control transistor on the substrate, the orthographic projection of the active layer of the second control transistor on the substrate, and the orthographic projection of the active layer of the third control transistor on the substrate are located on a side of the orthographic projections of the first clock signal line and the second clock signal line on the substrate close to the display area, The minimum distance in the second direction between the orthographic projection of the active layer of the first control transistor on the substrate and the orthographic projections of the first clock signal line and the second clock signal line on the substrate is a first distance, The minimum distance in the second direction between the orthographic projection of the active layer of the second control transistor on the substrate and the orthographic projections of the first clock signal line and the second clock signal line on the substrate is a second distance, The minimum distance between the orthographic projection of the active layer of the third control transistor on the substrate and the orthographic projections of the first clock signal line and the second clock signal line on the substrate in the second direction is a third distance, The difference between the first distance and the second distance is greater than or equal to 0 and less than or equal to the size of the active layer of the first control transistor in the second direction or the size of the active layer of the second control transistor in the second direction, The difference between the first distance and the third distance is greater than or equal to 0 and less than or equal to twice the size of the active layer of the first control transistor in the second direction or twice the size of the active layer of the third control transistor in the second direction, A difference between the second distance and the third distance is greater than or equal to 0 and less than or equal to twice the size of the active layer of the second control transistor in the second direction or twice the size of the active layer of the third control transistor in the second direction.

2. The display substrate according to claim 1, wherein: The first distance ranges from 40 μm to 55 μm, and the second distance ranges from 40 μm to 55 μm.

3. The display substrate according to claim 2, wherein: The first distance is 40 μm, 42 μm, 44 μm, 45 μm or 50 μm, The second distance is 40 μm, 42 μm, 44 μm, 45 μm or 50 μm.

4. The display substrate according to any one of claims 1 to 3, wherein: The gate of the first control transistor, the gate of the second control transistor, and the gate of the third control transistor are parallel to each other in the first direction.

5. The display substrate according to claim 4, wherein: The gate of the first control transistor includes a main portion extending along the second direction and two sub-gates extending from the main portion of the gate of the first control transistor and parallel to each other. The gate of the second control transistor includes a main portion extending along the second direction and two sub-gates extending from the main portion of the gate of the second control transistor and parallel to each other.

6. The display substrate according to any one of claims 1 to 3, wherein: The orthographic projection of the active layer of the third control transistor on the substrate is located on a side of the orthographic projection of the active layer of the second control transistor on the substrate away from the orthographic projection of the active layer of the first control transistor on the substrate.

7. The display substrate according to claim 6, wherein: The shift register unit includes an input circuit, a first node control circuit, a second node control circuit, a second node noise reduction circuit, a third node control circuit, an output control circuit and an output circuit; The first node control circuit is configured to input a first voltage to the first node under the control of an input signal and the second clock signal; The second node control circuit is configured to input the first clock signal to the second node in response to the level of the first node; The output control circuit is configured to output the first voltage to the output terminal of the shift register unit in response to the level of the second node; the input circuit being configured to input an input signal to a fourth node in response to the first clock signal; The second node noise reduction circuit is configured to input the first voltage to the second node in response to the level of the fourth node to reduce noise on the second node; The third node control circuit is configured to control the level of the third node under the control of the second voltage; the output circuit is configured to output the second voltage to the output terminal in response to the level of the third node, The first node control circuit includes the first control transistor and the second control transistor, and the second node control circuit includes the third control transistor.

8. The display substrate according to claim 7, further comprising a first connecting wire, in, The first connecting wire extends along the second direction, and the orthographic projection of the first connecting wire on the substrate is located on a side of the orthographic projection of the gate of the second control transistor on the substrate away from the display area. A first end of the first connecting wire is connected to the gate of the second control transistor, and a second end of the first connecting wire is connected to the second clock signal line through a via hole penetrating the insulating layer. The first connecting wire is formed integrally with the gate of the second control transistor.

9. The display substrate according to claim 7, further comprising a first switching electrode, in, The first switching electrode includes a first sub-portion extending along the first direction, A first end of the first sub-portion of the first switching electrode is connected to the second electrode of the first control transistor, and a second end of the first sub-portion of the first switching electrode is connected to the second electrode of the second control transistor.

10. The display substrate according to claim 9, further comprising a first power line for providing the first voltage and a first power line switching electrode, in, The first power line extends along the first direction, and the orthographic projection of the first power line on the base substrate is located on a side of the orthographic projection of the active layer of the first control transistor on the base substrate and the orthographic projection of the active layer of the second control transistor on the base substrate close to the display area. The first power line transfer electrode is connected to the first power line and is formed integrally, The first electrode of the first control transistor and the first electrode of the second control transistor are respectively connected to the first power line through the first power line switching electrode.

11. The display substrate according to claim 10, wherein: a ratio between a width of the first power line in the second direction and a width of the first clock signal line in the second direction is greater than or equal to 1.2 and less than or equal to 3, A ratio between a width of the first power line in the second direction and a width of the second clock signal line in the second direction is greater than or equal to 1.2 and less than or equal to 3.

12. The display substrate according to claim 10, further comprising a second switching electrode, in, The orthographic projection of the second switching electrode on the base substrate is located on a side away from the display area where the orthographic projection of the active layer of the first control transistor on the base substrate and the orthographic projection of the active layer of the second control transistor on the base substrate are located. The second transfer electrode extends along the first direction and is connected to the gate of the first control transistor through a via hole penetrating the insulating layer. The second switching electrode is connected to a trigger signal line or an output end of a previous-stage shift register unit to receive the input signal.

13. The display substrate according to claim 12, wherein: The output circuit includes an output transistor, the output control circuit includes an output control transistor, Among them, the orthographic projection of the active layer of the output transistor on the substrate and the orthographic projection of the active layer of the output control transistor on the substrate are located on a side where the orthographic projection of the active layer of the first control transistor on the substrate and the orthographic projection of the active layer of the second control transistor on the substrate are close to the display area, and are located on a side where the orthographic projection of the first power line on the substrate is away from the display area.

14. The display substrate according to claim 13, further comprising at least one common semiconductor pattern, in, The active layer of the output transistor and the active layer of the output control transistor are respectively different portions of the at least one common semiconductor pattern.

15. The display substrate according to claim 14, wherein: The at least one common semiconductor pattern includes a plurality of common semiconductor patterns that are spaced apart from each other and disposed in parallel in the second direction.

16. The display substrate according to claim 13, wherein: The gate of the output transistor includes a plurality of sub-gates connected in parallel, and the plurality of sub-gates of the output transistor are parallel to each other in the first direction. The gate of the output control transistor includes a plurality of sub-gates connected in parallel, and the plurality of sub-gates of the output control transistor are parallel to each other in the first direction.

17. The display substrate according to claim 13, further comprising a second power line for providing the second voltage, a second power line switching electrode and a third switching electrode, in, The second power line extends along the first direction, and the orthographic projection of the second power line on the base substrate is located on a side away from the display area where the orthographic projection of the active layer of the first control transistor on the base substrate and the orthographic projection of the active layer of the second control transistor on the base substrate are located. The second power line transfer electrode is connected to the second power line and is formed integrally. The first electrode of the output transistor is connected to the second power line through the second power line switching electrode, and the second electrode of the output transistor is connected to the third switching electrode. The first electrode of the output control transistor is connected to the first power line through the first power line switching electrode, and the second electrode of the output control transistor is connected to the third switching electrode. The output end includes the third switching electrode.

18. The display substrate according to claim 17, wherein: a ratio between a width of the second power line in the second direction and a width of the first clock signal line in the second direction is greater than or equal to 1.2 and less than or equal to 3, A ratio between a width of the second power line in the second direction and a width of the second clock signal line in the second direction is greater than or equal to 1.2 and less than or equal to 3.

19. The display substrate according to claim 17, wherein: The orthographic projection of the second power line on the base substrate is located on a side of the orthographic projections of the first clock signal line and the second clock signal line on the base substrate close to the display area.

20. The display substrate according to claim 17, wherein: The output circuit further includes a first capacitor, and the output control circuit further includes a second capacitor. The orthographic projection of the first capacitor on the substrate is located between the orthographic projection of the active layer of the output transistor on the substrate and the orthographic projection of the first power line on the substrate, and is arranged side by side with the orthographic projection of the active layer of the output transistor on the substrate in the second direction. The orthographic projection of the second capacitor on the substrate is located between the orthographic projection of the active layer of the output control transistor on the substrate and the orthographic projection of the first power line on the substrate, and is arranged side by side with the orthographic projection of the active layer of the output control transistor on the substrate in the second direction. The orthographic projection of the first capacitor on the substrate and the orthographic projection of the second capacitor on the substrate are arranged side by side in the first direction.

21. The display substrate according to claim 20, wherein: The first electrode of the first capacitor is connected to the gate of the output transistor and is formed integrally, and the second electrode of the first capacitor is connected to the third switching electrode through a via hole penetrating the insulating layer. The first electrode of the second capacitor is connected to the gate of the output control transistor and is formed integrally, and the second electrode of the second capacitor is connected to the first power line through a via hole penetrating the insulating layer.

22. The display substrate according to claim 17, wherein: The second node control circuit further includes a third capacitor, The orthographic projection of the third capacitor on the substrate is located between the orthographic projection of the active layer of the third control transistor on the substrate and the orthographic projection of the active layer of the second control transistor on the substrate in the first direction.

23. The display substrate according to claim 22, further comprising an electrode connection wiring and a fourth transfer electrode, in, The first switching electrode further includes a second sub-portion extending along the second direction, and an end of the second sub-portion of the first switching electrode is connected to the first electrode of the third capacitor through a via hole penetrating the insulating layer. The first electrode of the third capacitor is connected to the gate of the third control transistor and is formed as an integral whole, and the second electrode of the third capacitor is connected to the electrode connection wiring and is formed as an integral whole, The electrode connection line extends along the second direction, a first end of the electrode connection line is connected to the first clock signal line through a via hole penetrating the insulating layer, and a second end of the electrode connection line is connected to the second electrode of the third capacitor. The fourth switching electrode extends along the first direction, the first end of the fourth switching electrode is connected to the second end of the electrode connecting wire through a via hole penetrating the insulating layer, and the second end of the fourth switching electrode is connected to the first electrode of the third control transistor.

24. The display substrate according to claim 17, wherein: The second node noise reduction circuit includes a fourth control transistor, The active layer of the fourth control transistor extends along the second direction, The orthographic projection of the active layer of the fourth control transistor on the substrate is located on a side of the orthographic projection of the active layer of the third control transistor on the substrate away from the orthographic projection of the active layer of the second control transistor on the substrate in the first direction.

25. The display substrate according to claim 24, wherein: The minimum distance between the orthographic projection of the active layer of the fourth control transistor on the substrate and the orthographic projections of the first clock signal line and the second clock signal line on the substrate in the second direction is a fourth distance, A difference between the third distance and the fourth distance is greater than or equal to 0 and less than or equal to a size of an active layer of the third control transistor in the second direction or a size of an active layer of the fourth control transistor in the second direction.

26. The display substrate according to claim 25, further comprising a fifth transfer electrode and a second connecting wire, in, The fifth switching electrode extends along the second direction, the first end of the fifth switching electrode is connected to the second electrode of the third control transistor, and the second end of the fifth switching electrode is connected to the first electrode of the fourth control transistor. A first end of the second connecting wire is connected to the fifth transfer electrode through a via hole penetrating the insulating layer, and a second end of the second connecting wire is connected to the gate of the output control transistor. The second connecting wire is formed integrally with the gate of the output control transistor, The second electrode of the fourth control transistor is connected to the first power line switching electrode.

27. The display substrate according to claim 25, wherein: The input circuit includes an input transistor, the third node control circuit includes a fifth control transistor, The active layer of the input transistor and the active layer of the fifth control transistor extend along the first direction respectively and are arranged side by side in the second direction, The orthographic projection of the active layer of the input transistor on the substrate and the orthographic projection of the active layer of the fifth control transistor on the substrate are located on a side of the orthographic projection of the active layer of the fourth control transistor on the substrate away from the orthographic projection of the active layer of the third control transistor on the substrate.

28. The display substrate according to claim 27, wherein: The minimum distance between the orthographic projection of the active layer of the input transistor on the substrate and the orthographic projections of the first clock signal line and the second clock signal line on the substrate in the second direction is a fifth distance, A difference between the fourth distance and the fifth distance is greater than or equal to 0 and less than or equal to 1.5 times a size of an active layer of the fourth control transistor in the second direction.

29. The display substrate according to claim 27, wherein: The minimum distance between the orthographic projection of the active layer of the input transistor on the substrate and the orthographic projection of the active layer of the fourth control transistor on the substrate in the first direction is a sixth distance, The minimum distance between the orthographic projection of the active layer of the fifth control transistor on the substrate and the orthographic projection of the active layer of the fourth control transistor on the substrate in the first direction is a seventh distance, A difference between the sixth distance and the seventh distance is greater than or equal to 0 and less than or equal to a size of an active layer of the input transistor in the first direction or a size of an active layer of the fifth control transistor in the first direction.

30. The display substrate according to claim 27, further comprising a third connecting wire, a fourth connecting wire, a sixth switching electrode and a seventh switching electrode, in, The first electrode of the input transistor is connected to the first end of the sixth switching electrode, and the second electrode of the input transistor is connected to the second switching electrode. The third connecting wire extends along the second direction, a first end of the third connecting wire is connected to the first clock signal wire through a via hole penetrating the insulating layer, and a second end of the third connecting wire is connected to the gate of the input transistor. The third connecting wire is formed integrally with the gate of the input transistor, The gate of the fifth control transistor is connected to the second power line switching electrode through a via hole penetrating the insulating layer, the first electrode of the fifth control transistor is connected to the second end of the sixth switching electrode, and the second electrode of the fifth control transistor is connected to the first end of the seventh switching electrode. The second end of the seventh transfer electrode is connected to the first end of the fourth connection line through a via hole penetrating the insulating layer, the second end of the fourth connection line is connected to the gate of the output transistor, and the fourth connection line is integrated with the gate of the output transistor.

31. The display substrate according to claim 30, wherein: The sixth switching electrode extends along the second direction.

32. The display substrate according to any one of claims 1 to 3, further comprising a trigger signal line and a gate drive circuit, in, The gate driving circuit includes a plurality of cascaded shift register units. The trigger signal line is configured to provide a trigger signal to the gate drive circuit, The positive projection of the trigger signal line on the base substrate is located on a side away from the display area from the positive projection of the first clock signal line on the base substrate and the positive projection of the second clock signal line on the base substrate. The trigger signal line is connected to an input circuit of a first-stage shift register unit of the gate driving circuit to provide the trigger signal as an input signal of the first-stage shift register unit.

33. A display device comprising the display substrate according to claim 1.

34. The display device according to claim 33, wherein: The display device is an organic light emitting diode display device.

35. The display device according to claim 33 or 34, further comprising pixel units arranged in an array, in, An output signal output by an output circuit of a shift register unit of the display substrate is output to the pixel unit as a reset control signal.

36. A method for manufacturing a display substrate as claimed in claim 1, comprising: providing the substrate, and The shift register unit, a first power line providing a first voltage, a second power line providing a second voltage, the first clock signal line, and the second clock signal line are formed on the substrate, wherein forming the shift register unit includes: A semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer and a third conductive layer are sequentially formed in a direction perpendicular to the substrate, wherein the active layer of each transistor is located in the semiconductor layer, the gate of each transistor and the first electrode of each capacitor are located in the first conductive layer, the second electrode of each capacitor is located in the second conductive layer, and the first power line, the second power line, the first clock signal line, the second clock signal line and the first electrode and the second electrode of each transistor are located in the third conductive layer; The transistors and the capacitors are connected to each other and to the first power line, the second power line, the first clock signal line and the second clock signal line through vias penetrating the first insulating layer, the second insulating layer or the third insulating layer.

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