Fan fault detection method, device, computer equipment and storage medium

Abstract

The present application belongs to the field of fans and relates to a fan fault detection method, device, computer equipment and storage medium. The method includes the following steps: configuring the fan type and speed fault threshold; calculating the fan fault signal frequency and processing the fan feedback signal flip flag based on the configuration of the fan type and speed fault threshold; adaptively adjusting the cycle time of a single fan based on the fan fault signal frequency and the fan feedback signal flip flag; determining the current fan order based on the actual cycle time of the single fan by counting through a DSP time base counter; determining the fan type of the currently determined fan based on the fan order and the fan type configured during initialization, and determining the fan fault. By using a multiplexing switch and one isolation device to detect fan faults, the detection circuit is simple and can detect multiple sets of fan fault feedback signals simultaneously, reducing costs; generating a control signal through self-excited oscillation, it is convenient for fans with different fault feedback signals to be compatible.

Description

Technical Field

[0001] The present application relates to the field of fan technology, and in particular to a fan fault detection method, device, computer equipment, and storage medium. Background Art

[0002] Fans are used in air-cooling equipment to transfer heat to the outside world. DC fans are widely used because they are easy to adjust and control. Fan fault detection can be detected by detecting the fan's fault output signal: a level output or a square wave output. Some fans do not have a fault output signal, requiring fan current monitoring or wind speed sensors. Currently, there are two types of detection methods: isolated and non-isolated. Isolated detection sends the fault signal to the control system via an isolation device; non-isolated detection sends the fault signal directly to the control system. Currently, most fans require more detailed fault detection: stalls, abnormal speeds, and locating the faulty fan to facilitate maintenance. Current isolated detection circuits are simple for detecting a single fan, but for multiple fans, multiple separate power supplies and isolation detection devices are required, resulting in high detection costs and consuming significant control resources. Current non-isolated detection circuits require each fan circuit to be directly connected to the control system. Some fans can generate significant interference, affecting detection accuracy and disrupting the control system. Furthermore, fan failures can easily cause the control system to crash. Summary of the Invention

[0003] The purpose of the embodiments of the present application is to propose a fan fault detection method, device, computer equipment and storage medium to solve the problem that the current isolated detection circuit requires multiple sets of separate power supplies and isolation detection devices for multi-fan working conditions, and the detection cost is relatively high.

[0004] In order to solve the above technical problems, the present application provides a fan fault detection method, which adopts the following technical solution and includes the following steps:

[0005] Configure fan type and speed fault threshold;

[0006] Calculate the fan fault signal frequency f and process the fan feedback signal reversal flag according to the fan type and speed fault threshold configuration;

[0007] Adapt the cycle time of a single fan based on the frequency of the fan fault signal and the flip flag of the fan feedback signal;

[0008] According to the actual cycle time of a single fan, the order of the current fans is determined by counting the DSP time-base counter;

[0009] Based on the fan order and the fan type configured during initialization, the fan type of the currently identified fan is determined to determine if the fan is faulty.

[0010] Furthermore, the step of configuring the fan type and speed fault threshold specifically includes:

[0011] Establish a mapping relationship between fan types and speed fault thresholds, with each fan type corresponding to a speed fault threshold.

[0012] Furthermore, the step of calculating the fan fault signal frequency and processing the fan feedback signal reversal flag according to the configuration of the fan type and the speed fault threshold specifically includes:

[0013] Calculate the frequency f of the fan feedback signal using the ECAP module of the DSP according to the fan type and the configuration of the speed fault threshold;

[0014] When CEVT is triggered, the time base counter CTR is cleared. When CEVT is not triggered, the time base counter CTR increases until the DSP switching frequency CPU_FRQ, and then starts counting from 0 again. According to this rule, the flag of whether the fan feedback signal is flipped is processed.

[0015] Furthermore, the adaptive adjustment of the cycle time of a single fan according to the fan fault signal frequency and the fan feedback signal flip flag specifically includes:

[0016] Based on the fan fault signal frequency and the fan feedback signal flip flag, the maximum number of connected fan groups is calculated, the cycle time of a single fan is adaptively adjusted, and the starting point of the cycle time of a single fan is determined;

[0017] Assume that the actual cycle of a single fan is T1, the design cycle of a single fan is T2, and the coefficient K is introduced. K is the degree of consistency between the actual cycle of a single fan feedback signal and the designed cycle.

[0018] Furthermore, assuming that the DSP switching frequency is CPU_FRQ, register CAP1 is set to capture the rising edge, register CAP2 is set to capture the falling edge, register CAP3 is set to capture the rising edge, and register CAP4 is set to capture the falling edge;

[0019] When event CEVT1, event CEVT2, event CEVT3, and event CEVT4 are triggered, the values of capture registers CAP1, CAP2, CAP3, and CAP4 are TS1, TS2, TS3, and TS4 respectively.

[0020] Furthermore, the step of determining the order of the current fans by counting the actual cycle time of a single fan through a DSP time base counter specifically includes:

[0021] Counting starts from the beginning of the fan feedback signal cycle;

[0022] The actual cycle count of a single fan is determined to be K*N according to the time base counter t and the cycle Ts, and the fan order is [t / (K*N)]+1;

[0023] The fan types are determined in the corresponding order according to the configuration information of the fan application.

[0024] In order to solve the above technical problems, the present application also provides a fan fault detection device, which adopts the following technical solutions, including:

[0025] Configuration module, used to configure fan type and speed fault threshold;

[0026] A calculation module, configured to calculate the fan fault signal frequency f and process the fan feedback signal reversal flag according to the fan type and the configuration of the speed fault threshold;

[0027] An adaptive module is used to adapt the cycle time of a single fan according to the frequency of the fan fault signal and the flip flag of the fan feedback signal;

[0028] The positioning module is used to determine the order of the current fans according to the actual cycle time of a single fan through counting by the DSP time base counter.

[0029] Furthermore, the calculation module includes an oscillator, a counter, a multiplexing switch, and an isolation device. The oscillator generates a clock reference signal through self-oscillation. The counter modulates the clock reference signal into a multi-bit binary signal. The multiplexing switch selects the fault detection signals of different fans according to the binary signal. The output signal of the multiplexing switch passes through the isolation device, and then calculates the fan fault signal frequency f and processes the fan feedback signal flip flag.

[0030] In order to solve the above technical problems, the present application also provides a computer device, which adopts the technical solution described below, including a memory and a processor, wherein the memory stores computer-readable instructions, and the processor implements the steps of the above-mentioned fan fault detection method when executing the computer-readable instructions.

[0031] In order to solve the above technical problems, the present application also provides a computer-readable storage medium, which adopts the technical solution described below. The computer-readable storage medium stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the steps of the above-mentioned fan fault detection method are implemented.

[0032] Compared with the existing technology, the present application has the following main beneficial effects: fan faults can be detected by using a multiplex switch using one isolation device, the detection circuit is simple, the number of isolation devices used is small, multiple groups of fan fault feedback signals can be detected at the same time, and the cost of isolation devices is reduced; the control signal is generated by self-excited oscillation, and there is no need for a control system to control the selection of the multiplex switch; level-type feedback signals and square wave-type feedback signals can be detected, which facilitates the compatibility of fans with different fault feedback signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the solutions in this application, a brief introduction will be given below to the drawings required for use in the description of the embodiments of this application. Obviously, the drawings described below are some embodiments of this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0034] Figure 1 is an exemplary system architecture diagram to which the present application may be applied;

[0035] Figure 2 is a flow chart of an embodiment of a fan fault detection method of the present application;

[0036] Figure 3 is a timing diagram of a fault signal received by the control system in the fan fault detection method of the present application;

[0037] Figure 4 This is a schematic diagram of a fan fault signal in the fan fault detection method of the present application;

[0038] Figure 5 Schematic diagram of fan feedback signal and fan feedback flip signal in the fan fault detection method of the present application;

[0039] Figure 6 This is a flow chart of determining the fan order according to the time base counter t in the fan fault detection method of the present application;

[0040] Figure 7 This is a flow chart of fan stall fault detection in the fan fault detection method of the present application;

[0041] Figure 8 This is a flow chart of fan speed fault detection in the fan fault detection method of the present application;

[0042] Figure 9 Schematic diagram of fan detection timing, normal detection signal, and fault detection signal in the fan fault detection method of this application;

[0043] Figure 10 1 is a schematic structural diagram of an embodiment of a fan fault detection device of the present application;

[0044] Figure 11 is a detection principle diagram of the fan fault detection device of the present application;

[0045] Figure 12 It is a structural diagram of an embodiment of a computer device of the present application. DETAILED DESCRIPTION

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by those skilled in the art to which this application belongs. The terms used in the specification of the application are for the purpose of describing specific embodiments only and are not intended to limit this application. The terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of this application or the above-mentioned drawings are used to distinguish different objects, not to describe a specific order.

[0047] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0048] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0049] like Figure 1 As shown, system architecture 100 may include a first terminal device 101, a second terminal device 102, a third terminal device 103, a network 104, and a server 105. Network 104 is a medium for providing a communication link between the first terminal device 101, the second terminal device 102, the third terminal device 103, and the server 105. Network 104 may include various connection types, such as wired or wireless communication links or fiber optic cables.

[0050] A user may use a first terminal device 101, a second terminal device 102, or a third terminal device 103 to interact with a server 105 via a network 104 to receive or send messages, etc. Various communication client applications may be installed on the first terminal device 101, the second terminal device 102, or the third terminal device 103, such as web browser applications, shopping applications, search applications, instant messaging tools, email clients, social platform software, etc.

[0051] The first terminal device 101, the second terminal device 102, and the third terminal device 103 can be various electronic devices with display screens and supporting web browsing, including but not limited to smart phones, tablet computers, e-book readers, MP3 players (Moving Picture Experts Group Audio Layer III, Moving Picture Experts Group Audio Layer 3), MP4 (Moving Picture Experts Group Audio Layer IV, Moving Picture Experts Group Audio Layer 4) players, laptop computers and desktop computers, etc.

[0052] The server 105 may be a server that provides various services, such as a background server that provides support for pages displayed on the first terminal device 101 , the second terminal device 102 , and the third terminal device 103 .

[0053] It should be noted that the fan fault detection method provided in the embodiment of the present application is generally executed by a server / terminal device, and accordingly, the fan fault detection device is generally set in the server / terminal device.

[0054] It should be understood that Figure 1 The number of terminal devices, networks and servers in the embodiment is merely illustrative. Any number of terminal devices, networks and servers may be provided as required.

[0055] Example 1

[0056] Continue to refer Figure 2 , shows a flow chart of an embodiment of a fan fault detection method of the present application. The fan fault detection method comprises the following steps:

[0057] Step S201: Configure the fan type and speed fault threshold.

[0058] In this embodiment, the fan fault detection method is executed on the electronic device (eg Figure 1 The server / terminal device shown in FIG. 1 may receive the fan fault detection request via a wired connection or a wireless connection. It should be noted that the wireless connection may include, but is not limited to, 3G / 4G / 5G connections, WiFi connections, Bluetooth connections, WiMAXX connections, Zigbee connections, UWB (ultra wideband) connections, and other currently known or future developed wireless connection methods.

[0059] The steps for configuring the fan type and speed fault threshold are as follows:

[0060] Establish a correspondence between fan types and speed fault thresholds, with each fan type corresponding to a speed fault threshold. To facilitate establishing the correspondence between fan types and speed fault thresholds, during implementation, a description of each fan type and speed fault threshold may also be established.

[0061]

[0062] For example, fan types A, B, C, D, and E have corresponding speed fault thresholds of \ (that is, empty), \, \, 0.8f1, and 0.8f2, respectively. f1 indicates frequency, and f2 indicates frequency. The corresponding descriptions are: no fan configured, the normal signal output is high, the abnormal signal is low, the normal signal output is low, the abnormal signal is high, the normal signal output is square wave, the frequency is f1, the abnormal signal is continuously high or low, the normal signal output is square wave, the frequency is f2, and the abnormal signal is continuously high or low.

[0063] Step S202 : Calculate the fan fault signal frequency f and process the fan feedback signal reversal flag according to the fan type and the configuration of the speed fault threshold.

[0064] In this embodiment, the step specifically includes:

[0065] Calculate the frequency of the fan feedback signal using the ECAP module of the DSP according to the fan type and the configuration of the speed fault threshold;

[0066] When the event CEVT is triggered, the time base counter CTR is cleared. When the frequency f of the fan feedback signal is less than 1, the time base counter CTR starts counting from 0 again. This rule is used to process the flag of whether the fan feedback signal is flipped.

[0067] Assume that the DSP switching frequency is CPU_FRQ, register CAP1 is set to capture rising edges, register CAP2 is set to capture falling edges, register CAP3 is set to capture rising edges, and register CAP4 is set to capture falling edges. When events CEVT1, CEVT2, CEVT3, and CEVT4 are triggered, the values of capture registers CAP1, CAP2, CAP3, and CAP4 are TS1, TS2, TS3, and TS4, respectively.

[0068] Figure 3This is a timing diagram of the fault signal received by the control system in the fan fault detection method of the present application. Control system. In this embodiment, the control system can be understood as a system for detecting fan fault logic with DSP as the processing core, including corresponding hardware peripheral circuits and software. The peripheral circuit includes a DSP minimum system, a power supply circuit, a communication circuit, etc. The GPIO pin of the DSP receives the fan fault signal and realizes the fault detection of the fan through logical processing. Figure 3 As shown, the horizontal axis is time t; t1, t2, ..., tn-1, tn, etc. represent the time of each fan cycle, and the serial numbers 1, 2, ..., n-1, n correspond to the serial numbers of the fans. For the signal received from the DSP, the vertical axis can be the voltage of the DSP GPIO pin, up to 3.3V, in which case the unit is V; it can also be logic high (1) or low (0), in which case there is no unit.

[0069] Figure 4 FIG. 1 is a schematic diagram of a fan fault signal in the fan fault detection method of the present application. Figure 4 As shown, the horizontal axis is time t. The vertical axis of the square wave in the figure is the signal received from the DSP. The vertical axis can be the voltage of the DSP GPIO pin, which is up to 3.3V, and the unit is V. It can also be said to be logic high (1) and low (0), and there is no unit at this time. The triangle wave in the figure represents the time base counter CTR of the ECAP module, so the vertical axis has no unit. According to the software configuration of the ECAP module, when the CAPx PIN level (that is, the fan fault signal) changes from low to high, from high to low, from low to high, and from high to low in sequence, it will trigger events CEVT1, event CEVT2, event CEVT3, and event CEVT4. When event CEVT1 is triggered, the time base counter CTR of the ECAP module will be assigned to register CAP1 and cleared. The operations of registers CAP2, CAP3, and CAP4 are the same as those of register CAP1. TS1, TS2, TS3, and TS4 are equal to the values of registers CAP1, register CAP2, register CAP3, and register CAP4, respectively. CPU_FRQ is the DSP main frequency and the maximum value of the ECAP module's time-base counter CTR. If it exceeds CPU_FRQ, the counter will restart from 0. When the total CTR count reaches CPU_FRQ, the time has elapsed for 1 second. TS2 + TS3 is the total counter value for one cycle. f = (CPU_FRQ) / (TS2 + TS3), which is the signal frequency in Hz.

[0070] Figure 5 FIG. 1 is a schematic diagram of the fan feedback signal and the fan feedback flip signal in the fan fault detection method of the present application. Figure 5 This is to illustrate the relationship between the fan feedback flip signal and the fan feedback signal. The fan feedback signal is the signal sent by the isolation device to the control system. Figure 5 As shown, the horizontal axis of the fan feedback signal is time t. The vertical axis of the square wave in the figure is the signal received from the DSP. The vertical axis can be the voltage of the DSP GPIO pin, which is up to 3.3V. The unit is V at this time; it can also be said to be logic high (1) and low (0), and there is no unit at this time. The fan feedback flip signal can be understood as whether the fan feedback signal flips within the cycle. If it flips, it is 0, and if it does not flip, it is 1. Whether there is a flip within a cycle can be judged based on the time base counter CTR of the ECAP module. When CTR is greater than a certain value (if it flips, it is set to 0), it can be considered that there is no flip. The vertical axis can be said to be logic high (1) and low (0), and there is no unit at this time.

[0071] Step S203 : Adapting the cycle time of a single fan according to the frequency of the fan fault signal and the fan feedback signal flip flag.

[0072] In this embodiment, the step specifically includes:

[0073] Based on the fan fault signal frequency and the fan feedback signal flip flag, the maximum number of connected fan groups is calculated, the cycle time of a single fan is adaptively adjusted, and the starting point of the cycle time of a single fan is determined;

[0074] Assume that the actual cycle of a single fan is T1, the design cycle of a single fan is T2, and the coefficient K is introduced. K is the degree of consistency between the actual cycle of a single fan feedback signal and the designed cycle.

[0075] Step S204: Determine the order of the current fans by counting the actual cycle time of each fan through the DSP time base counter.

[0076] In this embodiment, the step specifically includes:

[0077] Counting starts from the beginning of the fan feedback signal cycle;

[0078] The actual cycle count of a single fan is determined to be K*N according to the time base counter t and the cycle Ts, and the fan order is [t / (K*N)]+1;

[0079] The fan types are determined in the corresponding order according to the configuration information of the fan application.

[0080] Figure 6It is a flowchart for determining the fan order according to the time - base counter t in the fan fault detection method of the present application. In the fan feedback signal, T1 represents the time of the signal corresponding to fan 1, T2 represents the signal corresponding to fan 2, and so on. The fan order refers to 1, 2... n in t1, t2... tn, that is, it represents which fan. For example, if the time - base period is 1 ms and the time - base counter t = 10, it represents the 10th ms. For example, the designed period of a single - fan feedback signal is T2 = 1 s. Due to errors such as temperature accuracy, the actual period of a single - fan feedback signal is T1 = 0.9 s. Then represents the degree of consistency between the time - base period and the designed period of a single - fan feedback signal. N = 1 s / 1 ms = 1000, representing the count for the designed period T2 time of a single - fan feedback signal. K*N is the count for the actual period T1 time of a single - fan feedback signal.

[0081] The fan order is [t / (K*N)] + 1. For example, t starts counting from 0 until nt ends and then starts counting from 0 again. [] is the integer - taking operator. When 0 < t < K*N, [t / (K*N)] + 1 = 1. At this time, the first fan is being judged, and so on for the following ones.

[0082] Step S205: Determine the fan type of the currently judged fan according to the fan order and the fan type configured during initialization, and judge the fan fault.

[0083] Fan faults include fan stall faults, fan speed faults, etc. Figure 7 It is a flowchart for detecting fan stall faults in the fan fault detection method of the present application. As Figure 7 shown, the fan stall fault detection method includes the steps:

[0084] S701: Judge whether the fan type is A. If not, execute step S702; if so, execute step S708;

[0085] S702: Judge whether the fan type is B. If not, execute step S703; if so, execute step S705;

[0086] S703: Judge whether the fan type is C. If not, execute step S704; if so, execute step S706;

[0087] S704: Judge whether the fan type is other fan types. If so, execute step S707;

[0088] S705: Judge whether the high - level time of the fan feedback signal is greater than 0.1K*T2. If so, execute step S709; if not, execute step S708;

[0089] S706, determine whether the low level time of the fan feedback signal is greater than 0.1K*T2, if yes, execute step S709, if no, execute step S708;

[0090] S707, determine whether the fan non-reversal signal time is greater than 0.1K*T2, if yes, execute step S709, if no, execute step S708;

[0091] S708: Determine that the [t / (K*N)]+1th fan has no stall fault;

[0092] S709: Determine whether the [t / (K*N)]+1th fan has stopped rotating.

[0093] Figure 8 This is a flow chart of fan speed fault detection in the fan fault detection method of this application. Figure 8 As shown, the fan speed fault detection method includes:

[0094] S801, determine whether the fan type is A, B or C, if not, execute step S802, otherwise execute step S805;

[0095] S802: Determine whether the fan type is other types. If yes, execute step S803.

[0096] S803, determine whether the fan flip signal is equal to 1, if so, execute step S804;

[0097] S804: Determine whether the fan feedback signal frequency is less than a set threshold. If so, proceed to step S806.

[0098] S805: Determine that the [t / (K*N)]+1th fan has no speed fault;

[0099] S806: Determine whether the [t / (K*N)]+1th fan has a speed fault.

[0100] Figure 9 This is a schematic diagram of the fan detection timing, normal detection signal, and fault detection signal in the fan fault detection method of this application. Figure 9 As shown, assuming that among fan numbers 1 to 8, fan numbers 1 to 4 are fan type B, fan numbers 5 to 6 are fan type C, fan numbers 7 to 8 are fan type D, fan number 3 is fan type B, the normal detection signal should be a high level, after being detected as a low level, it is a fault signal, fan 6 is fan type C, the normal detection signal should be a low level, after being detected as a high level, it is a fault signal, fan 7 is fan type D, the normal detection is a high-frequency square wave signal, after being detected as a high level, it is a fault signal.

[0101] If there are only three fans, fan 1 is type C, fan 2 is type D, and fan 3 is type E, then a set of four fault signal logic must be designed. Fan 4 is type A. In this case, t = 4N. For n fans, the value of t is the value closest to a power of 2 multiplied by N.

[0102] The present application can detect fan faults by using a multiplex switch and one isolation device. The detection circuit is simple, the number of isolation devices used is small, and multiple sets of fan fault feedback signals can be detected at the same time, reducing the cost of isolation devices. The control signal is generated by self-excited oscillation, and there is no need for a control system to control the selection of the multiplex switch. Level-type feedback signals and square wave-type feedback signals can be detected, which facilitates the compatibility of fans with different fault feedback signals.

[0103] The present application can be used in many general or special computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, and the like. The present application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, and the like that perform specific tasks or implement specific abstract data types. The present application can also be practiced in distributed computing environments in which tasks are performed by remote processing devices connected via a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media, including storage devices.

[0104] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing related hardware via computer-readable instructions. The computer-readable instructions can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes in the above-described method embodiments. The aforementioned storage medium can be a non-volatile storage medium such as a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0105] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the flowcharts of the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0106] Example 2

[0107] Further references Figure 10 , as a response to the above Figure 2 In order to realize the method shown in FIG, the present application provides an embodiment of a fan fault detection device. Figure 2 Corresponding to the method embodiment shown, the device can be specifically applied to various electronic devices.

[0108] like Figure 10 As shown, the fan fault detection device 900 of this embodiment includes: a configuration module 901, a calculation module 902, an adaptive module 903, a positioning module 904 and a judgment module 905. Among them:

[0109] Configuration module 901, used to configure fan type and speed fault threshold;

[0110] A calculation module 902 is configured to calculate the fan fault signal frequency f and process the fan feedback signal reversal flag according to the fan type and the speed fault threshold configuration;

[0111] An adaptive module 903, configured to adaptively adjust the cycle time of a single fan according to the frequency of the fan fault signal and the fan feedback signal flip flag;

[0112] Positioning module 904, for determining the order of the current fans based on the actual cycle time of a single fan by counting the DSP time-base counter;

[0113] The judgment module 905 is used to determine the fan type of the fan currently being judged according to the fan order and the fan type configured during initialization, and judge whether the fan is faulty.

[0114] Figure 11 This is a schematic diagram of the detection principle of the fan fault detection device of this application. Figure 11As shown, the calculation module may include an oscillator, a counter, a multiplexing switch, and an isolation device. The oscillator generates a clock reference signal through self-oscillation. The counter modulates the clock reference signal into a multi-bit binary signal. The multiplexing switch selects the fault detection signals of different fans according to the binary signal. The output signal of the multiplexing switch passes through the isolation device, and then calculates the fan fault signal frequency f and processes the fan feedback signal flip flag.

[0115] In this embodiment, a clock reference signal is generated through self-oscillation. A sampling counter modulates the clock reference signal into a multi-bit binary signal. A multiplexing switch selects the fault detection signals for different fans based on the binary signal from the control terminal. The output signal of the multiplexing switch is sent to the control system through an isolation device for logical analysis and processing. This eliminates the need for a control system to output a selection control signal, saving on isolation devices. As a minimum, only one isolation device is required to detect faults in multiple fan groups.

[0116] The device can detect both level-type feedback signals and square-wave-type feedback signals, facilitating fan compatibility. When detecting square-wave-type feedback signals, faults such as abnormal fan speed can be identified.

[0117] The device can detect multiple sets of fan fault signals. For example, when there are 2 bits of binary data, it can detect 2 2 = 4 sets of fans, 3-bit binary data can detect 2 3 =8 groups of fans. When the fans are not fully connected, the fan sequence can be determined by the idle fans. When the fans are fully connected, the output signal of the counter can be sent to the control system through the isolation device to facilitate the determination of the fan detection sequence.

[0118] By implementing this embodiment, fan faults can be detected by using a multiplex switch and one isolation device. The detection circuit is simple, the number of isolation devices used is small, and multiple sets of fan fault feedback signals can be detected simultaneously, reducing the cost of isolation devices. The control signal is generated by self-excited oscillation, and there is no need for a control system to control the selection of the multiplex switch. Level-type feedback signals and square-wave-type feedback signals can be detected, which facilitates compatibility with fans with different fault feedback signals.

[0119] Example 3

[0120] To solve the above technical problems, the present application also provides a computer device. Figure 12 , Figure 12 This is a basic structural block diagram of the computer device in this embodiment.

[0121] The computer device 6 includes a memory 61, a processor 62, and a network interface 63 that are interconnected through a system bus. It should be noted that the figure only shows a computer device 6 having components of a memory 61, a processor 62, and a network interface 63, but it should be understood that it is not required to implement all the components shown, and more or fewer components can be implemented instead. Among them, those skilled in the art can understand that the computer device here is a device that can automatically perform numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes but is not limited to a microprocessor, an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), an embedded device, etc.

[0122] The computer device may be a desktop computer, notebook computer, PDA, cloud server, etc. The computer device may interact with the user via a keyboard, mouse, remote control, touchpad, or voice control device.

[0123] The memory 61 includes at least one type of readable storage medium, including flash memory, a hard disk, a multimedia card, a card-type memory (e.g., SD or DX memory), random access memory (RAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic storage, a magnetic disk, an optical disk, etc. In some embodiments, the memory 61 may be an internal storage unit of the computer device 6, such as the hard disk or memory of the computer device 6. In other embodiments, the memory 61 may also be an external storage device of the computer device 6, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash memory card, etc. equipped on the computer device 6. Of course, the memory 61 may also include both the internal storage unit of the computer device 6 and its external storage device. In this embodiment, the memory 61 is generally used to store the operating system and various application software installed on the computer device 6, such as computer-readable instructions for the fan fault detection method. In addition, the memory 61 can also be used to temporarily store various types of data that have been output or are to be output.

[0124] In some embodiments, the processor 62 can be a central processing unit (CPU), a controller, a microcontroller, a microprocessor, or other data processing chip. The processor 62 is generally used to control the overall operation of the computer device 6. In this embodiment, the processor 62 is used to execute computer-readable instructions or process data stored in the memory 61, such as computer-readable instructions for executing the fan fault detection method.

[0125] The network interface 63 may include a wireless network interface or a wired network interface. The network interface 63 is generally used to establish a communication connection between the computer device 6 and other electronic devices.

[0126] By implementing this embodiment, fan faults can be detected by using a multiplex switch and one isolation device. The detection circuit is simple, the number of isolation devices used is small, and multiple sets of fan fault feedback signals can be detected simultaneously, reducing the cost of isolation devices. The control signal is generated by self-excited oscillation, and there is no need for a control system to control the selection of the multiplex switch. Level-type feedback signals and square-wave-type feedback signals can be detected, which facilitates compatibility with fans with different fault feedback signals.

[0127] Example 4

[0128] The present application also provides another embodiment, namely, providing a computer-readable storage medium, wherein the computer-readable storage medium stores computer-readable instructions, and the computer-readable instructions can be executed by at least one processor to enable the at least one processor to perform the steps of the fan fault detection method as described above.

[0129] By implementing this embodiment, fan faults can be detected by using a multiplex switch and one isolation device. The detection circuit is simple, the number of isolation devices used is small, and multiple sets of fan fault feedback signals can be detected simultaneously, reducing the cost of isolation devices. The control signal is generated by self-excited oscillation, and there is no need for a control system to control the selection of the multiplex switch. Level-type feedback signals and square-wave-type feedback signals can be detected, which facilitates compatibility with fans with different fault feedback signals.

[0130] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0131] Obviously, the embodiments described above are only some of the embodiments of the present application, rather than all of the embodiments. The preferred embodiments of the present application are given in the accompanying drawings, but they do not limit the patent scope of the present application. The present application can be implemented in many different forms. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive. Although the present application has been described in detail with reference to the aforementioned embodiments, for those skilled in the art, it is still possible to modify the technical solutions described in the aforementioned specific embodiments, or to make equivalent replacements for some of the technical features therein. Any equivalent structure made using the contents of the present application specification and the accompanying drawings, directly or indirectly used in other related technical fields, is also within the scope of patent protection of the present application.

Claims

1. A fan fault detection method, characterized in that: The steps include: Configure fan type and speed fault threshold; Calculate the fan fault signal frequency using the ECAP module of the DSP according to the fan type and the configuration of the speed fault threshold; When the event CEVT is triggered, the time base counter CTR of the ECAP module is cleared. When the event CEVT is not triggered, the time base counter CTR of the ECAP module increases until it reaches the DSP switching frequency CPU_FRQ, and then starts counting from 0 again. The fan feedback signal flip flag is processed according to this rule. Adapt the cycle time of a single fan based on the frequency of the fan fault signal and the flip flag of the fan feedback signal; According to the actual cycle time of a single fan, the order of the current fans is determined by counting the DSP time-base counter; Based on the fan order and the fan type configured during initialization, the fan type of the currently identified fan is determined to determine if the fan is faulty.

2. The fan fault detection method according to claim 1, wherein: The steps of configuring the fan type and speed fault threshold specifically include: Establish a mapping relationship between fan types and speed fault thresholds, with each fan type corresponding to a speed fault threshold.

3. The fan fault detection method according to claim 1, wherein: Adapting the cycle time of a single fan according to the fan fault signal frequency and the fan feedback signal flip flag specifically includes: Based on the fan fault signal frequency and the fan feedback signal flip flag, the maximum number of connected fan groups is calculated, the cycle time of a single fan is adaptively adjusted, and the starting point of the cycle time of a single fan is determined; Assume that the actual cycle of a single fan is T1, the design cycle of a single fan is T2, and the coefficient K is introduced. K is the degree of consistency between the actual cycle of a single fan feedback signal and the designed cycle.

4. The fan fault detection method according to claim 1, wherein: Assume that the DSP switching frequency is CPU_FRQ, register CAP1 is set to capture the first rising edge, register CAP2 is set to capture the first falling edge, register CAP3 is set to capture the second rising edge, and register CAP4 is set to capture the second falling edge; When event CEVT1, event CEVT2, event CEVT3, and event CEVT4 are triggered, the values of capture registers CAP1, CAP2, CAP3, and CAP4 are TS1, TS2, TS3, and TS4 respectively.

5. The fan fault detection method according to any one of claims 1 to 4, characterized in that: The step of determining the order of the current fans by counting the actual cycle time of the single fan through the DSP time base counter specifically includes: Counting starts from the beginning of the fan feedback signal cycle; According to the time base counter t and the period Ts, the actual cycle count of a single fan is determined to be K*N, and the fan order is [t / (K*N)]+1; The fan types are determined in the corresponding order according to the configuration information of the fan application.

6. A fan fault detection device, characterized in that: include: Configuration module, used to configure fan type and speed fault threshold; a calculation module, configured to calculate the fan fault signal frequency using the ECAP module of the DSP according to the fan type and the configuration of the speed fault threshold; when the event CEVT is triggered, the time base counter CTR of the ECAP module is cleared to zero; when the event CEVT is not triggered, the time base counter CTR of the ECAP module is incremented to the switching frequency CPU_FRQ of the DSP, and then restarts counting from 0, and processes the fan feedback signal flip flag according to this rule; An adaptive module is used to adapt the cycle time of a single fan according to the frequency of the fan fault signal and the flip flag of the fan feedback signal; Positioning module, used to determine the order of the current fans based on the actual cycle time of a single fan by counting the DSP time-base counter; The judgment module is used to determine the fan type of the current fan according to the fan sequence and the fan type configured during initialization, and judge whether the fan is faulty.

7. The fan fault detection device according to claim 6, wherein: The calculation module includes an oscillator, a counter, a multiplexing switch, and an isolation device. The oscillator generates a clock reference signal through self-excited oscillation. The counter modulates the clock reference signal into a multi-bit binary signal. The multiplexing switch selects the fault detection signals of different fans according to the binary signal. The output signal of the multiplexing switch passes through the isolation device, and then calculates the fan fault signal frequency f and processes the fan feedback signal reversal flag.

8. A computer device comprising a memory and a processor, wherein the memory stores computer-readable instructions, and the processor implements the steps of the fan fault detection method according to any one of claims 1 to 5 when executing the computer-readable instructions.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-readable instructions, which, when executed by a processor, implement the steps of the fan failure detection method according to any one of claims 1 to 5.

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