Doppler frequency shift adaptive matched filtering method based on control circuit

Abstract

The present invention discloses a Doppler frequency shift adaptive matched filtering method based on a control circuit, which mainly solves the problem that the existing technology has large amplitude loss of pulse compression peak or correlation peak and occupies many resources when Doppler frequency shift occurs. The scheme is: the receiving end down-converts the received frequency band signal into a baseband signal, takes its sign bit, and detects the edge jump of the sign bit through the designed control circuit: when the sign bit has an edge jump, the counter is reset and the cyclic counting is restarted, that is, each code element is sampled at the center of the count value to obtain the code element sample point to enter the matched filter, and a code element clock enable signal of i global clock cycles is generated. When the signal is valid, i samples of each code element enter the matched filter and output the final pulse compression peak or correlation peak. The pulse compression peak or correlation peak output by the present invention has no loss in amplitude, reduces the occupation of hardware resources, realizes Doppler frequency shift adaptive matched filtering, and can be used for radar detection and communication navigation.

Description

Technical Field

[0001] The invention belongs to the technical field of signal processing, and in particular relates to a matched filtering method, which can be used for radar detection and communication navigation. Background Art

[0002] In radar detection, pulse compression technology is used to solve the contradiction between the radar's range and range resolution, that is, a set of matched filters are used to compress the pulses emitted by the radar. In communication navigation, spread spectrum technology is used to achieve a long range and strong anti-interference ability. In spread spectrum technology, a matched filter is used to despread each bit of data.

[0003] Radar can obtain large transmission energy by transmitting wide pulses to achieve long range and detect targets. The received signal is processed by pulse compression to obtain narrow pulses, which can obtain high distance resolution. Pulse compression widely uses phase-coded signals. At the transmitting end, a single pulse is phase-encoded with a pseudo-random sequence code to form a baseband signal, that is, a wide pulse with a width of T. At the receiving end, the received baseband signal is convolved with the matching value in the matched filter to compress the wide pulse into a narrow pulse. The matching value is the same pseudo-random sequence code stored in advance. This narrow pulse is called a pulse compression peak. The time width of the wide pulse is T = N·τ, τ is the code width of the pseudo-random sequence code, N is the code length of the pseudo-random sequence code, that is, the number of code elements. The wide pulse contains N code elements with a width of τ. The phase of each code element is determined according to different rules. If the phase value is limited to 0 and π, it is a two-phase coded signal, otherwise it is a multi-phase coded signal, and the two-phase coded signal is the most widely used. The advantage of the phase-coded signal is that it can ensure high distance resolution and ranging accuracy, and the disadvantage is that it is sensitive to Doppler frequency shift.

[0004] Due to the relative motion between the radar and the target, the baseband signal at the receiving end is added with a Doppler frequency shift, resulting in a change in the baseband signal code element width: when the Doppler frequency shift is positive, the received signal frequency is higher than the local carrier frequency, and the code element width becomes narrower; when the Doppler frequency shift is negative, the received signal frequency is lower than the local carrier frequency, and the code element width becomes wider; assuming that the code element width of the Doppler frequency shift is τ', the difference in the bit width of each code element when there is a Doppler frequency shift and when there is no Doppler frequency shift is |τ'-τ|. The matched filter pre-stores a set of matching value points according to the standard code element bit width. Therefore, there is a mismatch between the baseband signal with Doppler frequency shift and the matching value pre-stored in the matched filter: the larger the Doppler frequency shift, the larger the bit width difference |τ'-τ| of each code element will be, resulting in an increase in the number of misplaced points and a mismatch. When the code length N is longer, the bit width difference N·|τ'-τ| of N consecutive code elements will be larger, the number of misplaced points will be more, and the mismatch will be aggravated, causing the amplitude of the pulse compression peak output by the matched filter to drop rapidly until there is no obvious peak. When the pulse compression peak amplitude is lower than the decision threshold, it is judged by the radar as no target, and the matched filter cannot play the role of pulse compression. Therefore, phase coded signals are generally used in scenarios where the target's Doppler frequency shift is small.

[0005] In practical applications, the Doppler shift of the target is unknown, but the maximum range of the Doppler shift is determined. In order to overcome the influence of the Doppler shift on the pulse compression peak amplitude, the existing method is to use multiple branches to try to select the largest method, and use a group of matched filters to work in parallel and simultaneously, and divide the maximum range of the Doppler shift into multiple intervals, corresponding to the matched filters of multiple branches. Each matched filter corresponds to a specific Doppler frequency, which matches the baseband signal of the specific Doppler frequency. The larger the Doppler shift, the more branches of the matched filter are required. The matched filter with the largest output pulse compression peak amplitude is selected from the multiple matched filters. At this time, the highest point of the output pulse compression peak amplitude of the matched filter is N, and the output signal-to-noise ratio is the largest, that is, the pulse compression of the signal is completed; however, in most actual scenarios, the Doppler shift of the target is not at a specific Doppler frequency, but between adjacent specific Doppler frequencies, resulting in a loss of the peak amplitude of the pulse compression output by the matched filter, and the reduction in amplitude directly affects the radar's detection of the target.

[0006] In spread spectrum communication, the transmitter uses a pseudo-random sequence code to phase encode each bit of transmitted data to achieve spread spectrum. The receiver needs to use the same pseudo-random sequence code as the transmitter to despread each bit of received data and restore each bit of data from the transmitter. The time width of each bit of data is T = N·τ, where N is the length of the pseudo-random sequence code and τ is the width of each bit of code element. Despreading is performed by correlating the pseudo-random sequence code pre-stored in the matched filter with the received data to output a correlation peak, and the highest amplitude point of the correlation peak is N. The presence of Doppler frequency shift will reduce the amplitude of the correlation peak. When the amplitude of the correlation peak is lower than the decision threshold, the data cannot be recovered and data despreading fails.

[0007] It can be seen that the despreading method of spread spectrum communication is similar to the pulse compression method of radar detection. Both require the use of matched filters. However, both pulse compression technology and data despreading technology are relatively complex to implement and have the following two problems:

[0008] 1. There is a loss in pulse compression peak amplitude or related peak amplitude.

[0009] In pulse compression, the maximum range of Doppler frequency shift f dMAX Divided into M intervals, each interval covers a frequency of f dMAX / M, each matched filter corresponds to a specific Doppler frequency, the specific Doppler frequency is f dMAX / M is an integer multiple of. When the Doppler shift of the target happens to be at a specific Doppler frequency, there is no loss in the pulse compression peak amplitude. However, in most scenarios, the Doppler shift of the target is not at a specific Doppler frequency, but in the interval of adjacent specific Doppler frequencies. In this case, there is a loss in the pulse compression peak amplitude. The reduction in amplitude directly affects the radar's detection of targets.

[0010] In spread spectrum communication, the presence of Doppler frequency shift will reduce the correlation peak amplitude. When the correlation peak amplitude is lower than the decision threshold, data despreading fails.

[0011] 2. The amount of calculation and equipment is large.

[0012] In pulse compression, a method of trying to select the larger of multiple branches is used to overcome the influence of Doppler frequency shift on the peak amplitude of phase-coded pulse compression. This requires a group of matched filters to work in parallel and simultaneously, and the matched filter with the largest pulse compression peak is selected as the output result, which requires a large amount of calculation and equipment.

[0013] In spread spectrum communication, the matched filter needs to complete carrier synchronization before performing correlation operations between the pseudo-random sequence code and the received data, and the receiving end needs to use automatic frequency control AFC to capture and track the carrier frequency.

[0014] The above two deficiencies will cause the pulse compression peak amplitude / correlation peak amplitude to decrease in scenarios with large Doppler frequency shift or weak signal, until it falls below the decision threshold, resulting in the radar being unable to detect the target and data despreading failing. Summary of the invention

[0015] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art and propose a Doppler frequency shift adaptive matched filtering method to reduce the loss of output pulse compression peak or correlation peak amplitude, reduce the probability of radar missing targets and data demodulation failure, and improve the radar's detection capability and data demodulation speed.

[0016] To achieve the above object, the technical solution of the present invention includes the following:

[0017] (1) Design a control circuit: it includes 4 D flip-flops, 1 matched filter, 1 binary modulo L counter, 1 pulse generator, 1 XOR gate and 1 AND gate;

[0018] (2) After the control circuit is powered on, the initial states of all D flip-flops, counters, pulse generators, and matched filters are set to a low level, and the operation of the D flip-flops, counters, matched filters, and pulse generators is controlled by the global clock CLK generated by the crystal oscillator;

[0019] (3) At the receiving end, the received frequency band signal is down-converted into a baseband signal with a code length of N and a code element width of τ. The sign bit of the baseband signal is taken to shape the signal waveform into a rectangular pulse signal.

[0020] (4) Detect the edge transition of the baseband signal sign bit, and generate a reset signal each time the edge transition occurs. The reset signal controls the counter to reset. The counter measures each code element in the baseband signal sign bit in a sliding window manner and restarts the cycle counting.

[0021] (5) The sampling time is controlled by a counter to generate a latch pulse signal WENA. A D flip-flop samples each code element in the baseband signal sign bit once, that is, each code element first obtains one code element sample point;

[0022] (6) Delaying the latch pulse signal by one global clock cycle to obtain the symbol clock enable signal CLKEN, so that the high level of the symbol clock enable signal lasts for i global clock cycles, thereby achieving i sampling points for each symbol;

[0023] (7) Outputting one sample point of each symbol obtained in (5) to the symbol sample point input terminal of the matched filter, outputting the symbol clock enable signal to the symbol clock enable terminal of the matched filter, and connecting the global clock to the clock terminal of the matched filter;

[0024] (8) According to the symbol clock enable signal obtained in (6), the matched filter after the symbol clock enable signal and the global clock are connected in (7) is subjected to the following operation:

[0025] When the symbol clock enable signal is at a low level, the matched filter maintains the status quo and does not act;

[0026] When the symbol clock enable signal is at a high level, at the rising edge of the global clock, the matched filter latches the newly input symbol samples, and performs sliding correlation between its own pre-stored matching value and the latched symbol samples, so that the duration of the pre-stored matching value is the same as the actual bit width of the symbol samples and changes synchronously, so as to automatically adapt to the Doppler frequency shift, and finally output a pulse compression peak or correlation peak with an amplitude of i×N. The peak amplitude has no loss and improves the output signal-to-noise ratio of the matched filter, that is, Doppler frequency shift adaptive matched filtering is realized.

[0027] Compared with the prior art, the present invention has the following advantages:

[0028] 1) Automatically adapt to Doppler frequency shift, the matched filter output peak has no loss, suitable for pulse compression and spread spectrum communication.

[0029] In the prior art, the baseband signal of the Doppler frequency shift and the matching value in the matched filter are mismatched in the interval of adjacent specific Doppler frequencies. The longer the code length, the greater the mismatch. The pulse compression peak or correlation peak amplitude of the matched filter output is lost. The reduction in amplitude directly affects the radar's detection of targets and data despreading.

[0030] The present invention adopts circuits such as a counter and a D flip-flop, takes the edge jump as the starting moment, and the counter measures each code element in a sliding window manner. At the center point of the count value, the D flip-flop is made to sample each code element in a baseband signal with Doppler frequency shift, which not only avoids over-sampling and missed sampling of code element samples, but also enables the code element clock enable signal generated after sampling to make the duration of the pre-stored matching value in the matching filter the same as the actual bit width of the code element sample point and change synchronously after the code element sample point enters the matching filter, and can automatically adapt to the Doppler frequency shift, so that the pulse compression peak or correlation peak amplitude output by the matching filter has no loss, and the signal-to-noise ratio is improved. The present invention is suitable for both pulse compression and data despreading in spread spectrum communication.

[0031] 2) Reduce the amount of calculation, save hardware resources and time.

[0032] In pulse compression, the existing technology uses a group of matched filters to work in parallel, which requires a lot of calculation and equipment. In spread spectrum communication, the existing technology uses automatic frequency control AFC at the receiving end to capture and track the frequency;

[0033] The present invention uses only one matched filter in pulse compression, which reduces the amount of calculation and saves hardware resources; in spread spectrum communication, automatic frequency control AFC is not required to capture and track the frequency, and only a counter and a D flip-flop are used to achieve synchronization, which improves the speed of data despreading and saves time. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a flow chart of the implementation of the present invention;

[0035] Figure 2 It is the control circuit principle diagram of the present invention. DETAILED DESCRIPTION

[0036] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0037] The present invention is based on a control circuit, into which the sign bit of the baseband signal at the receiving end is sent, and the control circuit is driven by a global clock CLK to output a pulse compression peak or a correlation peak.

[0038] Reference Figure 2 The control circuit includes 4 D flip-flops, 1 matched filter, 1 binary modulo L counter, 1 pulse generator, 1 XOR gate and 1 AND gate, wherein the output end of the first flip-flop D1 is connected to the input end of the XOR gate; the output end of the XOR gate is connected to the data input end of the second flip-flop D2, and the output end of the second flip-flop D2 is connected to the asynchronous reset end of the counter; the output end of the counter is connected to the input end of the AND gate, and the output end of the AND gate is respectively connected to the enable end ena of the third flip-flop D3 and the data input end of the fourth flip-flop D4, the output end of the fourth flip-flop D4 is connected to the data input end of the pulse generator, the output end of the pulse generator is connected to the symbol clock enable end of the matched filter, and the output end of the third flip-flop D3 is connected to the symbol sample point input end of the matched filter.

[0039] Reference Figure 1 The implementation steps of Doppler frequency shift adaptive matched filtering in this example based on the above control circuit are as follows:

[0040] Step 1: At the receiving end, the control circuit is driven by the global clock CLK.

[0041] After power is applied to the control circuit, the initial state of all D flip-flops, counters, pulse generators, and matched filters is set to a low level; a global clock CLK with a period of t is generated by an external crystal oscillator and output to the clock end of all D flip-flops, counters, matched filters, and pulse generators; under the synchronization of the global clock, the D flip-flops, matched filters, counters, and pulse generators inside the control circuit all start to work.

[0042] Step 2: At the receiving end, take the sign bit of the baseband signal, detect its edge transition and generate a reset signal, and use the reset signal to control the counter to reset and restart the cycle counting.

[0043] 2.1) The received frequency band signal is sampled, quantized, and digitally down-converted to obtain a baseband signal a(t). The code length of the baseband signal is N, and the bit width of each code element is L times the global clock period, that is, τ=L×t, where L is the count value of a counter cycle. The sign bit aF(t) in the baseband signal is taken;

[0044] 2.2) Use two D flip-flops and one XOR gate in the control circuit to detect the edge transition of the baseband signal sign bit aF(t). The detection of the edge transition takes two global clock cycles:

[0045] The baseband signal sign bit aF(t) is simultaneously sent to the data input terminal of the first D flip-flop D1 and the first input terminal of the "XOR" gate in the control circuit. The output terminal of the first D flip-flop D1 is connected to the second input terminal of the "XOR" gate. Each time the global clock CLK is triggered, the data of the first input terminal of the "XOR" gate is always the old data I0 of the sign bit aF(t), and the data of the second input terminal is always the new data I1 of the sign bit aF(t). When it is detected that the data output by the two D flip-flops are different, that is, I0≠I1, it means that the sign bit aF(t) has an edge jump. At this time, the second D flip-flop D2 connected to the "XOR" gate will output a high level. It will take 2 global clock cycles from the edge jump to the output of the high pulse.

[0046] 2.3) The high level output by the second D flip-flop D2 is used as a reset signal to reset the counter. When the reset signal becomes low, the counter measures each code element in the baseband signal sign bit in a sliding window manner and counts cyclically from 0 to L-1 according to the beat of the global clock.

[0047] In this example, the counter counts cyclically from 0 to 15 according to the beats of the global clock.

[0048] Step 3, the counter controls the sampling time to generate a latch pulse signal WENA, and then the D flip-flop samples each code element once.

[0049] 3.1) The first counting bit r0 of the counter is inverted and output, the second counting bit r1 is output normally, the third counting bit r2 is output normally, and the fourth counting bit r3 is inverted and output, and these four are simultaneously connected to the input end of the "AND gate";

[0050] 3.2) According to the principle that the midpoint value L / 2 counted by the counter corresponds to the center of each code element in the sign bit of the baseband signal, considering the two global clock cycles required to detect the edge transition of the baseband signal sign bit, the count value L / 2-2 of the counter is used as the sampling moment, at which the output value of the counter outputs the latch pulse signal WENA through the "AND gate"; when the latch pulse signal is valid, the third trigger D3 samples each code element in the sign bit of the baseband signal once, that is, each code element first obtains a code element sample point, which is latched to avoid over-sampling and missed sampling of each code element in the sign bit of the baseband signal.

[0051] In this example, whenever the count value of the counter is z=(L / 2)-2=6, the latch pulse signal is valid, and the third flip-flop D3 latches the baseband signal sign bit to obtain a code element sample point.

[0052] Step 4, output symbol clock enable signal CLKEN.

[0053] The fourth trigger D4 delays the latch pulse signal by 1 global clock cycle, and controls the pulse generator connected to it to output the code element clock enable signal CLKEN, which is valid at a high level. The pulse generator makes the code element clock enable signal last for i global clock cycles, thereby sampling i samples for each code element, where i is a positive integer greater than or equal to 2, but cannot be greater than the count value L of one cycle of the counter.

[0054] In this example, the high level duration of the symbol clock enable signal is 4 global clock cycles.

[0055] Step 5: The output of the matched filter is controlled by the symbol clock enable signal and the global clock.

[0056] The working state of the matched filter is determined by the level of the symbol clock enable signal and the rising edge of the global clock CLK:

[0057] When the symbol clock enable signal is at a low level, the matched filter maintains the status quo and does not act;

[0058] When the symbol clock enable signal is at a high level, at the rising edge of the global clock, i samples per symbol enter the matched filter, which latches them, shifting the stored symbol samples forward and shifting the earliest latched symbol samples out;

[0059] The matched filter performs sliding correlation between the existing codeword samples and the pre-stored matching values, so that the duration of the pre-stored matching values ​​is the same as the actual bit width of the codeword samples and changes synchronously, so as to realize automatic adaptation to Doppler frequency shift. If the pre-stored matching value matches the existing codeword samples, the matched filter will output a pulse compression peak or correlation peak with an amplitude of i×N, and the peak amplitude is not lost. In addition, compared with single-sample sampling, multi-point sampling improves the output signal-to-noise ratio of the matched filter, and realizes Doppler frequency shift adaptive matched filtering. In this example, 4 samples are latched per bit of codeword, the baseband signal code length is 127, and the amplitude of the pulse compression peak or correlation peak output by the matched filter is i×N=4×127=508, the peak amplitude is not lost, and the signal-to-noise ratio is improved by 4 times, which can realize Doppler frequency shift adaptive matched filtering.

[0060] The above description is only a specific example of the present invention and does not constitute any limitation to the present invention. It is obvious that for professionals in this field, after understanding the content and principles of the present invention, it is possible to make various modifications and changes in form and details without departing from the principles and structures of the present invention. However, these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A Doppler frequency shift adaptive matched filtering method based on a control circuit, characterized in that: include: (1) Design a control circuit: it includes 4 D flip-flops, 1 matched filter, 1 binary modulo L counter, 1 pulse generator, 1 XOR gate and 1 AND gate; (2) After the control circuit is powered on, the initial states of all D flip-flops, counters, pulse generators, and matched filters are set to a low level, and the operation of the D flip-flops, counters, matched filters, and pulse generators is controlled by the global clock CLK generated by the crystal oscillator; (3) At the receiving end, the received frequency band signal is down-converted into a baseband signal with a code length of N and a code element width of τ. The sign bit of the baseband signal is taken to shape the signal waveform into a rectangular pulse signal. (4) Detect the edge transition of the baseband signal sign bit. Each time the edge transition occurs, a reset signal is generated. The reset signal controls the counter to reset. The counter measures each code element in the baseband signal sign bit in a sliding window manner and restarts the cycle counting. (5) The sampling time is controlled by a counter to generate a latch pulse signal WENA. A D flip-flop samples each code element in the baseband signal sign bit once, that is, each code element first obtains one code element sample point; (6) Delaying the latch pulse signal by one global clock cycle to obtain the symbol clock enable signal CLKEN, so that the high level of the symbol clock enable signal lasts for i global clock cycles, thereby achieving i sampling points for each symbol; (7) Outputting one sample point of each symbol obtained in (5) to the symbol sample point input terminal of the matched filter, outputting the symbol clock enable signal to the symbol clock enable terminal of the matched filter, and connecting the global clock to the clock terminal of the matched filter; (8) According to the symbol clock enable signal obtained in (6), the matched filter after the symbol clock enable signal and the global clock are connected in (7) is subjected to the following operation: When the symbol clock enable signal is at a low level, the matched filter maintains the status quo and does not act; When the symbol clock enable signal is at a high level, at the rising edge of the global clock, the matched filter latches the newly input symbol samples, and performs sliding correlation between its own pre-stored matching value and the latched symbol samples, so that the duration of the pre-stored matching value is the same as the actual bit width of the symbol samples and changes synchronously, so as to automatically adapt to the Doppler frequency shift, and finally output a pulse compression peak or correlation peak with an amplitude of i×N. The peak amplitude has no loss and improves the output signal-to-noise ratio of the matched filter, that is, Doppler frequency shift adaptive matched filtering is realized.

2. The method according to claim 1, characterized in that: The working process of the control circuit is as follows: Under the global clock CLK, the received baseband signal sign bit passes through the first D flip-flop D1, the "XOR gate" and the second D flip-flop D2 in sequence to generate a reset signal, which passes through the asynchronous reset terminal of the counter to control the counter to reset and restart counting; The output value of the counter passes through the "AND gate" to output a latch pulse signal WENA, and the latch pulse signal passes through the fourth D flip-flop D4 and the pulse generator to output a symbol clock enable signal CLKEN; The received baseband signal sign bit and the latch pulse signal output by the "AND gate" pass through the third D flip-flop D3 to output a codeword sample point. When the codeword clock enable signal output by the pulse generator is valid, the codeword sample point is sent to the matching filter, and the output of the matching filter is controlled by the codeword clock enable signal and the global clock CLK.

3. The method according to claim 1, characterized in that: In (5), the sampling time is controlled by the counter to generate the latch pulse signal WENA. According to the principle that the midpoint value L / 2 of the counter count corresponds to the center of each code element in the baseband signal sign bit, considering the two global clock cycles consumed to detect the edge transition of the baseband signal sign bit, the counter count value L / 2-2 is used as the sampling time. At this time, the output value of the counter outputs the latch pulse signal WENA through the "AND gate". When the latch pulse signal WENA is valid, a D flip-flop samples each code element in the baseband signal sign bit once to avoid over-sampling and missed sampling of each code element in the baseband signal sign bit, where L is the count value of the counter for one cycle and is not less than 4.

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