A shift register unit and a digital microfluidic control chip driving circuit

Abstract

The shift register unit designed by the present invention comprises a first control switch connected to a first clock signal end, a first inverter, whose input end is connected to an input signal end through the first control switch to form the input end of the shift register unit, a second control switch connected to a second clock signal end, a second inverter, whose output end is connected to an output signal end to form the output end of the shift register unit, the output end of the first inverter is connected to the input end of the second inverter through the second control switch, the high level ends of the first inverter and the second inverter are both connected to a power supply, and the low level ends are both grounded, the output waveform is smoother at high voltage, and the rising edge and the falling edge are steeper, and the present invention can completely shift and register the input signal for one cycle, and the outputs of adjacent shift registers will not overlap.

Description

Technical Field

[0001] The present invention relates to the field of microfluidic technology, and in particular to a shift register unit and a driving method thereof, a shift register and a digital microfluidic control chip driving circuit. Background Art

[0002] Digital microfluidic chips refer to the control of discontinuous droplets. The core technology is to use electronic circuits to control the surface tension of liquids, thereby controlling the generation, movement, splitting, merging and other operations of droplets. The digital microfluidic biochip is mainly composed of a two-dimensional electrode array. The upper electrode is a large electrode covering all units in the array, which serves as a common ground terminal; the lower electrode applies different control voltages as needed during use. Based on dielectric wetting technology, nanoliter droplets are confined between the two plates during operation. By simultaneously applying a low level to the electrode where the droplet is located and a high level to the adjacent electrode, the surface tension of the droplet is changed, thereby achieving the movement of the droplet from a low level to a high level. The controller translates the experimental steps into a series of voltage sequences, which are loaded onto each electrode through the pins to achieve all operations such as droplet mixing, separation, dilution, and injection.

[0003] In digital circuits, a shift register is a device based on a trigger that works under several identical time pulses. Data is input into the device in parallel or serial mode, and then each time pulse is shifted one bit to the left or right in turn and output at the output end. This shift register is one-dimensional. In fact, there are multi-dimensional shift registers, that is, the input and output data are themselves columns of bits. The method to realize this multi-dimensional shift register is to connect several shift registers with the same number of bits in parallel.

[0004] The main application of shift registers in digital microfluidic chips is to provide driving voltage and interactive connection between digital microfluidic chips and external controllers.

[0005] like Figure 1 As shown, in the prior art, in the digital microfluidic chip driving circuit, the shift register is mainly a D trigger, and its first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, and the first capacitor C1 can form an input module P1, and the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the second capacitor C2 and the third capacitor C3 can form an output module P2. The input module P1 is used to provide a selection signal to the output module P2 according to the signal input by the first clock signal terminal Clk1, the second clock signal segment Clk2 and the data carry signal terminal STV; the output module P2 is used to select the output high level or low level according to the selection signal provided by the input module P1; Figure 2This is the simulation waveform diagram of the shift register. We can see that at high voltage, the output waveform is not smooth, the rising and falling edges are not steep enough, and the input signal can only be shifted and registered for half a cycle, causing the outputs of adjacent shift registers to overlap, thus affecting the drive of the digital microfluidic control chip. Summary of the invention

[0006] Therefore, the technical problem to be solved by the present invention is to overcome the problems in the prior art that the high voltage output waveform of the shift register is not smooth, the rising edge and the falling edge are not steep enough, and the shift register cycle is short.

[0007] In order to solve the above technical problems, the present invention provides a shift register unit, comprising:

[0008] A first inverter is configured such that when a high level signal is input to an input terminal of the first inverter, a low level signal is output at an output terminal thereof;

[0009] A second inverter having the same configuration as the first inverter, and

[0010] The first inverter and the second inverter have a high-level terminal commonly connected to a high-potential constant-voltage source and a low-level terminal commonly connected to a low-potential constant-voltage source;

[0011] A first control switch is provided between an input terminal of the first inverter and an external input signal, and the first control switch is turned on or off under the control of a first clock signal;

[0012] The second control switch is arranged between the output end of the first inverter and the input end of the second inverter. The second control switch is turned on or off under the control of a second clock signal, and the first clock signal and the second clock signal differ by 180°.

[0013] Preferably, the shift register unit further includes

[0014] a first storage capacitor, a positive electrode of which is connected to the output end of the first inverter, and a negative electrode of which is connected to the low potential constant voltage source;

[0015] A second storage capacitor has a positive electrode connected to the input end of the second inverter and a negative electrode connected to the low potential constant voltage source.

[0016] Preferably, the shift register unit is a serial-in parallel-out shift register unit.

[0017] Preferably, the shift register unit is a parallel-in serial-out shift register unit, and the parallel-in serial-out shift register unit further comprises:

[0018] a fourth control switch, arranged between the external input signal and the first control switch;

[0019] a fifth control switch, arranged between a preset signal and the first control switch;

[0020] The third inverter has the same configuration as the first inverter and / or the second inverter, the high level end of the third inverter is commonly connected to the high potential constant voltage source, the low level end is commonly connected to the low potential constant voltage source, the input end is connected to an enable signal, and the output end is connected to the control end of the fourth control switch; wherein

[0021] The fourth control switch is turned on or off by receiving the signal output by the third inverter;

[0022] The fifth control switch is turned on or off under the control of the enable signal.

[0023] Preferably, the first inverter and the second inverter have the same circuit structure, either of which comprises:

[0024] A first transistor, a gate and a drain of which are connected to the high level end;

[0025] a second transistor, a drain of which is connected to the high level end, and a gate of which is connected to the source of the first transistor;

[0026] a third transistor, whose gate constitutes the input terminal of the inverter, whose drain is connected to the source of the second transistor and constitutes the output terminal of the inverter, and whose source is connected to the low potential constant voltage source;

[0027] The bootstrap capacitor is connected between the gate and the source of the second transistor.

[0028] Preferably, the high potential constant voltage source is a voltage source, and its output voltage is greater than 70V.

[0029] Preferably, the low potential constant voltage source is a ground terminal.

[0030] Preferably, the shift register unit further comprises a third control switch connected between the high potential constant voltage source and the input end of the second inverter, and the third control switch is turned on or off under the control of a reset signal.

[0031] The present invention also provides a serial-in-parallel-out shift register, comprising a plurality of the above-mentioned shift register units, wherein the input end of the first-stage shift register unit of the serial-in-parallel-out shift register is connected to an input signal, the output end of the previous-stage shift register unit is connected to the input end of the next-stage shift register unit, and the output end of each stage of the shift register unit is output in parallel.

[0032] The present invention also provides a parallel-in-serial-out shift register, comprising a plurality of the above-mentioned shift register units, wherein the input end of the first-stage shift register unit of the parallel-in-serial-out shift register is connected to an input signal, the output end of the previous-stage shift register unit is connected to the input end of the next-stage shift register unit, the output end of the last-stage shift register unit constitutes the output end of the parallel-in-serial-out shift register, and the input end of each stage of the shift register unit is input in parallel with a preset signal.

[0033] The present invention also provides a digital microfluidic chip driving circuit, comprising the above-mentioned serial-in-parallel-out shift register or the above-mentioned parallel-in-serial-out shift register.

[0034] The above technical solution of the present invention has the following advantages compared with the prior art:

[0035] In the shift register unit designed by the present invention, amorphous silicon thin film transistors T1, T2, T3 and a bootstrap capacitor C1 constitute a first inverter P1; amorphous silicon thin film transistors T4, T5, T6 and a bootstrap capacitor C2 constitute a second inverter P2; amorphous silicon thin film transistors T7 and T8 are used as switches, which are controlled by clocks CLKA and CLKB respectively; in order to enhance the load carrying capacity of the shift register, a first storage capacitor C3 is added between the drain of the third transistor T3 and the low potential constant voltage source VSS, and a second storage capacitor C4 is added between the gate of the sixth transistor and the low potential constant voltage source VSS, which simultaneously enhances the register's ability to store input signals and filters out voltage fluctuations of the circuit; it can be seen from the simulation waveform diagram of the register unit that the waveform output by the register at high voltage is smoother, and the rising edge and the falling edge are steeper, and the present invention can completely shift and store the input signal for one cycle, and the outputs of adjacent shift registers will not overlap. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to make the content of the present invention more clearly understood, the present invention is further described in detail below according to specific embodiments of the present invention in conjunction with the accompanying drawings, wherein:

[0037] Figure 1 is a circuit diagram of an existing shift register unit;

[0038] Figure 2 It is a simulation waveform diagram of the existing shift register unit;

[0039] Figure 3 is a circuit diagram of a shift register unit of the present invention;

[0040] Figure 4 It is a simulation waveform diagram of the shift register unit of the present invention;

[0041] Figure 5It is the circuit diagram of the serial-in parallel-out shift register unit;

[0042] Figure 6 It is a simulation waveform diagram of the serial-in and parallel-out shift register unit circuit;

[0043] Figure 7 It is a circuit diagram of a parallel-in serial-out shift register unit;

[0044] Figure 8 It is a simulation waveform diagram of the parallel-in-serial-out shift register unit circuit;

[0045] Fig. 9 It is the circuit diagram of a fifth-order serial-input parallel-output shift register;

[0046] Fig.10 This is the simulation waveform of the fifth-order serial-input and parallel-output shift register circuit (with load: 1pF capacitor and 10gΩ resistor, negative power supply voltage is -5V);

[0047] Fig.11 It is a circuit diagram of a fifth-order parallel-input and serial-output shift register;

[0048] Fig.12 This is the simulation waveform of the fifth-order parallel-in serial-out shift register circuit (with load: 1pF capacitor and 10gΩ resistor, negative power supply voltage is -5V). DETAILED DESCRIPTION

[0049] The core of the present invention is to provide a shift register unit and a driving method thereof, a shift register and a digital microfluidic control chip driving circuit, the output high-voltage waveform of which is smoother, the rising and falling edges are steeper and a complete shift register cycle can be achieved.

[0050] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0051] Please refer to Figure 3 , Figure 3 The shift register unit circuit provided by the present invention is as follows:

[0052] The first inverter P1 is configured such that when a high level signal is input to the input terminal of the first inverter, a low level signal is output at the output terminal thereof;

[0053] The second inverter P2 has the same configuration as the first inverter, and

[0054] The first inverter and the second inverter have a high level end commonly connected to a high potential constant voltage source VDD and a low level end commonly connected to a low potential constant voltage source VSS;

[0055] A first control switch T7 is arranged between the input terminal of the first inverter and an external input signal, and the first control switch is turned on or off under the control of the first clock signal CLKA;

[0056] The second control switch T8 is arranged between the output terminal of the first inverter and the input terminal of the second inverter, and the second control switch is turned on or off under the control of the second clock signal CLKB, and

[0057] The first clock signal and the second clock signal differ in phase by 180°.

[0058] In the shift register unit provided by the present invention, the first inverter and the second inverter have the same circuit structure, either of which includes:

[0059] A first transistor T1 / T4, whose gate and drain are connected to the high level end;

[0060] A second transistor T2 / T5, a drain of which is connected to the high level end, and a gate of which is connected to the source of the first transistor;

[0061] a third transistor T3 / T6, whose gate constitutes the input terminal of the inverter, whose drain is connected to the source of the second transistor and constitutes the output terminal of the inverter, and whose source is connected to the low potential constant voltage source;

[0062] The bootstrap capacitor C1 / C2 is connected between the gate and the source of the second transistor.

[0063] When the input signal IN is at a low level VIL, the third transistor is gradually turned off from on, and the output voltage begins to increase; since the voltage across the bootstrap capacitor will not change suddenly, the gate voltage of the second transistor is gradually increased on the basis of the high potential constant voltage source minus the threshold voltage of the first transistor (VDD-VTH1); when the gate voltage of the second transistor increases to the high potential constant voltage source plus the threshold voltage of the second transistor (VDD+VTH2), the second transistor changes from a saturated state to a non-saturated state; since the current of the second transistor is equal to the current of the third transistor and equal to 0:

[0064] μCα((VDD+VTH2-VTH2-VOH)(VDD-VOH))=0

[0065] VOH=VDD

[0066] It can be obtained that the output voltage VOH is at a high level and is equal to the high potential constant voltage source VDD, so the inverter eliminates the influence of the threshold voltage, and when the output is at a high level, the voltage loss is 0.

[0067] When the input signal IN is at a high level VIH, since the gate voltage and drain voltage of T1 are the same and are VDD, T1 is in a saturated state, the source voltage of T1, that is, the gate voltage of T2 is VDD-VTH1, and the voltage across the capacitor C1 is VDD-VTH1-VOL. The currents of the saturated T2 tube and the unsaturated T3 tube are the same, so:

[0068] 0.5μCα(VDD-VTH1-VOL-VTH2) 2 =HCβ((VOH-VSS-VTH3)(VOL-VSS))

[0069]

[0070] Wherein, VTH3 is the threshold voltage of the third transistor;

[0071] Therefore, it can be known from the expression of VOL that VOL can be adjusted to the low level requirement by adjusting the low potential constant voltage source VSS.

[0072] Among them, α is the width-to-length ratio of the T2 tube, and β is the width-to-length ratio of the T3 tube. We optimized the width-to-length ratio of the device so that it can transmit high-voltage signals.

[0073] Based on the above embodiments, this embodiment provides a serial-in parallel-out shift register unit, which adds the following on the basis of the above embodiments:

[0074] A first storage capacitor C3, a positive electrode of which is connected to the output end of the first inverter, and a negative electrode of which is connected to the low potential constant voltage source;

[0075] A second storage capacitor C4, a positive electrode of which is connected to the input terminal of the second inverter, and a negative electrode of which is connected to the low potential constant voltage source;

[0076] The high potential constant voltage source is a voltage source, and its output voltage is greater than 70V;

[0077] The low potential constant voltage source is the ground terminal.

[0078] In order to enhance the load carrying capacity of the shift register, a first storage capacitor C3 is added between the drain of the third transistor T3 and the low potential constant voltage source VSS, and a second storage capacitor C4 is added between the gate of the sixth transistor and the low potential constant voltage source VSS, which simultaneously enhances the register's ability to store input signals and filters out voltage fluctuations in the circuit; Figure 4This is a simulation waveform diagram of the shift register unit of the present invention. It can be seen that compared with the simulation waveform diagram of the existing shift register unit, the output waveform of the present invention is smoother, the rising edge and the falling edge are steeper, and the input signal can be completely shifted and registered for one cycle, and the outputs of adjacent stages of shift registers will not overlap. However, the existing patent can only shift and register the input signal for half a cycle, and the outputs of adjacent stages of shift registers will overlap.

[0079] like Figure 5 As shown, based on the above embodiments, this embodiment adds:

[0080] The third control switch T9 is connected between the high potential constant voltage source and the input terminal of the second inverter. The third control switch is turned on or off under the control of a reset signal RESET, so that the shift register unit of the present invention has a reset function.

[0081] The simulation waveform is as follows Figure 6 As shown, the serial-in-parallel-out shift register unit circuit outputs a high level of approximately 74V and an output low level of approximately 4V.

[0082] The working process of the serial-in parallel-out shift register unit includes:

[0083] First, in static state, T1, T2, T4, and T5 are always in saturation state.

[0084] In the AB phase (i.e., the first phase), the reset signal RESET is high, T9 is turned on, the high potential constant voltage source VDD charges the second storage capacitor C4, the voltage across C4 becomes high, the gate of T6 is high, T6 is turned on, and the output O is low level VSS.

[0085] In the BC stage (i.e., the second stage), the reset signal RESET is at a low level, and T9 is closed; the clock signal CLKA is at a high level, T7 is turned on, the input signal IN is at a low level, T3 is closed, and the Q point level gradually increases. Due to the bootstrap effect of the bootstrap capacitor C1, the T2 gate voltage gradually increases, T2 changes from a saturated state to an unsaturated state, the Q point voltage becomes a high level VDD, and the voltage across the capacitor C3 also becomes a high potential constant voltage source VDD; the clock signal CLKB is at a low level, T8 is closed, the voltage across C4 is still at a high level, T6 is turned on, and the output O is still a low level VSS.

[0086] In the CD stage (i.e., the third stage), the reset signal RESET is at a low level, T9 is turned off; the clock signal CLKA is at a low level, T7 is turned off, and the states of T1, T2, and T3 remain unchanged; the clock signal CLKB is at a high level, T8 is turned on, the first storage capacitor C3 charges C4 through T8, the voltage across C4 is still at a high level, the gate of T6 is at a high level, T6 is turned on, and the output O is still at a low level VSS.

[0087] In the DE stage (i.e. the fourth stage), the reset signal RESET is at a low level and T9 is closed; the clock signal CLKA is at a high level, T7 is turned on, the input signal IN is at a high level, T3 is turned on, and VSS charges C3 to a low level; the clock signal CLKB is at a low level, T8 is closed, the voltage across C4 is still at a high level, the states of T4, T5, and T6 remain unchanged, and the output O is still at a low level VSS.

[0088] In the EF stage (i.e., the fifth stage), the reset signal RESET is at a low level, T9 is turned off; the clock signal CLKA is at a low level, T7 is turned off, and the states of T1, T2, and T3 remain unchanged; the clock signal CLKB is at a high level, T8 is turned on, C3 charges C4 to a low level through T8, the gate voltage of T6 becomes a low level, T6 is turned off, and the output O level gradually increases. Due to the bootstrap effect of capacitor C2, the gate voltage of T5 gradually increases, T5 changes from a saturated state to a non-saturated state, and the output O changes to a high level VDD.

[0089] In the FG stage (i.e., the sixth stage), the reset signal RESET is at a low level, and T9 is closed; the clock signal CLKA is at a high level, T7 is turned on, the input signal IN is at a low level, T3 is closed, and the Q point level gradually increases. Due to the bootstrap effect of the bootstrap capacitor C1, the T2 gate voltage gradually increases, T2 changes from a saturated state to an unsaturated state, the Q point voltage becomes a high level VDD, and the voltage across the capacitor C3 also becomes a high level VDD; the clock signal CLKB is at a low level, T8 is closed, the voltage across C4 is still at a low level, the states of T4, T5, and T6 remain unchanged, and the output O is a high level VDD.

[0090] In the GH stage (i.e. the seventh stage), the reset signal RESET is at a low level, T9 is turned off; the clock signal CLKA is at a low level, T7 is turned off, the states of T1, T2 and T3 remain unchanged, and the voltage across C3 is still at a high level VDD; the clock signal CLKB is at a high level, T8 is turned on, C3 charges C4 to a high level through T8, the gate voltage of T6 becomes a high level, T6 is turned on, and the output O becomes a low level VSS.

[0091] In the HI stage (i.e. the eighth stage), the process is the same as that in the BC stage and will not be repeated here.

[0092] Please refer to Figure 7This embodiment provides a parallel-in serial-out shift register unit, which adds the following components to the above serial-in parallel-out shift register unit:

[0093] A fourth control switch T13, arranged between the external input signal and the first control switch;

[0094] A fifth control switch T14, arranged between a preset signal SET and the first control switch;

[0095] The third inverter P3 has the same configuration as the first inverter and / or the second inverter, the high level end of the third inverter is commonly connected to the high potential constant voltage source, the low level end is commonly connected to the low potential constant voltage source, the input end is connected to an enable signal EN, and the output end is connected to the control end of the fourth control switch; wherein

[0096] The fourth control switch is turned on or off by receiving the signal output by the third inverter;

[0097] The fifth control switch is turned on or off under the control of the enable signal.

[0098] The simulation waveform is as follows Figure 8 As shown, the output high level of the parallel-in-serial-out shift register unit circuit is about 74V, and the output low level is about 4V.

[0099] The working process of the parallel-in serial-out shift register unit includes:

[0100] First, in static state, T1, T2, T4, T5, T10, and T11 are always in saturation state.

[0101] In the AB phase (i.e., the first phase), the reset signal RESET is high, T9 is turned on, the high potential constant voltage source VDD charges the capacitor C4, the voltage across C4 becomes high, the gate of T6 is high, T6 is turned on, and the output O is low level VSS.

[0102] In the BC stage (i.e., the second stage), the reset signal RESET is at a low level, and T9 is closed; the clock signal CLKA is at a high level, T7 is turned on, the enable signal EN is at a high level, T13 is turned on, T12 is turned on, and point P is at a low level VSS, that is, the gate of T14 is at a low level, T14 is turned off, and the transmission of the input signal IN is blocked, while the SET signal can be transmitted to the gate of T3 through T13 and T7 in sequence, and the SET signal is at a high level, then T3 is turned on, and VSS charges the capacitor C3 to a low level through T3; the clock signal CLKB is at a low level, T8 is turned off, the voltage across C4 is still at a high level, T6 is turned on, and the output O is still at a low level VSS.

[0103] In the CD stage (i.e. the third stage), the reset signal RESET is at a low level, T9 is turned off; the clock signal CLKA is at a low level, T7 is turned off, and the states of T1, T2 and T3 remain unchanged; the clock signal CLKB is at a high level, T8 is turned on, C3 charges C4 through T8, the voltage across C4 becomes low, the gate of T6 becomes low, T6 is turned off, and the output O level gradually increases. Due to the bootstrap effect of the bootstrap capacitor C2, the gate voltage of T5 gradually increases, T5 changes from a saturated state to a non-saturated state, and the output O becomes a high level VDD.

[0104] In the DE stage (i.e., the fourth stage), the reset signal RESET is at a low level, and T9 is closed; the clock signal CLKA is at a high level, T7 is turned on, the input control signal EN is at a low level, T13 is closed, the transmission of the SET signal is blocked, T12 is closed, and the level at point P gradually increases. Due to the bootstrap effect of capacitor C5, the gate voltage of T11 gradually increases, T11 changes from a saturated state to an unsaturated state, the voltage at point P becomes a high level VDD, the gate voltage of T14 is also at a high level, T14 is turned on, and the input signal IN is transmitted to the gate of T3 through T14 and T7 in turn. Because IN is at a low level, T3 is closed, and the level at point Q gradually increases. Due to the bootstrap effect of capacitor C1, the gate voltage of T2 gradually increases, T2 changes from a saturated state to an unsaturated state, the voltage at point Q becomes a high level VDD, and the voltage across capacitor C3 also becomes a high level VDD; the clock signal CLKB is at a low level, T8 is closed, the voltage across C4 is still at a low level, the states of T4, T5, and T6 remain unchanged, and the output O is still a high level VDD.

[0105] In the EF stage (i.e. the fifth stage), the reset signal RESET is at a low level, T9 is turned off; the clock signal CLKA is at a low level, T7 is turned off, and the states of T1, T2 and T3 remain unchanged; the clock signal CLKB is at a high level, T8 is turned on, C3 charges C4 to a high level through T8, the gate voltage of T6 becomes a high level, T6 is turned on, and the output O becomes a low level VSS.

[0106] In the FG stage (i.e. the sixth stage), the process is the same as that in the DE stage and will not be repeated here.

[0107] The present invention also provides a serial-in-parallel-out shift register comprising multiple stages of the above-mentioned serial-in-parallel-out shift register units:

[0108] Please refer to Fig. 9 , Fig. 9It is a five-stage serial-in parallel-out shift register. Five serial-in parallel-out shift register units are connected in sequence. The input end of the first-stage shift register unit is connected to an input signal. The output end of the previous-stage shift register unit is connected to the input end of the next-stage shift register unit. The output end of each stage of the shift register unit is output in parallel and a measurement port is led out at the same time. VDD is connected to a high-potential constant voltage source, VSS is connected to a low-potential constant voltage source, CLKA and CLKB are two clock signals with the same period and pulse width but not at the same high level at the same time. IN is a serial input signal, and RESET is a reset signal.

[0109] Please refer to Figure 10. The output high level of the five-stage serial-in-parallel-out shift register circuit is about 73V, and the output low level is about 4.5V. However, there is a slight drop in the middle of the high-level signal. The reason is that at this time, the signal needs to be transmitted to the next-level register, that is, charging.

[0110] The present invention also provides a parallel-in serial-out shift register comprising multiple stages of the above-mentioned parallel-in serial-out shift register units:

[0111] Please refer to Fig.11 , Fig.11 It is a five-stage parallel-in-serial-out shift register, and five parallel-in-serial-out shift register units are connected in sequence. The input end of the first-stage shift register unit is connected to an input signal, the output end of the previous-stage shift register unit is connected to the input end of the next-stage shift register unit, and the output end of the last-stage shift register unit constitutes the output end of the parallel-in-serial-out shift register, and the input end of each stage of the shift register unit is paralleled with a preset signal for input, and a measurement port is led out at the output end of the last stage. VDD is connected to a high-potential constant voltage source, VSS is connected to a low-potential constant voltage source, CLKA and CLKB are two clock signals with the same period and pulse width, but not at the same time at a high level, IN is not used (can be directly grounded), EN is an enable signal, D1-D5 are preset numbers, and RESET is a reset signal.

[0112] The parallel-in serial-out shift register circuit is a synchronous setting circuit. The preset number can only be stored in the shift register when EN and CLKA are both high.

[0113] Please refer to Fig.12 The output high level of the fifth-stage parallel-in-serial-out shift register circuit is about 73V, and the output low level is around 4V. Similarly, there will be a slight drop in the middle of the high-level signal. The reason is that at this time, the signal needs to be transmitted to the next-level register, that is, charging.

[0114] Integrating the above-mentioned serial-in-parallel-out shift register or parallel-in-serial-out shift register on the microfluidic chip driving circuit facilitates the driving and testing of the microfluidic chip. The high operating voltage of the shift register provides a high driving voltage option for the microfluidic chip.

[0115] Obviously, the above embodiments are merely examples for the purpose of clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the present invention.

Claims

1. A shift register unit, characterized in that: include; A first inverter is configured such that when a high level signal is input to an input terminal of the first inverter, a low level signal is output at an output terminal thereof; A second inverter having the same configuration as the first inverter, and The first inverter and the second inverter have a high-level terminal commonly connected to a high-potential constant-voltage source and a low-level terminal commonly connected to a low-potential constant-voltage source; a first storage capacitor, a positive electrode of which is connected to the output end of the first inverter, and a negative electrode of which is connected to the low potential constant voltage source; a second storage capacitor, a positive electrode of which is connected to the input terminal of the second inverter, and a negative electrode of which is connected to the low potential constant voltage source; A first control switch is provided between an input terminal of the first inverter and an external input signal, and the first control switch is turned on or off under the control of a first clock signal; a second control switch, arranged between the output terminal of the first inverter and the input terminal of the second inverter, the second control switch being turned on or off by the control of the second clock signal, and The first clock signal and the second clock signal differ in phase by 180°.

2. The shift register unit according to claim 1, characterized in that: The shift register unit is a serial-in parallel-out shift register unit.

3. The shift register unit according to claim 1, characterized in that: The shift register unit is a parallel-in serial-out shift register unit, and the parallel-in serial-out shift register unit further includes: a fourth control switch, arranged between the external input signal and the first control switch; a fifth control switch, arranged between a preset signal and the first control switch; The third inverter has the same configuration as the first inverter and / or the second inverter, the high level end of the third inverter is commonly connected to the high potential constant voltage source, the low level end is commonly connected to the low potential constant voltage source, the input end is connected to an enable signal, and the output end is connected to the control end of the fourth control switch; wherein The fourth control switch is turned on or off by receiving the signal output by the third inverter; The fifth control switch is turned on or off under the control of the enable signal.

4. The shift register unit according to claim 2 or 3, characterized in that: The first inverter and the second inverter have the same circuit structure, either of which includes: A first transistor, a gate and a drain of which are connected to the high level end; a second transistor, a drain of which is connected to the high level end, and a gate of which is connected to the source of the first transistor; a third transistor, whose gate constitutes the input terminal of the inverter, whose drain is connected to the source of the second transistor and constitutes the output terminal of the inverter, and whose source is connected to the low potential constant voltage source; The bootstrap capacitor is connected between the gate and the source of the second transistor.

5. The shift register unit according to claim 2 or 3, characterized in that: The high potential constant voltage source is a voltage source, and its output voltage is greater than 70V.

6. The shift register unit according to claim 2 or 3, characterized in that: The low potential constant voltage source is the ground terminal.

7. The shift register unit according to claim 2 or 3, characterized in that: It also includes a third control switch connected between the high potential constant voltage source and the input end of the second inverter, and the third control switch is controlled by a reset signal to be turned on or off.

8. A serial-in parallel-out shift register, characterized in that: It comprises a plurality of shift register units as described in any one of claims 2 or 4-7, wherein the input end of the first stage shift register unit of the serial-in-parallel-out shift register is connected to an input signal, the output end of the previous stage shift register unit is connected to the input end of the next stage shift register unit, and the output end of each stage shift register unit is output in parallel.

9. A parallel-in serial-out shift register, characterized in that: It comprises a plurality of shift register units as described in any one of claims 3 to 7, wherein the input end of the first stage shift register unit of the parallel-in-serial-out shift register is connected to an input signal, the output end of the previous stage shift register unit is connected to the input end of the next stage shift register unit, the output end of the last stage shift register unit constitutes the output end of the parallel-in-serial-out shift register, and the input end of each stage shift register unit is parallelly input with a preset signal.

10. A digital microfluidic chip driving circuit, characterized in that: It includes the serial-in-parallel-out shift register described in claim 8 or the parallel-in-serial-out shift register described in claim 9.

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