Transistor structure, gate driving circuit, driving method thereof, and display panel

Abstract

The present application provides a transistor structure, a gate driving circuit, a driving method thereof, and a display panel. Among them, the transistor structure includes a transistor and a plurality of gate lines electrically connected to the transistor; the transistor includes a semiconductor layer, a source electrode and a drain electrode disposed on the semiconductor layer, the source electrode is connected to the source region of the semiconductor layer, the drain electrode is connected to the drain region of the semiconductor layer, and the transistor further includes a plurality of gates corresponding to the channel region of the semiconductor layer, and the plurality of gates are spaced apart in the length direction of the source electrode and the drain electrode; wherein, the plurality of gates are respectively connected to the plurality of gate lines in one-to-one correspondence. The technical solution of the present application can compensate and adjust the transistor after the working environment temperature changes, and avoid abnormal display.

Description

Technical Field

[0001] The present application relates to the field of display driving technology, and particularly relates to a transistor structure, a gate driving circuit, a driving method thereof, and a display panel. Background Art

[0002] In the display field, display products usually face a working environment with a relatively large temperature change range. Especially for transistors, when the working environment temperature changes, the voltage threshold of the transistors often drifts. And the drift of the voltage threshold easily causes display anomalies.

[0003] The above information disclosed in the background art section is only used to enhance the understanding of the background mainly acting on reducing the present application, so it may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0004] An object of the present application is to provide a transistor structure, a gate driving circuit, a driving method thereof, and a display panel, which can compensate and adjust the transistors after the working environment temperature changes to avoid display anomalies.

[0005] The present application provides a transistor structure, which includes a transistor and a plurality of gate lines electrically connected to the transistor; the transistor includes a semiconductor layer, a source electrode and a drain electrode disposed on the semiconductor layer, the source electrode is connected to the source region of the semiconductor layer, and the drain electrode is connected to the drain region of the semiconductor layer.

[0006] The transistor further includes a plurality of gates corresponding to the channel region of the semiconductor layer, and the plurality of gates are spaced apart in the length direction of the source electrode and the drain electrode; wherein, the plurality of gates are respectively connected to the plurality of gate lines in one-to-one correspondence.

[0007] In one aspect, the drain electrode includes a first line segment, a second line segment and a connecting line segment, and the first line segment, the connecting line segment and the second line segment are sequentially connected to form a U-shaped line, and the source electrode is spaced between the first line segment and the second line segment.

[0008] In one aspect, the lengths of the first line segment and the second line segment are equal, and the distances between the source electrode and the first line segment, and between the source electrode and the second line segment are equal.

[0009] In one aspect, a plurality of the transistors are provided and are arranged in sequence in a direction perpendicular to the length direction of the source electrode.

[0010] In one aspect, in two adjacent transistors: the first line segment of the drain electrode of one transistor and the second line segment of the drain electrode of the other transistor are the same line segment.

[0011] In one aspect, there are at least two adjacent transistors in a direction perpendicular to the length direction of the source electrode. The two adjacent transistors are spaced apart and distributed. The transistor structure further includes a plurality of spaced gate lines, which are disposed between the transistors with spaced distribution, and the spaced gate lines are connected to the gates of the adjacent transistors.

[0012] In one aspect, the semiconductor layer includes at least one metal oxide layer.

[0013] To solve the above problems, the present application further provides a gate driving circuit, which includes at least one transistor structure as described above.

[0014] In one aspect, the gate driving circuit includes a pull-up control module, a pull-up module, a pull-down control module, and a pull-down module; the pull-up control module is used to access an input signal, and the pull-up module is used to access a clock signal; wherein, the pull-up control module and the pull-up module include at least one transistor structure as described above.

[0015] To solve the above problems, the present application further provides a driving method for a gate driving circuit. The gate driving circuit includes at least one transistor structure as described above. The driving method for the gate driving circuit includes:

[0016] Detecting the ambient temperature of the gate driving circuit;

[0017] Determining a predetermined enabled number of the gates based on the ambient temperature;

[0018] Inputting a gate signal to a predetermined enabled number of the gates through the predetermined enabled number of the gate lines to control the transistor structure to turn on or off.

[0019] In one aspect, the enabled number of the predetermined gate lines is negatively correlated with the ambient temperature.

[0020] To solve the above problems, the present application further provides a display panel. The display panel includes a display area and a non-display area. The display panel further includes a gate driving circuit. The gate driving circuit includes a transistor structure as described above. The gate driving circuit is disposed in the non-display area. The display panel further includes a temperature detector and a controller. The controller is connected to the gate lines, and the controller is further connected to the temperature detector. The temperature detector is used to detect the ambient temperature of the gate driving circuit, and the controller controls the enabled number of the gates based on the ambient temperature.

[0021] The present application provides a transistor structure, a gate driving circuit, a driving method thereof, and a display panel, which can adjust the aspect ratio of the transistor structure, thereby effectively supplementing and adjusting the electrical performance of the transistor structure and avoiding abnormal display.

[0022] It should be understood that the above general description and the following detailed description are exemplary and do not limit the present application. Description of the Drawings

[0023] By referring to the accompanying drawings and describing its exemplary embodiments in detail, the above and other objects, features, and advantages of the present application will become more apparent.

[0024] Figure 1 It is a schematic structural diagram of a transistor in the first embodiment of the present application.

[0025] Figure 2 In the present application Figure 1 It is a schematic cross-sectional structural diagram of a transistor.

[0026] Figure 3 In the present application Figure 1 It is a schematic structural diagram of a source electrode and a drain electrode.

[0027] Figure 4 In the present application Figure 1 It is a schematic diagram of the path through which current flows.

[0028] Figure 5 In the present application Figure 1 It is a schematic structural diagram of a plurality of transistors distributed in a direction perpendicular to the length of the source electrode.

[0029] Figure 6 It is a schematic connection diagram of a gate driving circuit in the second embodiment of the present application.

[0030] Figure 7 It is a flowchart of the process steps of a gate circuit driving method in the third embodiment of the present application.

[0031] Figure 8 It is a schematic structural diagram of a display device in the fourth embodiment of the present application.

[0032] The description of the reference numerals is as follows:

[0033] 10. Substrate; 20. Transistor; 30. Gate line; 40. Display panel; 50. Spacing gate line; 60. Pull-up control module; 70. Pull-up module; 80. Pull-down control module; 90. Pull-down module;

[0034] 210. Semiconductor layer; 230. Gate; 240. Insulating layer; 211. Channel region; 221. Source; 222. Drain; 222a. First line segment; 222b. Second line segment; 222c. Connecting line segment; 331. Main control gate line; 332. Compensation gate line; 410. Display area; 420. Non-display area; T1. First transistor switch; T2. Second transistor switch; T3. Third transistor switch; T4. Fourth transistor switch; C. Capacitor. Detailed implementation manners

[0035] Although the present application can be easily embodied in different forms of embodiments, only some specific embodiments are shown in the drawings and will be described in detail in this specification. At the same time, it can be understood that this specification should be regarded as a demonstration of the principles of the present application and is not intended to limit the present application to what is described herein.

[0036] Therefore, a feature pointed out in this specification will be used to illustrate one of the features of one embodiment of the present application, rather than implying that each embodiment of the present application must have the described feature. In addition, it should be noted that this specification describes many features. Although some features can be combined to show possible system designs, these features can also be used in other combinations that are not explicitly described. Therefore, unless otherwise stated, the described combinations are not intended to be limiting.

[0037] In the embodiments shown in the drawings, the indication of directions (such as up, down, left, right, front and back) is used to explain that the structures and movements of various elements of the present application are not absolute but relative. When these elements are in the positions shown in the drawings, these explanations are appropriate. If the description of the positions of these elements changes, then the indication of these directions also changes accordingly.

[0038] Now, example embodiments will be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these example embodiments are provided so that the description of the present application will be more complete and comprehensive, and the concept of the example embodiments will be fully conveyed to those skilled in the art. The drawings are only schematic illustrations of the present application and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus repeated descriptions thereof will be omitted.

[0039] The following will further elaborate in detail on the preferred embodiments of the present application with reference to the drawings of this specification.

[0040] Embodiment 1

[0041] Refer to Figure 1 and Figure 2As shown in the figure, the present application provides a transistor structure, which includes a transistor and multiple gate lines electrically connected to the transistor; the transistor includes a TFT (Thin Film Transistor) switch. The TFT switch has the advantages of high responsiveness, high brightness, and high contrast. Generally, the transistor is disposed on a substrate 10, and the substrate 10 can be understood as a transparent base material, such as silicon dioxide.

[0042] The transistor 20 includes a semiconductor layer 210, a source electrode 221, and a drain electrode 222 disposed on the semiconductor layer 210. The source electrode 221 is connected to the source region of the semiconductor layer 210, and the drain electrode 222 is connected to the drain region of the semiconductor layer 210. The semiconductor layer 210 refers to the active layer of the transistor. The semiconductor layer 210 includes at least one metal oxide layer, such as indium gallium zinc oxide (IGZO) generally. IGZO is an amorphous oxide containing indium, gallium, and zinc, and the carrier mobility is 20 - 30 times that of amorphous silicon, which can greatly improve the charge and discharge rate of the TFT switch to the electrodes, improve the response speed, achieve a faster refresh rate, and at the same time, the faster response also greatly improves the row scanning rate of the pixels.

[0043] The source electrode 221 and the drain electrode 222 are spaced apart and disposed on the semiconductor layer 210. The source electrode 221 is connected to the source region of the semiconductor layer 210, and the drain electrode 222 is connected to the drain region of the semiconductor layer 210.

[0044] The transistor 20 further includes multiple gate electrodes 230 disposed corresponding to the channel region 211 of the semiconductor layer 210. The multiple gate electrodes 230 are spaced apart in the length direction of the source electrode 221 and the drain electrode 222; wherein, the multiple gate electrodes 230 are respectively and correspondingly connected to multiple gate lines 30. That is to say, each gate electrode 230 of the transistor 20 is connected to a control line, and this control line is the gate line 30. The gate line 30 is used to connect to a processor, and the processor realizes switch control of the transistor 20 through the gate line 30. The multiple gate electrodes 230 are spaced apart in the length direction of the source electrode 221 and the drain electrode 222, and the orthographic projection of the gate electrode 230 on the substrate 10 covers the orthographic projection of the channel region 211 of the semiconductor layer 210 on the substrate 10, ensuring that the magnetic field formed by the gate electrode 230 can cover the channel region 211 of the semiconductor layer 210. Generally, in order to improve the driving accuracy, the gate electrode 230 covers the area of the semiconductor layer 210, and the coverage area of the gate electrode 230 can also be larger than the orthographic projection of the channel region 211 of the semiconductor layer 210 on the substrate 10. The gate electrode 230 is used to control the conduction between the drain electrode 222 and the source electrode 221. When the gate electrode 230 is powered on, a magnetic field is generated, and the magnetic field acts on the semiconductor layer 210, thereby making the drain electrode 222 and the source electrode 221 conductive.

[0045] Among them, the multiple gate lines 30 include a main control gate line 331 and at least one compensation gate line 332. The enabled number of the at least one compensation gate line 332 is determined based on the ambient temperature. When the ambient temperature is relatively high, only the main control gate line 331 can be turned on. When the ambient temperature is relatively low, a certain number of compensation gate lines 332 are enabled. By enabling the compensation gate lines 332, the aspect ratio of the transistor 20 is compensated, and the aspect ratio of the transistor 20 is increased. That is to say, in this embodiment, the aspect ratio of the transistor 20 can be adjusted according to the needs of the ambient temperature.

[0046] It should be emphasized that in the art, the channel width of the transistor 20 is greater than the channel length, and generally the ratio of the channel width to the channel length is greater than 1.

[0047] In the technical solution of this embodiment, the transistor structure provided by the present application can realize the adjustment of the aspect ratio of the transistor structure, so as to effectively supplement and adjust the electrical performance of the transistor structure and avoid display anomalies.

[0048] Specifically, a semiconductor layer 210 is disposed between the source 221 and the drain 222, and the semiconductor layer 210 forms a channel region 211. The width of the channel region 211 is along the length direction of the source 221 in the channel region 211, and the length of the channel region 211 is along the distance between the source 221 and the drain 222 in the channel region 211. When the gate is powered on, a magnetic field is generated, and the magnetic field acts on the semiconductor layer 210, so that a corresponding section of the semiconductor layer 210 is turned on. When the gate is powered on, the current flows through the channel region 211 corresponding to the main control gate line 331. When the ambient temperature changes, the compensation gate line 332 can be turned on or off, so that the path of the current flowing through the channel region 211 corresponding to the compensation gate line 332 also changes. That is, under the influence of the compensation gate line 332 being turned on or off, the length of the current flowing through the channel region 211 changes. It can be seen that in this embodiment, the aspect ratio of the transistor 20 can be controlled by enabling the number of compensation gate lines 332. Subsequently, after the working ambient temperature changes, the transistor 20 is compensated and adjusted to avoid display anomalies.

[0049] Refer to Figure 3As shown, in order to further increase the aspect ratio of the transistor 20, the drain 222 includes a first line segment 222a, a second line segment 222b, and a connecting line segment 222c. The first line segment 222a, the connecting line segment 222c, and the second line segment 222b are connected in sequence to form a U-shaped line. The source 221 is disposed between the first line segment 222a and the second line segment 222b, and the semiconductor layer 210 is located between the source 221 and the U-shaped line. In the path formed by the semiconductor layer 210, a U-shaped drain region matching the drain 222 and a linear source region matching the source 221 are also formed. The distance between the drain 222 and the source 221 is fixed. That is to say, the length of the channel is constant. By arranging the semiconductor layer 210 in a U-shaped line, compared with the semiconductor layer 210 arranged along the length direction of the source 221 on one side, the path passed by the semiconductor layer 210 is increased. The width of the channel region 211 is increased exponentially. The distance between the first line segment 222a and the source 221 remains unchanged, that is, the length of the channel region 211 remains unchanged. Therefore, by simply increasing the width of the channel region 211, the aspect ratio of the channel region 211 of the transistor 20 is increased.

[0050] Among them, when manufacturing the transistor, the source 221, the drain 222, and the semiconductor layer 210 are all straight lines. When arranging the transistor 20, the path jointly passed by the source 221, the drain 222, and the semiconductor layer 210 is divided into multiple control regions, and a gate 230 is arranged in each control region, thereby forming the transistor 20.

[0051] It should be noted that in this embodiment, increasing the aspect ratio of the transistor 20 is to increase the effective aspect ratio, that is, to increase the width of the channel region through which current flows. Refer to Figure 4 As shown, where the dotted arrow is the path of current flow. It can be seen that when the main control gate line 331 is energized, the current passes through the semiconductor path corresponding to the main control gate line 331. At this time, the aspect ratio of the transistor 20 is W 0 / L. The three compensation gate lines 332 are energized in sequence. When the adjacent first compensation gate line 332 is energized, the increased aspect ratio is W 1 / L. Then the total effective aspect ratio of the transistor 20 at this time is, W 0 / L + W 1 / L. When the second compensation gate line 332 is energized, the increased aspect ratio is W 2 / L. Then the total effective aspect ratio of the transistor 20 at this time is, W 0 / L + W 1 / L + W 2 / L. When the third compensation gate line 332 is energized, the increased aspect ratio is W 3 / L. Then the total effective aspect ratio of the transistor 20 at this time is, W 0 / L + W1 / L + W 2 / L + W 3 / L. In this way, the effective width-to-length ratio W / L of the transistor 20 increases as the activation of the compensation gate line 332 increases.

[0052] To reduce signal anomalies and for ease of processing, the lengths of the first line segment 222a and the second line segment 222b are equal, and the distances between the source electrode 221 and the first line segment 222a and between the source electrode 221 and the second line segment 222b are equal. In this way, the distances from the left and right sides of the source electrode 221 to the drain electrode 222 are equal. Compared with the setting of only the first line segment 222a and the source electrode 221, the setting of the second line segment 222b and the source electrode 221 is added, and the width of the channel region 211 is increased by at least twice. In addition, the length of the channel region 211 is also ensured to be consistent before and after on the extension path.

[0053] In some high-resolution refresh displays, a relatively large drive current is usually required. For this reason, multiple transistors 20 are provided and arranged in sequence in the length direction perpendicular to the source electrode 221. Each drain electrode 222 forms a U-shaped line, and the source electrode 221 is disposed in the U-shaped line. These source electrodes 221 and drain electrodes 222 can share an input line and an output line. By providing multiple transistors 20, the current flowing in the input line can be increased. In this way, for high-resolution refresh displays, this embodiment can provide a relatively large drive current to meet the usage requirements.

[0054] Refer to Figure 5 As shown, to make full use of the layout space of the transistor structure, in two adjacent transistors 20, the adjacent first line segment 222a and the second line segment 222b are the same line segment. It can also be understood that the first line segment 222a and the second line segment 222b of two adjacent transistors 20 overlap. In this way, when two transistors 20 are arranged adjacent to each other, when the second line segment 222b of one transistor 20 conducts current, the adjacent other transistor 20 is also working, and the second line segment 222b of the previous transistor 20 can also be used to conduct current. In this way, at least the layout position of one line segment is saved. By analogy, when multiple transistors 20 are provided, more transistors 20 can be arranged by saving space, or the area of the entire gate driving circuit can be reduced, thereby achieving a narrow border.

[0055] In addition, the transistor structure generates a large amount of heat during operation. To reduce the impact of heat on the structure and improve the heat dissipation effect of the structure, at least two adjacent transistors 20 are provided in the length direction perpendicular to the source electrode 221, and the two adjacent transistors 20 are spaced apart. The transistor structure further includes a plurality of spaced gate lines 50 disposed between the spaced transistors 20, and the spaced gate lines 50 are connected to the gate electrodes 230 of the adjacent transistors 20. There is a certain distance between the transistors 20, which avoids heat accumulation caused by overly close arrangement. The spaced gate lines 50 are connected to each transistor 20. Moreover, to ensure that the transistors 20 distributed in the path direction perpendicular to the source electrode 221 are uniformly controlled, the spaced gate lines 50 are all connected to the corresponding main control gate line 331 and compensation gate line 332.

[0056] Thus, when the main control gate line 331 is activated, through the setting of the spaced gate lines 50, the transistors 20 in the path direction perpendicular to the source electrode 221 are all turned on. Similarly, when the compensation gate line 332 is activated, through the setting of the spaced gate lines 50, the transistors 20 in the path direction perpendicular to the source electrode 221 are also all turned on.

[0057] It should be noted that a number of transistors 20 can be closely arranged. A number of transistors 20 form a group, and multiple groups can be provided. For example, three transistors 20 form a group, and a spaced gate line 50 is provided between each group.

[0058] In addition, the spaced gate line 50 can also be separately connected to a control terminal, so that individual control of the transistors 20 in each group can be achieved.

[0059] There are at least two wiring methods for the transistors 20.

[0060] The first one is the bottom gate. The gate electrode 230 is disposed on the side of the semiconductor layer 210 close to the substrate 10, and an insulating layer 240 is provided between the gate electrode 230 and the semiconductor layer 210. Among them, the source electrode 221 is directly in contact with the source region of the semiconductor layer 210, and the drain electrode 222 is directly in contact with the drain region of the semiconductor layer 210. In this setting method, the gate electrode 230 is first provided on the substrate 10, that is, the gate electrode 230 is provided at the bottom. The insulating layer 240 is provided on the gate electrode 230. Generally, the material of the insulating layer 240 is silicon dioxide. The semiconductor layer 210 is provided on the insulating layer 240, that is, the semiconductor layer 210 is formed on the insulating layer 240. The source electrode 221 and the drain electrode 222 are further provided on the semiconductor layer 210, thereby completing the structure setting of the first type of transistor 20. In this way, the gate electrode 230 can block the light incident on the semiconductor layer 210 and reduce the influence of the light on the semiconductor layer 210.

[0061] The second type is the top gate. The semiconductor layer 210 is disposed on the substrate 10. The transistor further includes an insulating layer 240 disposed between the gate 230 and the semiconductor layer 210. The source electrode 221 and the drain electrode 222 are respectively provided with extension lines that penetrate the insulating layer 240 and are connected to the semiconductor layer 210. In this setting method, the semiconductor layer 210 is first disposed on the substrate 10, the insulating layer 240 is disposed on the semiconductor layer 210, and the gate 230 is disposed on the insulating layer 240, that is, the gate is disposed on the insulating layer 240. The source electrode 221 and the drain electrode 222 are disposed above the gate 230. Among them, the gate 230 is insulated from the source electrode 221 and the drain electrode 222. And in order to ensure the connection between the source electrode 221 and the drain electrode 222 and the semiconductor layer 210, two through holes are provided in the insulating layer 240. One through hole corresponds to the source electrode 221 and the semiconductor layer 210, and the other through hole corresponds to the drain electrode 222 and the semiconductor layer 210. Extension lines are provided in the through holes. One extension line connects the source electrode 221 and the semiconductor layer 210, and the other extension line connects the drain electrode 222 and the semiconductor layer 210.

[0062] Embodiment 2

[0063] Refer to Figure 6 As shown, this embodiment further provides a gate driving circuit, and the gate driving circuit includes at least one transistor structure as described above.

[0064] Specifically, the gate driving circuit includes a pull-up control module 60, a pull-up module 70, a pull-down control module 80, and a pull-down module 90; the pull-up control module 60 is used to access an input signal, and the pull-up module 70 is used to access a clock signal; among them, the pull-up control module 60 and the pull-up module 70 include at least one transistor structure as described above. The pull-up control module 60 includes a first transistor switch T1 and a signal input terminal input; the pull-up module 70 includes a third transistor switch T3 and a clock signal terminal CK. The pull-down control module 80 includes a second transistor switch T2 and a reset voltage terminal Vgl. The pull-down module 90 includes a fourth transistor switch T4 and a reset terminal Reset.

[0065] The transistor 20 in the gate driving circuit generally refers to a transistor 20 with a large width-to-length ratio. In a gate driving circuit, the transistors of the first transistor switch T1 and the third transistor switch T3 have a large width-to-length ratio, for example, the width-to-length ratio is greater than 100. The first transistor switch T1 and the third transistor switch T3 are prone to threshold voltage shift due to temperature influence. Through this embodiment, the first transistor switch T1 and the third transistor switch T3 can be set as the transistors mentioned above. The adjustable width-to-length ratio of the transistor is realized.

[0066] When the input of the signal input terminal is at a high level, the first transistor switch T1 is turned on, the capacitor C is charged, and the third transistor switch T3 is turned on under the action of the high level. The clock signal is loaded on the capacitor C, and the control signal is output through the output terminal Gn. After the control signal is output, the reset terminal Reset outputs a high level, and the second transistor switch T2 and the fourth transistor switch T4 are turned on, and the voltage at both ends of the capacitor C is reset to the voltage of the reset voltage terminal Vgl.

[0067] Embodiment 3

[0068] Refer to Figure 7 As shown, the present application also provides a driving method for a gate driving circuit. The driving method of the gate driving circuit applies the transistor structure as described above. The driving method of the gate driving circuit includes:

[0069] Step S10, detecting the ambient temperature of the gate driving circuit. The gate driving circuit can be connected to a temperature detector to detect the ambient temperature of the gate driving circuit through the temperature detector and feed back the detected ambient temperature to the processor.

[0070] Step S20, determining the predetermined number of enabled gates based on the ambient temperature. The processor determines the number of gates to be started in advance according to the ambient temperature.

[0071] Step S30, inputting gate signals to the predetermined number of gates through the predetermined number of gate lines to control the opening or closing of the transistor structure. As the number of starts increases or decreases, the aspect ratio of the transistor increases or decreases accordingly.

[0072] Specifically, obtain the main control signal and start the main control gate line 331 according to the main control signal; connect the power supply through the main control signal of the main control gate line 331 to ensure that the source 221 and the drain 222 in the transistor 20 corresponding to the main control gate line 331 are continuously connected. That is to say, the main control gate line 331 is always open to ensure the basic signal transmission requirements.

[0073] Detect the ambient temperature of the detection pole driving circuit, and determine the number of enabled compensation gate lines 332 based on the ambient temperature. Thus, the number of enabled compensation gate lines 332 is determined according to the ambient temperature. The gate driving circuit is sensitive to the ambient temperature of its operation, and the threshold voltage of the TFT often drifts. In the case of low temperature, the driving ability is insufficient. By enabling the compensation gate line 332, more transistors 20 can be controlled to turn on, increasing the aspect ratio of the transistor, thereby improving the low-temperature driving ability.

[0074] In the case of high temperature, high-temperature heating will occur. By turning off the compensation gate line 332, the aspect ratio of the transistor is reduced. Thereby reducing the high-temperature heating of the TFT switch and improving the display abnormality caused by the threshold voltage drift of the TFT switch.

[0075] Further, the enabled number of the predetermined gate lines is negatively correlated with the ambient temperature. It can be understood that the higher the ambient temperature, the fewer the enabled compensation gate lines 332, and the lower the ambient temperature, the more the enabled compensation gate lines 332.

[0076] For example, the three compensation gate lines 332 are respectively a first compensation line, a second compensation line, and a third compensation line;

[0077] Detect the ambient temperature of the transistor, and generate a compensation signal according to the ambient temperature; when the ambient temperature is the first preset temperature, output the first compensation signal to the first compensation line, and the source 221 and the drain 222 corresponding to the first compensation line are turned on;

[0078] When the ambient temperature is the second preset temperature, output the first compensation signal to the first compensation line, output the second compensation signal to the second compensation line, and the source 221 and the drain 222 corresponding to the first compensation line, and the source 221 and the drain 222 corresponding to the second compensation line are all turned on; the aspect ratio of the transistor is increased.

[0079] When the ambient temperature is the third preset temperature, output the first compensation signal to the first compensation line, output the second compensation signal to the second compensation line, output the third compensation signal to the third compensation line, and the source 221 and the drain 222 corresponding to the first compensation line, the source 221 and the drain 222 corresponding to the second compensation line, and the source 221 and the drain 222 corresponding to the third compensation line are all turned on, wherein the first preset temperature is greater than the second preset temperature, and the second preset temperature is greater than the third preset temperature. For example, the first preset temperature is greater than 40 °C, the second preset temperature is between 0 °C and 40 °C, and the third preset temperature is less than 0 °C. Thus, the aspect ratio of the transistor is continuously increased to improve the low-temperature characteristics.

[0080] Embodiment 4

[0081] Refer to Figure 8 As shown, the present application further provides a display panel 40. The display panel 40 further includes a gate driving circuit. The gate driving circuit includes a transistor structure. The gate driving circuit is disposed in the non-display area 420. The display panel 40 further includes a temperature detector and a controller. The controller is connected to the gate line 30. The controller is further connected to the temperature detector. The temperature detector is used to detect the ambient temperature of the gate driving circuit. The controller controls the enabled number of the gate lines 30 based on the ambient temperature. The display area 410 is used for light to pass through. Generally, the non-display area 420 is disposed around the display area 410. Arranging the gate driving circuit in the non-display area 420 can avoid blocking the light of the display area 410. In addition, the area of the non-display area 420 is reduced, and the area of the display area 410 can be increased.

[0082] In this embodiment, the temperature detector is configured to detect the ambient temperature and send the detected ambient temperature to the processor. The processor sends a control voltage signal to the gate line 30 based on the detected ambient temperature.

[0083] The embodiments of the display panel of the present invention include all the technical solutions of all the above embodiments of the transistor, and the achieved technical effects are exactly the same, which will not be elaborated herein.

[0084] Although the present application has been described with reference to several exemplary embodiments, it should be understood that the terms used are illustrative and exemplary, rather than restrictive. Since the present application can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be construed broadly within the spirit and scope defined by the appended claims. Therefore, all changes and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A transistor structure, characterized in that, the transistor structure includes a transistor and a plurality of gate lines electrically connected to the transistor; the transistor includes a semiconductor layer, a source electrode and a drain electrode provided on the semiconductor layer, the source electrode is connected to the source region of the semiconductor layer, and the drain electrode is connected to the drain region of the semiconductor layer; the transistor further includes a plurality of gates provided corresponding to the channel region of the semiconductor layer, and the plurality of gates are spaced apart in the length direction of the source electrode and the drain electrode; wherein, the plurality of gates are connected to the plurality of gate lines in a one-to-one correspondence; the drain electrode includes a first line segment, a second line segment and a connecting line segment, and the first line segment, the connecting line segment and the second line segment are sequentially connected to form a U-shaped line, and the source electrode is spaced between the first line segment and the second line segment; the first line segment and the second line segment have equal lengths, and the distances between the source electrode and the first line segment and between the source electrode and the second line segment are equal.

2. The transistor structure according to claim 1, characterized in that, a plurality of the transistors are provided and are arranged in sequence in a direction perpendicular to the length direction of the source electrode.

3. The transistor structure according to claim 2, characterized in that, in two adjacent transistors: the first line segment of the drain electrode of one transistor and the second line segment of the drain electrode of the other transistor are the same line segment.

4. The transistor structure according to claim 1, characterized in that, there are at least two adjacent transistors in a direction perpendicular to the length direction of the source electrode, the two adjacent transistors are spaced apart, and the transistor structure further includes a plurality of spaced gate lines, the spaced gate lines are provided between the spaced transistors, and the spaced gate lines are connected to the gates of the adjacent transistors.

5. The transistor structure according to claim 1, characterized in that, the semiconductor layer includes at least one metal oxide layer.

6. A gate driving circuit, characterized in that, it includes at least one transistor structure according to any one of claims 1-5.

7. The gate driving circuit according to claim 6, characterized in that, the gate driving circuit includes a pull-up control module, a pull-up module, a pull-down control module and a pull-down module; the pull-up control module is used to access an input signal, and the pull-up module is used to access a clock signal; wherein, the pull-up control module and the pull-up module include at least one transistor structure according to any one of claims 1-5.

8. A driving method for a gate driving circuit, characterized in that, the gate driving circuit includes at least one transistor structure according to any one of claims 1-5, and the driving method for the gate driving circuit includes: detecting the ambient temperature of the gate driving circuit; determining a predetermined enabled number of the gates based on the ambient temperature; inputting a gate signal to a predetermined enabled number of the gates through a predetermined enabled number of the gate lines to control the opening or closing of the transistor structure.

9. The driving method for a gate driving circuit according to claim 8, characterized in that, the predetermined enabled number of the gate lines is negatively correlated with the ambient temperature.

10. A display panel, the display panel comprising a display area and a non-display area, characterized in that, the display panel further comprises a gate driving circuit, the gate driving circuit comprising the transistor structure according to any one of claims 1 to 5, the gate driving circuit being disposed in the non-display area, the display panel further comprising a temperature detector and a controller, the controller being connected to the gate line, the controller is further connected to the temperature detector, the temperature detector is configured to detect the ambient temperature of the gate driving circuit, and the controller controls the number of enabled gates based on the ambient temperature.

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