A flat panel detector and its driving method and detection device

Abstract

The present invention discloses a flat panel detector and a driving method and a detection device thereof. The flat panel detector is divided into a detection area and a peripheral area surrounding the detection area. The flat panel detector comprises: a plurality of scanning signal lines located in the detection area, and the scanning signal lines are divided into a plurality of groups; at least one first multiplexer circuit is located in the peripheral area on one side of the detection area, each signal output end of the first multiplexer circuit is connected to each scanning signal line in a one-to-one correspondence, and the signal output ends of the first multiplexer circuits of other levels serve as the signal input ends of the first multiplexer circuits of the previous level, and the first multiplexer circuit is configured to provide the signal of the signal input end to each signal output end in a time-sharing manner; wherein the signal input ends and signal output ends of the first multiplexer circuits of different levels are different, and the number of the signal input ends and the signal output ends decreases step by step from the first multiplexer circuit of the first level to the last multiplexer circuit of the last level.

Description

Technical Field

[0001] The present invention relates to the technical field of digital medical imaging, and in particular to a flat panel detector and a driving method and a detection device thereof. Background Art

[0002] In the field of digital medical imaging, the application of X-ray flat panel detectors is very common.

[0003] Existing breast X-ray flat panel detectors have high requirements for spatial resolution, so the pixel size is relatively small. In addition, breast X-ray flat panel detectors usually require one side to have a narrow frame, generally within 1.5mm. This results in the inability to set up a lead binding area on the side with a narrow frame design for binding, so breast products need to be bound on one side. Due to the limited wiring space of the flat panel detector, the large number of external leads required, and the small pin width of the binding area, the binding process is difficult and the cost is high. Summary of the invention

[0004] The embodiments of the present invention provide a flat panel detector and a driving method and a detection device thereof, so as to solve the above problems in the prior art.

[0005] In a first aspect, in order to solve the above technical problems, an embodiment of the present invention provides a flat panel detector, which is divided into a detection area and a peripheral area surrounding the detection area;

[0006] A plurality of scanning signal lines are located in the detection area, and the plurality of scanning signal lines are divided into a plurality of groups;

[0007] At least one level of first multiplexer circuit is located in the peripheral area on one side of the detection area, each signal output terminal of the first multiplexer circuit of the first level is connected one-to-one with each of the scanning signal lines, and the signal output terminals of the first multiplexer circuits of other levels serve as signal input terminals of the first multiplexer circuit of the previous level, and the first multiplexer circuit is configured to provide the signal of the signal input terminal to each signal output terminal in a time-sharing manner; wherein the signal input terminals and signal output terminals included in the first multiplexer circuits of different levels are different, and the number of signal input terminals and signal output terminals decreases step by step from the first multiplexer circuit of the first level to the last multiplexer circuit of the first level.

[0008] In one possible implementation manner, the first multi-way selection circuit is divided into a plurality of first repeating units, one of the first repeating units includes a plurality of first transistors, a gate of each of the first transistors in one of the first repeating units is electrically connected to the same first signal selection terminal, a first electrode of each of the first transistors in one of the first repeating units is electrically connected to different signal input terminals of the first multi-way selection circuit at this level, and a second electrode of each of the first transistors in one of the first repeating units serves as signal output terminals of the first multi-way selection circuit at this level.

[0009] In a possible implementation manner, in the first multiplex selection circuit, different first repeating units are connected to different first signal selection ends, and the number of the first repeating units included is the same as the number of the first signal selection ends.

[0010] In a possible implementation manner, the number of first transistors included in each of the first repeating units is the same, and the number of first transistors included in one of the first repeating units is the same as the number of signal input terminals of the first multiplexer circuit.

[0011] In a possible implementation manner, scanning signal lines electrically connected to the second electrodes of multiple first transistors included in a first repetitive unit within the first multi-way selection circuit of the first stage are arranged continuously; wherein the number of signal input terminals and signal output terminals decreases step by step from the first multi-way selection circuit of the first stage to the first selection circuit of the last stage.

[0012] A possible implementation further includes:

[0013] A second multiplexer circuit, wherein the second multiplexer circuit is divided into a plurality of second repeating units, a plurality of second transistors are included in a second repeating unit, a gate of each of the second transistors in a second repeating unit is electrically connected to the same second signal selection terminal, a first electrode of each of the second transistors in each of the second repeating units is electrically connected to the same signal input terminal of the second multiplexer circuit, and a second electrode of each of the second transistors in a second repeating unit serves as each of the signal output terminals of the second multiplexer circuit; wherein the same signal input terminal of the second multiplexer circuit is connected to a specified voltage source, and the second repeating units in the second multiplexer circuit correspond one-to-one to the first repeating units in the first-stage first multiplexer circuit, and the second transistors in the second repeating units correspond one-to-one to the first transistors in the corresponding first repeating units in the first-stage first multiplexer circuit.

[0014] In a possible implementation manner, different second repeating units are connected to different second signal selection ends, and the number of the second repeating units is the same as the number of the second signal selection ends.

[0015] In one possible implementation, the number of second transistors contained in each of the second repeating units is the same, and the second multiplexer circuit is configured to provide a specified voltage to the signal output terminal of the first repeating unit in the first multiplexer circuit of the first stage that does not output a signal to the scan line, so as to stop the detection pixel connected to the corresponding scan signal line from working.

[0016] In a second aspect, an embodiment of the present invention provides a method for driving a flat panel detector, comprising:

[0017] Each stage of the first multiplexer circuits is controlled to be turned on in time-sharing mode, so that the signal received by the signal input terminal of the first multiplexer circuit of the current stage is provided to the signal output terminals of the first multiplexer circuit of the current stage in time-sharing mode.

[0018] A possible implementation further includes:

[0019] When any one of the first repeating units in the first multiplexer circuit of the first stage is turned on, the second repeating unit in the second multiplexer circuit corresponding to the unturned first repeating unit in the first multiplexer circuit of the first stage is controlled to be turned on, so that the detection pixels on the scanning signal line corresponding to the unturned first repeating unit stop working.

[0020] In a third aspect, an embodiment of the present invention provides a detection device, comprising the flat panel detector as described in the first aspect, and a driving chip bound to a peripheral area of ​​the flat panel detector through a flexible circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of the structure of a flat panel detector provided by an embodiment of the present invention;

[0022] Figure 2 A schematic diagram of the structure of a first multi-way selection circuit provided by an embodiment of the present invention;

[0023] Figure 3 A timing diagram of a first multiplexer selection circuit provided in an embodiment of the present invention;

[0024] Figure 4 A schematic diagram of the structure of another flat panel detector provided by an embodiment of the present invention;

[0025] Figure 5 A timing diagram of a two-stage first multiplexer selection circuit provided by an embodiment of the present invention;

[0026] Figure 6 A schematic diagram of the structure of another flat panel detector provided in an embodiment of the present invention;

[0027] Figure 7A schematic diagram of the structure of another flat panel detector provided by an embodiment of the present invention;

[0028] Figure 8 This is a timing diagram of the second multiplexer selection circuit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0029] The embodiments of the present invention provide a flat panel detector and a driving method and a detection device thereof, so as to solve the above problems in the prior art.

[0030] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and understandable, the present invention will be further described below with reference to the accompanying drawings and examples. However, the exemplary embodiments can be implemented in various forms and should not be understood as being limited to the embodiments described herein; on the contrary, these embodiments are provided to make the present invention more comprehensive and complete, and to fully convey the concepts of the exemplary embodiments to those skilled in the art. The same figure marks in the figures represent the same or similar structures, and thus their repeated descriptions will be omitted. The words expressing position and direction described in the present invention are all explained using the accompanying drawings as examples, but changes can be made as needed, and the changes made are all included in the scope of protection of the present invention. The drawings of the present invention are only used to illustrate the relative position relationship and do not represent the true proportions.

[0031] It should be noted that specific details are described in the following description to facilitate a full understanding of the present invention. However, the present invention can be implemented in a variety of other ways different from those described herein, and those skilled in the art can make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below. The subsequent description of the specification is a preferred embodiment of the present application, but the description is for the purpose of illustrating the general principles of the present application and is not intended to limit the scope of the present application. The scope of protection of the present application shall be determined by the definition of the attached claims.

[0032] A flat panel detector and a driving method and a detection device provided by an embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

[0033] See also Figure 1 A schematic diagram of the structure of a flat panel detector provided in an embodiment of the present invention, wherein the flat panel detector is divided into a detection area A and a peripheral area NA surrounding the detection area A;

[0034] Multiple scanning signal lines scan are located in the detection area A, and the multiple scanning signal lines scan are divided into multiple groups ( Figure 1 In the example, multiple scan lines enclosed in a curly bracket are grouped together).

[0035] At least one first multiplexer circuit 11 is located in the peripheral area NA on one side of the detection area A ( Figure 1In the figure, the signal output terminals of the first-stage first multiplexer selection circuit 11 are connected one-to-one with the scanning signal lines scan, and the signal output terminals of the first multiplexer selection circuits 11 of other stages serve as the signal input terminals of the first multiplexer selection circuits 11 of the previous stage. The first multiplexer selection circuit 11 is configured to provide the signal of the signal input terminal to each signal output terminal in a time-sharing manner; wherein, the signal input terminals and signal output terminals included in the first multiplexer selection circuits 11 of different stages are different, and the number of the signal input terminals and the signal output terminals decreases step by step from the first-stage first multiplexer selection circuit 11 to the last-stage first multiplexer selection circuit 11.

[0036] It is important to understand that Figure 1 Since two stages of the first multiplexer selection circuit 11 are shown, the first multiplexer selection circuits 11 of the other stages (in Figure 1 The first multiplexer selection circuit 11 of the two-stage first multiplexer selection circuit 11 shown in FIG. 1 is equivalent to the first multiplexer selection circuit 11 of the second stage, that is, the first multiplexer selection circuit 11 of the first stage. Figure 1 The signal output end of the second-stage first multiplexer selection circuit 11 serves as the signal input end of the first-stage first multiplexer selection circuit 11.

[0037] In the embodiment provided by the present invention, the signal from the signal input terminal is provided to each signal output terminal in a time-sharing manner through the at least one first multiplexer circuit 11 mentioned above, which can greatly reduce the number of leads connected to the at least one first multiplexer circuit 11, and the binding area corresponding to these leads is set on one side of the detection area, and the other side can be designed with a narrow frame, so that it can be suitable for the detection needs of breast images.

[0038] See also Figure 2 , is a schematic diagram of the structure of the first multiplexer circuit provided in an embodiment of the present invention, the first multiplexer circuit 11 is divided into a plurality of first repeating units 1, a first repeating unit 1 includes a plurality of first transistors TFT1, a gate of each first transistor TFT1 in a first repeating unit 1 is electrically connected to the same first signal selection terminal X1, a first electrode of each first transistor TFT1 in a first repeating unit 1 is electrically connected to different signal input terminals of the first multiplexer circuit 11, and a second electrode of each first transistor TFT1 in a first repeating unit 1 serves as each signal output terminal of the first multiplexer circuit 11.

[0039] Different first repeating units 1 in the first multiplex selection circuit 11 are connected to different first signal selection terminals X1 , and the number of the first repeating units 1 included is the same as the number of the first signal selection terminals.

[0040] The number of first transistors TFT1 included in each first repeating unit 1 is the same, and the number of first transistors TFT1 included in one first repeating unit 1 is the same as the number of signal input terminals of the first multiplexer circuit 11 .

[0041] exist Figure 2 The first multiplexer circuit 11 includes M signal input terminals, N signal output terminals, K first signal selection terminals X1, and a total of K first repeating units 1. The first electrodes of the first transistors TFT1 in the K first repeating units 1 are electrically connected to different signal input terminals of the first multiplexer circuit 11, so that the K first repeating units 1 can share the signal input terminal of the first multiplexer circuit 11, and the gate electrodes of the first transistors TFT1 in the same first repeating unit 1 are connected to the same first signal selection terminal, and different first repeating units 1 are connected to different first selection terminals. The first selection signal can be sent to each first selection terminal in a time-sharing manner to control the K first repeating units 1 in the first multiplexer circuit 11 to use the signal input terminal of the first multiplexer circuit 11 to transmit signals to the corresponding signal output terminal in a time-sharing manner, thereby reducing the number of signal input terminals of the first multiplexer circuit 11.

[0042] See also Figure 3 This is a timing diagram of the first multiplexer selection circuit provided in an embodiment of the present invention.

[0043] Assumptions Figure 2 The first multiplexer circuit 11 includes m first repeating units 1, and the first selection signals received by their corresponding first selection signal terminals are successively the first selection signal 1 to the first selection signal m. The first multiplexer circuit 11 has n signal input terminals, and the first input signals received by them are successively the first input signal 1 to the first input signal n. The first multiplexer circuit 11 includes m×n signal output terminals; and it is assumed that the first transistor TFT1 in the first repeating unit 1 is an N-type transistor.

[0044] See also Figure 3 When the first first repeating unit 1 receives a valid first selection signal 1 (i.e., a high level signal), it receives the corresponding first input signals 1 to first input signals n (high level valid) from the n signal input terminals of the first multiplexer selection circuit 11, and outputs the first input signals 1 to first input signals n to the signal output terminal of the first first repeating unit 1.

[0045] When the second first repeating unit 1 receives a valid first selection signal 2 (i.e., a high level signal), it receives the corresponding first input signals 1 to first input signals n (high level valid) from the n signal input terminals of the first multiplexer selection circuit 11, and outputs the first input signals 1 to first input signals n to the signal output terminal of the first first repeating unit 1.

[0046] When the mth first repeating unit 1 receives a valid first selection signal m (i.e., a high level signal), it receives the corresponding first input signals 1 to first input signals n (high level valid) from the n signal input terminals of the first multiplexer selection circuit 11, and outputs the first input signals 1 to first input signals n to the signal output terminal of the first first repeating unit 1.

[0047] It should be noted that the duration of the high level of the first selection signal 1 to the first selection signal m is ΔT, the duration of the high level of the first input signal 1 to the first input signal n is Δt, and ΔT=n×Δt. Figure 2 The first transistor TFT1 in the embodiment may also be a P-type transistor. Figure 2 When the first thin film transistor TFT1 is a P-type transistor, the thin film transistor connected to the scanning signal line that controls the detection pixel is also P-type, and the corresponding first input signal 1 to the first input signal n and the first selection signal 1 to the first selection signal m are all valid at low levels, and the corresponding timing diagram also needs to be adjusted accordingly.

[0048] See also Figure 4 A schematic diagram of the structure of another flat panel detector provided in an embodiment of the present invention.

[0049] Assumptions Figure 4 The number of scanning signal lines included in the flat panel detector is n, and the first-stage first multiplexer circuit 11 (i.e., the first multiplexer circuit 11 whose signal output end is directly connected to the scanning line) includes m first repeating units 1. Then, the total number of first signal selection ends included in the first-stage first multiplexer circuit 11 is m, and the total number of signal input ends is n / m. The number of signal input ends and signal output ends of the first repeating units 1 in the first-stage first multiplexer circuit 11 is n / m. The signal output end of the second-stage first multiplexer circuit 11 is connected to the signal input end of the first-stage first multiplexer circuit 11 in a one-to-one correspondence. Assuming that the second-stage first multiplexer circuit 11 includes i first repeating units 1, the total number of first signal selection ends included in the second-stage first multiplexer circuit 11 is also i. Assuming that the total number of signal input ends included in the second-stage first multiplexer circuit 11 is j, then j=n / m / i.

[0050] The signals received by the first signal selection end of the first-stage first multiplexer selection circuit 11 are sequentially recorded as the first selection signal 11 to the first selection signal 1m, the signals received by the first signal selection end of the second-stage first multiplexer selection circuit 11 are sequentially recorded as the first selection signal 21 to the first selection signal 2i, and the signals received by the signal input end of the second-stage first multiplexer selection circuit 11 are sequentially recorded as the first input signal 2i to the first input signal 2j. Figure 4 For the corresponding timing diagram, see Figure 5 A timing diagram of a two-stage first multiplexer selection circuit provided in an embodiment of the present invention.

[0051] exist Figure 5 The duration of the high-level signal received by the signal input end of the second-stage first multiplexer selection circuit 11 is △t, the duration of each high-level signal in the first selection signal 21 to the first selection signal 2i received by the first selection signal end of the second-stage first multiplexer selection circuit 11 is j×△t, the duration of each high-level signal in the first selection signal 11 to the first selection signal 1m received by the first-stage first multiplexer selection circuit 11 is △T=i×j×△t, and the time required to complete one scan of the n scanning signal lines of the flat-panel detector is m×△T.

[0052] It should be noted that at least one level of first multiplexer selection circuit 11 can also be set at the first signal selection end included in the first multiplexer selection circuit 11 to reduce the number of leads that need to be introduced at the first signal selection end. The setting method is similar to the method of setting at least one level of first multiplexer selection circuit 11 on one side of the scanning signal line, and will not be repeated here.

[0053] See also Figure 6 FIG. 1 is a schematic diagram of the structure of another flat panel detector according to an embodiment of the present invention. Figure 6 In the figure, the flat panel detector only includes the first multi-way selection circuit 11 of the first stage.

[0054] The scanning signal lines scan, to which the second electrodes of a plurality of first transistors TFT1 electrically connected, are arranged in series in a first repetitive unit 1 in the first-stage first multiplexer circuit 11 .

[0055] When the flat panel detector includes a plurality of first multiplexer selection circuits 11, the connection mode between the first first multiplexer selection circuit 11 and the scanning signal line scan is the same as Figure 3 Consistent.

[0056] In the embodiment provided by the present invention, by continuously arranging the scanning signal lines scan electrically connected to the second electrodes of multiple first transistors TFT1 included in a first repetitive unit 1 in the first-stage first multiplexer circuit 11, it is convenient to transmit the scanning signals corresponding to each scanning signal line scan to the corresponding scanning signal line scan row by row when the first repetitive unit 1 is time-sharing controlled.

[0057] See also Figure 7 A schematic diagram of the structure of another flat panel detector provided in an embodiment of the present invention.

[0058] The flat panel detector also includes: a second multiplexer circuit 12. The second multiplexer circuit 12 is divided into a plurality of second repeating units 2. A second repeating unit 2 includes a plurality of second transistors TFT2. The gates of the second transistors TFT2 in a second repeating unit 2 are electrically connected to the same second signal selection terminal X2. The first electrodes of the second transistors TFT2 in the second repeating units 2 are electrically connected to the same signal input terminal of the second multiplexer circuit 12. The second electrodes of the second transistors TFT2 in a second repeating unit 2 serve as signal output terminals of the second multiplexer circuit 12.

[0059] It should be noted that in Figure 7 For ease of viewing, the second multiplexer circuit 12 and the first multiplexer circuit 11 are arranged on different sides of the detection area A. In actual use, the second multiplexer circuit 12 and the first multiplexer circuit 11 can be arranged on the same side of the detection area A, which facilitates the implementation of a narrow frame design on one side of the detection area A.

[0060] Different second repeating units 2 are connected to different second signal selection terminals X2, and the number of the second repeating units 2 is the same as the number of the second signal selection terminals.

[0061] The number of second transistors TFT2 included in each of the second repeating units 2 is the same, and the signal input end of the second multiplexer circuit 12 is electrically connected to the specified voltage end. The second multiplexer circuit 12 is configured to provide a specified voltage to the signal output end of the first repeating unit 1 in the first multiplexer circuit 11 of the first stage that does not output a signal to the scan line scan, so as to stop the detection pixel (not shown in the figure) connected to the corresponding scan signal line scan from working.

[0062] For example Figure 7 In the example, if the detection pixel connected to each scanning signal line scan is controlled by an N-type transistor to determine whether it is working, the specified voltage is a low voltage. Figure 6 The first first repetition unit 1 in the current first multiplexer circuit 11 of the first stage uses the signal input end of the first multiplexer circuit 11 of this stage to receive the scanning signal, and transmits the scanning signal to the scanning line scan of the corresponding row. Except for the first second repetition unit 2 (corresponding to the first first repetition unit 1) in the second multiplexer circuit 12, the other second repetition units 2 receive the second selection signal through their respective second signal selection ends X2 to select the corresponding second repetition unit 2, so that all the second repetition units 2 except the first second repetition unit 2 apply a low voltage signal to the signal output end of the corresponding first repetition unit 1, so that the detection pixels connected to the corresponding scanning signal line stop working, so that it can be ensured that only the detection pixels on the scanning signal line corresponding to the first first repetition unit 1 can work at present, thereby preventing errors in reading the detection signal data.

[0063] See also Figure 8 This is a timing diagram of the second multiplexer selection circuit provided in an embodiment of the present invention.

[0064] Assumptions Figure 7 The first-stage first multiplexer selection circuit 11 includes m first repeating units 1, and the first selection signals received by the first selection signal terminals corresponding to them are first selection signals 1 to first selection signals m in sequence. The first-stage first multiplexer selection circuit 11 has n signal input terminals, and the first output signals received by them are first input signals 1 to first input signals n in sequence. The first-stage first multiplexer selection circuit 11 includes m×n signal output terminals;

[0065] Correspondingly, the second multiplexer selection circuit 12 also includes m second repeating units 2, and the second selection signals received by their corresponding second selection signal terminals are successively the second selection signal 1 to the second selection signal m. The second multiplexer selection circuit 12 also has n signal input terminals, and the second output signals received by them are successively the second input signal 1 to the second input signal n. The second multiplexer selection circuit 12 includes m×n signal output terminals.

[0066] It is assumed that the first transistor TFT1 in the first repeating unit 1 and the second transistor TFT2 in the second repeating unit 2 are both N-type transistors, wherein the first first repeating unit 1 to the m-th first repeating unit 1 correspond one-to-one with the first second repeating unit 2 to the m-th second repeating unit 2, and the first first transistor TFT1 to the n-th first transistor TFT1 in the corresponding first repeating unit 1 and the second repeating unit 2 also correspond one-to-one with the first second transistor TFT2 to the n-th second transistor TFT2.

[0067] Please continue to see Figure 8 When the first first repeating unit 1 receives a valid first selection signal 1 (i.e., a high-level signal), the first second repeating unit 2 receives an invalid second selection signal 1 (a low-level signal indicates invalidity), and the other second repeating units 2 receive a valid second selection signal (second selection signal 2 to second selection signal m, high level is valid), so that the other second repeating units 2 except the first second repeating unit 2 are turned on, and the low-level signal (assuming that the control signal required for the detection pixel to work is a high-level signal) received at the signal input end of the second multiplex selection point 12 is transmitted to the corresponding scanning signal line, so that the detection pixels on these scanning signal lines stop working. Figure 5 It is only necessary to connect the signal input terminal of the second multiplexer circuit 12 to the low voltage terminal (such as the ground terminal).

[0068] When the second first repeating unit 1 receives a valid first selection signal 2 (i.e., a high-level signal), the second second repeating unit 2 receives an invalid second selection signal 2 (a low-level signal indicates invalidity), and other second repeating units 2 receive a valid second selection signal (high level is valid), so that other second repeating units 2 except the second second repeating unit 2 are turned on, and the low-level signal received at the signal input end of the second multi-way selection point 12 is transmitted to the corresponding scanning signal lines, so that the detection pixels on these scanning signal lines stop working.

[0069] When the mth first repeating unit 1 receives a valid first selection signal m (i.e., a high-level signal), the mth second repeating unit 2 receives an invalid second selection signal m (a low-level signal indicates invalidity), and other second repeating units 2 receive a valid second selection signal (high level is valid), so that the other second repeating units 2 except the mth second repeating unit 2 are turned on, and the low-level signal received at the signal input end of the second multi-way selection point 12 is transmitted to the corresponding scanning signal lines, so that the detection pixels on these scanning signal lines stop working.

[0070] Based on the same inventive concept, an embodiment of the present invention provides a driving method of a flat panel detector, the driving method comprising:

[0071] The first multiplexer selection circuits of each stage are controlled to be turned on in time-sharing mode, so that the signal received by the signal input terminal of the first multiplexer selection circuit of the same stage is provided to the signal output terminals of the first multiplexer selection circuit of the same stage in time-sharing mode.

[0072] In a possible implementation manner, the driving method further includes:

[0073] When any one of the first repeating units in the first multiplexer circuit of the first stage is turned on, the second repeating unit in the second multiplexer circuit corresponding to the unturned first repeating unit in the first multiplexer circuit of the first stage is controlled to be turned on, so that the detection pixels on the scanning signal line corresponding to the unturned first repeating unit stop working.

[0074] Based on the same inventive concept, an embodiment of the present invention provides a detection device, including the flat panel detector as described above, and a driving chip bound to the peripheral area of ​​the flat panel detector through a flexible circuit board.

[0075] The detection device may be an X-ray detection device, which may be used to detect breast images.

[0076] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0077] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A flat panel detector, characterized in that: Divided into a detection area and a peripheral area surrounding the detection area; A plurality of scanning signal lines are located in the detection area, and the plurality of scanning signal lines are divided into a plurality of groups; At least one level of first multiplexer circuit is located in the peripheral area on one side of the detection area, each signal output end of the first multiplexer circuit of the first level is connected to each of the scanning signal lines in a one-to-one correspondence, and the signal output ends of the first multiplexer circuits of other levels serve as the signal input ends of the first multiplexer circuit of the previous level, and the first multiplexer circuit is configured to provide the signal of the signal input end to each signal output end in a time-sharing manner; wherein the first multiplexer circuits of different levels include different signal input ends and signal output ends, and the number of signal input ends and signal output ends decreases step by step from the first multiplexer circuit of the first level to the last multiplexer circuit of the first level; A second multiplexer circuit, wherein the second multiplexer circuit is divided into a plurality of second repeating units, wherein one of the second repeating units includes a plurality of second transistors, wherein the gates of the second transistors in one of the second repeating units are electrically connected to the same second signal selection terminal, the first electrodes of the second transistors in each of the second repeating units are electrically connected to the same signal input terminal of the second multiplexer circuit, and the second electrodes of the second transistors in one of the second repeating units serve as signal output terminals of the second multiplexer circuit; wherein the same signal input terminal of the second multiplexer circuit is connected to a specified voltage source, and the second repeating units in the second multiplexer circuit correspond one-to-one to the first repeating units in the first multiplexer circuit of the first stage, and the second transistors in the second repeating units correspond one-to-one to the first transistors in the corresponding first repeating units in the first multiplexer circuit of the first stage; The number of second transistors contained in each of the second repeating units is the same, and the second multiplexer circuit is configured to provide a specified voltage to the signal output terminal of the first repeating unit in the first multiplexer circuit of the first stage that does not output a signal to the scan line, so as to stop the detection pixel connected to the corresponding scan signal line from working.

2. The flat panel detector according to claim 1, characterized in that: The first multi-way selection circuit is divided into multiple first repeating units, one of the first repeating units includes multiple first transistors, the gates of the first transistors in the first repeating unit are electrically connected to the same first signal selection terminal, the first electrodes of the first transistors in the first repeating unit are electrically connected to different signal input terminals of the first multi-way selection circuit at this level, and the second electrodes of the first transistors in the first repeating unit serve as signal output terminals of the first multi-way selection circuit at this level.

3. The flat panel detector according to claim 2, characterized in that: In the first multiplex selection circuit, different first repeating units are connected to different first signal selection ends, and the number of the first repeating units is the same as the number of the first signal selection ends.

4. The flat panel detector according to claim 3, characterized in that: The number of first transistors included in each of the first repeating units is the same, and the number of first transistors included in one of the first repeating units is the same as the number of signal input terminals of the first multiplexer circuit.

5. The flat panel detector according to claim 4, characterized in that: The scanning signal lines to which the second electrodes of the plurality of first transistors included in one of the first repetitive units in the first multiplex selection circuit of the first stage are electrically connected are arranged continuously.

6. The flat panel detector according to claim 1, characterized in that: Different second repeating units are connected to different second signal selection ends, and the number of the second repeating units is the same as the number of the second signal selection ends.

7. A driving method of a flat panel detector according to any one of claims 1 to 6, characterized in that: include: Each stage of the first multiplexer circuits is controlled to be turned on in time-sharing mode, so that the signal received by the signal input terminal of the first multiplexer circuit of the current stage is provided to the signal output terminals of the first multiplexer circuit of the current stage in time-sharing mode.

8. The driving method according to claim 7, characterized in that: Also includes: When any one of the first repeating units in the first multiplexer circuit of the first stage is turned on, the second repeating unit in the second multiplexer circuit corresponding to the unturned first repeating unit in the first multiplexer circuit of the first stage is controlled to be turned on, so that the detection pixels on the scanning signal line corresponding to the unturned first repeating unit stop working.

9. A detection device, characterized in that: The invention comprises the flat panel detector according to any one of claims 1 to 6, and a driving chip bound to the peripheral area of ​​the flat panel detector through a flexible circuit board.

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