Signal delay control method, device, equipment and medium

Abstract

The present application relates to a signal delay control method, device, equipment and medium. The method includes: obtaining a sample instruction error signal sent by a memory through a host; the delay control circuit on the host includes multiple delay units; each delay unit is connected to a tap interface; the tap interface can derive a signal from the delay control circuit; training is performed based on the sample instruction error signal to determine delay adjustment information; a target tap interface is determined based on the delay adjustment information; a target delay unit in front of the target tap interface is used to perform signal offset adjustment on the instruction error signal to obtain an instruction error signal aligned with the sampling edge of the host's signal sampling clock; after the instruction error signal input by the memory is processed by the target delay unit, the offset-adjusted target instruction error signal is derived from the delay control circuit through the target tap interface for sampling by the signal sampling clock. The use of this method can improve the working stability of memory instructions.

Description

Technical Field

[0001] The present application relates to computer technology, and in particular to a signal delay control method, apparatus, device and medium. Background Art

[0002] In a high-bandwidth memory system, the host in the HBM system sends instructions to the memory within the HBM system, enabling control of the memory's operations. During the process of sending instructions from the host to the memory, the transmission of instructions is susceptible to environmental changes and signal crosstalk, which can cause offsets between the instruction sampling clock and the instruction sampling clock in the memory, resulting in instruction sampling errors. If the instruction sampling error occurs, the host's operation on the memory will be erroneous, and in severe cases, data stored in the memory will be lost. Therefore, when an instruction sampling error occurs in the memory, the memory promptly sends a command error signal to the host, allowing the host to implement measures such as retransmission or line diagnostics to ensure the correct transmission of the instruction.

[0003] However, the transmission of the instruction error signal may also be affected by factors such as environmental changes and crosstalk between signals, affecting the stability of the instruction error signal transmission, thereby causing the sampling edge of the instruction error signal and the signal sampling clock in the host to be offset, resulting in errors in the host's sampling of the instruction error signal. When the host makes an error in sampling the instruction error signal, it is very likely that the instruction error signal will be missampled or missed. At this time, the instruction error signal fed back by the memory to the host will not be responded to in a timely manner, the memory will experience instruction execution errors, and may even cause the loss of data stored in the memory, resulting in low stability of the memory's instruction operation. Summary of the Invention

[0004] Based on this, it is necessary to provide a signal delay control method, device, equipment and medium that can improve the working stability of memory instructions to address the above technical problems.

[0005] In a first aspect, the present application provides a signal delay control method, the method comprising:

[0006] A sample instruction error signal sent by a memory is obtained through a host; a delay control circuit provided on the host includes delay units connected in sequence; each delay unit is connected to a tap interface; the tap interface supports deriving a signal from the delay control circuit;

[0007] performing delay adjustment training based on the sample instruction error signal to determine delay adjustment information for a delay control circuit on the host;

[0008] Based on the delay adjustment information, a target tap interface is determined from the delay control circuit; wherein the target delay unit before the target tap interface is used to perform signal offset adjustment on the instruction error signal through delay processing to obtain the instruction error signal aligned with the sampling edge of the signal sampling clock of the host;

[0009] After the instruction error signal input from the memory is processed by the target delay unit, the offset-adjusted target instruction error signal obtained by the processing is derived from the delay control circuit through the target tap interface for sampling by the signal sampling clock.

[0010] In a second aspect, the present application provides a signal delay control device, the device comprising:

[0011] An acquisition module is configured to acquire, through a host, a sample instruction error signal sent by a memory; the delay control circuit provided on the host includes delay units connected in sequence; each delay unit is connected to a tap interface; the tap interface supports deriving a signal from the delay control circuit;

[0012] a training module configured to perform delay adjustment training based on the sample instruction error signal to determine delay adjustment information for a delay control circuit on the host; and to determine a target tap interface from the delay control circuit based on the delay adjustment information; wherein a target delay unit preceding the target tap interface is configured to perform signal offset adjustment on the instruction error signal through delay processing to obtain an instruction error signal aligned with a sampling edge of a signal sampling clock of the host;

[0013] The export module is used to export the offset-adjusted target instruction error signal obtained by processing the instruction error signal input by the memory from the delay control circuit through the target tap interface after the instruction error signal is processed by the target delay unit, so as to be sampled by the signal sampling clock.

[0014] In one embodiment, the training module is further used to adjust the delay control circuit on the host in the direction of increasing the delay of the sample instruction error signal when the host samples the sample instruction error signal through the signal sampling clock in the first state, until the host does not sample the sample instruction error signal through the signal sampling clock in the second state, and obtain first adjustment information for the delay control circuit on the host; restore the second state to the first state, and adjust the delay control circuit on the host in the direction of reducing the delay of the sample instruction error signal until the host does not sample the sample instruction error signal through the signal sampling clock in the second state, and obtain second adjustment information for the delay control circuit on the host; determine the delay adjustment information for the delay control circuit on the host based on the first adjustment information and the second adjustment information.

[0015] In one embodiment, the delay control circuit includes a first subcircuit and a second subcircuit; the second subcircuit is connected after the first subcircuit; the first subcircuit and the second subcircuit respectively include delay units connected in sequence; the first adjustment information includes a first number of delay units in the second subcircuit through which the sample instruction error signal has been transmitted; the training module is further used to control the acquired sample instruction error signal to pass through each delay unit in the first subcircuit in sequence to perform initial delay control processing to obtain the sample instruction error signal after initial control; in a first state in which the host samples the sample instruction error signal after initial control through a signal sampling clock, the sample instruction error signal after initial control is continuously controlled to be transmitted through the delay units in the second subcircuit one by one in a direction of increasing the delay of the sample instruction error signal after initial control until a second state in which the signal sampling clock does not sample the sample instruction error signal from the corresponding tap interface of the second subcircuit occurs, and the first number of delay units in the second subcircuit through which the sample instruction error signal has been transmitted is recorded.

[0016] In one embodiment, the second adjustment information includes a second number of delay units through which the sample instruction error signal is not transmitted; the training module is further used to restore the second state to the first state, and control the sample instruction error signal after the initial control to be transmitted through the delay units in the first sub-circuit one by one in the direction of reducing the delay of the sample instruction error signal after the initial control, until the second state in which the signal sampling clock does not sample the sample instruction error signal from the corresponding tap interface of the first sub-circuit occurs, and record the second number of delay units through which the sample instruction error signal is not transmitted.

[0017] In one embodiment, the training module is further configured to determine delay adjustment information for a delay control circuit on the host according to an average of the first number and the second number.

[0018] In one embodiment, the training module is also used to perform frequency reduction adjustment processing on the current operating frequency of the host in the second state where the host does not sample the sample instruction error signal through the signal sampling clock to obtain a reduced target operating frequency; the target operating frequency is the operating frequency that enables the host to sample the sample instruction error signal through the signal sampling clock; based on the signal sampling clock in the host operating at the target operating frequency, the sample instruction error signal is sampled so that the signal sampling clock samples the sample instruction error signal.

[0019] In one embodiment, the acquisition module is further configured to acquire a sample instruction; the sample instruction carries a field set that causes the memory to generate a sample instruction error signal after acquiring the sample instruction;

[0020] The device further comprises:

[0021] A sending module is used to send the sample instruction to the memory through the host, so that the memory performs an exclusive-OR operation on each field in the field set to perform instruction verification on the sample instruction, and triggers the generation of a sample instruction error signal based on the verification result obtained; and sends the generated sample instruction error signal to the host through the memory.

[0022] In one embodiment, the field set includes an instruction check field and multiple non-instruction check fields; the second XOR result obtained by performing an XOR operation on the instruction check field and the first XOR result is used to characterize that the memory generates a sample instruction error signal after receiving the sample instruction; the first XOR result is the result obtained by performing an XOR operation on the multiple non-instruction check fields.

[0023] In one embodiment, the apparatus further comprises:

[0024] The timing module is used to periodically trigger and notify the acquisition module through a timer to execute the step of acquiring the sample instruction error signal sent by the memory through the host through hardware control, so as to trigger re-delay adjustment training.

[0025] In one embodiment, the apparatus further comprises:

[0026] A monitoring module is configured to monitor the system operating status of a high-bandwidth memory system including a host and a memory; if the system operating status is not busy, the acquisition module is notified to re-execute the step of acquiring a sample instruction error signal sent by the memory through the host through software control to trigger re-delay adjustment training.

[0027] In one embodiment, the apparatus further comprises:

[0028] A sending module, configured to send the target instruction to the memory via the host;

[0029] The acquisition module is also used to receive the instruction error signal sent by the memory through the host; the instruction error signal sent by the memory is a signal generated by the memory after the memory performs instruction verification on the target instruction; the instruction error signal sent by the memory is controlled to be transmitted to the target delay unit in the delay control circuit in sequence, so as to perform delay control processing on the instruction error signal sent by the memory.

[0030] In one embodiment, the apparatus further comprises:

[0031] A sampling module is configured to sample a target instruction error signal derived from the delay control circuit using the signal sampling clock; align the derived target instruction error signal with a sampling edge of the host's signal sampling clock; and resend the target instruction corresponding to the target instruction error signal to the memory based on the target instruction error signal obtained by sampling by the host.

[0032] In a third aspect, the present application provides a computer device including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the steps in the method embodiments of the present application are implemented.

[0033] In a fourth aspect, the present application provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in the various method embodiments of the present application.

[0034] In a fifth aspect, the present application provides a computer program product, including a computer program, which implements the steps in the various method embodiments of the present application when the computer program is executed by a processor.

[0035] The above-mentioned signal delay control method, device, equipment and medium obtain the sample instruction error signal sent by the memory through the host; the delay control circuit provided on the host includes delay units connected in sequence; each delay unit is connected to a tap interface; the tap interface supports the export of signals from the delay control circuit. By performing delay adjustment training based on the sample instruction error signal, the delay adjustment information for the delay control circuit on the host can be determined. Based on the delay adjustment information, the target tap interface can be determined from the delay control circuit, and the target delay unit before the target tap interface can be used to perform signal offset adjustment on the instruction error signal through delay processing to obtain an instruction error signal aligned with the sampling edge of the signal sampling clock of the host. The instruction error signal input by the memory can be subjected to delay control processing through the target delay unit to obtain the target instruction error signal after offset adjustment, and the target instruction error signal can be directly exported from the delay control circuit through the target tap interface. Since the target instruction error signal derived from the delay control circuit has been realigned with the sampling edge of the host's signal sampling clock, the host can be guaranteed to correctly sample the target instruction error signal, thereby ensuring that the target instruction error signal fed back by the memory to the host can be responded to in a timely manner, avoiding instruction execution errors in the memory, and thus improving the stability of the memory instruction operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A diagram showing an application environment of a signal delay control method in one embodiment;

[0037] Figure 2 1 is a flow chart of a signal delay control method according to an embodiment;

[0038] Figure 3 1 is a schematic structural diagram of a delay control circuit in one embodiment;

[0039] Figure 4 is a schematic structural diagram of a delay control circuit in another embodiment;

[0040] Figure 5 FIG1 is a schematic diagram of alignment of a command error signal and a signal sampling clock in one embodiment;

[0041] Figure 6 A schematic diagram of a delay adjustment training process in one embodiment;

[0042] Figure 7 Schematic diagram illustrating each line of instructions in one embodiment;

[0043] Figure 8 Schematic diagram illustrating various columns of instructions in one embodiment;

[0044] Figure 9A schematic diagram of a situation where an instruction error occurs in one embodiment;

[0045] Figure 10 A schematic diagram of a situation where two instruction errors occur in one embodiment;

[0046] Figure 11 A schematic diagram of a situation where three instruction errors occur in one embodiment;

[0047] Figure 12 FIG. 1 is a schematic diagram illustrating rules for checking instructions using an even parity check method in one embodiment;

[0048] Figure 13 Schematic diagram of various fields of a sample instruction in one embodiment;

[0049] Figure 14 is a schematic diagram of various fields of a sample instruction in another embodiment;

[0050] Figure 15 is a basic structural diagram of a delay adjustment training circuit in one embodiment;

[0051] Figure 16 A schematic diagram of a sample instruction sending timing in one embodiment;

[0052] Figure 17 A schematic diagram of a sample instruction sending timing in another embodiment;

[0053] Figure 18 is a flow chart of a signal delay control method according to another embodiment;

[0054] Figure 19 is a structural block diagram of a signal delay control device in one embodiment;

[0055] Figure 20 FIG. 1 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0056] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0057] The signal delay control method provided by this application can be applied to Figure 1In the application environment shown. Among them, the terminal 102 communicates with the server 104 through the network. The data storage system can store the data that the server 104 needs to process. The data storage system can be integrated on the server 104, or it can be placed on the cloud or other servers. Among them, the terminal 102 can be, but is not limited to, various desktop computers, laptops, smart phones, tablets, Internet of Things devices and portable wearable devices. The Internet of Things devices can be smart speakers, smart TVs, smart air conditioners, smart car-mounted devices, etc. Portable wearable devices can be smart watches, smart bracelets, head-mounted devices, etc. The server 104 can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms. The terminal 102 and the server 104 can be directly or indirectly connected via wired or wireless communication, and this application does not limit this.

[0058] A high-bandwidth memory system including a host and a memory is deployed in the server 104. The server 104 can obtain a sample instruction error signal sent by the memory through the host; the delay control circuit provided on the host includes delay units connected in sequence; each delay unit is connected to a tap interface; the tap interface supports the export of a signal from the delay control circuit. The server 104 can perform delay adjustment training based on the sample instruction error signal to determine the delay adjustment information for the delay control circuit on the host, and determine the target tap interface from the delay control circuit based on the delay adjustment information; wherein the target delay unit before the target tap interface is used to perform signal offset adjustment on the instruction error signal through delay processing to obtain an instruction error signal aligned with the sampling edge of the signal sampling clock of the host. After the instruction error signal input from the memory is processed by the target delay unit, the server 104 can export the offset-adjusted target instruction error signal obtained through the processing from the delay control circuit through the target tap interface for sampling by the signal sampling clock.

[0059] It is understood that the host in the server 104 can generate a sample instruction and send the sample instruction to the memory in the server 104. Then, the memory in the server 104 can generate a sample instruction error signal based on the sample instruction and send the generated sample instruction error signal to the host in the server 104. It is also understood that the terminal 102 can also generate a sample instruction and send the sample instruction to the server 104. The memory in the server 104 can generate a sample instruction error signal based on the received sample instruction and send the generated sample instruction error signal to the host in the server 104. This embodiment does not limit this, and it is understood that Figure 1The application scenarios are only for illustration and are not limited to this.

[0060] In one embodiment, Figure 2 As shown, a signal delay control method is provided. The method can be applied to a computer device, which can be a terminal or a server. The method can be executed by the terminal or server itself or through interaction between the terminal and the server. This embodiment uses the method applied to a computer device as an example to illustrate, and includes the following steps:

[0061] Step 202: Obtain a sample instruction error signal sent by the memory through the host; the delay control circuit provided on the host includes delay units connected in sequence; each delay unit is connected to a tap interface; the tap interface supports deriving a signal from the delay control circuit.

[0062] The sample instruction error signal is a instruction error signal used to train the delay control circuit provided on the host during the training phase. It can be understood that the sample instruction error signal is a type of sample data used to train the delay control circuit. The delay control circuit is a circuit used to perform delay control processing on the instruction error signal to control the alignment of the instruction error signal with the sampling edge of the host's signal sampling clock, so that the host's signal sampling clock can correctly sample the instruction error signal. The delay unit is the smallest unit in the delay control circuit used to perform delay control processing on the instruction error signal. It can be understood that the more delay units there are that perform delay control processing on the instruction error signal, the greater the delay of the instruction error signal, and vice versa. The tap interface is an interface provided after each delay unit in the delay control circuit. The tap interface supports the derivation of signals from the delay control circuit. It can be understood that the instruction error signal can be connected from any tap interface when transmitting through the delay control circuit, so that the instruction error signal can be derived from the delay control circuit. It can be understood that the delay unit before the tap interface responsible for deriving the instruction error signal in the delay control circuit will perform delay control processing on the instruction error signal, while the delay unit after the tap interface will not perform delay control processing on the instruction error signal.

[0063] It can be understood that the control instruction error signal is aligned with the sampling edge of the host's signal sampling clock, specifically, the signal center of the control instruction error signal is aligned with the sampling edge of the host's signal sampling clock.

[0064] In one embodiment, the sampling edge of the signal sampling clock includes a rising edge and a falling edge of the signal sampling clock. If the computer device samples the instruction error signal using the rising edge of the host's signal sampling clock, the signal center of the instruction error signal is controlled to be aligned with the rising edge of the host's signal sampling clock. If the computer device samples the instruction error signal using the falling edge of the host's signal sampling clock, the signal center of the instruction error signal is controlled to be aligned with the falling edge of the host's signal sampling clock.

[0065] Specifically, the computer device includes a host and a memory. The computer device can generate a sample instruction error signal through the memory and send the sample instruction error signal to the host, and then the computer device can receive the sample instruction error signal sent by the memory through the host.

[0066] In one embodiment, the host and the memory are components of a high bandwidth memory system, and the high bandwidth memory system is deployed in a computer device.

[0067] In one embodiment, the memory may be a dynamic random access memory or a random access memory. The embodiment of the present application does not specifically limit the type of memory.

[0068] In one embodiment, Figure 3 As shown, the delay control circuit may include a plurality of delay units connected in sequence, and the delay units may be used to perform delay control processing on the input instruction error signal.

[0069] In one embodiment, Figure 4 As shown, each delay unit in the delay control circuit is connected to a tap interface, and each tap interface can support the output of a signal from the delay control circuit. A step counter in the delay control circuit can be used to subsequently determine the delay adjustment information of the delay control circuit.

[0070] Step 204 : Perform delay adjustment training based on the sample command error signal to determine delay adjustment information for a delay control circuit on the host.

[0071] The delay adjustment information is information used to adjust the delay control circuit. It is understood that adjusting the delay control circuit refers to adjusting the number of delay units in the delay control circuit through which the instruction error signal is transmitted, so as to increase or decrease the delay of the instruction error signal.

[0072] Specifically, the computer device can perform delay adjustment training on the delay control circuit based on the sample instruction error signal. After the training is completed, the computer device can obtain delay adjustment information for the delay control circuit on the host.

[0073] In one embodiment, the computer device performs delay adjustment training on the delay control circuit based on the sample instruction error signal. Specifically, the computer device may adjust the delay control circuit on the host in the direction of increasing the delay of the sample instruction error signal, and adjust the delay control circuit on the host in the direction of reducing the delay of the sample instruction error signal, so as to complete the delay adjustment training of the delay control circuit and obtain delay adjustment information.

[0074] In one embodiment, the computer device may increase the delay of the SIE signal by increasing the number of delay units through which the SIE signal passes, and may decrease the delay of the SIE signal by decreasing the number of delay units through which the SIE signal passes.

[0075] Step 206: Determine a target tap interface from the delay control circuit based on the delay adjustment information; wherein the target delay unit before the target tap interface is used to perform signal offset adjustment on the instruction error signal through delay processing to obtain an instruction error signal that is aligned with the sampling edge of the host's signal sampling clock.

[0076] The target tap interface is a tap interface for deriving a command error signal from the delay control circuit, and the target delay unit is all delay units located before the target tap interface in the delay control circuit.

[0077] Specifically, the computer device may determine a target tap interface from among the various tap interfaces in the delay control circuit based on the delay adjustment information. It will be appreciated that the computer device may delay the command error signal using a target delay unit located before the target tap interface to adjust the offset between the command error signal and the sampling edge of the signal sampling clock, thereby realigning the command error signal with the sampling edge of the host's signal sampling clock.

[0078] In one embodiment, the computer device samples the instruction error signal through the rising edge of the host's signal sampling clock. Figure 5 As shown in Figure 2, the center of the command error signal in (a) is aligned with the rising edge of the signal sampling clock. In this case, the host can accurately sample the command error signal using the signal sampling clock. In (b), there is an offset between the center of the command error signal and the rising edge of the signal sampling clock. The rising edge of the signal sampling clock has even drifted out of the data window of the command error signal. In this case, the host cannot sample the command error signal using the signal sampling clock. In (c), there is also an offset between the center of the command error signal and the rising edge of the signal sampling clock. In this case, the host may not be able to accurately sample the command error signal using the signal sampling clock.

[0079] Step 208 : After the instruction error signal inputted from the memory is processed by the target delay unit, the offset-adjusted target instruction error signal obtained by the processing is exported from the delay control circuit through the target tap interface for sampling by the signal sampling clock.

[0080] The target instruction error signal is a instruction error signal that has been subjected to delay control processing by the target delay unit to adjust the offset between the instruction error signal and the sampling edge of the signal sampling clock.

[0081] Specifically, the delay adjustment training is to determine the target tap interface from the delay control circuit. In the actual application stage after the delay adjustment training, the computer device can generate an instruction error signal in the actual application scenario through the memory, and send the generated instruction error signal to the host. After receiving the instruction error signal input from the memory through the host, the computer device can transmit the received instruction error signal through the target delay unit to perform delay control processing to obtain the offset-adjusted target instruction error signal. Furthermore, the computer device can derive the processed offset-adjusted target instruction error signal from the delay control circuit through the target tap interface. After the computer device derives the target instruction error signal from the delay control circuit, the computer device can sample the target instruction error signal through the signal sampling clock of the host.

[0082] In the above-mentioned signal delay control method, a sample instruction error signal sent by a memory is obtained by a host; a delay control circuit provided on the host includes sequentially connected delay units; each delay unit is connected to a tap interface; and the tap interface supports signal derivation from the delay control circuit. By performing delay adjustment training based on the sample instruction error signal, delay adjustment information for the delay control circuit on the host can be determined. Based on the delay adjustment information, a target tap interface can be determined from the delay control circuit. The target delay unit preceding the target tap interface can be used to perform signal offset adjustment on the instruction error signal through delay processing to obtain an instruction error signal aligned with the sampling edge of the host's signal sampling clock. The instruction error signal input by the memory can be subjected to delay control processing through the target delay unit to obtain an offset-adjusted target instruction error signal, which can then be directly derived from the delay control circuit via the target tap interface. Because the target instruction error signal derived from the delay control circuit has been realigned with the sampling edge of the host's signal sampling clock, the host can be guaranteed to correctly sample the target instruction error signal, thereby ensuring that the target instruction error signal fed back from the memory to the host can be responded to in a timely manner, avoiding instruction execution errors in the memory and improving the stability of the memory's instruction operation.

[0083] In one embodiment, delay adjustment training is performed based on a sample instruction error signal to determine delay adjustment information for a delay control circuit on a host, including: in a first state in which the host samples the sample instruction error signal through a signal sampling clock, adjusting the delay control circuit on the host in a direction of increasing the delay of the sample instruction error signal until a second state in which the host does not sample the sample instruction error signal through the signal sampling clock occurs, thereby obtaining first adjustment information for the delay control circuit on the host; restoring the second state to the first state, and adjusting the delay control circuit on the host in a direction of reducing the delay of the sample instruction error signal until a second state in which the host does not sample the sample instruction error signal through the signal sampling clock occurs, thereby obtaining second adjustment information for the delay control circuit on the host; and determining the delay adjustment information for the delay control circuit on the host based on the first adjustment information and the second adjustment information.

[0084] The first state is a state in which the host samples a sample instruction error signal through the signal sampling clock. The second state is a state in which the host does not sample the sample instruction error signal through the signal sampling clock. The first adjustment information is adjustment information recorded when the host goes from sampling the sample instruction error signal to not sampling the sample instruction error signal through the signal sampling clock during the process of increasing the delay of the sample instruction error signal, that is, when the sample instruction error signal is in a critical state. The second adjustment information is adjustment information recorded when the host goes from sampling the sample instruction error signal to not sampling the sample instruction error signal through the signal sampling clock during the process of reducing the delay of the sample instruction error signal, that is, when the sample instruction error signal is in a critical state.

[0085] Specifically, the computer device can transmit a sample instruction error signal to the host via a memory and sample the sample instruction error signal using the host's signal sampling clock. In a first state where the host samples the sample instruction error signal using the signal sampling clock, the computer device can adjust the host's delay control circuit to increase the delay of the sample instruction error signal, namely, gradually increasing the number of delay cells through which the sample instruction error signal is transmitted, until a second state in which the host does not sample the sample instruction error signal using the signal sampling clock occurs, at which point first adjustment information for the host's delay control circuit is recorded. The second state is restored to the first state, namely, the second state in which the host does not sample the sample instruction error signal using the signal sampling clock is restored to the first state in which the host does sample the sample instruction error signal using the signal sampling clock at the beginning of training, and the delay control circuit on the host is adjusted to decrease the delay of the sample instruction error signal, namely, gradually reducing the number of delay cells through which the sample instruction error signal is transmitted, until a second state in which the host does not sample the sample instruction error signal using the signal sampling clock occurs again, at which point second adjustment information for the host's delay control circuit is recorded. Furthermore, the computer device can determine delay adjustment information for the host's delay control circuit based on the recorded first and second adjustment information.

[0086] In one embodiment, the computer device gradually increases or decreases the number of delay units through which the sample instruction error signal is transmitted. Specifically, the number of delay units through which the sample instruction error signal is transmitted may be increased or decreased step by step, and the number of delay units increased or decreased in each step may be at least one. For example, the number of delay units may be increased or decreased by one, two, or three delay units in one step.

[0087] In one embodiment, Figure 6As shown, the computer device can sample the sample instruction error signal using the host's signal sampling clock. In the first stage of delay adjustment training, when the host samples the sample instruction error signal using the signal sampling clock, the computer device can adjust the delay control circuit on the host in the direction of increasing the delay of the sample instruction error signal until the host enters the second state where the sample instruction error signal is not sampled using the signal sampling clock, thus reaching the second stage of delay adjustment training. At this point, the computer device immediately records the first adjustment information for the delay control circuit on the host. Furthermore, the computer device can restore the second state to the first state, i.e., restore to the first stage of delay adjustment training, and adjust the delay control circuit on the host in the direction of decreasing the delay of the sample instruction error signal until the host enters the second state where the sample instruction error signal is not sampled using the signal sampling clock again. This reaches the third stage of delay adjustment training, at which point the computer device immediately records the second adjustment information for the delay control circuit on the host.

[0088] In the above embodiment, the host can sample a sample instruction error signal via the signal sampling clock, indicating that the sampling edge of the signal sampling clock has not drifted outside the data window where the sample instruction error signal is located. In this case, adjusting the delay control circuit on the host in a direction that increases the delay of the sample instruction error signal can increase the delay of the sample instruction error signal. If the sample instruction error signal is not sampled during the delay increase process, first adjustment information indicating a critical state on one side of the data window can be immediately recorded. Furthermore, restoring the second state to the first state and adjusting the delay control circuit on the host in a direction that decreases the delay of the sample instruction error signal can reduce the delay of the sample instruction error signal. If the sample instruction error signal is not sampled during the delay reduction process, second adjustment information indicating a critical state on the other side of the data window can be immediately recorded. In this way, based on the first adjustment information and the second adjustment information, the delay adjustment information corresponding to the sample instruction error signal that can be sampled can be accurately determined.

[0089] In one embodiment, a delay control circuit includes a first subcircuit and a second subcircuit; the second subcircuit is connected after the first subcircuit; the first subcircuit and the second subcircuit each include sequentially connected delay units; first adjustment information includes a first number of delay units in the second subcircuit through which a sample instruction error signal has been transmitted; in a first state in which a host samples the sample instruction error signal using a signal sampling clock, adjusting the delay control circuit on the host in a direction of increasing the delay of the sample instruction error signal until a second state in which the host does not sample the sample instruction error signal using the signal sampling clock occurs, thereby obtaining first adjustment information for the delay control circuit on the host, including: controlling the acquired sample instruction error signal to sequentially pass through each delay unit in the first subcircuit to perform initial delay control processing to obtain a sample instruction error signal after initial control; in the first state in which the host samples the sample instruction error signal after initial control using the signal sampling clock, continuing to control the sample instruction error signal after initial control to transmit through each delay unit in the second subcircuit one by one in a direction of increasing the delay of the sample instruction error signal after initial control until a second state in which the signal sampling clock does not sample the sample instruction error signal from a corresponding tap interface of the second subcircuit occurs, thereby recording the first number of delay units in the second subcircuit through which the sample instruction error signal has been transmitted.

[0090] The first sub-circuit and the second sub-circuit are sub-circuits in the delay control circuit respectively.

[0091] Specifically, the computer device can send a sample instruction error signal to a host via a memory, and receive the sample instruction error signal via the host. Furthermore, the computer device can control the acquired sample instruction error signal via the host to sequentially pass through each delay unit in the first sub-circuit, thereby performing initial delay control processing on the acquired sample instruction error signal and obtaining a sample instruction error signal after initial control. The computer device can sample the sample instruction error signal after initial control via the host's signal sampling clock. When the host samples the sample instruction error signal after initial control via the signal sampling clock in a first state, the computer device can continue to control the sample instruction error signal after initial control to be transmitted through the delay units in the second sub-circuit one by one in a direction increasing the delay of the sample instruction error signal after initial control, until a second state occurs in which the signal sampling clock does not sample the sample instruction error signal from the corresponding tap interface of the second sub-circuit, and then record the first number of delay units in the second sub-circuit through which the sample instruction error signal has been transmitted.

[0092] In the above embodiment, the first sub-circuit performs initial delay control processing on the sample instruction error signal to obtain the sample instruction error signal after the initial control. At this time, the sample instruction error signal after the initial control may not be aligned with the sampling edge of the signal sampling clock. By, in a first state in which the sample instruction error signal after the initial control is sampled, continuously controlling the sample instruction error signal after the initial control to be transmitted through the delay cells in the second sub-circuit one by one in a direction of increasing the delay of the sample instruction error signal after the initial control until a second state in which the signal sampling clock does not sample the sample instruction error signal from the corresponding tap interface of the second sub-circuit occurs, immediately recording the first number of delay cells in the second sub-circuit through which the sample instruction error signal has been transmitted. In this way, first adjustment information accurately representing the critical state of one side of the data window of the sample instruction error signal can be recorded, thereby further improving the accuracy of the obtained delay adjustment information.

[0093] In one embodiment, the second adjustment information includes a second number of delay units that the sample instruction error signal has not been transmitted through; restoring the second state to the first state, and adjusting the delay control circuit on the host in the direction of reducing the delay of the sample instruction error signal until the host reaches the second state in which the sample instruction error signal has not been sampled by the signal sampling clock, thereby obtaining second adjustment information for the delay control circuit on the host, including: restoring the second state to the first state, and controlling the sample instruction error signal after the initial control to be transmitted through the delay units in the first sub-circuit one by one in the direction of reducing the delay of the sample instruction error signal after the initial control, until the signal sampling clock reaches the second state in which the sample instruction error signal has not been sampled from the corresponding tap interface of the first sub-circuit, and recording the second number of delay units that the sample instruction error signal has not been transmitted through.

[0094] Specifically, the computer device can restore the second state to the first state, that is, restore the second state in which the host fails to sample the sample instruction error signal after initial control via the signal sampling clock to the first state in which the host fails to sample the sample instruction error signal after initial control via the signal sampling clock during initial training. Furthermore, the computer device can control the sample instruction error signal after initial control to be transmitted through fewer delay units in the first sub-circuit one by one, in a direction that reduces the delay of the sample instruction error signal after initial control, until the second state in which the signal sampling clock fails to sample the sample instruction error signal from the corresponding tap interface of the first sub-circuit is reached. The computer device can then record the second number of delay units through which the sample instruction error signal failed to be transmitted.

[0095] In one embodiment, reference Figure 4The step counter in the delay control circuit can be used to record a first number of delay units in the second sub-circuit through which the sample instruction error signal has been transmitted, and to record a second number of delay units through which the sample instruction error signal has not been transmitted.

[0096] In the above embodiment, in order to reduce the delay of the sample instruction error signal after initial control, the sample instruction error signal after initial control is controlled to be transmitted through the delay cells in the first sub-circuit one by one, one by one, until a second state occurs in which the signal sampling clock fails to sample the sample instruction error signal from the corresponding tap interface of the first sub-circuit. Then, the second number of delay cells through which the sample instruction error signal failed to pass is immediately recorded. In this way, second adjustment information accurately representing the critical state on the other side of the data window of the sample instruction error signal can be recorded, thereby further improving the accuracy of the obtained delay adjustment information.

[0097] In one embodiment, determining delay adjustment information for a delay control circuit on the host according to the first adjustment information and the second adjustment information includes: determining the delay adjustment information for the delay control circuit on the host according to an average of the first quantity and the second quantity.

[0098] Specifically, the computer device may calculate an average of the first number and the second number, and obtain delay adjustment information for the delay control circuit on the host based on the average of the first number and the second number.

[0099] In one embodiment, the computer device may directly use the calculated average of the first quantity and the second quantity as delay adjustment information for the delay control circuit on the host.

[0100] In the above embodiment, the delay adjustment information is determined by the average of the first number and the second number, which can further improve the accuracy of the delay adjustment information.

[0101] In one embodiment, in a first state in which the host samples a sample instruction error signal through a signal sampling clock, before adjusting a delay control circuit on the host in a direction of increasing a delay of the sample instruction error signal, the method further includes: in a second state in which the host does not sample a sample instruction error signal through the signal sampling clock, performing frequency reduction adjustment processing on a current operating frequency of the host to obtain a reduced target operating frequency; the target operating frequency is an operating frequency at which the host samples the sample instruction error signal through the signal sampling clock; and sampling the sample instruction error signal based on the signal sampling clock in the host operating at the target operating frequency so that the signal sampling clock samples the sample instruction error signal.

[0102] The current operating frequency is the host's current operating frequency, that is, the host's operating frequency when the host fails to sample the sample instruction error signal through the signal sampling clock. The target operating frequency is the frequency obtained by adjusting the current operating frequency to a lower frequency.

[0103] Specifically, the computer device can transmit a sample instruction error signal to the host via a memory and sample the sample instruction error signal using the host's signal sampling clock. In the second state where the host fails to sample the sample instruction error signal using the signal sampling clock, this indicates that the host's current operating frequency is too high, resulting in a short duration for the sample instruction error signal to remain high, and thus preventing the host from sampling the sample instruction error signal using the signal sampling clock. In this case, the computer device can adjust the host's current operating frequency to reduce the frequency and obtain a lowered target operating frequency. It will be appreciated that reducing the host's operating frequency can extend the duration for which the sample instruction error signal remains high, allowing the signal sampling clock in the host operating at the target operating frequency to successfully sample the sample instruction error signal. Furthermore, the computer device can sample the sample instruction error signal based on the signal sampling clock in the host operating at the target operating frequency, ensuring that the signal sampling clock samples the sample instruction error signal. Subsequently, in the first state where the host samples the sample instruction error signal using the signal sampling clock, the aforementioned step of adjusting the delay control circuit on the host to increase the delay of the sample instruction error signal and subsequent steps are performed.

[0104] In the above embodiment, after the host receives the sample instruction error signal sent by the memory, if the host fails to sample the sample instruction error signal through the signal sampling clock, it means that the sampling edge of the signal sampling clock has drifted out of the data window where the sample instruction error signal is located. At this time, by reducing the current operating frequency of the host to the target operating frequency, the host operating at the target operating frequency can extend the time that the sample instruction error signal remains high, thereby allowing the host's signal sampling clock to sample the sample instruction error signal, thereby improving the success rate of delay adjustment training.

[0105] In one embodiment, the method also includes: obtaining a sample instruction; the sample instruction carries a field set that causes the memory to generate a sample instruction error signal after obtaining the sample instruction; sending the sample instruction to the memory through the host, so that the memory performs an XOR operation on each field in the field set to perform instruction verification on the sample instruction, and triggers the generation of a sample instruction error signal based on the verification result obtained by the verification; and sending the generated sample instruction error signal to the host through the memory.

[0106] The sample instruction is an instruction used to trigger the memory to generate a sample instruction error signal. It is understood that a sample instruction may include multiple fields. A field set is a set consisting of the fields in the sample instruction. Performing an XOR operation on the fields refers to performing an XOR operation on the field values.

[0107] Specifically, the computer device may generate, through the host, a sample instruction containing a set of fields that causes the memory to generate a sample instruction error signal, and send the sample instruction to the memory through the host. The computer device may receive the sample instruction through the memory and perform an exclusive-OR operation on each field in the set of fields of the sample instruction to perform instruction verification on the sample instruction to obtain a verification result. The computer device may trigger the generation of a sample instruction error signal through the memory based on the verification result obtained through the verification, and send the generated sample instruction error signal to the host through the memory.

[0108] In one embodiment, the instructions supported by the computer device include line instructions, such as Figure 7 As shown, row instructions may specifically include row no operation instructions (Row No Operation instruction), activate instruction (Activate instruction), precharge instruction (Precharge instruction), all precharge instructions (Precharge All instruction), single address refresh instruction (Single Bank Refresh instruction), refresh instruction (Refresh instruction), power-down entry instruction (Power-Down Entry instruction), automatic refresh entry instruction (Self Refresh Entry instruction), power-down instruction / automatic refresh exit instruction (Power-Down / Self Refresh Exit instruction). Each row instruction includes seven fields, namely field 1 to field 7, where the H field represents 1, the L field represents 0, the V field can represent 1 or 0, the PAR field represents the instruction check field, the BA field represents the bank address, the RA field represents the row address, and the SID represents the stack identification number.

[0109] In one embodiment, the instructions supported by the computer device include column instructions, such as Figure 8As shown, column instructions may specifically include Column No Operation instructions (column no operation instructions), Read instructions, Read w / AP instructions (Read with Auto Precharge, read instructions with automatic precharge), Write instructions, Write w / AP instructions (Write with Auto Precharge, write instructions with automatic precharge), and Mode Register Set instructions. Each column instruction includes nine fields, namely field 1 to field 9, where the H field represents 1, the L field represents 0, the V field can represent 1 or 0, the PAR field represents the instruction check field, the BA field represents the bank address, the CA field represents the column address, the SID represents the stack identification number, and the OP field represents the operation code.

[0110] In one embodiment, Figure 9 As shown, the command sent by the host to the memory is an activation command. Figure 7 It can be seen that the activation instruction is a two-cycle instruction, which occupies two cycles, T0 and T1. Among them, BAx and RAy (Bank address and row address) are sent at T0, and RAy (row address) is sent at T1. The instruction sent by the host to the memory is a read / write instruction. Figure 8 It can be seen that the read / write instruction is a single-cycle instruction, which takes up a total of one cycle T2. Among them, BAZ and CAn (Bank address and column address) are sent on the rising edge, and CAn (column address) is sent on the falling edge. If an instruction check error occurs in the first clock cycle of the activation instruction sent at time T0, the memory can generate a corresponding instruction error signal, and after a preset two-cycle delay, that is, at time T2, the memory can return a preset instruction error signal to the host for one clock cycle. Among them, clock 1 and clock 2 are two differential clocks, and x, y, z and n can represent natural numbers respectively.

[0111] In one embodiment, Figure 10 As shown, if a command parity error occurs in the first clock cycle of the activation command sent at time T0, the memory may generate a corresponding command error signal and, after a preset two-cycle delay, at time T2, return a command error signal to the host for a preset one-clock cycle. Simultaneously, if a command parity error occurs in the read / write command sent at time T2, the memory may generate a corresponding command error signal and, after a preset two-cycle delay, at time T4, return a command error signal to the host for a preset one-clock cycle.

[0112] In one embodiment, Figure 11As shown, if an instruction check error occurs in the first clock cycle of the activation instruction sent at time T0, the memory may generate a corresponding instruction error signal, and after a preset two-cycle delay, that is, at time T2, the memory may return an instruction error signal to the host that lasts for a preset one clock cycle. At the same time, if an instruction check error occurs in the second clock cycle of the activation instruction sent at time T1, the memory may generate a corresponding instruction error signal, and after a preset two-cycle delay, that is, at time T3, the memory may return an instruction error signal to the host that lasts for a preset one clock cycle. In addition, if an instruction check error occurs in the read / write instruction sent at time T2, the memory may generate a corresponding instruction error signal, and after a preset two-cycle delay, that is, at time T4, the memory may return an instruction error signal to the host that lasts for a preset one clock cycle.

[0113] In the above embodiment, by generating a sample instruction that carries a field set that causes the memory to generate a sample instruction error signal after obtaining the sample instruction, and performing an XOR operation on each field in the field set through the memory to perform instruction verification on the sample instruction to generate a sample instruction error signal, the smooth progress of the delay adjustment training process can be ensured and the success rate of the delay adjustment training can be improved.

[0114] In one embodiment, the field set includes an instruction check field and multiple non-instruction check fields; the second XOR result obtained by performing an XOR operation on the instruction check field and the first XOR result is used to indicate that the memory generates a sample instruction error signal after receiving the sample instruction; the first XOR result is the result obtained by performing an XOR operation on multiple non-instruction check fields.

[0115] The instruction check field is a check field in the sample instruction, used to perform instruction check on the sample instruction. The non-instruction check field is a field in the sample instruction other than the instruction check field. The first XOR result is the result obtained by performing an XOR operation on the values ​​of each non-instruction check field in the sample instruction. The second XOR result is the result obtained by performing an XOR operation on the value of the instruction check field and the first XOR result.

[0116] Specifically, the computer device may perform an exclusive-OR operation on the values ​​of each non-instruction check field in the sample instruction in sequence to obtain a first exclusive-OR result. Furthermore, the computer device may perform an exclusive-OR operation on the value of the instruction check field and the first exclusive-OR result to obtain a second exclusive-OR result. It is understood that the second exclusive-OR result is the verification result obtained by performing instruction check on the sample instruction. The computer device may trigger the generation of a sample instruction error signal based on the verification result via the memory.

[0117] In one embodiment, Figure 12 As shown, the computer can Figure 12 The even parity check method shown is used to check instructions. It is understood that instructions may include row instructions and column instructions. If the instruction fields in the instruction except the PAR field (instruction parity field), that is, the values ​​of each non-instruction parity field in the row instruction, are sequentially XORed, if the result of the operation is an even number (i.e., 0) and the PAR field (instruction parity field) is L (i.e., 0), the output of the instruction error signal is L (i.e., 0, indicating that the instruction parity is not an error and the memory does not generate an instruction error signal). If the result of the operation is an even number (i.e., 0) and the PAR field (instruction parity field) is H (i.e., 1), the output of the instruction error signal is H (i.e., 1, indicating that an instruction parity error occurred and the memory will generate an instruction error signal). If the result of the operation is an odd number (i.e., 1) and the PAR field (instruction parity field) is L (i.e., 0), the output of the instruction error signal is H (i.e., 1, indicating that an instruction parity error occurred and the memory will generate an instruction error signal). If the operation result is an odd number (i.e., 1) and the PAR field (instruction parity field) is H (i.e., 1), the instruction error signal output is L (i.e., 0, meaning the instruction parity is correct and the memory does not generate an instruction error signal). Therefore, it can be understood that if an instruction error signal is to be generated, the second XOR result obtained by performing an XOR operation on the instruction parity field (i.e., PAR field) and the first XOR result must be 1. The first XOR result is the result obtained by sequentially performing an XOR operation on the values ​​of each non-instruction parity field in the instruction.

[0118] In one embodiment, Figure 13 As shown, the computer device can generate a sample instruction for delay adjustment training, namely a precharge all instruction (PREA instruction, i.e., Precharge All instruction). If the result of the XOR operation of the values ​​of the non-instruction check fields in the precharge all instruction is 1, and the instruction check field (i.e., PAR field) is 0, then the precharge all instruction will cause a memory check error and generate a corresponding instruction error signal.

[0119] In one embodiment, Figure 14 As shown, the computer device can generate a sample instruction for delay adjustment training, namely a read instruction (RD instruction, i.e., Read instruction). If the result of the XOR operation of the values ​​of the non-instruction check fields in the read instruction is 0, and the instruction check field (i.e., PAR field) is 1, then the read instruction will cause a memory check error, generating a corresponding instruction error signal.

[0120] In the above embodiment, by generating a sample instruction that carries a field set that causes the memory to generate a sample instruction error signal after obtaining the sample instruction, an error can be caused when the memory performs instruction verification on the sample instruction, so as to generate a sample instruction error signal for delay adjustment training, thereby ensuring the smooth progress of the delay adjustment training and further improving the success rate of the delay adjustment training.

[0121] In one embodiment, after determining the target tap interface from the delay control circuit based on the delay adjustment information, the method further includes: periodically triggering, through a timer, the step of obtaining a sample instruction error signal sent by the host through hardware control to trigger re-delay adjustment training.

[0122] Specifically, a timer is deployed in the computer device, and the computer device can use the timer to periodically trigger the step of obtaining a sample instruction error signal sent by the memory through the host through hardware control, thereby triggering the re-delay adjustment training. It is understood that the computer device can use the timer to trigger the re-delay adjustment training through hardware control once every preset interval.

[0123] For example, a computer device can use a timer to time and trigger delay adjustment training through hardware control every 24 hours.

[0124] In the above embodiment, the delay control circuit is periodically retrained through hardware control by periodically triggering the timer, which can ensure that there will be no deviation between the instruction error signal and the sampling edge of the signal sampling clock during the operation of the computer, further improving the stability of the memory instruction operation.

[0125] In one embodiment, after determining the target tap interface from the delay control circuit based on the delay adjustment information, the method further includes: monitoring the system operating status of the high-bandwidth memory system; the high-bandwidth memory system includes a host and a memory; if the system operating status is not busy, re-executing the step of obtaining a sample instruction error signal sent by the memory through the host through software control to trigger re-delay adjustment training.

[0126] Specifically, a high-bandwidth memory system is deployed in the computer device, and the computer device can monitor the working status of the high-bandwidth memory system. If the system working status of the high-bandwidth memory system is detected to be a non-busy state, the computer device can re-execute the step of obtaining the sample instruction error signal sent by the memory through the host through software control to trigger re-delay adjustment training. If the system working status of the high-bandwidth memory system is detected to be a busy state, the computer device can temporarily not perform delay adjustment training through software control, and wait until the next time the system working status of the high-bandwidth memory system is detected to be a non-busy state, then perform delay adjustment training again.

[0127] In the above embodiment, through software control, the delay control circuit can be retrained when the high-bandwidth memory system is not busy. This further ensures that the instruction error signal and the sampling edge of the signal sampling clock do not deviate during computer operation, further improving the stability of memory instruction operation. Furthermore, retraining the delay control circuit when the high-bandwidth memory system is not busy can also ensure the operating efficiency of the entire high-bandwidth memory system.

[0128] In one embodiment, the method also includes: sending the target instruction to the memory through the host; receiving the instruction error signal sent by the memory through the host; the instruction error signal sent by the memory is a signal generated after the memory performs instruction verification on the target instruction; controlling the instruction error signal sent by the memory to be transmitted to the target delay unit in the delay control circuit in sequence, so as to perform delay control processing on the instruction error signal sent by the memory.

[0129] Among them, the target instruction is the instruction generated by the host after the delay adjustment training is completed. It can be understood that the target instruction is the instruction generated by the host in actual application, and is not an instruction generated for delay adjustment training.

[0130] Specifically, the computer device can obtain a target instruction through a host and send the target instruction to a memory through the host. The computer device can receive the target instruction sent by the host through the memory and perform an instruction check on the target instruction. If the check result indicates that the target instruction is incorrect, the computer device triggers the generation of an instruction error signal based on the check result and sends the generated instruction error signal to the host. The computer device can receive the instruction error signal sent by the memory through the host and control the instruction error signal sent by the memory to be sequentially transmitted to the target delay unit in the delay control circuit through the target delay unit, so that the instruction error signal sent by the memory is subjected to delay control processing.

[0131] In the above embodiment, the host can transmit the instruction error signal generated in the actual application stage to the target delay unit in the delay control circuit in sequence to perform delay control processing on the instruction error signal sent by the memory, so that the target instruction error signal after delay control processing is aligned with the sampling edge of the signal sampling clock, thereby ensuring that the host can correctly sample the target instruction error signal.

[0132] In one embodiment, the method further includes: sampling a target instruction error signal derived from the delay control circuit through a signal sampling clock; aligning the derived target instruction error signal with a sampling edge of a signal sampling clock of a host; and resending a target instruction corresponding to the target instruction error signal to a memory through the host based on the target instruction error signal obtained through sampling.

[0133] Specifically, the computer device can sample the target instruction error signal derived from the delay control circuit using the host's signal sampling clock. The computer device can regenerate the target instruction corresponding to the target instruction error signal based on the sampled target instruction error signal through the host, and resend the target instruction corresponding to the target instruction error signal to the memory.

[0134] In one embodiment, the derived target instruction error signal is aligned with the sampling edge of the host's signal sampling clock. Specifically, the center of the target instruction error signal is aligned with the sampling edge of the host's signal sampling clock, wherein the sampling edge of the signal sampling clock can be the rising edge or the falling edge of the signal sampling clock.

[0135] In the above embodiment, the host resends the target instruction corresponding to the target instruction error signal to the memory based on the target instruction error signal obtained by correct sampling, so as to ensure the normal operation of the instruction of the memory and further ensure the stability of the instruction operation of the memory.

[0136] In one embodiment, Figure 15As shown, during the delay adjustment training process, the computer device can generate a sample instruction through the instruction generation unit on the host, and send the sample instruction to the memory through the instruction sending unit. The memory can receive the sample instruction sent by the host through the instruction receiving unit, and parse the sample instruction through the instruction parsing unit, and then perform instruction verification on the parsed sample instruction through the instruction verification unit. Since the sample instruction carries a field set that causes the memory to generate a sample instruction error signal after obtaining the sample instruction, the instruction verification unit performs instruction verification on the parsed sample instruction and then generates a sample instruction error signal. The memory can send the sample instruction error signal to the host based on the instruction error signal sending pin through the sample instruction error signal sending unit. Furthermore, the host can train the delay control circuit on the host based on the sample instruction error signal to determine the target tap interface for deriving the instruction error signal. In actual application, after the instruction error signal input by the memory is processed by the target delay unit before the target tap interface, the offset-adjusted target instruction error signal obtained by processing is exported from the delay control circuit through the target tap interface for sampling by the host's signal sampling clock. The sampled target instruction error signal can be sent to the instruction error signal receiving unit, so that the host can perform corresponding processing based on the target instruction error signal, such as resending instructions to the memory or performing corresponding circuit maintenance.

[0137] In one embodiment, the host's instruction sending unit needs to send corresponding instructions in the timing that each instruction should follow. Figure 16 As shown, with reference Figure 7 From the details of the Precharge Instruction / Precharge All Instruction (i.e., Precharge Instruction / Precharge All Instruction), it can be seen that each field in the Precharge Instruction / Precharge All Instruction (i.e., Field 1 to Field 7) must be sent at the corresponding timing. The only difference between the Precharge Instruction / Precharge All Instruction is that in Field 5, if it is a Precharge Instruction, Field 5 is L (i.e., 0), and if it is a Precharge All Instruction, Field 5 is H (i.e., 1). For another example,

[0138] like Figure 17 As shown, with reference Figure 8 From the details of the read instruction and the read instruction with automatic pre-charging (i.e., Read instruction and Readw / AP instruction), it can be seen that each field in the read instruction and the read instruction with automatic pre-charging (i.e., field 1 to field 9) must be sent at the corresponding timing. Among them, the only difference between the read instruction and the read instruction with automatic pre-charging is in field 4. If it is a read instruction, field 4 is L (i.e., 0), and if it is a read instruction with automatic pre-charging, field 4 is H (i.e., 1).

[0139] like Figure 18As shown, in one embodiment, a signal delay control method is provided. The method can be applied to a computer device, which can be a terminal or a server. The method can be executed independently by the terminal or server itself, or through interaction between the terminal and the server. This embodiment uses the method applied to a computer device as an example to illustrate, and includes the following steps:

[0140] Step 1802 , obtain a sample instruction; the sample instruction carries a field set that causes the memory to generate a sample instruction error signal after obtaining the sample instruction.

[0141] In step 1804, the sample instruction is sent to the memory through the host, so that the memory performs an XOR operation on each field in the field set to perform instruction verification on the sample instruction, and triggers the generation of a sample instruction error signal based on the verification result obtained; the delay control circuit set on the host includes delay units connected in sequence; each delay unit is connected to a tap interface; the tap interface supports the derivation of signals from the delay control circuit; the delay control circuit includes a first subcircuit and a second subcircuit; the second subcircuit is connected after the first subcircuit; the first subcircuit and the second subcircuit respectively include delay units connected in sequence.

[0142] Step 1806: Send the generated sample instruction error signal to the host through the memory; obtain the sample instruction error signal sent by the memory through the host;

[0143] Step 1808 : Control the acquired sample instruction error signal to pass through each delay unit in the first sub-circuit in sequence to perform initial delay control processing to obtain a sample instruction error signal after initial control.

[0144] Step 1810, in the second state where the host does not sample the sample instruction error signal after initial control through the signal sampling clock, the current operating frequency of the host is adjusted to reduce the frequency to obtain a reduced target operating frequency; the target operating frequency is the operating frequency that causes the host to sample the sample instruction error signal after initial control through the signal sampling clock.

[0145] Step 1812: based on the signal sampling clock in the host operating at the target operating frequency, sample the sample instruction error signal after the initial control, so that the signal sampling clock samples the sample instruction error signal after the initial control.

[0146] Step 1814: In the first state where the host samples the sample instruction error signal after initial control through the signal sampling clock, continue to control the sample instruction error signal after initial control to be transmitted through the delay units in the second sub-circuit one by one in the direction of increasing the delay of the sample instruction error signal after initial control, until the second state where the signal sampling clock does not sample the sample instruction error signal from the corresponding tap interface of the second sub-circuit appears, and record the first number of delay units in the second sub-circuit through which the sample instruction error signal has been transmitted.

[0147] Step 1816: restore the second state to the first state, and control the sample instruction error signal after the initial control to be transmitted through the delay units in the first sub-circuit one by one in the direction of reducing the delay of the sample instruction error signal after the initial control, until a second state occurs in which the signal sampling clock does not sample the sample instruction error signal from the corresponding tap interface of the first sub-circuit, and record the second number of delay units through which the sample instruction error signal has not been transmitted.

[0148] Step 1818: Determine delay adjustment information for a delay control circuit on the host according to an average of the first number and the second number.

[0149] Step 1820: Based on the delay adjustment information, determine the target tap interface from the delay control circuit; wherein, the target delay unit before the target tap interface is used to perform signal offset adjustment on the instruction error signal through delay processing to obtain an instruction error signal that is aligned with the sampling edge of the host's signal sampling clock.

[0150] Step 1822, the target instruction is sent to the memory through the host; the instruction error signal sent by the memory is received through the host; the instruction error signal sent by the memory is a signal generated after the memory performs instruction verification on the target instruction.

[0151] Step 1824 , controlling the instruction error signal sent by the memory to be transmitted to the target delay unit in the delay control circuit in sequence, so as to perform delay control processing on the instruction error signal sent by the memory.

[0152] Step 1826: After the instruction error signal input from the memory is processed by the target delay unit, the offset-adjusted target instruction error signal obtained by the processing is exported from the delay control circuit through the target tap interface for sampling by the signal sampling clock.

[0153] Step 1828: Sample the target instruction error signal derived from the delay control circuit using the signal sampling clock; the derived target instruction error signal is aligned with the sampling edge of the host's signal sampling clock.

[0154] Step 1830 : The host resends the target instruction corresponding to the target instruction error signal to the memory based on the target instruction error signal obtained through sampling.

[0155] The present application also provides an application scenario, which applies the above-mentioned signal delay control method. Specifically, the signal delay control method can be applied to the scenario of activation instruction error signal delay control, wherein the memory is a dynamic random access memory. The computer device can obtain a sample activation instruction; the sample activation instruction carries a field set that causes the dynamic random access memory to generate a sample activation instruction error signal after obtaining the sample activation instruction. The sample activation instruction is sent to the dynamic random access memory by the host, so that the dynamic random access memory performs an XOR operation on each field in the field set to perform instruction verification on the sample activation instruction, and triggers the generation of a sample activation instruction error signal based on the verification result obtained by the verification; the delay control circuit set on the host includes delay units connected in sequence; each delay unit is connected to a tap interface; the tap interface supports the derivation of signals from the delay control circuit; the delay control circuit includes a first subcircuit and a second subcircuit; the second subcircuit is connected after the first subcircuit; the first subcircuit and the second subcircuit respectively include delay units connected in sequence.

[0156] The computer device can send the generated sample activation instruction error signal to the host through the dynamic random access memory; obtain the sample activation instruction error signal sent by the dynamic random access memory through the host; control the obtained sample activation instruction error signal to pass through each delay unit in the first sub-circuit in sequence to perform initial delay control processing to obtain the sample activation instruction error signal after initial control. In the second state where the host does not sample the sample activation instruction error signal after initial control through the signal sampling clock, the current operating frequency of the host is adjusted to reduce the frequency to obtain the target operating frequency after reduction; the target operating frequency is the operating frequency that enables the host to sample the sample activation instruction error signal after initial control through the signal sampling clock. Based on the signal sampling clock in the host operating at the target operating frequency, the sample activation instruction error signal after initial control is sampled so that the signal sampling clock samples the sample activation instruction error signal after initial control. In a first state where the host samples a sample activation command error signal after initial control via a signal sampling clock, the sample activation command error signal after initial control is continuously controlled to be transmitted through the delay cells in the second sub-circuit one by one, in a direction increasing the delay of the sample activation command error signal after initial control, until a second state where the signal sampling clock fails to sample the sample activation command error signal from the corresponding tap interface of the second sub-circuit occurs, at which point a first number of delay cells in the second sub-circuit through which the sample activation command error signal has been transmitted is recorded. The second state is restored to the first state, and the sample activation command error signal after initial control is controlled to be transmitted through the delay cells in the first sub-circuit one by one, in a direction decreasing the delay of the sample activation command error signal after initial control, until a second state where the signal sampling clock fails to sample the sample activation command error signal from the corresponding tap interface of the first sub-circuit occurs, at which point a second number of delay cells through which the sample activation command error signal has not been transmitted is recorded. Delay adjustment information for the delay control circuit on the host is determined based on the average of the first and second numbers. Based on the delay adjustment information, a target tap interface is determined from the delay control circuit; wherein, the target delay unit before the target tap interface is used to perform signal offset adjustment on the instruction error signal through delay processing to obtain an instruction error signal that is aligned with the sampling edge of the host's signal sampling clock.

[0157] The computer device can send a target instruction to a dynamic random access memory through a host; receive an instruction error signal sent by the dynamic random access memory through the host; the instruction error signal sent by the dynamic random access memory is a signal generated after the dynamic random access memory performs instruction verification on the target instruction; and the instruction error signal sent by the dynamic random access memory is controlled to be sequentially transmitted to the target delay unit in the delay control circuit to perform delay control processing on the instruction error signal sent by the dynamic random access memory. After the instruction error signal input by the dynamic random access memory is processed by the target delay unit, the offset-adjusted target instruction error signal obtained by the processing is exported from the delay control circuit through the target tap interface for sampling by the signal sampling clock.

[0158] The computer device can sample a target instruction error signal derived from a delay control circuit using a signal sampling clock; the derived target instruction error signal is aligned with a sampling edge of a host's signal sampling clock. The host retransmits a target instruction corresponding to the target instruction error signal to a dynamic random access memory based on the sampled target instruction error signal.

[0159] The present application also provides an application scenario, which applies the above-mentioned signal delay control method. Specifically, the signal delay control method can be applied to the scenario of read instruction error signal delay control, and can also be applied to the scenario of write instruction error signal delay control, etc.

[0160] It should be understood that, although the various steps in the flow chart of the above-mentioned embodiments are shown in sequence, these steps are not necessarily performed in sequence. Unless clearly stated herein, the execution of these steps does not have strict order restrictions, and these steps can be performed in other sequences. Moreover, at least a portion of the steps in the above-mentioned embodiments may include a plurality of sub-steps or a plurality of stages, and these sub-steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution order of these sub-steps or stages is not necessarily performed in sequence, but can be performed in turn or alternately with at least a portion of other steps or sub-steps or stages of other steps.

[0161] In one embodiment, Figure 19 As shown, a signal delay control device 1900 is provided. The device can be a software module or a hardware module, or a combination of the two to form a part of a computer device. The device specifically includes:

[0162] The acquisition module 1902 is used to obtain the sample instruction error signal sent by the memory through the host; the delay control circuit set on the host includes delay units connected in sequence; each delay unit is connected to a tap interface; the tap interface supports the export of signals from the delay control circuit.

[0163] Training module 1904 is used to perform delay adjustment training based on the sample instruction error signal to determine delay adjustment information for the delay control circuit on the host; based on the delay adjustment information, a target tap interface is determined from the delay control circuit; wherein, the target delay unit before the target tap interface is used to perform signal offset adjustment on the instruction error signal through delay processing to obtain an instruction error signal that is aligned with the sampling edge of the signal sampling clock of the host.

[0164] The export module 1906 is used to export the offset-adjusted target instruction error signal obtained by processing the instruction error signal input from the memory through the target delay unit from the delay control circuit through the target tap interface for sampling by the signal sampling clock.

[0165] In one embodiment, the training module 1904 is also used to adjust the delay control circuit on the host in the direction of increasing the delay of the sample instruction error signal when the host samples the sample instruction error signal through the signal sampling clock in the first state, until the host does not sample the sample instruction error signal through the signal sampling clock in the second state, and obtain first adjustment information for the delay control circuit on the host; restore the second state to the first state, and adjust the delay control circuit on the host in the direction of reducing the delay of the sample instruction error signal until the host does not sample the sample instruction error signal through the signal sampling clock in the second state, and obtain second adjustment information for the delay control circuit on the host; determine the delay adjustment information for the delay control circuit on the host based on the first adjustment information and the second adjustment information.

[0166] In one embodiment, the delay control circuit includes a first subcircuit and a second subcircuit; the second subcircuit is connected after the first subcircuit; the first subcircuit and the second subcircuit respectively include delay units connected in sequence; the first adjustment information includes a first number of delay units in the second subcircuit through which the sample instruction error signal has been transmitted; the training module 1904 is further used to control the acquired sample instruction error signal to pass through each delay unit in the first subcircuit in sequence to perform initial delay control processing to obtain the sample instruction error signal after initial control; in a first state in which the host samples the sample instruction error signal after initial control through the signal sampling clock, the sample instruction error signal after initial control is continued to be controlled to be transmitted through the delay units in the second subcircuit one by one in the direction of increasing the delay of the sample instruction error signal after initial control until a second state in which the signal sampling clock does not sample the sample instruction error signal from the corresponding tap interface of the second subcircuit occurs, and the first number of delay units in the second subcircuit through which the sample instruction error signal has been transmitted is recorded.

[0167] In one embodiment, the second adjustment information includes a second number of delay units through which the sample instruction error signal is not transmitted; the training module 1904 is also used to restore the second state to the first state, and in the direction of reducing the delay of the sample instruction error signal after the initial control, control the sample instruction error signal after the initial control to be transmitted through the delay units in the first sub-circuit one by one, until the second state occurs in which the signal sampling clock does not sample the sample instruction error signal from the corresponding tap interface of the first sub-circuit, and record the second number of delay units through which the sample instruction error signal is not transmitted.

[0168] In one embodiment, the training module 1904 is further configured to determine delay adjustment information for a delay control circuit on the host according to an average of the first number and the second number.

[0169] In one embodiment, the training module 1904 is also used to perform frequency reduction adjustment processing on the current operating frequency of the host in the second state in which the host does not sample the sample instruction error signal through the signal sampling clock to obtain the reduced target operating frequency; the target operating frequency is the operating frequency that enables the host to sample the sample instruction error signal through the signal sampling clock; based on the signal sampling clock in the host operating at the target operating frequency, the sample instruction error signal is sampled so that the signal sampling clock samples the sample instruction error signal.

[0170] In one embodiment, the acquisition module 1902 is also used to acquire sample instructions; the sample instructions carry a field set that causes the memory to generate a sample instruction error signal after acquiring the sample instructions; the device also includes: a sending module, used to send the sample instructions to the memory through the host, so that the memory performs an XOR operation on each field in the field set to perform instruction verification on the sample instructions, and triggers the generation of a sample instruction error signal based on the verification result obtained by the verification; the generated sample instruction error signal is sent to the host through the memory.

[0171] In one embodiment, the field set includes an instruction check field and multiple non-instruction check fields; the second XOR result obtained by performing an XOR operation on the instruction check field and the first XOR result is used to indicate that the memory generates a sample instruction error signal after receiving the sample instruction; the first XOR result is the result obtained by performing an XOR operation on multiple non-instruction check fields.

[0172] In one embodiment, the apparatus further includes: a timing module, configured to periodically trigger, through a timer, the notification acquisition module 1902 to execute, through hardware control, the step of acquiring a sample instruction error signal sent by the memory through the host, so as to trigger re-delay adjustment training.

[0173] In one embodiment, the device further includes: a monitoring module for monitoring the system working status of the high-bandwidth memory system; the high-bandwidth memory system includes a host and a memory; if the system working status is not busy, the notification acquisition module 1902 is controlled by software to re-execute the step of acquiring the sample instruction error signal sent by the host to the memory to trigger re-delay adjustment training.

[0174] In one embodiment, the device also includes: a sending module, which is used to send the target instruction to the memory through the host; the acquisition module 1902 is also used to receive the instruction error signal sent by the memory through the host; the instruction error signal sent by the memory is a signal generated after the memory performs instruction verification on the target instruction; the instruction error signal sent by the memory is controlled to be transmitted to the target delay unit in the delay control circuit in sequence, so as to perform delay control processing on the instruction error signal sent by the memory.

[0175] In one embodiment, the device further includes: a sampling module for sampling a target instruction error signal derived from the delay control circuit through a signal sampling clock; aligning the derived target instruction error signal with a sampling edge of the host's signal sampling clock; and retransmitting the target instruction corresponding to the target instruction error signal to the memory through the host based on the target instruction error signal obtained through sampling.

[0176] The signal delay control device described above obtains a sample instruction error signal sent by a memory through a host. The delay control circuit provided on the host includes sequentially connected delay units; each delay unit is connected to a tap interface; and the tap interface supports signal derivation from the delay control circuit. Delay adjustment training based on the sample instruction error signal can determine delay adjustment information for the delay control circuit on the host. Based on the delay adjustment information, a target tap interface can be determined from the delay control circuit. The target delay unit preceding the target tap interface can be used to perform signal offset adjustment on the instruction error signal through delay processing to obtain an instruction error signal aligned with the sampling edge of the host's signal sampling clock. The instruction error signal input by the memory can be subjected to delay control processing through the target delay unit to obtain an offset-adjusted target instruction error signal, which can then be directly derivated from the delay control circuit via the target tap interface. Because the target instruction error signal derived from the delay control circuit is realigned with the sampling edge of the host's signal sampling clock, the host can be guaranteed to correctly sample the target instruction error signal, thereby ensuring that the target instruction error signal fed back from the memory to the host is promptly responded to, avoiding instruction execution errors in the memory and improving the stability of the memory's instruction operation.

[0177] Each module in the aforementioned signal delay control device may be implemented in whole or in part through software, hardware, or a combination thereof. Each module may be embedded in or independent of a processor in a computer device in the form of hardware, or may be stored in a memory in the computer device in the form of software, so that the processor can call and execute the corresponding operations of each module.

[0178] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Figure 20 As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, abbreviated as I / O) and a communication interface. The processor, memory and input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a signal delay control method is implemented.

[0179] Those skilled in the art will understand that Figure 20 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0180] In one embodiment, a computer device is further provided, including a memory and a processor. The memory stores a computer program, and the processor implements the steps in the above method embodiments when executing the computer program.

[0181] In one embodiment, a computer-readable storage medium is provided, storing a computer program, which implements the steps in the above-mentioned method embodiments when executed by a processor.

[0182] In one embodiment, a computer program product is provided, including a computer program. When the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0183] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions.

[0184] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory, etc. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0185] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0186] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A signal delay control method, characterized in that: The method comprises: A sample instruction error signal sent by a memory is obtained through a host; a delay control circuit provided on the host includes delay units connected in sequence; each delay unit is connected to a tap interface; the tap interface supports deriving a signal from the delay control circuit; In a first state where the host samples the sample instruction error signal through the signal sampling clock, adjusting the delay control circuit on the host in a direction of increasing the delay of the sample instruction error signal until a second state where the host does not sample the sample instruction error signal through the signal sampling clock occurs, thereby obtaining first adjustment information for the delay control circuit on the host; Restoring the second state to the first state, and adjusting the delay control circuit on the host in a direction of reducing the delay of the sample instruction error signal until a second state occurs in which the host does not sample the sample instruction error signal through the signal sampling clock, thereby obtaining second adjustment information for the delay control circuit on the host; determining delay adjustment information for a delay control circuit on the host according to the first adjustment information and the second adjustment information; Based on the delay adjustment information, a target tap interface is determined from the delay control circuit; wherein the target delay unit before the target tap interface is used to perform signal offset adjustment on the instruction error signal through delay processing to obtain the instruction error signal aligned with the sampling edge of the signal sampling clock of the host; After the instruction error signal input from the memory is processed by the target delay unit, the offset-adjusted target instruction error signal obtained by the processing is derived from the delay control circuit through the target tap interface for sampling by the signal sampling clock.

2. The method according to claim 1, characterized in that The delay control circuit includes a first subcircuit and a second subcircuit; the second subcircuit is connected after the first subcircuit; the first subcircuit and the second subcircuit each include a delay unit connected in sequence; the first adjustment information includes a first number of delay units in the second subcircuit through which the sample instruction error signal has been transmitted; The method of adjusting the delay control circuit on the host in a direction of increasing the delay of the sample instruction error signal in a first state in which the host samples the sample instruction error signal through the signal sampling clock until a second state in which the host does not sample the sample instruction error signal through the signal sampling clock occurs, and obtaining first adjustment information for the delay control circuit on the host includes: Controlling the acquired sample instruction error signal to pass through each delay unit in the first sub-circuit in sequence to perform initial delay control processing to obtain a sample instruction error signal after initial control; In a first state in which the host samples the sample instruction error signal after initial control through a signal sampling clock, the sample instruction error signal after initial control is continuously controlled to be transmitted through the delay units in the second sub-circuit one by one in a direction of increasing the delay of the sample instruction error signal after initial control until a second state in which the signal sampling clock does not sample the sample instruction error signal from the corresponding tap interface of the second sub-circuit occurs, and a first number of delay units in the second sub-circuit through which the sample instruction error signal has been transmitted is recorded.

3. The method according to claim 2, characterized in that The second adjustment information includes a second number of delay units through which the sample instruction error signal is not transmitted; Restoring the second state to the first state and adjusting the delay control circuit on the host in a direction of reducing the delay of the sample instruction error signal until the host reaches a second state where the sample instruction error signal is not sampled by the signal sampling clock, thereby obtaining second adjustment information for the delay control circuit on the host, including: Restoring the second state to the first state, and controlling the sample instruction error signal after the initial control to be transmitted through the delay units in the first sub-circuit one by one in a direction of reducing the delay of the sample instruction error signal after the initial control, until a second state occurs in which the signal sampling clock does not sample the sample instruction error signal from the corresponding tap interface of the first sub-circuit, and recording a second number of delay units through which the sample instruction error signal has not been transmitted.

4. The method according to claim 3, characterized in that The determining, according to the first adjustment information and the second adjustment information, delay adjustment information for the delay control circuit on the host includes: Delay adjustment information for a delay control circuit on the host is determined according to an average of the first number and the second number.

5. The method according to claim 1, wherein In a first state where the host samples the sample instruction error signal through a signal sampling clock, before adjusting the delay control circuit on the host in a direction of increasing the delay of the sample instruction error signal, the method further includes: In a second state in which the host does not sample the sample instruction error signal through the signal sampling clock, performing frequency reduction adjustment processing on the current operating frequency of the host to obtain a reduced target operating frequency; the target operating frequency is the operating frequency at which the host samples the sample instruction error signal through the signal sampling clock; The sample command error signal is sampled based on a signal sampling clock in a host operating at the target operating frequency, so that the signal sampling clock samples the sample command error signal.

6. The method according to claim 1, characterized in that The method further comprises: Acquire a sample instruction; the sample instruction carries a field set that causes the memory to generate a sample instruction error signal after acquiring the sample instruction; The host sends the sample instruction to the memory, so that the memory performs an exclusive-OR operation on each field in the field set to perform instruction verification on the sample instruction, and triggers generation of a sample instruction error signal based on a verification result obtained by the verification; The generated sample instruction error signal is sent to the host through the memory.

7. The method according to claim 6, characterized in that The field set includes an instruction check field and multiple non-instruction check fields; a second XOR result obtained by performing an XOR operation on the instruction check field and the first XOR result is used to indicate that the memory generates a sample instruction error signal after receiving the sample instruction; The first XOR result is a result obtained by performing an XOR operation on the multiple non-instruction check fields.

8. The method according to claim 1, characterized in that After determining a target tap interface from the delay control circuit based on the delay adjustment information, the method further includes: The step of acquiring the sample instruction error signal sent by the memory through the host is periodically triggered by a timer and executed through hardware control to trigger re-delay adjustment training.

9. The method according to claim 1, characterized in that After determining a target tap interface from the delay control circuit based on the delay adjustment information, the method further includes: Monitoring a system operating status of a high-bandwidth memory system; the high-bandwidth memory system includes the host and the memory; If the system working state is not busy, the step of obtaining the sample instruction error signal sent by the memory through the host is re-executed through software control to trigger the delay adjustment training to be performed again.

10. The method according to claim 1, characterized in that The method further comprises: Sending a target instruction to the memory through the host; receiving, through the host, a command error signal sent by the memory; the command error signal sent by the memory is a signal generated after the memory performs command verification on the target command; The instruction error signal sent by the memory is controlled to be transmitted to the target delay unit in the delay control circuit in sequence, so as to perform delay control processing on the instruction error signal sent by the memory.

11. The method according to any one of claims 1 to 10, characterized in that The method further comprises: Sampling a target instruction error signal derived from the delay control circuit using the signal sampling clock; aligning the derived target instruction error signal with a sampling edge of the signal sampling clock of the host; The host resends the target instruction corresponding to the target instruction error signal to the memory based on the target instruction error signal obtained by sampling.

12. A signal delay control device, characterized in that: The device comprises: An acquisition module is configured to acquire, through a host, a sample instruction error signal sent by a memory; the delay control circuit provided on the host includes delay units connected in sequence; each delay unit is connected to a tap interface; the tap interface supports deriving a signal from the delay control circuit; A training module is configured to adjust a delay control circuit on the host in a direction of increasing the delay of the sample instruction error signal when the host samples the sample instruction error signal through a signal sampling clock, until a second state occurs when the host does not sample the sample instruction error signal through the signal sampling clock, thereby obtaining first adjustment information for the delay control circuit on the host; restore the second state to the first state, and adjust the delay control circuit on the host in a direction of decreasing the delay of the sample instruction error signal until a second state occurs when the host does not sample the sample instruction error signal through the signal sampling clock, thereby obtaining second adjustment information for the delay control circuit on the host; determine delay adjustment information for the delay control circuit on the host based on the first adjustment information and the second adjustment information; and determine a target tap interface from the delay control circuit based on the delay adjustment information; wherein a target delay unit before the target tap interface is configured to perform signal offset adjustment on the instruction error signal through delay processing to obtain an instruction error signal aligned with a sampling edge of the signal sampling clock of the host; The export module is used to export the offset-adjusted target instruction error signal obtained by processing the instruction error signal input by the memory from the delay control circuit through the target tap interface after the instruction error signal is processed by the target delay unit, so as to be sampled by the signal sampling clock.

13. The signal delay control device according to claim 12, wherein: The delay control circuit includes a first subcircuit and a second subcircuit; the second subcircuit is connected after the first subcircuit; the first subcircuit and the second subcircuit each include a delay unit connected in sequence; the first adjustment information includes a first number of delay units in the second subcircuit through which the sample instruction error signal has been transmitted; The training module is also used to control the acquired sample instruction error signal to pass through each delay unit in the first sub-circuit in sequence to perform initial delay control processing to obtain the sample instruction error signal after initial control; in the first state where the host samples the sample instruction error signal after initial control through the signal sampling clock, continue to control the sample instruction error signal after initial control to be transmitted through the delay units in the second sub-circuit one by one in the direction of increasing the delay of the sample instruction error signal after initial control, until the second state where the signal sampling clock does not sample the sample instruction error signal from the corresponding tap interface of the second sub-circuit appears, and record the first number of delay units in the second sub-circuit through which the sample instruction error signal has been transmitted.

14. The signal delay control device according to claim 13, wherein: The second adjustment information includes a second number of delay units through which the sample instruction error signal is not transmitted; The training module is further configured to restore the second state to the first state, and control the sample instruction error signal after the initial control to be transmitted through the delay units in the first sub-circuit one by one in the direction of reducing the delay of the sample instruction error signal after the initial control, until a second state occurs in which the signal sampling clock does not sample the sample instruction error signal from the corresponding tap interface of the first sub-circuit, and record a second number of delay units through which the sample instruction error signal has not been transmitted.

15. The signal delay control device according to claim 14, wherein: The training module is further configured to determine delay adjustment information for a delay control circuit on the host according to an average of the first number and the second number.

16. The signal delay control device according to claim 12, wherein: The training module is further configured to, in a second state in which the host does not sample the sample instruction error signal through the signal sampling clock, perform frequency reduction adjustment processing on the current operating frequency of the host to obtain a reduced target operating frequency; the target operating frequency is the operating frequency at which the host samples the sample instruction error signal through the signal sampling clock; The sample command error signal is sampled based on a signal sampling clock in a host operating at the target operating frequency, so that the signal sampling clock samples the sample command error signal.

17. The signal delay control device according to claim 12, wherein: The acquisition module is further configured to acquire a sample instruction; the sample instruction carries a field set that causes the memory to generate a sample instruction error signal after acquiring the sample instruction; The device also includes: a sending module, configured to send the sample instruction to the memory through the host, so that the memory performs an exclusive OR operation on each field in the field set to perform instruction verification on the sample instruction, and trigger the generation of a sample instruction error signal based on the verification result obtained; and send the generated sample instruction error signal to the host through the memory.

18. The signal delay control device according to claim 17, wherein: The field set includes an instruction check field and multiple non-instruction check fields; a second XOR result obtained by performing an XOR operation on the instruction check field and the first XOR result is used to indicate that the memory generates a sample instruction error signal after receiving the sample instruction; The first XOR result is a result obtained by performing an XOR operation on the multiple non-instruction check fields.

19. The signal delay control device according to claim 12, wherein: The device further includes: a timing module, configured to periodically trigger, through a timer, notification to the acquisition module to execute, through hardware control, the step of acquiring the sample instruction error signal sent by the memory through the host, so as to trigger re-delay adjustment training.

20. The signal delay control device according to claim 12, wherein: The device also includes: a monitoring module for monitoring the system working status of a high-bandwidth memory system; the high-bandwidth memory system includes the host and the memory; if the system working status is not busy, notifying the acquisition module to re-execute the step of acquiring the sample instruction error signal sent by the memory through the host through software control, so as to trigger re-delay adjustment training.

21. The signal delay control device according to claim 12, wherein: The device further includes: a sending module, configured to send the target instruction to the memory via the host; The acquisition module is also used to receive the instruction error signal sent by the memory through the host; the instruction error signal sent by the memory is a signal generated by the memory after the memory performs instruction verification on the target instruction; the instruction error signal sent by the memory is controlled to be transmitted to the target delay unit in the delay control circuit in sequence, so as to perform delay control processing on the instruction error signal sent by the memory.

22. The signal delay control device according to any one of claims 12 to 21, characterized in that: The device also includes: a sampling module, configured to sample a target instruction error signal derived from the delay control circuit using the signal sampling clock; align the derived target instruction error signal with a sampling edge of the signal sampling clock of the host; and resend the target instruction corresponding to the target instruction error signal to the memory based on the target instruction error signal obtained by sampling by the host.

23. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the method according to any one of claims 1 to 11 is implemented.

24. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 11 is implemented.

25. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the method according to any one of claims 1 to 11 is implemented.

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