An integrated circuit, chip and electronic device

Abstract

The embodiment of the application provides an integrated circuit, a chip and an electronic device, relates to the technical field of microelectronic circuits, and can improve the failure of the integrated circuit caused by electrostatic discharge. The integrated circuit comprises a substrate and a transistor arranged on the substrate; the gate of the transistor is coupled with the first end of an electrostatic discharge wire, and the first active electrode of the transistor is coupled with the second end of the electrostatic discharge wire, wherein the first active electrode of the transistor is also coupled with a ground terminal; wherein the electrostatic discharge wire is used for outputting the electrostatic voltage of the gate of the transistor to the ground terminal; or when the integrated circuit is located on a chip, the electrostatic discharge wire is disconnected.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of microelectronic circuits, and in particular to an integrated circuit, a chip and an electronic device. BACKGROUND

[0002] Currently, electro-static discharging (ESD) often occurs in the assembly process of integrated circuits (for example, in the process of mounting a chip on a packaging substrate), and ESD is usually harmful and cannot be eliminated. ESD may damage the integrated circuit. For example, the signal electrode (electrode pad, pin, etc.) of the integrated circuit may generate static electricity during the assembly process, and the ESD current may be discharged from the transistor coupled with the signal electrode in the integrated circuit, thereby causing damage to the transistor coupled with the signal electrode in the integrated circuit, and further causing the integrated circuit to fail. In particular, for a high electron mobility transistor (HEMT) formed by epitaxially forming a channel layer of a III-nitride material different from the material of the substrate on the substrate in a hetero-epitaxy manner, the gate leakage current of such a transistor is large when it is working. When an ESD event occurs on the gate, the physical structure of the gate that withstands the ESD pulse is almost only the gate dielectric layer and the barrier layer. When the current passing through is greater than a certain value, the gate dielectric layer will be broken down, causing the device to fail. SUMMARY

[0003] The embodiments of the present application provide an integrated circuit, a chip and an electronic device, which can improve the failure of the integrated circuit caused by electro-static discharging.

[0004] To achieve the above object, the present application adopts the following technical solutions:

[0005] In a first aspect, an integrated circuit is provided. The integrated circuit can be in the form of a bare chip, a die or a die. The integrated circuit comprises: a substrate and a transistor disposed on the substrate; a gate of the transistor is coupled with a first end of an electro-static discharge (ESD) wire, and a first active electrode of the transistor is coupled with a second end of the ESD wire, wherein the first active electrode of the transistor is also coupled with a ground terminal; wherein the ESD wire is used to output the electro-static voltage of the gate of the transistor to the ground terminal; or when the integrated circuit is located on a chip, the ESD wire is disconnected. Specifically, the melting voltage V fuseThe electrostatic discharge wire is fused. Among them, the source S of the transistor can be understood as the first active electrode, and the drain D of the transistor can be understood as the second active electrode. In one embodiment, the source S of the transistor is coupled to the ground terminal, and the drain D of the transistor is coupled to the working power supply; in another embodiment, the drain D of the transistor can also be coupled to the ground terminal, and the source S of the transistor is coupled to the working power supply. In this way, in the process of attaching the integrated circuit patch to the packaging substrate, the electrostatic voltage V ESD of the gate G of the transistor is conducted to the ground terminal GND; it can effectively avoid the electrostatic discharge from breaking down the transistor and causing the integrated circuit to fail. In addition, after the integrated circuit is attached to the packaging substrate to form a chip, the electrostatic discharge wire is disconnected, for example, a fuse voltage V fuse is applied to the electrostatic discharge wire to fuse the electrostatic discharge wire, thereby ensuring that the electrostatic discharge wire between the gate G and the source S of the transistor is disconnected, thereby ensuring the normal function of the transistor in operation.

[0006] In a possible implementation, the electrostatic discharge wire is also coupled with an electrostatic discharge electrode for receiving the fuse voltage, or the electrostatic discharge electrode for receiving the electrostatic voltage. The separately arranged electrostatic discharge electrode can increase the effective area of the electrostatic protection, thereby improving the electrostatic protection capability of the integrated circuit. In addition, when the electrostatic discharge wire needs to be fused after the integrated circuit is attached, the fuse voltage can also be input from the electrostatic discharge electrode, thereby enriching the selectivity of the fuse voltage input.

[0007] In a possible implementation, the electrostatic discharge wire is fused at a negative voltage. The transistor using a III-nitride HEMT is avoided from being broken down by the fuse voltage. The fuse voltage can usually be a negative voltage.

[0008] In a possible implementation, the electrostatic discharge wire and the electrostatic discharge electrode are electrically connected through a via hole.

[0009] In a possible implementation, the gate of the transistor is also coupled with a gate electrode, wherein the gate electrode is used to receive the fuse voltage. For example, the gate of the transistor and the gate electrode are electrically connected through a via hole. Since the gate of the transistor is usually covered inside the protective layer, in order to realize the connection between the gate of the transistor and other components such as the packaging substrate, an electrode (gate electrode) is usually made outside the protective layer to connect with the gate of the transistor. When the integrated circuit is connected to other components such as the packaging substrate by patching, the electrode (gate electrode) outside the protective layer is connected with the electrode on the packaging substrate, thereby realizing the signal transmission from the PCB to the integrated circuit or from the integrated circuit to the PCB.

[0010] In one possible implementation, for on-chip screening of the bare die integrated circuit, a switching device is coupled between the electrostatic discharge wire and the gate, and the control terminal of the switching device is coupled to a control electrode; the switching device is in an on or off state under the control signal input to the control electrode; wherein, in the on state, the switching device transmits the electrostatic voltage, or in the on state, the switching device transmits the fusing voltage, or in the off state, the switching device disconnects the gate and the first active electrode of the transistor. Thus, during the on-chip screening stage before the integrated circuit is mounted onto the packaging substrate, a control signal is applied to the control electrode to turn off the switching device M. This disconnects the transistor's gate G and source S, allowing a test signal to be applied to the gate electrode of the transistor. On-chip screening is then achieved by detecting the output signal from the drain D. During the mounting process of the integrated circuit onto the packaging substrate, a control signal is applied to the control electrode to turn on the switching device M. This short-circuits the transistor's gate G and source S through the switching device M and the electrostatic discharge wire. The electrostatic discharge wire on the integrated circuit then discharges the electrostatic voltage V at the transistor's gate G. ESD The transistor is connected to ground (GND). After mounting the integrated circuit onto the package substrate, the electrostatic discharge wire between the transistor's gate (G) and source (S) needs to be disconnected to ensure normal operation. Therefore, a fusing voltage V is applied to the electrostatic discharge wire. fuse The electrostatic discharge wire is fused. Specifically, the fusing voltage is V. fuse The application methods can include the following: Method 1: Control the switching device M to turn on by a control signal, and apply a fusing voltage V to the gate electrode. fuse Method 1: Melt the electrostatic discharge wire; Method 2: Regardless of whether the switching device M is in the on or off state, directly apply the melting voltage V to the electrostatic discharge electrode. fuse The electrostatic discharge wire will be melted. Furthermore, after the integrated circuit is mounted onto the packaging substrate, to ensure the transistor functions properly, a control signal can be used to disconnect the switching device M, thus disconnecting the transistor's gate G and source S. It should be noted that before the integrated circuit is mounted onto the packaging substrate, the test signal and the melting voltage V applied to the gate electrode are... fuse The control signal applied to the control electrode and the fusing voltage V applied to the electrostatic discharge electrode fuse All of these can be provided by probe devices capable of providing the corresponding signals or voltages. Specifically, the corresponding probes can be connected to the corresponding electrodes on the fixture and the aforementioned signals or voltages can be applied.

[0011] In one possible implementation, the switching device includes a depletion-mode HEMT, with a first active electrode of the depletion-mode HEMT coupled to a first end of the electrostatic discharge conductor, a second active electrode of the depletion-mode HEMT coupled to the gate of the transistor, and the gate of the depletion-mode HEMT coupled to the control electrode. For example, the control electrode is electrically connected to the gate of the depletion-mode HEMT via a via. The depletion-mode HEMT is in a conducting state, or the gate of the depletion-mode HEMT is used to receive a first control voltage transmitted by the control electrode, and the depletion-mode HEMT is in a disconnected state under the control of the first control voltage. The source S of the depletion-mode HEMT can be understood as the first active electrode, and the drain D of the depletion-mode HEMT can be understood as the second active electrode. In one embodiment, the source S of the depletion-mode HEMT is coupled to the first end of the electrostatic discharge conductor, and the drain D of the depletion-mode HEMT is coupled to the gate of the transistor; in another embodiment, the drain D of the depletion-mode HEMT may also be coupled to the first end of the electrostatic discharge conductor, and the source S of the depletion-mode HEMT may be coupled to the gate of the transistor. Thus, during the on-chip screening stage before the integrated circuit is mounted onto the packaging substrate, a negative voltage is applied to the control electrode, causing the depletion-mode HEMT to be in the off state. This leaves the transistor's gate (G) and source (S) in an open-circuit state, allowing a test signal to be applied to the gate electrode Pg of the transistor. On-chip screening of the transistor is then achieved by detecting the output signal of the transistor's drain (D). During the mounting process of the integrated circuit onto the packaging substrate, no voltage is applied to the control electrode (the control electrode is left floating), causing the depletion-mode HEMT to be in the on state. This short-circuits the transistor's gate (G) and source (S) through the depletion-mode HEMT and the electrostatic discharge wire. The electrostatic discharge voltage V at the transistor's gate is then discharged through the electrostatic discharge wire on the integrated circuit. ESD When the circuit is connected to ground (GND), the specific electrostatic discharge voltage V of the electrostatic discharge electrode Pesd and the gate electrode Pg is... ESD Both can be discharged to ground (GND) via the electrostatic discharge wire. After the integrated circuit is mounted onto the package substrate, the electrostatic discharge wire between the transistor's gate (G) and source (S) needs to be disconnected to ensure normal operation. Therefore, a fusible voltage V is applied to the electrostatic discharge wire. fuse The electrostatic discharge wire is fused. Specifically, the fusing voltage is V. fuse The application methods can include the following: Method 1: Since the depletion-type HEMT is in the on state when no voltage is applied to the control electrode, a fusing voltage V can be applied to the gate electrode. fuse Method 1: Melt the electrostatic discharge wire; Method 2: Directly apply a melting voltage V to the electrostatic discharge electrode. fuseThis will melt the electrostatic discharge wire. Furthermore, after mounting the integrated circuit onto the packaging substrate, to ensure the transistor functions properly, a negative voltage can be applied to the control electrode to turn off the depletion-type HEMT, effectively disconnecting the transistor's gate (G) and source (S). This will result in additional power consumption.

[0012] In one possible implementation, the switching device includes an enhancement-mode HEMT, wherein a first active terminal of the enhancement-mode HEMT is connected to a first end of the electrostatic discharge wire, the drain of the enhancement-mode HEMT is connected to the gate of the transistor, and the gate of the enhancement-mode HEMT is coupled to the control electrode. For example, the control electrode and the gate of the enhancement-mode HEMT are electrically connected through a via; the enhancement-mode HEMT is in an off state, or the gate of the enhancement-mode HEMT is used to receive a second control voltage transmitted by the control electrode, and the enhancement-mode HEMT is in a conducting state under the control of the second control voltage. The source S of the enhancement-mode HEMT can be understood as the first active terminal, and the drain D of the enhancement-mode HEMT can be understood as the second active terminal. In one embodiment, the source S of the enhancement-mode HEMT is coupled to the first end of the electrostatic discharge wire, and the drain D of the enhancement-mode HEMT is coupled to the gate of the transistor; in another embodiment, the drain D of the enhancement-mode HEMT may also be coupled to the first end of the electrostatic discharge wire, and the source S of the enhancement-mode HEMT may be coupled to the gate of the transistor. During the on-chip screening stage before mounting the integrated circuit to the packaging substrate, no voltage is applied to the control electrode (the control electrode is floating), causing the enhancement-mode HEMT to be in the off state. This leaves the transistor's gate (G) and source (S) in an open-circuit state. A test signal can then be applied to the gate electrode of the transistor, and on-chip screening can be achieved by detecting the output signal of the transistor's drain (D). During the mounting process of the integrated circuit to the packaging substrate, a positive voltage is applied to the control electrode, causing the enhancement-mode HEMT to be in the on state. This short-circuits the transistor's gate (G) and source (S) through the enhancement-mode HEMT and the electrostatic discharge (ESD) wire. The ESD voltage V at the transistor's gate (G) is then discharged through the ESD wire on the integrated circuit. ESD The electrostatic discharge voltage V of the specific electrostatic discharge electrode and gate electrode is connected to the ground terminal GND. ESD Both can be discharged to ground (GND) via the electrostatic discharge wire. After the integrated circuit is mounted onto the package substrate, the electrostatic discharge wire between the transistor's gate (G) and source (S) needs to be disconnected to ensure normal operation. Therefore, a fusible voltage V is applied to the electrostatic discharge wire. fuse The electrostatic discharge wire is fused. Specifically, the fusing voltage is V. fuseThe application methods can include the following: Method 1: Since the enhancement-mode HEMT is in the on state when a positive voltage is applied to the control electrode, a positive voltage can be applied to the control electrode to turn on the enhancement-mode HEMT, and a fusing voltage V can be applied to the gate electrode. fuse Method 1: Melt the electrostatic discharge wire; Method 2: Directly apply a melting voltage V to the electrostatic discharge electrode. fuse The electrostatic discharge wire will be melted. Furthermore, after the integrated circuit is mounted onto the packaging substrate, the gate (G) and source (S) of the transistor need to be disconnected to ensure normal operation. Since enhancement-mode HEMTs are in the off state when no voltage is applied to the gate (G), the gate (G) and source (S) of the transistor can also be directly disconnected through the enhancement-mode HEMT. To reduce process costs, the gate (G) of the enhancement-mode HEMT can also be directly coupled to the drain (D), eliminating the need for a control electrode.

[0013] In one possible implementation, the absolute value of the electrostatic voltage is greater than the absolute value of the fusing voltage. Typically, the electrostatic voltage during electrostatic discharge is characterized by high voltage, extremely short duration, and extremely high current, while the fusing voltage is limited by the maximum voltage that the electronic device can provide and is usually not very high, especially since the maximum voltage that the terminal can provide is usually no more than 10V. Therefore, the absolute value of the electrostatic voltage is usually greater than the absolute value of the fusing voltage. Furthermore, the duration of the fusing voltage is greater than a first duration or greater than the duration of the electrostatic voltage. Typically, the electrostatic voltage released during electrostatic discharge is extremely high in value and extremely short in duration, for example, a few nanoseconds. Therefore, the material of the electrostatic discharge wire can be selected accordingly so that the heat generated on the electrostatic discharge wire during the duration of the electrostatic voltage is insufficient to melt the electrostatic discharge wire. When it is necessary to melt the electrostatic discharge wire subsequently, a lower voltage value (that the terminal can provide) can be continuously applied as a fusing voltage. When the duration is long enough (e.g., -10V for 0.5s), sufficient heat can be generated to melt the electrostatic discharge wire.

[0014] In one possible implementation, the channel layer of the transistor comprises a group III nitride.

[0015] In one possible implementation, the channel layer of the transistor comprises a material different from the substrate, and the channel layer of the transistor is located on the substrate. For example, the channel layer is formed on the substrate epitaxially.

[0016] In one possible implementation, the electrostatic discharge wire includes any of the following: a metallic material, a metallic compound, a semiconductor material, and a semiconductor heterojunction.

[0017] In a possible implementation, the integrated circuit further comprises a protective layer and a metal wiring layer; the metal wiring layer covers the transistor, and the metal wiring layer has metal wires therein for interconnection; the protective layer covers the metal wiring layer, and the electrostatic discharge wire is located above the metal wiring layer and is covered by the protective layer. In this way, the preparation is relatively simple, and the exposure mask process added between the preparation of the protective layer and the preparation of the metal wiring layer only needs one pass. In addition, another advantage of the electrostatic discharge wire being located between the protective layer and the metal wiring layer is that, when the electrostatic discharge wire is fused, the released heat does not affect the performance of the metal wires in the metal wiring layer and the transistor.

[0018] In a possible implementation, the shape of the electrostatic discharge wire includes at least one of the following: a straight line, a broken line, and a serpentine curve. In this way, the structure of the electrostatic discharge wire is diversified. In addition, limited by the level of ESD, when the electrostatic voltage is relatively high, a longer electrostatic discharge wire can be needed, and therefore, in order to save the area of the integrated circuit or chip, the electrostatic discharge wire can adopt a broken line or a serpentine curve.

[0019] In a possible implementation, the metal material includes at least one of the following: nickel, aluminum, and titanium.

[0020] In a possible implementation, the metal compound includes a metal nitride or a metal silicide.

[0021] In a possible implementation, the semiconductor material includes polycrystalline silicon or monocrystalline silicon.

[0022] In a possible implementation, the integrated circuit is a monolithic microwave integrated circuit (MMIC).

[0023] In a second aspect, a chip is provided, and the integrated circuit and the packaging substrate described above, wherein the integrated circuit is coupled to the packaging substrate.

[0024] In a third aspect, an electronic device is provided, and includes a printed circuit board and the chip described above; the chip is coupled to the printed circuit board.

[0025] In a fourth aspect, an electrostatic protection method is provided, and is applied to the integrated circuit provided in the first aspect; the method comprises the following steps: in the process of mounting the integrated circuit on a packaging substrate, an electrostatic voltage of a gate of the transistor is conducted to the ground terminal through the electrostatic discharge wire on the integrated circuit; after the integrated circuit is mounted on the packaging substrate, a fuse voltage is applied to the electrostatic discharge wire, and the electrostatic discharge wire is fused.

[0026] In a possible implementation, when the integrated circuit further comprises a switching device, before the integrated circuit is pasted to the packaging substrate, the method further comprises: controlling the switching device to be in an off state, and outputting a test signal to the gate of the transistor.

[0027] In a possible implementation, when the integrated circuit further comprises a switching device, during the process of pasting the integrated circuit to the packaging substrate, the method comprises: controlling the switching device to be in an on state.

[0028] In a possible implementation, when the integrated circuit further comprises a switching device, after the integrated circuit is pasted to the packaging substrate, the method of applying a fuse voltage to the electrostatic discharge wire to fuse the conductive strip comprises: controlling the switching device to be in an on state, and inputting the fuse voltage to the gate of the transistor.

[0029] The technical effects brought by any possible implementation of the second aspect, the third aspect, or the fourth aspect can refer to the technical effects brought by the different implementations of the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0030] FIG. 1A A structural schematic diagram of an electronic device provided for an embodiment of the present application is shown in FIG. 1.

[0031] FIG. 1B A structural schematic diagram of an electronic device provided for another embodiment of the present application is shown in FIG. 2.

[0032] FIG. 1C A structural schematic diagram of an electronic device provided for yet another embodiment of the present application is shown in FIG. 3.

[0033] FIG. 2 A structural schematic diagram of a base station provided for an embodiment of the present application is shown in FIG. 4.

[0034] FIG. 3 A structural schematic diagram of a chip provided for an embodiment of the present application is shown in FIG. 5.

[0035] FIG. 4 A structural schematic diagram of an integrated circuit provided for an embodiment of the present application is shown in FIG. 6.

[0036] FIG. 5 A structural schematic diagram of an integrated circuit provided for another embodiment of the present application is shown in FIG. 7.

[0037] FIG. 6 A structural schematic diagram of an integrated circuit provided for yet another embodiment of the present application is shown in FIG. 8.

[0038] FIG. 7 A structural schematic diagram of an integrated circuit provided for still another embodiment of the present application is shown in FIG. 9.

[0039] FIG. 8 A structure diagram of an integrated circuit according to another embodiment of the present application;

[0040] FIG. 9 A structure diagram of an integrated circuit according to another embodiment of the present application;

[0041] FIG. 10 A structure diagram of an electrostatic discharge wire according to an embodiment of the present application;

[0042] FIG. 11 A structure diagram of an electrostatic discharge wire according to another embodiment of the present application;

[0043] FIG. 12 A structure diagram of an integrated circuit according to another embodiment of the present application;

[0044] FIG. 13 A structure diagram of an integrated circuit according to another embodiment of the present application;

[0045] FIG. 14 A structure diagram of an integrated circuit according to another embodiment of the present application;

[0046] FIG. 15 A structure diagram of an integrated circuit according to another embodiment of the present application;

[0047] FIG. 16 A structure diagram of a depletion-mode HEMT according to an embodiment of the present application;

[0048] FIG. 17 A structure diagram of an enhancement-mode HEMT according to an embodiment of the present application;

[0049] FIG. 18 A structure diagram of an enhancement-mode HEMT according to another embodiment of the present application;

[0050] FIG. 19 A structure diagram of an integrated circuit according to another embodiment of the present application;

[0051] FIG. 20 A structure diagram of an integrated circuit according to another embodiment of the present application;

[0052] FIG. 21 A structure diagram of an integrated circuit according to another embodiment of the present application;

[0053] FIG. 22 A structure diagram of an integrated circuit according to another embodiment of the present application;

[0054] FIG. 23 A schematic diagram of a structure of an integrated circuit is provided for yet another embodiment of the present application.

[0055] FIG. 24 A schematic diagram of a structure of an integrated circuit is provided for still another embodiment of the present application.

[0056] FIG. 25 A schematic diagram of a structure of an integrated circuit is provided for another embodiment of the present application. DETAILED DESCRIPTION

[0057] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments can be some but not all of the embodiments of the present application.

[0058] Unless otherwise defined, all technical terms used herein have the same meaning as those commonly understood by one of ordinary skill in the art. In the present application, "at least one" means one or more, and "multiple" means two or more. The "and / or" describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or similar expressions means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b or c can mean a, b, c, a and b, a and c, b and c, or a, b and c, where a, b and c can be single or multiple. In addition, in the embodiments of the present application, "first", "second", etc. do not limit the quantity and order.

[0059] In addition, in the present application, the orientation terms such as "upper", "lower", etc. are defined with respect to the orientation in which the components in the drawings are placed. It should be understood that these directional terms are relative concepts, which are used for relative description and clarification, and can change accordingly according to the change of the orientation in which the components are placed in the drawings.

[0060] It should be noted that in the present application, the words "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design presented as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or advantageous than other embodiments or designs. Rather, the use of "exemplary" or "for example" is merely intended to present concepts in a concrete manner. Therefore, "exemplary" or "for example" in the present application does not mean "preferred" or "superior" to other embodiments or designs.

[0061] The integrated circuit and chip provided by the embodiments of the present application can be applied to electronic devices, which are different types of terminals such as mobile phones, tablet computers, personal computers (PC), personal digital assistants (PDA), smart watches, netbooks, wearable electronic devices, augmented reality (AR) devices, virtual reality (VR) devices, vehicle-mounted devices, smart cars, smart speakers, robots, smart glasses, and the like; the electronic devices can also be network devices such as base stations. The electronic devices can also be chips and the like used in the above electronic devices. The electronic devices can also include printed circuit boards, and the chips described above are arranged on the printed circuit boards. The chip encapsulates an integrated circuit arranged on a packaging substrate, and the integrated circuit can be connected to the packaging substrate in a patch manner. The embodiments of the present application do not specially limit the specific form of the electronic device.

[0062] Taking a mobile phone as an example, FIGS. 1A-1C A structural schematic diagram of an electronic device 100 is shown, wherein, FIG. 1A A top view of the electronic device 100 of the described embodiments is shown. FIG. 1B A bottom view of the electronic device 100 of the described embodiments is shown. FIG. 1C A top view of the electronic device 100 after the back cover is opened is shown, which shows a specific configuration of various internal components according to the described embodiments, FIG. 1C The dashed arrow in indicates the direction in which the back cover is opened. It can be understood that the structure shown in the embodiments does not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 can include more or fewer components than shown, or combine certain components, or split certain components, or different component arrangements.

[0063] As FIG. 1A and FIG. 1BAs shown, the electronic device 100 may include a housing 100A, which may include a front cover 101, a rear cover 103, and a frame 102. The front cover 101 and the rear cover 103 are disposed opposite to each other, and the frame 102 surrounds the front cover 101 and the rear cover 103, connecting them together. The front cover 101 may be a glass cover, and a display 194 is disposed below the front cover 101. The electronic device 100 may have input / output components arranged around the outer periphery of the housing 100A. For example, a hole 105A for a front-facing camera and a hole 106 for a receiver may be provided on the top of the front cover 101. A button 190 may be provided on one edge of the frame 102, and a microphone hole 107, a speaker hole 108, and a USB interface hole 109 may be provided on the bottom edge of the frame 102. A hole 105B for a rear-facing camera may be provided on the top of the rear cover 103.

[0064] The housing 100A may have an interior cavity 104, within which internal components are encapsulated. For example... FIG. 1CAs shown, the internal components can be housed within the cavity 104, the internal components can include a printed circuit board (PCB) 110, a speaker 170A for converting audio electrical signals into sound signals, a receiver 170B for converting audio electrical signals into sound signals, a microphone 170C for converting sound signals into electrical signals, a USB interface 130, a front camera 193A, a rear camera 193B, and a motor 191 for generating a vibration prompt, etc. Among them, the printed circuit board 110 can be provided with a processor 120, a power management integrated circuit (PMIC) 140, at least one power amplifier (in an embodiment, including power amplifiers (PAs) 152A, 152B, 152C, 152D, different power amplifiers PA support different frequency bands, for amplifying transmission signals of different frequency bands, for example, power amplifiers PA 152A and 152B can be used to amplify transmission signals of a first bandwidth range, and power amplifiers PA 152C and 152D can be used to amplify transmission signals of a second bandwidth range), at least one envelope tracking modulator (ETM) for powering the power amplifier (in an embodiment, including envelope tracking modulators ETM 151A and 151B, different envelope tracking modulators ETM support different bandwidths, for example, envelope tracking modulator ETM 151A powers power amplifiers PA 152A and 152B, and envelope tracking modulator ETM 151B powers power amplifiers PA 152C and 152D), a switching switch 153, and an antenna circuit 154, etc. In addition, the printed circuit board 110 can also include filters, low-noise amplifiers, audio codecs, internal memories, sensors, inductors, capacitors, etc. In order to clearly display the embodiment, the filters, low-noise amplifiers, audio codecs, internal memories, sensors, inductors, and capacitors are not shown on the printed circuit board 110. The components on the printed circuit board 110 are arranged closely to accommodate all the components in a limited space. The arrangement of the components on the printed circuit board 110 is not limited. In some embodiments, the components on the printed circuit board 110 can be arranged on one side of the printed circuit board 110 (e.g., the side facing the back cover 102). In some embodiments, the components on the printed circuit board 110 can be arranged on both sides of the printed circuit board 110 (e.g., on the side facing the back cover 102, and on the side facing the front cover 101, respectively). FIG. 1C The components on the printed circuit board 110 are arranged closely to accommodate all the components in a limited space. The arrangement of the components on the printed circuit board 110 is not limited. In some embodiments, the components on the printed circuit board 110 can be arranged on one side of the printed circuit board 110 (e.g., the side facing the back cover 102). In some embodiments, the components on the printed circuit board 110 can be arranged on both sides of the printed circuit board 110 (e.g., on the side facing the back cover 102, and on the side facing the front cover 101, respectively).

[0065] The processor 120 can include one or more processing units, e.g., the processor 120 can include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a neural-network processing unit (NPU), a controller, a video code, a digital signal processor (DSP), a baseband, and / or a radio frequency circuit, etc. The controller can generate operation control signals according to instruction opcodes and timing signals, and complete the control of fetching and executing instructions.

[0066] The processor 120 can be provided with a memory for storing instructions and data. In some embodiments, the memory in the processor 120 is a cache memory. The memory can hold instructions or data that the processor 120 has just used or recycled. If the processor 120 needs to use the instructions or data again, it can be directly called from the memory. Repeated access is avoided, the waiting time of the processor 120 is reduced, and thus the efficiency of the system is improved.

[0067] The processor 120 can frequency-modulate a signal according to a mobile communication technology or a wireless communication technology. The mobile communication technology can include global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (CDMA), wideband code division multiple access (WCDMA), time-division code division multiple access (TD-SCDMA), long term evolution (LTE), an emerging wireless communication technology (also referred to as 5th generation mobile communication technology, English: 5th generation mobile networks or 5th generation wireless systems, 5th-Generation, 5th-Generation New Radio, 5G, 5G technology, or 5G NR), etc. The wireless communication technology can include wireless local area networks (WLAN) (such as a wireless fidelity (Wi-Fi) network), bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR) technology, etc.

[0068] The processor 120 can also include at least one baseband and at least one radio frequency circuit. The baseband refers to a circuit used to synthesize a baseband signal to be transmitted or / and to decode a received baseband signal. Specifically, when transmitting, the baseband encodes a voice or other data signal into a baseband signal (baseband code) to be transmitted; when receiving, the baseband decodes a received baseband signal (baseband code) into a voice or other data signal. The baseband can include components such as an encoder, a decoder, and a baseband processor. The encoder is used to synthesize a baseband signal to be transmitted, and the decoder is used to decode a received baseband signal. The baseband processor can be a microprocessor (MCU), which can be used to control the encoder and the decoder, for example, the baseband processor can be used to complete the scheduling of encoding and decoding, the communication between the encoder and the decoder, the driving of peripherals (which can be enabled by sending an enable signal to components outside the baseband), and the like. The radio frequency circuit is used to process the baseband signal to form a transmit (TX) signal and transmit the transmit signal to the power amplifier PA for amplification; or / and, the radio frequency circuit is used to process a receive (RX) signal to form a baseband signal and transmit the formed baseband signal to the baseband for decoding. In some embodiments, each baseband corresponds to a radio frequency circuit to frequency-modulate signals according to one or more communication technologies. For example, a first baseband and a first radio frequency circuit frequency-modulate signals according to a 5G technology, a second baseband and a second radio frequency circuit frequency-modulate signals according to a 4G technology, a third baseband and a third radio frequency circuit frequency-modulate signals according to a Wi-Fi technology, a fourth baseband and a fourth radio frequency circuit frequency-modulate signals according to a Bluetooth technology, and the like. Alternatively, a first baseband and a first radio frequency circuit can frequency-modulate signals according to both a 4G technology and a 5G technology, a second baseband and a second radio frequency circuit frequency-modulate signals according to a Wi-Fi technology, and the like. In some embodiments, a baseband can correspond to multiple radio frequency circuits to improve integration.

[0069] In some embodiments, the baseband and the radio frequency circuit can be integrated with other components of the processor 120 in an integrated circuit. In some embodiments, the baseband and the radio frequency circuit can be independent devices independent of the processor 120. In some embodiments, a baseband and a radio frequency circuit can be integrated in a device independent of the processor 120.

[0070] In the processor 120, different processing units can be independent devices or integrated in one or more integrated circuits.

[0071] The antenna circuit 154 is used to transmit and receive electromagnetic wave signals (radio frequency signals). Multiple antennas or multiple sets of antennas (a set of antennas includes more than two antennas) can be included in the antenna circuit 154, each of which can be used to cover a single or multiple communication frequency bands. The multiple antennas can be one or more of a multi-frequency antenna, an array antenna, or an on-chip antenna.

[0072] The processor 120 is coupled to the antenna circuit 154 to implement various functions associated with transmitting and receiving radio frequency signals. For example, when the electronic device 100 transmits a signal, the baseband synthesizes data (digital signals) to be transmitted into a baseband signal to be transmitted, the baseband signal is converted into a transmission signal (radio frequency signal) by the radio frequency circuit, the transmission signal is amplified by the power amplifier, the amplified output signal output by the power amplifier is transmitted to the switch 153, and the transmission signal is transmitted through the antenna circuit 154. The path of the transmission signal sent by the processor 120 to the switch 153 is the transmission link (or transmission path). When the electronic device 100 needs to receive a signal, the antenna circuit 154 transmits the received signal (radio frequency signal) to the switch 153, the switch 153 transmits the radio frequency signal to the radio frequency circuit, the radio frequency circuit processes the radio frequency signal into a baseband signal, and the radio frequency circuit converts the processed baseband signal into data and sends it to the corresponding application processor. The path of the radio frequency signal sent by the switch 153 to the processor 120 is the reception link (or reception path).

[0073] The switch 153 can be configured to selectively electrically connect the antenna circuit 154 to the transmission link or the reception link. In some embodiments, the switch 153 can include multiple switches. The switch 153 can also be configured to provide additional functions, including filtering and duplexing signals.

[0074] The SIM card interface 195 is configured to connect a SIM card. The SIM card can be inserted into or removed from the SIM card interface 195 to achieve contact and separation with the electronic device 100. The electronic device 100 can support one or N SIM card interfaces, where N is a positive integer greater than 1. The SIM card interface 195 can support Nano SIM cards, Micro SIM cards, SIM cards, and the like. Multiple cards can be inserted into the same SIM card interface 195 at the same time. The types of the multiple cards can be the same or different. Each SIM card can support one or more communication standards, each of which has a specified frequency band and a different maximum bandwidth. The SIM card interface 195 can also be compatible with different types of SIM cards. The SIM card interface 195 can also be compatible with external storage cards. The electronic device 100 interacts with a network through the SIM card to achieve functions such as calling and data communication. In some embodiments, the electronic device 100 uses an eSIM, i.e., an embedded SIM card. The eSIM card can be embedded in the electronic device 100 and cannot be separated from the electronic device 100.

[0075] The PMIC 140 is configured to manage power in the electronic device 100. For example, the PMIC 140 can include a charging management circuit and a power supply management circuit. The charging management circuit is configured to receive a charging input from a charger, for example, in some wired charging embodiments, the charging management circuit can receive a charging input from a wired charger through the USB interface 130. The power supply management circuit is configured to receive an input of the battery 142 and / or the charging management circuit, and supply power to the processor 120, the display 194, the front camera 193A, the rear camera 193B, and the motor 191, and the like. In other embodiments, the charging management circuit and the power supply management circuit can also be disposed in the processor 120. In other embodiments, the charging management circuit and the power supply management circuit can also be disposed in different devices.

[0076] In another example, the electronic device provided by the embodiments of the present application takes a 5G base station as an example. The 5G base station can be divided into baseband processing units (BBU)-active antenna units (AAU), central units-distributed units (CU-DU)-AAU, BBU-remote radio units (RRU)-antennas (antenna), CU-DU-RRU-antenna, integrated 5G base stations (5G node base stations, gNB), and the like. Taking a base station with a BBU-RRU architecture as an example, referring to FIG. 2As shown, the base station includes a BBU 21, an RRU 22, and an antenna 23; the BBU 21 is connected to the RRU 22 through an optical fiber, and the interface between the two is based on the open CPRI (common public radio interface) and OBSAI (open base station architecture initiative). The BBU 21 generates baseband signals, which are sent to the antenna 23 for transmission after being processed by the RRU 22. The RRU 22 includes a digital intermediate frequency module 221, a transceiver module 222, a power amplifier 223 (PA), and a filter 224. The digital intermediate frequency module 221 is used for modulation and demodulation, digital upconversion and downconversion, D / A conversion (digital to analog converter), etc. of the baseband signals transmitted through the optical fiber to form intermediate frequency signals; the transceiver module 222 completes the conversion of the intermediate frequency signals to radio frequency signals; the power amplifier 223 is used for power amplification of the small-power radio frequency signals; and the filter 224 is used for filtering the radio frequency signals, which are then transmitted through the antenna 23.

[0077] The technologies involved in the following embodiments can be implemented in the electronic device described above, and in the following embodiments, components or signals with the same names as those in the electronic device described above can be configured as the same components or the same signals in the electronic device described above. Hereinafter, the integrated circuit, chip, and electronic device provided by the embodiments of the present application are exemplified.

[0078] In combination with the above description, part of the components in the electronic device (such as one or more of the processor, the power management integrated circuit, the PA, the ETM, the filter, the low-noise amplifier, the audio codec, and the internal memory) can be provided in the form of a chip on the printed circuit board 110 and coupled to the printed circuit board 110, for example, in the form of pin soldering or pad mounting connected to the printed circuit board 110. Another part of the components (such as sensors, inductors, capacitors, etc.) are connected to the printed circuit board 110 in the form of independent components through pin insertion (for example, a board-to-board connector (BTB)) or soldering, etc. In combination with the above description, the printed circuit board 110 can be provided in the form of a chip on the printed circuit board 110 and coupled to the printed circuit board 110, for example, in the form of pin soldering or pad mounting connected to the printed circuit board 110. FIG. 3As shown, a chip is provided, which includes an integrated circuit 30 and a package substrate 50. The integrated circuit 30 is in the form of a die, a bare chip or a die. The integrated circuit 30 is coupled with the package substrate 50. It should be noted that the functional circuit inside the integrated circuit 30 is coupled with the electrode (pin or pad) on the package substrate 50 through the electrode (pin or pad), for example, the pin P of the integrated circuit 30 is welded together with the electrode (pin or pad) on the package substrate 50 through a soldering ball, wherein the package substrate 50 is provided with metal wires (not shown), which connect the pin P of the integrated circuit 30 with the pin 60 of the external chip. In this way, when the chip is connected with the printed circuit board 110 through the pin 60 of the chip, the connection between the integrated circuit 30 and the printed circuit board 110 is realized. In addition, the periphery of the integrated circuit 30 is also filled with a packaging material 40, such as a resin, a ceramic or other insulating material.

[0079] Specifically, the integrated circuit 30 provided by the embodiments of the present application can contain the transistor applied to FIGS. 1A-1C or FIG. 2 the PA of the electronic device. Of course, the specific application scenarios are not limited to the above FIGS. 1A-1C the mobile phone shown, FIG. 2 the base station shown, it can be understood that any of the above electronic devices that need to use the transistor to process the signal belong to the application scenarios of the embodiments of the present application. The integrated circuit can be one or more transistors connected on a substrate. For example, when used to realize the radio frequency function in the electronic device, the integrated circuit can be a monolithic microwave integrated circuit (MMIC) or a radio frequency integrated circuit (RFIC). It can be understood that the MMIC can be integrated with the above-mentioned filter, low noise amplifier, PA, and in some examples, can also be integrated with a mixer, frequency multiplier, phased array unit, etc.

[0080] As shown in FIG. 4 , FIG. 5 the integrated circuit 30 mainly includes a substrate 31 and a transistor 32 disposed on the substrate 31. In some embodiments of the present application, the gate (G) of the transistor 32 is coupled with the first end of the electrostatic discharge wire 33, the source (S) of the transistor 32 is coupled with the second end of the electrostatic discharge wire 33, and the source (S) of the transistor 32 is also coupled with the ground terminal GND; as shown in FIG. 4 the electrostatic discharge wire 33 is used to output the electrostatic voltage V ESD of the gate G of the transistor 32 to the ground terminal GND; or, asFIG. 5 As shown, when the integrated circuit 30 is located on the chip, the static electricity release conductor 33 is disconnected. Specifically, the static electricity release conductor 33 can be disconnected by applying a fuse voltage V fuse to the static electricity release conductor 33.

[0081] In this way, during the process of patching the integrated circuit 30 to the packaging substrate, the static electricity voltage V ESD on the gate G of the transistor 32 is conducted to the ground terminal GND through the static electricity release conductor 33 on the integrated circuit 30; the static electricity discharge can effectively avoid breaking the transistor 32, leading to the failure of the integrated circuit. In addition, after the integrated circuit 30 is patched to the packaging substrate to form the chip, the static electricity release conductor 33 is disconnected, for example, a fuse voltage V fuse is applied to the static electricity release conductor 33 to fuse the static electricity release conductor 33, ensuring that the static electricity release conductor 33 between the gate G and the source S of the transistor 32 is disconnected, thereby ensuring the normal function of the transistor 32 in operation.

[0082] In particular, there are serious ESD problems for transistors based on hetero-epitaxial channel layers on substrates. Among others, the channel layer of such transistors comprises a material different from the substrate, and the channel layer of the transistor is located on the substrate, for example, epitaxially on the substrate. As an example, high electron mobility transistors (HEMTs) employing group III nitrides are widely used in power amplifiers of base stations. However, compared to base stations, the battery supply voltage of terminals determines that the HEMTs employing group III nitrides can only work at low voltage, which puts a high requirement on the current density of the HEMTs. The large current density is used to compensate for the reduction of power density caused by the reduction of working voltage, and to reduce the knee voltage to improve the effective voltage swing, which requires the introduction of a barrier layer with a high aluminum (Al) component, for example, an aluminum content higher than 20%, in the HEMT employing group III nitrides. In addition, from the perspective of cost control, it is a feasible solution to epitaxially grow the channel layer of group III nitrides on a silicon (Si) substrate instead of a silicon carbide (SiC) substrate. However, due to the large lattice mismatch and thermal mismatch between Si and group III nitrides (for example, gallium nitride (GaN)), it is difficult to grow high Al component materials, which results in poor material quality and a large number of defects. When metals and these materials form Schottky contacts through a semiconductor process, these defects will act as leakage channels, resulting in a large gate leakage current of the HEMT based on the above materials, and the device characteristics deteriorate. In order to reduce the gate leakage current, an insulating layer (gate dielectric layer) needs to be introduced on the barrier layer to form a metal-insulator-semiconductor (MIS) HEMT structure, so as to realize a device with low gate leakage current. In the process of mounting an integrated circuit (for example, in the form of a power amplifier chip, a die, a die, etc.) based on the above HEMT employing group III nitrides to a package substrate of a radio frequency module, there will inevitably be an ESD problem. When an ESD event occurs on the gate, the physical structure that bears the ESD pulse is almost only the gate dielectric and the barrier layer. The MIS structure is an insulating medium, which will be broken down when the current through it is greater than a certain value, causing the HEMT to fail. Although the integrated circuit based on group III nitrides will finally be connected to the pin 60 outside the chip through each electrode (such as pin P) in the chip, there are still ESD problems in the chip. FIG. 3 FIG. 3 ​The P) shown will not be exposed. However, in the integrated circuit back-end process, such as the integrated circuit packaging process, due to the problems of production line management and control ability, etc., the integrated circuit may have an ESD event, resulting in failure of the integrated circuit. In such a case, the application of the III-nitride integrated circuit in the terminal will not be mass-produced due to the ESD problem.

[0083] However, in the process of attaching the integrated circuit to the packaging substrate, the electrostatic voltage V ESD of the gate of the transistor is conducted to the ground terminal GND through the electrostatic discharge wire on the integrated circuit; effectively avoiding the problem of electrostatic discharge breaking down the transistor and causing the integrated circuit to fail.

[0084] Among them, the source S of the transistor 32 in FIG. 4 and FIG. 5 can be understood as the first active electrode, and the drain D of the transistor 32 can be understood as the second active electrode. In one embodiment, the source S of the transistor 32 is coupled to the ground terminal, and the drain D of the transistor 32 is coupled to the working power supply; in another embodiment, the drain D of the transistor 32 can also be coupled to the ground terminal, and the source S of the transistor 32 is coupled to the working power supply. The source S of the transistor 32 is the first active electrode, and the drain D of the transistor 32 is the second active electrode in the following scheme.

[0085] Taking an integrated circuit containing a HEMT as an example, the integrated circuit contains a laminated structure formed by a plurality of material layers arranged in layers. As FIG. 6 shown, the transistor 32 mainly includes a channel layer 321, a barrier layer 322, a gate dielectric layer 323, and an electrode such as a gate 325, a source 324 and a drain 326 on the gate dielectric layer 323, which are arranged on the substrate 31. The source 324 and the drain 326 are in contact with the channel layer 321; in some examples, the electrode is also covered with a first dielectric layer 34. When the HEMT includes a III-nitride HEMT, the barrier layer 322 in the transistor 32 usually adopts GaN and / or AlGaN materials, and the electrode usually adopts metal, for example: copper Cu. Among them, the source 324 and the drain 326 respectively form a conductive ohmic contact with the barrier layer 324, and the gate 325 forms a Schottky contact with the barrier layer 322. The dashed line in the channel layer 321 represents the two-dimensional electron gas (2DEG) generated in the heterostructure formed by the channel layer 321 and the barrier layer 322 in the HEMT, which is along the horizontal direction (such as FIG. 6In some examples, the mobility of the channel layer 321 is very high, which is the basis for the operation of the HEMT. In some examples, other functional layer structures can also be arranged between the channel layer 321 and the barrier layer 322, or between the channel layer 321 and the substrate 31, for example: an insertion layer can be arranged between the channel layer 321 and the barrier layer 322. The function of the insertion layer is to improve the density, localization degree and mobility of the two-dimensional electron gas 2DEG, thereby improving the performance of the device, such as obtaining excellent switching performance, etc. Therefore, the insertion layer is an optional structure, and when the insertion layer is not arranged in the HEMT, the performance of the device will be reduced. In addition, a buffer layer can be arranged between the channel layer 321 and the substrate 31, and the buffer layer is also an optional structure. The main function of the buffer layer is to act as a transition when the crystal structure difference between the materials of the channel layer 321 and the substrate 31 is large. For example: when the crystal structure difference between the materials of the channel layer 321 and the substrate is large, a buffer layer with a smaller crystal structure difference with the substrate can be first epitaxially generated on the substrate 31, and then the channel layer 321 is epitaxially formed on the buffer layer.

[0086] Generally, the integrated circuit is also provided with a first dielectric layer 34 covering the transistor 32, a metal wiring layer 35 arranged on the first dielectric layer 34, and a protective layer 36 covering the metal wiring layer 35, wherein the electrodes of the transistor 32 and the metal wires in the metal wiring layer 35 are electrically connected through vias h, and the metal wires in the metal wiring layer 35 and the electrodes (gate electrode Pg, source electrode Ps and drain electrode Pd) outside the protective layer 36 are electrically connected through vias h, so that when the integrated circuit is connected to other components such as a packaging substrate by means of a patch, the electrodes outside the protective layer 36 are connected to the electrodes on the packaging substrate, thereby realizing the PCB providing signals to the integrated circuit or transmitting signals output by the integrated circuit to the PCB. The protective layer 36 and the first dielectric layer 34 can be made of insulating materials such as silicon oxide and resin. The metal wiring layer 35 can be one or more layers of metal wires for interconnection formed in an insulating material layer (such as silicon oxide) by one or more patterning processes, and the metal wires in different layers can be electrically connected through vias. The metal wires are used for interconnection. The protective layer 36 is usually the outermost material layer on the die, and the protective layer is specifically used to protect the devices or metal wires on the die. The via in the embodiments of the present application can also be referred to as a metallized hole. Generally, in order to electrically connect the conductive structures on both sides of the dielectric layer, a common hole, i.e. a via, is drilled at the intersection of the conductive structures on both sides of the dielectric layer that need to be electrically connected. On the cylindrical surface of the hole wall of the via, a layer of conductive material, such as metal, is made to electrically connect the conductive structures that need to be connected. In the embodiments of the present application, the metal wires in the metal wiring layer 35 and the gate electrode Pg, the source electrode Ps and the drain electrode Pd can be electrically connected by vias, and the metal wires in the metal wiring layer 35 and the gate G, the source S and the drain D of the transistor 32 can be electrically connected by vias.

[0087] Specifically, as shown in FIG. 6 , in order to lead out the gate 325, the source 324 and the drain 326 to connect with other components outside, the gate electrode Pg, the source electrode Ps and the drain electrode Pd which are different from the gate 325, the source 324 and the drain 326 are arranged in different layers, wherein the gate electrode Pg, the source electrode Ps and the drain electrode Pd are arranged outside the protection layer 36, the gate 325 of the transistor 30 is coupled with the gate electrode Pg, the source 324 of the transistor 30 is coupled with the source electrode Ps, and the drain 326 of the transistor 30 is coupled with the drain electrode Pd. Among them FIG. 6 , it is shown in that three electrodes (the gate electrode Pg, the source electrode Ps and the drain electrode Pd) are arranged outside the protection layer for the transistor, which is described as an example, of course, when one of the gate G, the source S and the drain D of the transistor is directly coupled with other devices in the integrated circuit, without the need to be coupled with the circuit outside through the pin of the chip, it can also be selected to arrange only one or two of the gate electrode Pg, the source electrode Ps and the drain electrode Pd. In addition, it is also shown in FIG. 6 that the embodiment of the present application provides a possible position of the electrostatic discharge wire 33, for example, the electrostatic discharge wire 33 can be located on the metal wiring layer 35 and covered by the protection layer 36. The electrostatic discharge wire 33 is located above the metal wiring layer 35 connected with the gate of the transistor covered by the protection layer 36. The protection layer 36 covers the electrostatic discharge wire 33. In this way, it is relatively simple to prepare, and the exposure mask process for manufacturing the electrostatic discharge wire is only one additional process between the manufacturing of the protection layer 36 and the manufacturing of the metal wiring layer 36. In addition, another advantage of the electrostatic discharge wire 33 between the protection layer 36 and the metal wiring layer 35 is that when the electrostatic discharge wire 33 is fused, the released heat will not affect the metal wiring in the metal wiring layer 35 and the performance of the transistor 32. In addition, FIG. 6 , it is not shown in that the electrostatic discharge wire 33 can be electrically connected to the metal wiring of the metal wiring layer 36 through the via hole and the metal wiring of the metal wiring layer 36 through the via hole to the gate of the transistor 32. In this way, the coupling between the gate (G) of the transistor 32 and the electrostatic discharge wire 33 is achieved.

[0088] In other examples, as shown in FIG. 6 , FIG. 7 , FIG. 8 and FIG. 9 , the electrostatic discharge wire 33 is also coupled with the electrostatic discharge electrode Pesd, which is used to receive the fuse voltage V fuse , or the electrostatic discharge electrode Pesd is used to receive the electrostatic voltage V ESDThe separately arranged static electricity release electrode Pesd can increase the effective area of the static electricity protection, thereby improving the static electricity protection capability of the integrated circuit. In addition, after the integrated circuit is mounted, the static electricity release conductor needs to be fused, and the static electricity release electrode Pesd can input the fusing voltage V fuse , thereby enriching the selection of the fusing voltage input.

[0089] Generally, the static electricity voltage in the static electricity release process has the characteristics of high voltage, extremely short time, and extremely large current. The fusing voltage is limited by the highest voltage that the electronic device can provide, and is usually not very high. In particular, the highest voltage that the terminal can provide is usually not more than 10V. Therefore, the absolute value of the static electricity voltage is usually greater than the absolute value of the fusing voltage. In this way, in order to make the static electricity release conductor well guide the static electricity voltage V ESD to the ground terminal GND, and be able to be fused by the appropriate fusing voltage V fuse , the material of the static electricity release conductor needs to be selected in combination with one or more of the resistivity, the electron mobility, and the melting point of the material. In some examples, the static electricity release conductor includes any one of the following: a metal material, a metal compound, a semiconductor material, and a semiconductor heterojunction. The metal material includes any one of the following: nickel (Ni), aluminum (Al), titanium (Ti). The metal compound includes a metal nitride such as titanium nitride, or a metal silicide such as titanium silicon (TiSi) and cobalt silicon (CoSi). The semiconductor material includes, for example, polycrystalline silicon and single-crystal silicon. The semiconductor heterojunction can be formed by overlapping two or more materials, for example, including an aluminum gallium nitride / gallium nitride (AlGaN / GaN) heterojunction formed by overlapping two layers of aluminum gallium nitride and gallium nitride.

[0090] In some examples, the duration of the fusing voltage is greater than the first duration or the duration of the static electricity voltage. For example, a static electricity release conductor formed of nickel metal with a length of 80um, a width of 2um, and a thickness of 50nm can withstand a static electricity voltage of 100V and can be fused by a fusing voltage of -10V after 0.5s. Generally, the voltage value of the static electricity voltage released in the static electricity release process is extremely high, and the duration is extremely short, for example, a few nanoseconds. Therefore, the material of the static electricity release conductor can be selected according to the duration of the static electricity voltage, so that the heat generated on the static electricity release conductor during the duration of the static electricity voltage is not enough to fuse the static electricity release conductor. When it is necessary to fuse the static electricity release conductor later, a fusing voltage with a lower voltage value (which can be provided by a terminal) can be continuously applied. When the duration is long enough (for example, 0.5s), a high heat can be generated to fuse the static electricity release conductor. As shown in the following FIG. 10 , FIG. 11 , the fusing position of the static electricity release conductor formed of nickel metal is at the middle position of the static electricity release conductor after the fusing experiment. Specifically, as shown in the following FIG. 11As shown, the melting position is at 102.67 μm from the left electrode 102 and 99.83 μm from the right electrode. For the ESD lead made of the above-mentioned materials, the geometry, the position of the material layer in the integrated circuit, and the shape of the ESD lead are not limited, for example, the ESD lead can be a straight line, a broken line, a serpentine curve, or the like. For example, when the ESD level is high, a longer ESD lead can be needed, in which case, in order to save the area of the integrated circuit or chip, the ESD lead can be in the form of a broken line or a serpentine curve. In addition, in order to avoid the breakdown of the transistor using a III-nitride HEMT, the melting voltage can be a negative voltage.

[0091] At present, the cost of the three parts of the wafer screening, the die packaging, and the module test screening after the chip flow process is basically 1:1:1. Taking the integrated circuit based on III-nitride as an example, at present, the yield of the mature process is only 80%, and the yield of the new process is only 70%. In this case, if the wafer screening is not performed on the integrated circuit after the flow process, but the bad die is packaged by die packaging and then screened out by module test, the cost will be greatly increased. If the yield of the die after the flow process is 70%, the total cost difference between the wafer screening and the non-wafer screening reaches 20% ((1+0.7+0.7) / (1+1+1)). Therefore, from the perspective of cost control, the die needs to be screened on the wafer. In order to screen the integrated circuit on the wafer, the switch device M is further coupled between the ESD lead 33 and the gate G, wherein the control end of the switch device M is coupled to the control electrode Pm; the switch device M is in the on state or the off state under the control signal input by the control electrode Pm; wherein the switch device M transmits the ESD voltage V ESD in the on state, or the switch device M transmits the melting voltage V fuse in the on state, or the switch device M disconnects the gate G of the transistor 32 and the first active electrode in the off state.

[0092] It should be noted that the switch device M can be a switch device with a structure similar to that of the transistor 32. For example, the switch device M can be a depletion mode HEMT or an enhancement mode HEMT. The control electrode Pm can be made on the outside of the protective layer 36 together with the gate electrode Pg, the source electrode Ps, the drain electrode Pd, and the ESD electrode Pesd in the FIG. 6 . And the control electrode Pm can be coupled to the control end of the switch device M through the metal wiring in the metal wiring layer 35.

[0093] In this way, in the wafer screening stage before the integrated circuit is die attached to the packaging substrate, the switch device M is in the off state, and the ESD voltage V FIG. 12As shown, applying a control signal to the control electrode Pm causes the switching device M to be in the off state. This puts the gate G and source S of transistor 32 in an open-circuit state. A test signal can then be applied to the gate electrode Pg of transistor 32, and the on-chip screening of transistor 32 can be achieved by detecting the output signal of the drain D. During the process of mounting the integrated circuit to the packaging substrate, refer to... FIG. 13 As shown, when a control signal is applied to the control electrode Pm, the switching device M is turned on. This short-circuits the gate G and source S of transistor 32 through the switching device M and the electrostatic discharge wire 33. The electrostatic voltage V at the gate G of transistor 32 is then released through the electrostatic discharge wire 33 on the integrated circuit. ESD Connect to ground (GND); after mounting the integrated circuit onto the package substrate, refer to... FIG. 14 As shown, in order to ensure the normal operation of transistor 32, the electrostatic discharge wire between the gate G and the source S of transistor 32 needs to be disconnected. Therefore, a fusing voltage V is applied to the electrostatic discharge wire 33. fuse The electrostatic discharge wire 33 is fused. Specifically, the fusing voltage V... fuse The application methods can include the following: Method 1: Refer to FIG. 14 As shown, the switching device M is turned on by a control signal, and a fusing voltage V is applied to the gate electrode Pg. fuse Method 2: Refer to the electrostatic discharge wire 33 for melting; FIG. 15 As shown, regardless of whether the switching device M is in the on or off state, the fusing voltage V is directly applied to the electrostatic discharge electrode Pesd. fuse The electrostatic discharge lead 33 is then melted. Furthermore, after the integrated circuit is mounted onto the packaging substrate, to ensure the normal operation of the transistor 32, the switching device M can be disconnected via a control signal, thus disconnecting the gate G and source S of the transistor 32. It should be noted that before the integrated circuit is mounted onto the packaging substrate, the test signal and the melting voltage V applied to the gate electrode Pg are... fuse The control signal applied to the control electrode Pm and the fusing voltage V applied to the electrostatic discharge electrode Pesd fuse All of these can be provided by probe devices capable of providing the corresponding signals or voltages. Specifically, the corresponding probes can be connected to the corresponding electrodes on the fixture and the aforementioned signals or voltages can be applied.

[0094] For depletion-mode HEMT, there is enough 2DEG concentration when no voltage is applied to the gate, so the source S and the drain D of the depletion-mode HEMT are always on, and the off state requires a negative voltage to be applied to the gate G. When the negative voltage applied to the gate G is less than the threshold voltage, the depletion-mode HEMT is off. The negative voltage applied to the gate G generates an electric field opposite to the built-in electric field, which reduces the band bending at the heterojunction interface between the barrier layer and the channel layer, and reduces the depth of the triangular potential well, thereby reducing the 2DEG concentration. For enhancement-mode HEMT, when no voltage is applied to the gate G, the 2DEG concentration is very low due to the influence of the Schottky barrier of the gate G or the low doping concentration of the barrier layer, so the source S and the drain D cannot be turned on. When a positive voltage is applied to the gate G and the positive voltage is greater than the threshold voltage, an electric field is generated in the same direction as the built-in electric field, which increases the band bending at the heterojunction interface between the barrier layer and the channel layer, and increases the depth of the triangular potential well, thereby increasing the 2DEG concentration and turning on the HEMT. Referring to FIG. 16 , a structural schematic diagram of a depletion-mode HEMT is provided, referring to FIG. 17 , FIG. 18 , a structural schematic diagram of an enhancement-mode HEMT is provided. Similar to the structure of the HEMT in FIG. 6 , both the depletion-mode HEMT and the enhancement-mode HEMT include a channel layer, a barrier layer, a gate dielectric layer, and an electrode such as a gate, a source, and a drain disposed on a substrate, wherein the source and the drain are in contact with the channel layer; wherein FIG. 18 The gate dielectric layer in the enhancement-mode HEMT shown is a P (positive) type conductive layer. The difference between the structures of the depletion-mode HEMT and the enhancement-mode HEMT is that, in combination with FIG. 16 , the barrier layer of the depletion-mode HEMT is continuously distributed between the gate stop layer and the channel layer, so that in the normal state, the N (negative) type doping of the barrier layer can further increase the electron concentration in the channel layer, so that the source and the drain are turned on; in combination with FIG. 17 , the barrier layer of the enhancement-mode HEMT is separated by the gate dielectric layer between the source and the drain, so that in the normal state, the electron concentration in the channel layer below the separated part of the barrier layer is low, so that the source and the drain are turned off; in another scheme, referring to FIG. 18As shown, the gate dielectric layer of an enhancement-mode HEMT can also be replaced with a P-type conductive layer disposed only below the gate. Since the holes provided by the P-type conductive layer recombine with electrons in the channel layer, the electron concentration in the channel layer is low under normal conditions, causing the source and drain to disconnect. The above provides commonly used depletion-mode HEMT and enhancement-mode HEMT structures. Of course, with the evolution of technology, other structural forms of depletion-mode HEMT and enhancement-mode HEMT have emerged. Therefore, it should not be understood that only the above-described depletion-mode HEMT and enhancement-mode HEMT structures are applicable to the switching devices of this application. In other embodiments, any device that can achieve the functions of the above-described depletion-mode HEMT and enhancement-mode HEMT should be considered an implementation of this application.

[0095] Based on the above principles, referring to FIG. 19 As shown, the switching device M can be a depletion-type HEMT. The source S of the depletion-type HEMT is coupled to the first end of the electrostatic discharge wire 33, and the drain D of the depletion-type HEMT is coupled to the gate G of the transistor 32. The gate G of the depletion-type HEMT is coupled to the control electrode Pm. For example, the control electrode Pm and the gate G of the depletion-type HEMT are electrically connected through a via. The depletion-type HEMT is in the ON state, or the gate G of the depletion-type HEMT is used to receive the first control voltage (which can be a negative voltage as described above) transmitted by the control electrode Pm, and the depletion-type HEMT is in the OFF state under the control of the first control voltage.

[0096] Specifically, in the on-chip screening stage before the integrated circuit is mounted onto the packaging substrate, refer to FIG. 19 As shown, applying a negative voltage to the control electrode Pm puts the depletion-type HEMT in the off state, thus opening the gate G and source S of transistor 32. A test signal can then be applied to the gate G of transistor 32 connected to the gate electrode Pg, and the on-chip screening of transistor 32 can be achieved by detecting the output signal of the drain D of transistor 32. During the process of mounting the integrated circuit to the packaging substrate, refer to... FIG. 20 As shown, when no voltage is applied to the control electrode Pm (control electrode Pm is floating), the depletion-type HEMT is in the on state. Thus, the gate G and source S of transistor 32 are short-circuited through the depletion-type HEMT and the electrostatic discharge wire 33. The electrostatic voltage V at the transistor gate is then released through the electrostatic discharge wire 33 on the integrated circuit. ESD When the circuit is connected to ground (GND), the specific electrostatic discharge voltage V of the electrostatic discharge electrode Pesd and the gate electrode Pg is... ESD All can be discharged to the ground terminal GND through the electrostatic discharge wire 33; after the integrated circuit is mounted onto the packaging substrate, refer to FIG. 21As shown, in order to ensure that the transistor 32 works normally, the electrostatic discharge wire between the gate G and the source S of the transistor 32 needs to be disconnected, so the fuse voltage V fuse is applied to the electrostatic discharge wire 33 to fuse the electrostatic discharge wire 33. Specifically, the fuse voltage V fuse may be applied in the following ways: way one: since the depletion-mode HEMT is in the on state when no voltage is applied to the control electrode Pm, the fuse voltage V fuse may be applied to the gate electrode Pg to fuse the electrostatic discharge wire 33; way two: the fuse voltage V fuse is directly applied to the electrostatic discharge electrode Pesd to fuse the electrostatic discharge wire 33. In addition, after the integrated circuit is attached to the packaging substrate, in order to ensure that the transistor 32 works normally, the control electrode Pm can also be applied with a negative voltage so that the depletion-mode HEMT is in the off state, thereby disconnecting the gate G and the source S of the transistor 32, which will cause additional power consumption. In the depletion-mode HEMT in FIGS. 19-21 , the source S of the depletion-mode HEMT can be understood as a first active electrode, and the drain D of the depletion-mode HEMT can be understood as a second active electrode. In one embodiment, the source S of the depletion-mode HEMT is coupled to the first end of the electrostatic discharge wire 33, and the drain D of the depletion-mode HEMT is coupled to the gate of the transistor 32. In another embodiment, the drain D of the depletion-mode HEMT can also be coupled to the first end of the electrostatic discharge wire, and the source S of the depletion-mode HEMT is coupled to the gate of the transistor 32.

[0097] Based on the above principle, referring to FIG. 22 , the switch device M can be an enhancement-mode HEMT. The source S of the enhancement-mode HEMT is connected to the first end of the electrostatic discharge wire 33, the drain D of the enhancement-mode HEMT is connected to the gate G of the transistor 32, and the gate G of the enhancement-mode HEMT is coupled to the control electrode Pm, for example, the control electrode Pm and the gate G of the enhancement-mode HEMT are electrically connected through a via. The enhancement-mode HEMT is in the off state, or the gate G of the enhancement-mode HEMT is used to receive the second control voltage (as described above, which can be a positive voltage) transmitted by the control electrode Pm, and the enhancement-mode HEMT is in the on state under the control of the second control voltage.

[0098] In the on-wafer screening stage before the integrated circuit is attached to the packaging substrate, referring to FIG. 22 , the control electrode Pm is not applied with a voltage (the control electrode Pm is suspended), so that the enhancement-mode HEMT is in the off state, and the gate G and the source S of the transistor 32 are in the disconnected state. A test signal can be applied to the gate electrode Pg connected to the gate G of the transistor 32, and the on-wafer screening of the transistor 32 can be realized by detecting the output signal of the drain D of the transistor 32; in the attachment process of attaching the integrated circuit to the packaging substrate, referring to FIG. 23As shown, applying a positive voltage to the control electrode Pm puts the enhancement-mode HEMT into the on state. This shorts the gate G and source S of transistor 32 through the enhancement-mode HEMT and the electrostatic discharge wire 33. The electrostatic voltage V at the gate G of transistor 32 is then released through the electrostatic discharge wire 33 on the integrated circuit. ESD When the circuit is connected to ground (GND), the specific electrostatic discharge voltage V of the electrostatic discharge electrode Pesd and the gate electrode Pg is... ESD All can be discharged to the ground terminal GND through the electrostatic discharge wire 33; after the integrated circuit is mounted onto the packaging substrate, refer to FIG. 24 As shown, in order to ensure the normal operation of transistor 32, the electrostatic discharge wire between the gate G and the source S of transistor 32 needs to be disconnected. Therefore, a fusing voltage V is applied to the electrostatic discharge wire 33. fuse The electrostatic discharge wire 33 is fused. Specifically, the fusing voltage V... fuse The application methods can include the following: Method 1: Since the enhancement-mode HEMT is in the on state when a positive voltage is applied to the control electrode Pm, a positive voltage can be applied to the control electrode Pm to turn on the enhancement-mode HEMT, and a fusing voltage V can be applied to the gate electrode Pg. fuse Method 1: Melt the electrostatic discharge lead 33; Method 2: Directly apply a melting voltage V to the electrostatic discharge electrode Pesd. fuse The electrostatic discharge wire 33 is melted. Furthermore, after the integrated circuit is mounted onto the packaging substrate, to ensure the normal operation of transistor 32, the gate G and source S of transistor 32 need to be disconnected. Since enhancement-mode HEMTs are in the off state when no voltage is applied to the gate G, the gate G and source S of transistor 32 can also be directly disconnected via the enhancement-mode HEMT. Among these, in FIGS. 22-24 In the enhancement-mode HEMT, the source S can be understood as the first active electrode, and the drain D can be understood as the second active electrode. In one embodiment, the source S of the enhancement-mode HEMT is coupled to the first end of the electrostatic discharge wire 33, and the drain D of the enhancement-mode HEMT is coupled to the gate of the transistor 32. In another embodiment, the drain D of the enhancement-mode HEMT can also be coupled to the first end of the electrostatic discharge wire, and the source S of the enhancement-mode HEMT can be coupled to the gate of the transistor 32. In some examples, such as... FIG. 25As shown, to reduce process costs, the gate G of the enhancement-mode HEMT can be directly coupled to the drain D of the enhancement-mode HEMT, thus eliminating the need for a control electrode Pm. In this state, the turn-on threshold voltage of the enhancement-mode HEMT needs to be greater than the threshold voltage of the transistor. Typically, since the voltage input to transistor 32 from the pre-amplifier circuit (e.g., RF circuit) is very small, usually -5V to 0V for the terminal, the turn-on threshold voltage of the enhancement-mode HEMT can be set to be greater than or equal to 1V. Thus, during the on-chip screening stage, as long as the voltage of the test signal applied to the gate G connected to the gate electrode Pg of transistor 32 is less than the turn-on threshold voltage of the enhancement-mode HEMT, the enhancement-mode HEMT is in the off state, and the gate G and source S of transistor 32 are in an open-circuit state, allowing for normal on-chip screening of transistor 32. During the mounting process of the integrated circuit to the packaging substrate, due to the electrostatic voltage V of the gate electrode Pg... ESD The voltage is much greater than the turn-on threshold voltage of the enhancement-mode HEMT, causing the enhancement-mode HEMT to be in the on state. This shorts the gate G and source S of transistor 32 through the enhancement-mode HEMT and the electrostatic discharge wire 33, and the electrostatic discharge voltage V at the gate G of transistor 32 is released through the electrostatic discharge wire 33 on the integrated circuit. ESD When the circuit is connected to ground (GND), the specific electrostatic discharge voltage V of the electrostatic discharge electrode Pesd and the gate electrode Pg is... ESD All can be discharged to the ground terminal GND through the electrostatic discharge lead 33; after the integrated circuit is mounted onto the package substrate, in order to ensure the normal operation of transistor 32, the electrostatic discharge lead between the gate G and source S of transistor 32 needs to be disconnected. Therefore, a fusing voltage V is applied to the electrostatic discharge lead 33. fuse The electrostatic discharge wire 33 is fused. Specifically, the fusing voltage V... fuse The application methods can include the following: Method 1: Directly apply the fusing voltage V to the electrostatic discharge electrode Pesd. fuse The electrostatic discharge lead 33 is melted. Furthermore, after the integrated circuit is mounted onto the packaging substrate, since the gate voltage of transistor 32 during normal operation is usually insufficient to turn on the enhancement-mode HEMT, the enhancement-mode HEMT is in the off state. Alternatively, the gate G and source S of transistor 32 can be directly disconnected through the enhancement-mode HEMT.

[0099] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An integrated circuit, characterized by The integrated circuit is used for a radio frequency module, comprising a substrate and a transistor disposed on the substrate, the transistor comprising a HEMT; a gate of the transistor is coupled with a first end of an electrostatic discharge wire, a first active electrode of the transistor is coupled with a second end of the electrostatic discharge wire, wherein the first active electrode of the transistor is also coupled with a ground terminal; the transistor is used for a power amplifier PA of the radio frequency module; a channel layer of the transistor comprises a group III nitride; The electrostatic discharge wire is used for outputting an electrostatic voltage of the gate of the transistor to the ground terminal; or when the integrated circuit is located on a chip, the electrostatic discharge wire is disconnected. The electrostatic discharge wire is also coupled with an electrostatic discharge electrode, the electrostatic discharge electrode is used for receiving a fuse voltage, or the electrostatic discharge electrode is used for receiving the electrostatic voltage, and an absolute value of the electrostatic voltage is greater than an absolute value of the fuse voltage.

2. The integrated circuit of claim 1, wherein, The electrostatic discharge wire is fused at a negative voltage.

3. The integrated circuit of claim 1, wherein, The electrostatic discharge wire is electrically connected with the electrostatic discharge electrode through a via.

4. The integrated circuit of claim 1, wherein, The gate of the transistor is also coupled with a gate electrode, wherein the gate electrode is used for receiving the fuse voltage.

5. The integrated circuit of claim 1, wherein, The electrostatic discharge wire and the gate are also coupled with a switching device, a control terminal of the switching device is coupled with a control electrode; the switching device is in a conduction state or an off state under a control signal input by the control electrode; The switching device transmits the electrostatic voltage in the conduction state, or the switching device transmits the fuse voltage in the conduction state, or the switching device disconnects the gate and the first active electrode of the transistor in the off state.

6. The integrated circuit of claim 5, wherein, The switching device comprises a depletion-mode HEMT, a first active electrode of the depletion-mode HEMT is coupled with the first end of the electrostatic discharge wire, a second active electrode of the depletion-mode HEMT is coupled with the gate of the transistor, and a gate of the depletion-mode HEMT is coupled with the control electrode; The depletion-mode HEMT is in the conduction state, or the gate of the depletion-mode HEMT is used for receiving a first control voltage transmitted by the control electrode, and the depletion-mode HEMT is in the off state under control of the first control voltage.

7. The integrated circuit of claim 5, wherein, The switching device comprises an enhancement-mode HEMT, a first active electrode of the enhancement-mode HEMT is connected with the first end of the electrostatic discharge wire, a second active electrode of the enhancement-mode HEMT is connected with the gate of the transistor, and a gate of the enhancement-mode HEMT is coupled with the control electrode; The enhancement-mode HEMT is in the off state, or the gate of the enhancement-mode HEMT is used for receiving a second control voltage transmitted by the control electrode, and the enhancement-mode HEMT is in the conduction state under control of the second control voltage.

8. The integrated circuit of claim 1, wherein, An absolute value of the electrostatic voltage is greater than an absolute value of the fuse voltage, and a duration of the fuse voltage is greater than a first time length or greater than a duration of the electrostatic voltage.

9. The integrated circuit of any of claims 1-8, wherein, The channel layer of the transistor comprises a material different from the substrate, and the channel layer of the transistor is located on the substrate.

10. The integrated circuit of any of claims 1-8, wherein, The electrostatic discharge conductor comprises any one of: a metallic material, a metal compound, a semiconductor material, and a semiconductor heterojunction.

11. The integrated circuit of any of claims 1-8, wherein, The integrated circuit further comprises a protective layer and a metal wiring layer; The metal wiring layer covers the transistor, and the metal wiring layer has metal wires therein for interconnection; The protective layer covers the metal wiring layer, the electrostatic discharge conductor is above the metal wiring layer, and the protective layer covers the electrostatic discharge conductor.

12. The integrated circuit of any of claims 1-8, wherein, The electrostatic discharge conductor has a shape comprising at least any one of: a straight line, a broken line, and a serpentine curve.

13. The integrated circuit of claim 10, wherein, The metallic material comprises any one of: nickel, aluminum, and titanium.

14. The integrated circuit of claim 10, wherein, The metal compound comprises a metal nitride or a metal silicide.

15. The integrated circuit of claim 10, wherein, The semiconductor material comprises polysilicon or monocrystalline silicon.

16. The integrated circuit of any of claims 1-8, wherein, The integrated circuit is a monolithic microwave integrated circuit (MMIC).

17. A chip, characterized by An integrated circuit as claimed in any one of claims 1 to 16 and a package substrate, wherein the integrated circuit is coupled to the package substrate.

18. An electronic device, comprising: A printed circuit board and a chip as claimed in claim 17, wherein the chip is coupled to the printed circuit board.

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