A large swing output circuit with overcurrent and overvoltage protection

Abstract

This invention belongs to the field of integrated circuit design, specifically relating to a large-swing output circuit with overcurrent and overvoltage protection. The circuit includes an output circuit module, a voltage detection circuit module, and a logic unit circuit module; these modules are interconnected. The output circuit module includes a first output module, a second output module, a third output module, and a fourth output module; the second output module is connected to the first output module, the first output module is connected to the third output module, and the third output module is connected to the fourth output module. This invention features a large differential output swing, excellent overcurrent and overvoltage protection performance, high reliability, simple structure, and strong practicality. It can be widely used in communication interfaces such as RS422 / RS485 and has broad application prospects.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design, specifically relating to a large swing output circuit with overcurrent and overvoltage protection. Background Technology

[0002] RS485 bus has wide applications in industrial control, traffic automation, and fieldbus communication networks. It boasts advantages such as strong noise suppression, high data transmission rate, high data transmission reliability, support for multiple nodes, and long-distance communication. Driver design is a key focus and challenge in RS485 interface circuit design. Traditional RS485 interface drivers include... Figure 1 As shown, to ensure the output port can achieve overvoltage protection, i.e., operate normally within a voltage range of -7V to +12V, the following needs to be added to the pull-up MOSFET and pull-down MOSFET terminals: Figure 1 The diode shown is used to implement overvoltage protection. Due to the addition of the diode, the output high level is VCC-V. DS,M1 -V D1 The output low level is V DS,M2 +V D2 This sacrifices the voltage margin of the forward conduction voltage drop of the two diodes, resulting in a reduction in the differential output amplitude. Furthermore, traditional RS485 interface drivers achieve current protection through the current saturation of the MOSFET, lacking a short-circuit current foldback function. In this case, the short-circuit current increases quadratically with the gate voltage, and a large short-circuit current reduces the chip's reliability.

[0003] In summary, there is an urgent need for a large-swing output circuit with overcurrent and overvoltage protection that can solve the problem of small differential output swing while having good overvoltage and overcurrent protection performance. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention proposes a large swing output circuit with overcurrent and overvoltage protection. The circuit includes an output circuit module, a voltage detection circuit module, and a logic unit circuit module; the output circuit module, voltage detection circuit module, and logic unit circuit module are interconnected.

[0005] The output circuit module includes a first output module, a second output module, a third output module, and a fourth output module; the second output module is connected to the first output module, the first output module is connected to the third output module, and the third output module is connected to the fourth output module; by using four output modules, combined with a voltage detection circuit module and a logic unit circuit module, the output circuit module achieves a large swing output signal and high reliability overvoltage and overcurrent protection capabilities.

[0006] Preferably, the first output module includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first inverter, a second inverter, and a third inverter;

[0007] The gate of the first NMOS transistor is connected to the output terminal of the first inverter, the source of the first NMOS transistor is connected to the substrate of the first NMOS transistor, and the drain of the first NMOS transistor is connected to the third output module.

[0008] The gate of the second NMOS transistor is connected to the output terminal of the second inverter, the source of the second NMOS transistor is connected to the substrate of the second NMOS transistor and the source of the first NMOS transistor, and the drain of the second NMOS transistor is connected to the drain of the first NMOS transistor.

[0009] The gate of the third NMOS transistor is connected to the output terminal of the third inverter, the source of the third NMOS transistor is connected to the substrate of the third NMOS transistor and the source of the first NMOS transistor, and the drain of the third NMOS transistor is connected to the drain of the first NMOS transistor.

[0010] The sources and substrates of the NMOS transistors in the first, second, and third inverters are all connected to the source of the first NMOS transistor, and the sources and substrates of the PMOS transistors in the first, second, and third inverters are all connected to the power supply.

[0011] Preferably, the second output module includes a fourth NMOS transistor and a seventh inverter;

[0012] The drain of the fourth NMOS transistor is connected to the substrate of the fourth NMOS transistor and the first output module, the gate of the fourth NMOS transistor is connected to the output terminal of the seventh inverter, and the source of the fourth NMOS transistor is connected to ground.

[0013] In the seventh inverter, the source and substrate of the NMOS transistor are connected to the drain of the fourth NMOS transistor and the voltage detection circuit module, while the source and substrate of the PMOS transistor in the seventh inverter are connected to the power supply.

[0014] Preferably, the third output module includes a first PMOS transistor, a second PMOS transistor, a fourth inverter, and a fifth inverter;

[0015] The source of the first PMOS transistor is connected to the substrate of the first PMOS transistor and the fourth output module, the gate of the first PMOS transistor is connected to the output terminal of the fourth inverter, and the drain of the first PMOS transistor is connected to the drain of the second PMOS transistor.

[0016] The source of the second PMOS transistor is connected to the substrate of the second PMOS transistor and the source of the first PMOS transistor, respectively; the gate of the second PMOS transistor is connected to the output terminal of the fifth inverter.

[0017] In the fourth and fifth inverters, the source and substrate of the NMOS transistors are both connected to ground;

[0018] The source and substrate of the PMOS transistors in the fourth and fifth inverters are both connected to the source of the first PMOS transistor.

[0019] Preferably, the fourth output module includes a sixth inverter and a third PMOS transistor;

[0020] The drain of the third PMOS transistor is connected to the substrate of the third PMOS transistor; the source of the third PMOS transistor is connected to the power supply; the gate of the third PMOS transistor is connected to the output terminal of the sixth inverter.

[0021] In the sixth inverter, the source and substrate of the PMOS transistor are connected to the drain of the third PMOS transistor, and the source and substrate of the NMOS transistor in the sixth inverter are connected to ground.

[0022] Preferably, the voltage detection circuit module includes a voltage detection unit and a comparator; the REFN port of the voltage detection unit is connected to the negative input terminal of the comparator; the output terminal of the comparator is connected to the logic unit circuit module, and both the DT_P output port and the DT_N output port of the voltage detection unit are connected to the logic unit circuit module.

[0023] Preferably, the logic unit circuit module includes logic units; the DIP ports and DIN ports of the logic units are connected to differential CMOS signal inputs, and the ports UP0, UP1, UP2, DW0, DW1, DW2 and DW3 of the logic units are all connected to the output circuit module.

[0024] The beneficial effects of this invention are as follows: The circuit of this invention consists of seven MOSFETs, seven inverters, one comparator, one voltage detection unit, and one logic unit. By controlling the gate and substrate of the MOSFETs (P0 and N0), compared with the traditional RS485 driver output structure, this invention has a higher high-level voltage and a lower low-level voltage, enabling the driver to achieve a large differential output voltage swing during normal operation. This invention can improve the transmission distance and transmission performance of RS485 interface circuits. The circuit of this invention implements overcurrent and overvoltage protection functions at the output port through loop control, giving the driver good and reliable overcurrent and overvoltage performance. This invention features a large differential output swing, good overcurrent and overvoltage protection performance, simple structure, and strong practicality, and can be widely used in RS422 / RS485 and other communication interfaces, with broad application prospects. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the output structure of a traditional RS485 driver;

[0026] Figure 2This is a structural diagram of a large swing output circuit with overcurrent and overvoltage protection according to the present invention;

[0027] Figure 3 This is the equivalent circuit diagram of P0 in this invention;

[0028] Figure 4 This is the equivalent circuit diagram of N0 in this invention;

[0029] Figure 5 This is a circuit diagram of the voltage detection circuit unit in this invention;

[0030] Figure 6 This is a schematic diagram of the output curve of the voltage detection unit in this invention;

[0031] Figure 7 This is a schematic diagram of the overcurrent protection curve when the output level is low in this invention;

[0032] Figure 8 This is a schematic diagram of the overcurrent protection curve when the output is high level in this invention. Detailed Implementation

[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] This invention proposes a large swing output circuit with overcurrent and overvoltage protection, such as... Figure 2 As shown, the circuit includes: an output circuit module 100, a voltage detection circuit module 200, and a logic unit circuit module 300; the output circuit module 100, the voltage detection circuit module 200, and the logic unit circuit module 300 are interconnected.

[0035] The output circuit module 100 includes a first output module 101, a second output module 102, a third output module 103, and a fourth output module 104; the second output module 102 is connected to the first output module 101, the first output module 101 is connected to the third output module 103, and the third output module 103 is connected to the fourth output module 104.

[0036] The first output module 101 includes a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a first inverter INV1, a second inverter INV2, and a third inverter INV3;

[0037] The gate of the first NMOS transistor N1 is connected to the output terminal of the first inverter INV1, the source of the first NMOS transistor N1 is connected to the substrate of the first NMOS transistor N1, and the drain of the first NMOS transistor N1 is connected to the drain of the first PMOS transistor P1 in the third output module 103.

[0038] The gate of the second NMOS transistor N2 is connected to the output terminal of the second inverter INV2. The source of the second NMOS transistor N2 is connected to the substrate of the second NMOS transistor N2 and the source of the first NMOS transistor N1, respectively. The drain of the second NMOS transistor N2 is connected to the drain of the first NMOS transistor N1.

[0039] The gate of the third NMOS transistor N3 is connected to the output terminal of the third inverter INV3. The source of the third NMOS transistor N3 is connected to the substrate of the third NMOS transistor N3 and the source of the first NMOS transistor N1, respectively. The drain of the third NMOS transistor N3 is connected to the drain of the first NMOS transistor N1.

[0040] The sources and substrates of the NMOS transistors in the first inverter INV1, the second inverter INV2, and the third inverter INV3 are all connected to the source of the first NMOS transistor N1. The sources and substrates of the PMOS transistors in the first inverter INV1, the second inverter INV2, and the third inverter INV3 are all connected to the power supply VCC.

[0041] The second output module 102 includes a fourth NMOS transistor N0 and a seventh inverter INV0;

[0042] The drain of the fourth NMOS transistor N0 is connected to the substrate of the fourth NMOS transistor N0 and the source of the first NMOS transistor N1 in the first output module 101, respectively. The gate of the fourth NMOS transistor N0 is connected to the output terminal of the seventh inverter INV0, and the source of the fourth NMOS transistor N0 is connected to ground GND.

[0043] In the seventh inverter INV0, the source and substrate of the NMOS transistor are connected to the drain of the fourth NMOS transistor N0 and the positive input terminal of the comparator 201 in the voltage detection circuit module 200. The source and substrate of the PMOS transistor in the seventh inverter INV0 are connected to the power supply VCC.

[0044] The third output module 103 includes a first PMOS transistor P1, a second PMOS transistor P2, a fourth inverter INV4, and a fifth inverter INV5;

[0045] The source of the first PMOS transistor P1 is connected to the substrate of the first PMOS transistor P1 and the drain of the third PMOS transistor P0 in the fourth output module 104, respectively. The gate of the first PMOS transistor P1 is connected to the output terminal of the fourth inverter INV4, and the drain of the first PMOS transistor P1 is connected to the drain of the second PMOS transistor P2.

[0046] The source of the second PMOS transistor P2 is connected to the substrate of the second PMOS transistor P2 and the source of the first PMOS transistor P1, respectively; the gate of the second PMOS transistor P2 is connected to the output terminal of the fifth inverter INV5.

[0047] In the fourth inverter INV4 and the fifth inverter INV5, the source and substrate of the NMOS transistor are both connected to ground GND.

[0048] The source and substrate of the PMOS transistors of the fourth inverter INV4 and the fifth inverter INV5 are both connected to the source of the first PMOS transistor P1.

[0049] The fourth output module 104 includes a sixth inverter INV6 and a third PMOS transistor P0;

[0050] The drain of the third PMOS transistor P0 is connected to the substrate of the third PMOS transistor P0; the source of the third PMOS transistor P0 is connected to the power supply VCC; the gate of the third PMOS transistor P0 is connected to the output terminal of the sixth inverter INV6.

[0051] In the sixth inverter INV6, the source and substrate of the PMOS transistor are connected to the drain of the third PMOS transistor P0, and the source and substrate of the NMOS transistor in the sixth inverter INV6 are connected to ground GND.

[0052] The voltage detection circuit module 200 includes a voltage detection unit 202 and a comparator 201; the REFN port of the voltage detection unit 202 is connected to the negative input terminal of the comparator 201; the output terminal of the comparator 201 is connected to the DT_N0 port of the logic unit in the logic unit circuit module 300; the DT_P output port and DT_N output port of the voltage detection unit 202 are both connected to the logic unit in the logic unit circuit module 300.

[0053] The logic unit circuit module 300 includes logic units; the DIP ports and DIN ports of the logic units are connected to differential CMOS signal inputs, and the ports UP0, UP1, UP2, DW0, DW1, DW2, and DW3 of the logic units are all connected to the output circuit module 100; specifically, the ports UP0, UP1, UP2, DW0, DW1, DW2, and DW3 of the logic units are respectively connected to the sixth inverter INV6, the fifth inverter INV5, the fourth inverter INV4, the seventh inverter INV0, the first inverter INV1, the second inverter INV2, and the third inverter INV3.

[0054] This invention features a large differential output swing, and its principle is as follows:

[0055] When the driver circuit is working normally, the equivalent circuit of the third PMOS transistor P0 is as follows: Figure 3 As shown, from Figure 3 It can be seen that the parasitic diodes of P0 and P0 are connected in parallel and conducting. At this time, the forward voltage drop of P0 is approximately the forward voltage drop V of a PMOS transistor. DSP The pull-up circuit network of the driver consists of P1 and P2 connected in parallel and then connected in series with P0, so the high level output of the circuit can reach VCC-V. ds,P0 -V ds,P1 Compared to the traditional RS485 driver output structure, it has a higher high-level voltage for the same amplitude. Similarly, when the output is low, the equivalent circuit diagram of N0 is as follows: Figure 4 As shown, from Figure 4 It can be seen that N0 and its parasitic diodes are connected in parallel and conducting. At this time, the forward voltage drop of N0 is approximately the forward voltage drop V of an NMOS transistor. DSN The pull-down circuit network of the driver consists of N1, N2, and N3 connected in parallel and then connected in series with N0. The low level output of the circuit can be V. ds,N0 +V ds,N1 Compared to the traditional RS485 driver structure, the circuit of this invention can provide a lower low-level voltage, thus enabling a large differential output voltage swing.

[0056] The overvoltage protection function principle of this invention is as follows:

[0057] When this invention is applied to an RS485 driver, the voltage range of the output port is between -7V and +12V, such as... Figure 5 As shown, when the output voltage OUT of the voltage detection unit 202 is greater than 0V, the voltage at node VN is greater than the threshold voltage of M11, and transistor M11 is turned on, making node V1 low. At this time, DT_N is high. When the output voltage OUT decreases to less than 0V, the voltage at node VN is less than the threshold voltage of M11, and transistor M11 is turned off, making node V1 high. At this time, DT_N is low. Figure 6 As shown in the figure, the hysteresis function represented by the curve is... Figure 5 The voltage generated by M12 and M13 in the logic unit 300, after passing through the logic unit 300, results in a high-level output from port DW0. The DW0 output controls INV0 to connect the gate and drain of transistor N0. Simultaneously, the parasitic diode of N0 is reverse-biased, allowing N0 to withstand voltage and thus achieving negative overvoltage protection. Similarly, when the output voltage OUT of voltage detection unit 202 is less than VCC, the voltage at node VP is less than VCC-V. TH8 When transistor M1 is turned on and DT_P is pulled high, when the output voltage OUT increases to be greater than VCC, the voltage at node VP will be greater than VCC-V. TH8 This causes transistor M1 to turn off, transistor M0 to be pulled down, and DT_P to generate a low level, such as... Figure 6As shown in the figure, the hysteresis function represented by the curve is... Figure 5 The M3 and M6 in the logic unit 300 generate the P0 gate and drain. After passing through the logic unit 300, the UP0 output of the logic unit 300 is low. The UP0 output controls INV6 to connect the gate and drain of P0. At the same time, the parasitic diode of P0 is reverse biased. At this time, P0 can withstand the voltage and thus realize the positive overvoltage protection function.

[0058] The overcurrent protection function principle of this invention is as follows:

[0059] When this invention is applied to an RS485 driver, overcurrent protection is divided into the following two cases:

[0060] (1) When the output terminal OUT is low, the pull-down circuit is turned on. At this time, the common-mode voltage at the output terminal increases from 0V to 12V. When the common-mode voltage at the output terminal increases to V1 (for example, V1 is 1.8V), Figure 2 The voltage at the middle node VN (approximately 0.5V) is greater than the reference voltage REFN at the positive terminal of comparator 201 (the reference voltage REFN is set to 0.5V, e.g.) Figure 5 As shown, when the reference voltage REFN is generated through M14-M17, the comparator outputs a high level to logic unit 300. The output of port DW3 of logic unit 300 is high. The output of DW3 controls inverter INV1 to connect the gate and source of transistor N1, thus shutting off the current flowing through N1. Figure 7 As shown, the current foldback function is achieved when the common-mode voltage at the output terminal OUT increases to the V1 voltage point. When the common-mode voltage at the output terminal OUT continues to increase and reaches VCC, the output terminal DT_P of the voltage detection unit 202 outputs a low level to the logic unit 300. The output of port DW2 of the logic unit 300 is high. The output of DW2 controls the inverter INV2 to connect the gate and source of N2, thereby turning off the current flowing through N2. When the common-mode voltage at the output terminal OUT increases to the VCC voltage point, the current foldback function is achieved again, thus realizing the overcurrent protection function.

[0061] (2) When the output terminal OUT is high, the pull-up circuit is turned on. At this time, the common-mode voltage of the output terminal OUT decreases from VCC to -7V. When the common-mode voltage of the output terminal OUT decreases to 0V, the output terminal DT_N of the voltage detection unit 202 outputs a low level to the logic unit 300. The output of port UP2 of the logic unit 300 is high. UP2 controls the inverter INV4 to connect the gate and source of P1, thus turning off the current of P1 transistor. Figure 8 As shown, the current foldback function is realized when the common-mode voltage at the output terminal OUT decreases to 0V, thereby realizing the overcurrent protection function.

[0062] The circuit of this invention consists of seven MOSFETs, seven inverters, one comparator, one voltage detection unit, and one logic unit. By controlling the gate and substrate of the MOSFETs (P0 and N0), compared to the traditional RS485 driver output structure, this invention has better high-level voltage and lower low-level voltage, enabling the driver to achieve a large differential output voltage swing during normal operation. This invention can improve the transmission distance and performance of RS485 interface circuits. The circuit of this invention implements overcurrent and overvoltage protection at the output port through loop control, giving the driver good and reliable overcurrent and overvoltage performance. This invention features a large differential output swing, high reliability of overcurrent and overvoltage protection, simple structure, and strong practicality, and can be widely used in RS422 / RS485 communication interfaces, showing broad application prospects.

[0063] The above-described embodiments further illustrate the purpose, technical solution, and advantages of the present invention. It should be understood that the above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made to the present invention within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A large swing output circuit with overcurrent and overvoltage protection, characterized in that, include: Output circuit module, voltage detection circuit module, and logic unit circuit module; The output circuit module, voltage detection circuit module, and logic unit circuit module are interconnected. The output circuit module includes a first output module, a second output module, a third output module, and a fourth output module; the second output module is connected to the first output module, the first output module is connected to the third output module, and the third output module is connected to the fourth output module; by employing four output modules, combined with a voltage detection circuit module and a logic unit circuit module, the output circuit module achieves a large-swing output signal and highly reliable overvoltage and overcurrent protection capabilities. The first output module includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first inverter, a second inverter, and a third inverter; The gate of the first NMOS transistor is connected to the output terminal of the first inverter, the source of the first NMOS transistor is connected to the substrate of the first NMOS transistor, and the drain of the first NMOS transistor is connected to the third output module. The gate of the second NMOS transistor is connected to the output terminal of the second inverter, the source of the second NMOS transistor is connected to the substrate of the second NMOS transistor and the source of the first NMOS transistor, and the drain of the second NMOS transistor is connected to the drain of the first NMOS transistor. The gate of the third NMOS transistor is connected to the output terminal of the third inverter, the source of the third NMOS transistor is connected to the substrate of the third NMOS transistor and the source of the first NMOS transistor, and the drain of the third NMOS transistor is connected to the drain of the first NMOS transistor. The source and substrate of the NMOS transistors in the first, second, and third inverters are all connected to the source of the first NMOS transistor, and the source and substrate of the PMOS transistors in the first, second, and third inverters are all connected to the power supply. The second output module includes a fourth NMOS transistor and a seventh inverter; The drain of the fourth NMOS transistor is connected to the substrate of the fourth NMOS transistor and the first output module, the gate of the fourth NMOS transistor is connected to the output terminal of the seventh inverter, and the source of the fourth NMOS transistor is connected to ground. In the seventh inverter, the source and substrate of the NMOS transistor are connected to the drain of the fourth NMOS transistor and the voltage detection circuit module, and the source and substrate of the PMOS transistor in the seventh inverter are connected to the power supply. The third output module includes a first PMOS transistor, a second PMOS transistor, a fourth inverter, and a fifth inverter; The source of the first PMOS transistor is connected to the substrate of the first PMOS transistor and the fourth output module, the gate of the first PMOS transistor is connected to the output terminal of the fourth inverter, and the drain of the first PMOS transistor is connected to the drain of the second PMOS transistor. The source of the second PMOS transistor is connected to the substrate of the second PMOS transistor and the source of the first PMOS transistor, respectively. The gate of the second PMOS transistor is connected to the output of the fifth inverter; In the fourth and fifth inverters, the source and substrate of the NMOS transistors are both connected to ground; The source and substrate of the PMOS transistors in the fourth and fifth inverters are both connected to the source of the first PMOS transistor. The fourth output module includes a sixth inverter and a third PMOS transistor; The drain of the third PMOS transistor is connected to the substrate of the third PMOS transistor; the source of the third PMOS transistor is connected to the power supply; the gate of the third PMOS transistor is connected to the output terminal of the sixth inverter. In the sixth inverter, the source and substrate of the PMOS transistor are connected to the drain of the third PMOS transistor, and the source and substrate of the NMOS transistor in the sixth inverter are connected to ground.

2. The large swing output circuit with overcurrent and overvoltage protection according to claim 1, characterized in that, The voltage detection circuit module includes a voltage detection unit and a comparator; the REFN port of the voltage detection unit is connected to the negative input terminal of the comparator; the output terminal of the comparator is connected to the logic unit circuit module, and the DT_P output port and DT_N output port of the voltage detection unit are both connected to the logic unit circuit module.

3. The large swing output circuit with overcurrent and overvoltage protection according to claim 1, characterized in that, The logic unit circuit module includes logic units; the DIP and DIN ports of the logic units are connected to differential CMOS signal inputs, and the ports UP0, UP1, UP2, DW0, DW1, DW2, and DW3 of the logic units are all connected to the output circuit module.

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