Semiconductor device and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor device and a method of manufacturing the same. In a method of manufacturing a semiconductor device, a first conductive layer is formed over a first interlayer dielectric (ILD) layer disposed over a substrate, a second ILD layer is formed over the first conductive layer, a via is formed in the second ILD layer to contact an upper surface of the first conductive layer, a hard mask pattern is formed over the second ILD layer, the second ILD layer and the first conductive layer are patterned by using the hard mask pattern as an etching mask, thereby forming a patterned second ILD layer and a first wiring pattern, after the patterning, the hard mask pattern is removed, and a third ILD layer is formed between the patterned second ILD layer and the first wiring pattern.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and more particularly to semiconductor devices and methods of manufacturing the same. Background Technology

[0002] Semiconductor devices (integrated circuits) comprise multiple wiring layers with wiring patterns and vias connecting vertically adjacent wiring patterns to enable complex circuit system functions. Improved cover control is required when forming vias and metal wiring during semiconductor device fabrication. Damascene processes (especially dual damascene processes) are widely used for forming vias and metal wiring. However, further improvements to wiring layer formation processes are still needed to manufacture advanced semiconductor devices. Summary of the Invention

[0003] According to one aspect of this disclosure, a method of manufacturing a semiconductor device is provided, comprising: forming a first conductive layer on a first interlayer dielectric (ILD) layer disposed on a substrate; forming a second ILD layer on the first conductive layer; forming a via in the second ILD layer to contact an upper surface of the first conductive layer; forming a hard mask pattern on the second ILD layer; transferring the hard mask pattern into the second ILD layer and the first conductive layer to form a patterned second ILD layer and a patterned first wiring pattern; removing the hard mask pattern after patterning; and forming a third ILD layer between the patterned second ILD layer and the patterned first wiring pattern.

[0004] According to one aspect of this disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a first conductive layer on a first interlayer dielectric (ILD) layer disposed on a substrate; forming a second ILD layer on the first conductive layer; forming a dummy via in the second ILD layer to contact an upper surface of the first conductive layer; forming a hard mask pattern on the second ILD layer; patterning the second ILD layer and the first conductive layer by using the hard mask pattern as an etching mask to form a patterned second ILD layer and a first wiring pattern; removing the hard mask pattern after patterning; forming a third ILD layer between the patterned second ILD layer and the first wiring pattern; and replacing the dummy via with a conductive via.

[0005] According to one aspect of this disclosure, a semiconductor device is provided, comprising: a transistor disposed on a substrate; and a plurality of wiring layers disposed on the transistor, wherein: one of the plurality of wiring layers includes a wiring pattern and a via connected to an upper surface of the wiring pattern, and the wiring pattern includes a lateral protrusion projecting relative to a side of the wiring pattern. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 This is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2A and Figure 2B A view is shown of the various stages of sequential manufacturing operations of a semiconductor device according to embodiments of the present disclosure.

[0009] Figure 3A and Figure 3B A view is shown of the various stages of sequential manufacturing operations of a semiconductor device according to embodiments of the present disclosure.

[0010] Figure 4A and Figure 4B A view is shown of the various stages of sequential manufacturing operations of a semiconductor device according to embodiments of the present disclosure.

[0011] Figure 5A , Figure 5B , Figure 5C and Figure 5D A view is shown of the various stages of sequential manufacturing operations of a semiconductor device according to embodiments of the present disclosure.

[0012] Figure 6A , Figure 6B and Figure 6C A view is shown of the various stages of sequential manufacturing operations of a semiconductor device according to embodiments of the present disclosure.

[0013] Figure 7A , Figure 7B and Figure 7C A view is shown of the various stages of sequential manufacturing operations of a semiconductor device according to embodiments of the present disclosure.

[0014] Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E , Figure 8F and Figure 8G A view is shown of the various stages of sequential manufacturing operations of a semiconductor device according to embodiments of the present disclosure.

[0015] Figure 9A , Figure 9B and Figure 9CA view is shown of the various stages of sequential manufacturing operations of a semiconductor device according to embodiments of the present disclosure.

[0016] Figure 10A , Figure 10B and Figure 10C A view is shown of the various stages of sequential manufacturing operations of a semiconductor device according to embodiments of the present disclosure.

[0017] Figure 11A and Figure 11B A view is shown of the various stages of sequential manufacturing operations of a semiconductor device according to embodiments of the present disclosure.

[0018] Figure 12A , Figure 12B , Figure 12C and Figure 12D A view is shown of the various stages of sequential manufacturing operations of a semiconductor device according to embodiments of the present disclosure.

[0019] Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 13E and Figure 13F A view showing the connection structure of vias and wiring patterns of a semiconductor device according to an embodiment of the present disclosure is provided.

[0020] Figure 14A , Figure 14B , Figure 14C and Figure 14D A plan view of a hard mask pattern and vias according to an embodiment of the present disclosure is shown.

[0021] Figure 15A , Figure 15B , Figure 15C and Figure 15D A plan view of wiring patterns and vias according to embodiments of the present disclosure is shown.

[0022] Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 16E , Figure 16F , Figure 16G Figure 16H shows a view of the various stages of sequential manufacturing operations of a semiconductor device according to an embodiment of the present disclosure.

[0023] Figure 17A , Figure 17B , Figure 17C , Figure 17D and Figure 17E A view is shown of the various stages of sequential manufacturing operations of a semiconductor device according to embodiments of the present disclosure.

[0024] Figure 18A and Figure 18B The wiring structure of a semiconductor device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0025] It should be understood that the following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, the dimensions of elements are not limited to the disclosed range or values, but may depend on process conditions and / or the desired properties of the device. Furthermore, in the following description, forming a first feature on or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed to be inserted between the first and second features such that the first and second features are not in direct contact. For simplicity and clarity, various features may be drawn at arbitrary scales. In the drawings, some layers / features may be omitted for simplicity.

[0026] Furthermore, spatially related terms (e.g., "below," "below," "lower than," "above," "upper," etc.) may be used herein to readily describe the relationship of one element or feature shown in the figures relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted accordingly. Additionally, the term "made of" may mean "comprising" or "consisting of." Furthermore, in the manufacturing processes described below, one or more additional operations may occur during / between the operations, and the order of operations may be changed.

[0027] In back-end assembly (BEOL) processes used to form metal wiring layers, a dual damascene process is employed. This process creates trenches for metal lines (conductive wiring patterns) and holes for vias, then simultaneously fills both trenches and holes with conductive material. In this dual damascene process, vias and metal wiring patterns disposed on top of the vias are formed simultaneously (i.e., the metal wiring layer is on top of the vias). As the critical dimension (CD) of the trenches and / or holes becomes smaller, it becomes more difficult to fill the very narrow trenches and holes with conductive material. Furthermore, coverage errors between vias and the metal layer (formed on top of the vias) in the dual damascene process can lead to high resistance or electrical short circuits. Via coverage errors can also cause smaller gaps between metal wiring patterns at the same layer level, potentially increasing the risk of electrical short circuits. Additionally, via coverage errors, along with over-etching during the formation of holes for vias, can cause cross-layer tunneling and lead to electrical short circuits.

[0028] This disclosure provides a novel process for forming metal wiring patterns and vias using a metal etching process, which can reduce coverage errors. Specifically, this embodiment provides a self-alignment process between vias and the metal wiring pattern disposed beneath the vias. More specifically, vias are formed by a metal filling process (e.g., damascene or etching process); and the metal wiring pattern is formed by an etching process using an etching mask.

[0029] Figure 1 This is a cross-sectional view of a semiconductor device including multiple wiring layers according to an embodiment of the present disclosure.

[0030] In some embodiments, a transistor 15 (e.g., a field-effect transistor (FET)) is disposed on a substrate 10. In some embodiments, the FET 15 includes a gate electrode 15G, a source electrode 15S, and a drain electrode 15D. In this disclosure, the source and drain electrodes may be used interchangeably and may have the same structure. In some embodiments, the FET is a planar FET, a fin FET, or a gate-all-around (GAA) FET. In some embodiments, one or more interlayer dielectric (ILD) layers 30 are formed on the FET.

[0031] In some embodiments, the substrate 10 may be made of a suitable elemental semiconductor, such as silicon, diamond, or germanium; or of a suitable alloy or compound semiconductor, such as a Group IV compound semiconductor (e.g., silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), GeSn, SiSn, SiGeSn), or a Group III-V compound semiconductor (e.g., gallium arsenide, indium gallium arsenide (InGaAs), indium arsenide, indium phosphide, indium antimonide, gallium arsenide, or gallium indium phosphide). In some embodiments, the substrate 10 includes isolation regions, such as shallow trench isolation (STI), located between active regions and separating one or more electronic components from other electronic components.

[0032] In some embodiments, a plurality of wiring layers L are formed on top of the FET. x (The x-th wiring layer), where x is 1, 2, 3…, such as Figure 1 As shown. Each wiring layer L x Including conductive wiring pattern M x and connected in wiring pattern M x The upper via V x (via contact), and each wiring layer L x+1 (The (x+1)th wiring layer) includes the conductive wiring pattern M. x+1 and connected in wiring pattern M x+1 The upper via V x+1 Similarly, wiring layer L x-1 Including conductive wiring pattern M x-1 and connected in wiring pattern M x-1 The upper via V x-1 .

[0033] In some embodiments, when wiring layer L x Includes wiring pattern M extending in the X direction x At that time, wiring layer L x+1 Includes wiring pattern M extending in the Y direction x+1 In other words, the X-direction metal wiring patterns and the Y-direction metal wiring patterns are stacked alternately in the vertical direction. In some embodiments, x is at most 20. In some embodiments, wiring layer L1 may include the wiring pattern M1 closest to FET 15, excluding local interconnects. Each wiring layer L... x It also includes one or more ILD layers or intermetallic dielectric (IMD) layers. In other embodiments, the wiring layer may include vias formed over the metal wiring pattern.

[0034] Figure 2A and Figures 2B to 9A and Figure 9BVarious views are shown of the various stages of sequential manufacturing operations of a semiconductor device according to embodiments of the present disclosure. It should be understood that, for additional embodiments of the method, [further details may be needed]. Figures 2A to 9B Additional operations are provided before, during, and after the process shown, and some of these operations can be substituted or eliminated. The order of operations / processes can be interchanged. Figures 2A to 9B In the diagram, "A" is a perspective view, and "B" is a cross-sectional view.

[0035] like Figure 2A and Figure 2B As shown, a first conductive layer 60, serving as a blanket layer, is formed on a first dielectric (ILD) layer 50 disposed on a substrate 10. The first dielectric layer 50 includes a conductive layer 60 disposed on a FET (FET). Figure 2A and Figure 2B One or more dielectric layers above (not shown in the image) and including a lower via (via contact) 40. In some embodiments, the lower via 40 corresponds to, for example... Figure 1 The via V shown x-1 Or, local interconnects can be directly disposed on the source and / or drain of the FET.

[0036] In some embodiments, the first conductive layer 60 comprises one or more layers of conductive material, such as Cu, Al, Ru, W, Co, Ti, or Ta, or alloys thereof. In some embodiments, the thickness of the first conductive layer 60 is in the range of about 20 nm to about 200 nm. In some embodiments, when the first conductive layer is made of a single metal element, the purity of the metal element is greater than 99%. In some embodiments, the purity is less than 100%, and the first conductive layer may include impurities (e.g., carbon). In some embodiments, Ru, Co, or Cu is used. In some embodiments, the first conductive layer 60 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) including sputtering, electroplating, or atomic layer deposition (ALD).

[0037] In some embodiments, the first ILD layer 50 includes one or more layers of the following: silicon oxide, SiON, SiOCN, SiCN, SiOC, silicon nitride, organic materials, low-k dielectric materials, or very low-k dielectric materials.

[0038] Next, as Figure 3A and Figure 3BAs shown, a second ILD layer 70 is formed on top of the first conductive layer 60. In some embodiments, the second ILD layer 70 is made of the same or different material as the first ILD layer 50, and includes one or more layers of the following: silicon oxide, SiON, SiOCN, SiCN, SiOC, silicon nitride, organic materials, low-k dielectric materials, or very low-k dielectric materials. In some embodiments, the thickness of the second ILD layer 70 is in the range of about 20 nm to about 200 nm.

[0039] Then, as Figure 3A and Figure 3B As shown, one or more first vias (via contacts) 80 are formed in the second ILD layer 70. In some embodiments, the first via 80 corresponds to a via V. x .

[0040] In some embodiments, a single damascene process is used to form the first via 80. In this single damascene process, a resist pattern having holes corresponding to the via 80 is formed on the second ILD layer 70, and the second ILD layer 70 is patterned by forming holes in the second ILD layer 70 using plasma etching. Then, one or more conductive layers are formed in the holes (fill process) and on the upper surface of the second ILD layer 70, and one or more planarization operations, such as chemical mechanical polishing (CMP) processes, are performed to remove excess portions of the conductive layers.

[0041] In some embodiments, the first via 80 includes one or more conductive material layers, such as Cu, Al, Ru, W, Co, Ti, or Ta, or alloys thereof. In some embodiments, the first via 80 includes one or more barrier or adhesion layers (e.g., Ti, TiN, Ta, and / or TaN) and one or more host layers (e.g., Cu, Ru, Co, etc.). In some embodiments, the first via 80 (particularly the host layer) is made of the same or different material as the first conductive layer 60. In some embodiments, the first conductive layer 60 includes Ru, and the first via 80 includes Cu. In some embodiments, the first via 80 includes a host layer and a cap layer disposed on the host layer. In some embodiments, the cap layer is made of a material similar to... Figure 4A and Figure 4B The hard mask layers explained herein may be made of the same or different materials. In some embodiments, when the vias (particularly the body layer) are made of a single metal element, the purity of the metal element is greater than 99%. In some embodiments, the purity is less than 100%, and the material may include impurities (e.g., carbon).

[0042] Then, as Figure 4A and Figure 4BAs shown, a hard mask layer 90 is formed over the second ILD layer 70 and the first via 80. In some embodiments, the hard mask layer 90 comprises one or more dielectric materials (e.g., silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, etc.) or one or more metal or metal nitride layers (e.g., Ta, Ti, TaN, or TiN) different from the second ILD layer 70. In some embodiments, TiN is used. In some embodiments, the hard mask layer 90 is formed by CVD, PVD, or ALD. In some embodiments, the thickness of the hard mask layer 90 is in the range of about 5 nm to about 100 nm, depending on process requirements. In some embodiments, one or more additional ILD layers are formed prior to the formation of the hard mask layer 90.

[0043] Furthermore, such as Figure 5A and Figure 5B As shown, the hard mask layer 90 is patterned into a hard mask pattern 92 using one or more photolithography and etching operations. In some embodiments, the hard mask pattern 92 corresponds to Figure 1 Wiring pattern M x The hard mask pattern 92 is designed to align with the lower via 40.

[0044] In other embodiments, the hard mask pattern 92 is formed using a single damascene process. In this case, as... Figure 5C As shown, a resist pattern with trench openings corresponding to the hard mask pattern 92 is formed over an additional ILD layer 71 (formed on the second ILD layer 70). The additional ILD layer 71 is patterned by forming trenches in the additional ILD layer 71 using plasma etching. One or more hard mask materials are formed in the trench cavities and upper surface of the additional ILD layer 71, followed by a CMP process. In some embodiments, the additional ILD layer 71 is made of the same or similar material as the second ILD layer 70. In other embodiments, no additional ILD layer is formed, and trenches are formed in the second ILD layer 70 and filled with a material for hard mask patterning, such as... Figure 5D As shown in the image.

[0045] like Figure 5A and Figure 5B As shown, the hard mask pattern 92 does not necessarily completely cover a portion of the via 80. In some embodiments, two patterns are adjacent to each other along the X direction (pattern extension direction) and have an end-to-end spacing D2. In some embodiments, the spacing D2 is smaller than the end-to-end spacing D1 along the X direction between adjacent vias 80. In some embodiments, the spacing D2 is equal to or greater than the spacing D1 in the layout pattern (layout design).

[0046] Next, the second ILD layer 70 is patterned using one or more etch operations that employ hard mask pattern 92 as an etch mask, such as... Figure 6A and Figure 6B As shown. In some embodiments, a plasma etching process is employed. The etching gas in the plasma etching includes one or more selected from the group consisting of carbon tetrafluoride (CF4), difluoromethane (CH2F2), trifluoromethane (CHF3), and octafluorocyclobutane (C4F8), or any suitable reactant. In some embodiments, carbon dioxide (CO) is also added to the plasma source gas. Other suitable etching gases may be used. In some embodiments, portions of the via 80 not completely covered by the hard mask pattern 92 are also used as etching masks. The plasma dry etching essentially stops on the first conductive layer 60.

[0047] Figure 6C It shows in Figure 5D The cross-sectional view of the second ILD layer 70 after patterning in the case of the structure shown.

[0048] Then, as Figure 7A and Figure 7B As shown, the first conductive layer 60 is patterned using one or more etch operations that employ a hard mask pattern 92, a via 80, and a patterned second dielectric layer 72 as etch masks. In some embodiments, a portion of the upper surface of the via 80 is exposed to plasma (not covered by the hard mask pattern 92). This etch operation forms a layer corresponding to... Figure 1 Wiring pattern M x The metal wiring pattern 62. In some embodiments, the etching gas in the plasma etching includes Cl2 and / or O2, or any other suitable etching gas. The plasma dry etching essentially stops on the first ILD layer 50. Figure 7C It shows in Figure 5D and Figure 6C The cross-sectional view of the first conductive layer 60 after patterning in the structure shown.

[0049] like Figure 7A and Figure 7BAs shown, when via 80 is positioned at the line end of wiring pattern 62 along the X direction, the line end of wiring pattern 62 is defined by via 80 rather than the line end of hard mask pattern 92. Similarly, when via 80 is laterally misaligned with hard mask pattern 92 (i.e., there is a coverage error between the hard mask pattern and the via), for example, when a portion of via 80 protrudes relative to the side of hard mask pattern 92 along the Y direction in the plan view, the side of wiring pattern 62 is defined by via 80 rather than the side of hard mask pattern 92 after etching the first conductive layer 60. In other words, wiring pattern 62 is formed in a self-aligned manner relative to via 80, which is formed before wiring pattern 62 is formed (patterned). Therefore, in some embodiments, a protrusion 65 is formed on the misaligned side of wiring pattern 62 just below via 80. In some embodiments, this misalignment means that the center of the via in the plan view does not match (or deviate from) the center of the wiring pattern in the width (short side) direction.

[0050] Then, as Figures 8A to 8D As shown, the hard mask pattern 92 is removed by using appropriate etching operations. Figure 8C and Figure 8D These are also perspective views from different angles. In some embodiments, a wet etching operation is used to remove the hard mask pattern 92. Figure 8E A plan view (top view) is shown that does not show the second ILD layer 72, and Figure 8F A plan view (top view) is shown, excluding the second ILD layer 72 and the via 80. Figure 8G It shows in Figure 5D , Figure 6C and Figure 7C The cross-sectional view after the hard mask pattern 92 has been removed in the case shown in the diagram.

[0051] As described above, the misaligned via 80 protruding relative to the side portion of the hard mask pattern 92 protects the underlying wiring pattern 62 that forms a self-aligned structure. In some embodiments, the side of the wiring pattern 62 includes a protrusion or bump 65, on which the via 80 is disposed.

[0052] Furthermore, a third ILD layer 100 is formed, such as... Figure 9A and Figure 9BAs shown. In some embodiments, a blanket layer of one or more dielectric layers is formed in the trenches between and above the patterned second ILD layer 72 and the wiring pattern 62, and a planarization operation such as CMP is performed to expose the upper surface of the via 80. In some embodiments, the third ILD layer 100 is made of the same or different material as the first ILD layer and / or the second ILD layer, and includes one or more layers of the following: silicon oxide, SiON, SiOCN, SiCN, SiOC, silicon nitride, organic materials, low-k dielectric materials, or very low-k dielectric materials. Figure 9A and Figure 9B As shown, by from Figure 2A and Figure 2B arrive Figure 9A and Figure 9B The operation forms the wiring pattern M x and via V x . Figure 9C It shows in Figure 5D , Figure 6C , Figure 7C and Figure 8D The cross-sectional view after the formation of the third ILD layer 100 in the structure shown is shown.

[0053] In some embodiments, repeating about Figure 2A and Figures 2B to 9A and Figure 9B The operation is explained to form a wiring pattern M. x+1 and via V x+1 The wiring structure. Figure 10A and Figure 10B This shows the formation of wiring pattern M x+1 and via V x+1 Subsequent structure. Wiring pattern M x+1 Includes a wiring pattern 112 similar to wiring pattern 62 but extending in a different direction from wiring pattern 62, and via V x+1 This includes a via 120, similar to a via 80, disposed on the wiring pattern 112. In some embodiments, a fourth ILD layer 132 is formed on the wiring pattern 112, and a fifth ILD layer 140 fills the gap between the patterned fourth ILD layer 132 and the wiring pattern 112. Figure 10C It shows in Figure 5D , Figure 6C , Figure 7C , Figure 8D and Figure 9C The cross-sectional view after forming the wiring pattern 112, via 120, fourth ILD layer 132 and fifth ILD layer 140 in the case shown.

[0054] In some embodiments, depending on design and / or process requirements, the width of the wiring pattern 62 ranges from about 5 nm to about 15 nm, wherein the spacing is from about 15 nm to 30 nm. In some embodiments, depending on design and / or process requirements, the diameter of the via 80 ranges from about 5 nm to about 15 nm, wherein the minimum spacing in the X direction extending along the wiring pattern 62 is from about 12 nm to about 30 nm, and the spacing in the Y direction is from about 15 nm to about 30 nm.

[0055] In some embodiments, the diameter of the via 80 is approximately the same as the width of the wiring pattern 62. In some embodiments, this difference is greater than 0 nm and less than + / - 20% of the width of the wiring pattern 62. In some embodiments, the minimum via spacing of the via 80 along the Y direction is approximately the same as the spacing of the wiring pattern 62, while the minimum via spacing of the via 80 along the X direction is approximately the same as the spacing of the upper wiring pattern 112 (M). x+1 The spacing between them is roughly the same.

[0056] In some embodiments, wiring pattern M x+1 Wiring pattern 114 through Figure 11A And formed by the single damascene process shown in 11B, rather than by repeating the process described above. Figure 2A and Figures 2B to 9A and Figure 9B The operation is explained. In some embodiments, wiring pattern 114 is embedded in a trench formed in ILD layer 145.

[0057] Figures 12A to 12D Various views of the various stages of the sequential manufacturing operations according to embodiments of the present disclosure are shown. It should be understood that, for additional embodiments of the method, [further details may be needed]. Figure 12A Additional operations are provided before, during, and after the process shown in Figure 12D, and some of these operations can be replaced or eliminated. The order of operations / processes can be interchanged.

[0058] In some embodiments, such as Figure 12A As shown, a dummy via 80D is formed in the second ILD layer 70. In some embodiments, a dielectric material or semiconductor material different from the second ILD layer 70 is used for the dummy via 80D. In some embodiments, amorphous silicon or polycrystalline silicon is used as the dummy via 80D. Then, through regarding Figures 4A to 9B The explained operations, patterning the second ILD layer 72 and wiring pattern 62 are similar to Figure 9A and Figure 9B Formation, such as Figure 12B As shown. Then, the dummy via 80D is removed to leave hole 81, as... Figure 12CAs shown. In some embodiments, when the dummy via 80D is made of silicon, the dummy via 80D can be removed by a wet etching operation using, for example, tetramethylammonium hydroxide (TMAH). The holes 81 are then filled with one or more conductive materials to form via 80, as shown. Figure 12D As shown.

[0059] Figure 13A and Figure 13B Detailed views of a via 80 and wiring pattern 62 according to embodiments of the present disclosure are shown. In some embodiments, the via 80 has a generally columnar (cylindrical) shape. In some embodiments, the angle θ between the sidewall of the via 80 and the upper surface of the wiring pattern 62 is in the range of about 89 degrees to about 91 degrees. In some embodiments, the area and / or shape of the upper surface of the via 80 is substantially the same as the area and / or shape of the bottom of the via 80. The area difference between the upper surface and the bottom of the via 80 is approximately 1-5% of the upper surface area. Figure 13A and Figure 13B As shown, in some embodiments, the wiring pattern 62 below the via 80 may be defined or limited by the largest portion of the via 80.

[0060] Figure 13C and Figure 13D Detailed views of a via 80 and wiring pattern 62 according to embodiments of the present disclosure are shown. In some embodiments, the via 80 has an inverted tapering columnar shape. In some embodiments, the angle θ between the sidewall of the via 80 and the upper surface of the wiring pattern 62 is in the range of about 80 degrees to about 89 degrees, and in other embodiments, the angle is in the range of about 82 degrees to about 87 degrees. In some embodiments, the area of ​​the upper surface of the via 80 is greater than the area of ​​the bottom of the via 80. The area difference between the upper surface and the bottom of the via 80 is approximately 1-20% of the upper surface area. Figure 13C and Figure 13D As shown, in some embodiments, the wiring pattern 62 below the via 80 may be defined or limited by the largest portion (upper portion) of the via 80.

[0061] Figure 13E and Figure 13F Detailed views of a via 80 and wiring pattern 62 according to embodiments of the present disclosure are shown. In some embodiments, the via 80 has a tapered cylindrical shape. In some embodiments, the angle θ between the sidewall of the via 80 and the upper surface of the wiring pattern 62 is in the range of about 91 degrees to about 100 degrees, and in other embodiments, the angle is in the range of about 93 degrees to about 97 degrees. In some embodiments, the area of ​​the upper surface of the via 80 is smaller than the area of ​​the bottom of the via 80. The area difference between the upper surface and the bottom of the via 80 is approximately 1-20% of the upper surface area. Figure 13E and Figure 13F As shown, in some embodiments, the wiring pattern 62 below the via 80 may be defined or limited by the largest portion (bottom portion) of the via 80.

[0062] The different shapes of via 80 depend on the etching results of forming holes in the first ILD layer during the single damascene process (as per [reference]). Figure 3A and Figure 3B (As explained).

[0063] Figures 14A to 14D A plan view (top view) of the via 80 and hard mask pattern 92 according to an embodiment of the present disclosure is shown, and Figures 15A to 15D A plan view (top view) of a corresponding wiring pattern 62 according to an embodiment of the present disclosure is shown. Figures 14A to 15D As shown, wiring pattern 62 has the same shape in the plan view as the combination (logic and) of hard mask pattern 92 and via 80.

[0064] When using a single-damascene or dual-damascene process, a specific via package budget is required for CD and coverage error. In some embodiments, the via package budget can be estimated as EB = (D2 - D1) / 2, where D2 is the end-to-end spacing between adjacent vias 80, and D1 is the end-to-end spacing between two patterns of the hard mask pattern 92 along the X direction. In the damascene process, EB is greater than 0 nm.

[0065] In some embodiments of this disclosure, EB is zero (e.g. Figure 14A (as shown) or can be negative (such as) Figure 14B As shown). In some embodiments, the left boundary D12 of EB is the same as the right boundary D21 of EB, as shown. Figure 14B As shown. In other embodiments, due to the coverage error between via 80 and hard mask pattern 92, D12 is different from (less than or greater than) D21, as... Figure 14C As shown. Figures 14A to 14C As shown, the end-to-end spacing D1 can be expanded or larger than the end-to-end spacing D2 of the via, and the patterning of the hard mask pattern 92 in the photolithography operation (e.g., the pattern edges in the layout) can have a large tolerance.

[0066] In some embodiments, such as Figure 14D As shown, the coverage error between via 80 and hard mask pattern 92 is greater than [a certain value]. Figure 14C In some embodiments, one end of one of the hard mask patterns protrudes above one of the vias 80. In this case, the wiring pattern 62 also has the same shape as the combination (logical AND) of the hard mask pattern 92 and the via 80.

[0067] Figures 16A to 16G Various views are shown of the various stages of the sequential manufacturing operations for forming the via 80 according to embodiments of the present disclosure. It should be understood that, for additional embodiments of the method, [further details may be needed]. Figures 16A to 16G Additional operations are provided before, during, and after the processes shown, and some of these operations can be substituted or eliminated. The order of operations / processes can be interchanged.

[0068] Figures 16A to 16G The method shown is basically the same as the single-ingle inlay technique. For example... Figure 16A As shown, a second ILD layer 70 is formed over the first conductive layer 60. Then, in some embodiments, a resist layer (e.g., photoresist layer 150) is formed over the second ILD layer 70, such as... Figure 16B As shown, photolithography is then used to pattern the resist layer into a resist pattern 152 with holes corresponding to the vias 80, as shown. Figure 16C As shown. Then, the second ILD layer 70 is patterned by using plasma etching to form holes in the second ILD layer 70, as... Figure 16D As shown. Then, remove the resist pattern 152, as... Figure 16E As shown. Then, one or more conductive layers 80L are formed in the holes (filling process) and on the upper surface of the second ILD layer 70, as shown. Figure 16F As shown, one or more planarization operations (e.g., CMP process) are performed to remove excess portions of the conductive layer, thereby forming via 80, as... Figure 16G As shown. In some embodiments, the via 80S and the first conductive layer 60 are made of the same material, such as... Figure 16H As shown, there is no obvious interface between the via 80S and the first conductive layer 60.

[0069] Figures 17A to 17D Various views are shown of the various stages of the sequential manufacturing operations for forming the via 80 according to embodiments of the present disclosure. It should be understood that, for additional embodiments of the method, [further details may be needed]. Figures 17A to 17D Additional operations are provided before, during, and after the processes shown, and some of these operations can be substituted or eliminated. The order of operations / processes can be interchanged.

[0070] In some embodiments, the via 80 is formed as follows Figure 17A As shown (and) Figure 16G (Same) After that, the upper part of the via 80 is partially recessed as follows: Figure 17BAs shown. In some embodiments, the recess amount (depth) is in the range of about 1 nm to about 20 nm. In other embodiments, the recess amount is about 5% to 30% of the total thickness of the via 80. Then, one or more conductive layers 160L are formed on the upper surface of the recessed via 80R and the second ILD layer 70, as shown. Figure 17C As shown, one or more planarization operations (e.g., CMP process) are performed to remove excess portions of the conductive layer, thereby forming the cap conductive layer 160 (e.g. Figure 17D As shown). In some embodiments, such as Figure 17E As shown, via 80S and the first conductive layer 60 are made of the same material, and there is no obvious interface between via 80S and the first conductive layer 60. When the thickness of the cap conductive layer 160 is too large, the resistance of the via increases, while when the thickness of the cap conductive layer 160 is too small, the functionality of the cap conductive layer 160 (e.g., etch stop) may be reduced. In some embodiments, the cap conductive layer 160 comprises one or more metal or metal nitride layers, such as Ta, Ti, TaN, or TiN layers. In some embodiments, TiN is used. In some embodiments, the conductive layer 160L is formed by CVD, PVD, electroplating, or ALD.

[0071] Applicable to: Figures 16E to 16H and / or Figures 17A to 17E The operation of the explanation, in order to... Figure 12C As shown, after removing the dummy via 80D, a via 80 is formed in the hole 81.

[0072] Figure 18A and Figure 18B The following diagram illustrates the formation and... according to embodiments of the present disclosure. Figure 10A A cross-sectional view of the wiring structure following the upper wiring layer, similar to Figure 10B, wherein a cap conductive layer 160 is present above the via 80R. In some embodiments, such as Figure 18A As shown, the upper wiring pattern 112 is aligned with the via 80R having a capped conductive layer 160, so the upper wiring pattern 112 completely covers the capped conductive layer 160. In other embodiments, the upper wiring pattern 112 is not aligned with the via 80R having the capped conductive layer 160, and a portion of the capped conductive layer 160 is exposed from the wiring pattern 112. In this case, when the material of the capped conductive layer 160 is the same as the material used to form the hard mask pattern for the upper wiring structure, the etching of the conductive layer for the wiring pattern 112 substantially stops at the capped conductive layer 160. Therefore, the capped conductive layer 160 serves as an etch stop or etch barrier. In some embodiments, the capped conductive layer 160 is removed after the planarization operation and before the next layer is applied to the via 80R.

[0073] In embodiments of this disclosure, a (patterned) wiring pattern is formed after vias or dummy vias disposed on the wiring pattern are formed in an interlayer dielectric layer. In this process, the wiring pattern is defined by the vias, so even if there is an overlay error between the mask pattern (hard mask pattern and / or resist pattern) and the vias, the patterned wiring pattern has a protrusion under the vias, which ensures the connection between the vias and the wiring pattern.

[0074] It should be understood that not all advantages are necessarily discussed in this document, not all embodiments or examples require a particular advantage, and other embodiments or examples may provide different advantages.

[0075] According to one aspect of this disclosure, in a method of manufacturing a semiconductor device, a first conductive layer is formed on a first interlayer dielectric (ILD) layer disposed on a substrate, a second ILD layer is formed on the first conductive layer, a via is formed in the second ILD layer to contact the upper surface of the first conductive layer, a hard mask pattern is formed on the second ILD layer, and the second ILD layer and the first conductive layer are patterned by using the hard mask pattern as an etching mask to form a patterned second ILD layer and a first wiring pattern. After the patterning, the hard mask pattern is removed, and a third ILD layer is formed between the patterned second ILD layer and the first wiring pattern. In one or more of the foregoing or following embodiments, the first conductive layer comprises one of Co, Cu, or Ru. In one or more of the foregoing or following embodiments, the via comprises one of Co, Cu, or Ru. In one or more of the foregoing or following embodiments, the first conductive layer and the via are made of different materials. In one or more of the foregoing or following embodiments, the hard mask pattern contacts the upper surface of the via. In one or more of the foregoing or following embodiments, a portion of the upper surface of the via is exposed from the hard mask pattern, and the via also serves as an etching mask. In one or more of the foregoing or narrated embodiments, the hard mask pattern comprises TiN. In one or more of the foregoing or narrated embodiments, the first ILD layer includes a lower via, and the hard mask pattern includes a pattern aligned with the lower via. In one or more of the foregoing or narrated embodiments, the via includes a body portion and a cap layer disposed on the body portion, the cap layer being made of a different material than the body portion. In one or more of the foregoing or narrated embodiments, the hard mask pattern is made of the same material as the cap layer.

[0076] According to another aspect of this disclosure, in a method of manufacturing a semiconductor device, a first conductive layer is formed on a first interlayer dielectric (ILD) layer disposed on a substrate, a second ILD layer is formed on the first conductive layer, a dummy via is formed in the second ILD layer to contact the upper surface of the first conductive layer, a hard mask pattern is formed on the second ILD layer, and the second ILD layer and the first conductive layer are patterned using the hard mask pattern as an etching mask to form a patterned second ILD layer and a first wiring pattern. After this patterning, the hard mask pattern is removed, and a third ILD layer is formed between the patterned second ILD layer and the first wiring pattern, and the dummy via is replaced with a conductive via. In one or more of the foregoing or following embodiments, the dummy via comprises a material different from the second ILD layer and the first conductive layer. In one or more of the foregoing or following embodiments, the dummy via comprises amorphous or polysilicon. In one or more of the foregoing or following embodiments, the dummy via comprises a dielectric material. In one or more of the foregoing or following embodiments, the first conductive layer and the conductive via are made of the same material. In one or more of the foregoing or the following embodiments, a second wiring pattern is also formed over the conductive via.

[0077] According to another aspect of this disclosure, in a method of manufacturing a semiconductor device, the semiconductor device includes a lower wiring pattern, a higher wiring pattern, and vias connecting the lower wiring pattern and the higher wiring pattern. In this method, vias are formed in a dielectric layer, and after the vias are formed, a lower wiring pattern disposed below the vias is formed. In one or more of the foregoing or following embodiments, when forming the lower wiring pattern, a blanket layer of conductive material is formed before forming the dielectric layer, and the blanket layer is patterned by plasma dry etching. In one or more of the foregoing or following embodiments, the blanket layer is patterned using a hard mask pattern disposed on the dielectric layer. In one or more of the foregoing or following embodiments, the hard mask pattern is formed using a damascene process.

[0078] According to another aspect of this disclosure, a semiconductor device includes a transistor disposed on a substrate and a plurality of wiring layers disposed on the transistor. One of the plurality of wiring layers includes a wiring pattern and a via connected to an upper surface of the wiring pattern, and the wiring pattern includes lateral protrusions projecting relative to the sides of the wiring pattern. In one or more of the foregoing or following embodiments, a portion of the via is disposed on the lateral protrusion. In one or more of the foregoing or following embodiments, the via and the wiring pattern are made of the same material. In one or more of the foregoing or following embodiments, the wiring pattern includes one of Co or Ru. In one or more of the foregoing or following embodiments, the via includes a body layer and a cap layer disposed on the body layer and made of a material different from the body layer. In one or more of the foregoing or following embodiments, the body layer includes at least one of Cu, Al, Ru, W, Co, Ti, or Ta, and the cap layer is made of TiN. In one or more of the foregoing or following embodiments, the via has a tapered columnar shape with a top smaller than a bottom. In one or more of the foregoing or following embodiments, the angle between the sides of the via and the upper surface of the wiring pattern is in the range of 91 degrees to 100 degrees. In one or more of the foregoing or narrated embodiments, the via has a reverse tapering columnar shape with a top larger than the bottom. In one or more of the foregoing or narrated embodiments, the angle between the side of the via and the upper surface of the wiring pattern is in the range of 80 degrees to 89 degrees.

[0079] According to another aspect of this disclosure, a semiconductor device includes a transistor disposed on a substrate and a plurality of wiring layers disposed on the transistor. One of the plurality of wiring layers includes a first wiring pattern, a second wiring pattern, a first via connected to an upper surface of the first wiring pattern, and a second via connected to an upper surface of the second wiring pattern. The first wiring pattern and the second wiring pattern extend in a first direction and are aligned with each other in the first direction. The first via is disposed at an end of the first wiring pattern, and the second via is disposed at an end of the second wiring pattern. The end-to-end spacing between the first and second vias is equal to the end-to-end spacing between the first and second wiring patterns in the first direction. In one or more of the foregoing or following embodiments, the end of the first wiring pattern is defined by the first via, and the end of the second wiring pattern is defined by the second via. In one or more of the foregoing or following embodiments, the first via and the second via are made of a material different from the first wiring pattern and the second wiring pattern. In one or more of the foregoing or following embodiments, the via includes a body layer and a cap layer disposed on the body layer and made of a material different from the body layer. In one or more of the foregoing or following embodiments, the body layer includes at least one of Cu, Al, Ru, W, Co, Ti, or Ta, and the cap layer is made of TiN.

[0080] According to another aspect of this disclosure, a semiconductor device includes a transistor disposed on a substrate and a plurality of wiring layers disposed on the transistor. The plurality of wiring layers includes an nth wiring layer and an (n+1)th wiring layer. The nth wiring layer includes a first wiring pattern and a first via connected to an upper surface of the first wiring pattern. The (n+1)th wiring layer includes a second wiring pattern and a second via connected to an upper surface of the second wiring pattern. The first wiring pattern includes a lateral protrusion projecting from a side of the first wiring pattern below the second via. In one or more of the foregoing or following embodiments, the second via is not aligned with the first wiring pattern. In one or more of the foregoing or following embodiments, the second via includes a body layer and a cap layer disposed on the body layer and made of a material different from the body layer. In one or more of the foregoing or following embodiments, the second wiring pattern is not aligned with the second via. In one or more of the foregoing or following embodiments, a portion of the upper surface of the cap layer is exposed from the second wiring pattern.

[0081] The foregoing has outlined features of several embodiments or examples to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments or examples described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made therein without departing from the spirit and scope of this disclosure.

[0082] Example 1. A method for manufacturing a semiconductor device, comprising:

[0083] A first conductive layer is formed on top of a first interlayer dielectric (ILD) layer disposed on a substrate;

[0084] A second ILD layer is formed on top of the first conductive layer;

[0085] A via is formed in the second ILD layer to contact the upper surface of the first conductive layer;

[0086] A hard mask pattern is formed on top of the second ILD layer;

[0087] The hard mask pattern is transferred to the second ILD layer and the first conductive layer to form a patterned second ILD layer and a patterned first wiring pattern.

[0088] After patterning, the hard mask pattern is removed; and

[0089] A third ILD layer is formed between the patterned second ILD layer and the patterned first wiring pattern.

[0090] Example 2. The method according to Example 1, wherein the hard mask pattern is in contact with the upper surface of the via.

[0091] Example 3. The method according to Example 2, wherein a portion of the upper surface of the via is exposed from the hard mask pattern, and the via also serves as an etching mask.

[0092] Example 4. The method according to Example 1, wherein the first conductive layer comprises one of Co, Cu or Ru.

[0093] Example 5. The method according to Example 1, wherein the via comprises one of Co, Cu or Ru.

[0094] Example 6. The method according to Example 1, wherein the first conductive layer and the via are made of different materials.

[0095] Example 7. The method according to Example 1, wherein the hard mask pattern comprises TiN.

[0096] Example 8. According to the method described in Example 1, wherein:

[0097] The first ILD layer includes a lower via, and

[0098] The hard mask pattern includes a pattern aligned with the underlying via.

[0099] Example 9. The method according to Example 1, wherein the via includes a body portion and a cap layer disposed on the body portion, the cap layer being made of a different material from the body portion.

[0100] Example 10. The method according to Example 9, wherein the hard mask pattern is made of the same material as the cap layer.

[0101] Example 11. A method of manufacturing a semiconductor device, comprising:

[0102] A first conductive layer is formed on top of a first interlayer dielectric (ILD) layer disposed on a substrate;

[0103] A second ILD layer is formed on top of the first conductive layer;

[0104] A dummy via is formed in the second ILD layer to contact the upper surface of the first conductive layer;

[0105] A hard mask pattern is formed on top of the second ILD layer;

[0106] The second ILD layer and the first conductive layer are patterned by using the hard mask pattern as an etching mask, thereby forming a patterned second ILD layer and a first wiring pattern;

[0107] After patterning, the hard mask pattern is removed;

[0108] A third ILD layer is formed between the patterned second ILD layer and the first wiring pattern; and

[0109] Replace the dummy via with a conductive via.

[0110] Example 12. The method according to Example 11, wherein the dummy via comprises a material different from the second ILD layer and the first conductive layer.

[0111] Example 13. The method according to Example 11, wherein the dummy via comprises amorphous silicon or polycrystalline silicon.

[0112] Example 14. The method according to Example 11, wherein the dummy via comprises a dielectric material.

[0113] Example 15. The method according to Example 11, wherein the first conductive layer and the conductive via are made of the same material.

[0114] Example 16. The method according to Example 11 further includes forming a second wiring pattern over the conductive via.

[0115] Example 17. A semiconductor device comprising:

[0116] Transistors disposed on a substrate; and

[0117] Multiple wiring layers are disposed above the transistor, wherein:

[0118] One of the plurality of wiring layers includes a wiring pattern and a via connected to the upper surface of the wiring pattern, and

[0119] The wiring pattern includes lateral protrusions that project relative to the sides of the wiring pattern.

[0120] Example 18. The semiconductor device according to Example 17, wherein a portion of the via is disposed on the lateral protrusion.

[0121] Example 19. The semiconductor device according to Example 17, wherein the vias and the wiring pattern are made of the same material.

[0122] Example 20. The semiconductor device according to Example 17, wherein the wiring pattern includes one of Co or Ru.

Claims

1. A method for manufacturing a semiconductor device, comprising: A first conductive layer is formed on top of a first interlayer dielectric (ILD) layer disposed on a substrate; A second ILD layer is formed on top of the first conductive layer; A via is formed in the second ILD layer to contact the upper surface of the first conductive layer; A hard mask pattern is formed on top of the second ILD layer; The hard mask pattern is transferred to the second ILD layer and the first conductive layer to form a patterned second ILD layer and a patterned first wiring pattern. After patterning, the hard mask pattern is removed; as well as A third ILD layer is formed between the patterned second ILD layer and the patterned first wiring pattern, wherein: The first ILD layer includes a lower via, and The hard mask pattern includes a pattern aligned with the underlying via.

2. The method according to claim 1, wherein, The hard mask pattern is in contact with the upper surface of the via.

3. The method according to claim 2, wherein, A portion of the upper surface of the via is exposed from the hard mask pattern, and the via also serves as an etching mask.

4. The method according to claim 1, wherein, The first conductive layer includes one of Co, Cu or Ru.

5. The method according to claim 1, wherein, The via includes one of Co, Cu or Ru.

6. The method according to claim 1, wherein, The first conductive layer and the via are made of different materials.

7. The method according to claim 1, wherein, The hard mask pattern includes TiN.

8. The method according to claim 1, wherein, The via includes a main body portion and a cap layer disposed on the main body portion, the cap layer being made of a different material than the main body portion.

9. The method according to claim 8, wherein, The hard mask pattern is made of the same material as the cap layer.

10. A method for manufacturing a semiconductor device, comprising: A first conductive layer is formed on top of a first interlayer dielectric (ILD) layer disposed on a substrate; A second ILD layer is formed on top of the first conductive layer; A dummy via is formed in the second ILD layer to contact the upper surface of the first conductive layer; A hard mask pattern is formed on top of the second ILD layer; The second ILD layer and the first conductive layer are patterned by using the hard mask pattern as an etching mask, thereby forming a patterned second ILD layer and a first wiring pattern; After patterning, the hard mask pattern is removed; A third ILD layer is formed between the patterned second ILD layer and the first wiring pattern; as well as Replace the dummy via with a conductive via, wherein: The first ILD layer includes a lower via, and The hard mask pattern includes a pattern aligned with the underlying via.

11. The method according to claim 10, wherein, The dummy via comprises a material different from the second ILD layer and the first conductive layer.

12. The method according to claim 10, wherein, The dummy vias include amorphous silicon or polycrystalline silicon.

13. The method according to claim 10, wherein, The dummy via includes a dielectric material.

14. The method of claim 10, wherein, The first conductive layer and the conductive via are made of the same material.

15. The method of claim 10, further comprising forming a second wiring pattern on the conductive via.

16. A semiconductor device, comprising: Transistors disposed on a substrate; as well as Multiple wiring layers are disposed above the transistor, wherein: One of the plurality of wiring layers includes a wiring pattern and a via connected to the upper surface of the wiring pattern, and The wiring pattern includes a lateral protrusion that projects relative to the side of the wiring pattern, wherein a portion of the via is disposed on the lateral protrusion.

17. The semiconductor device according to claim 16, wherein, The vias and the wiring pattern are made of the same material.

18. The semiconductor device according to claim 16, wherein, The wiring pattern includes either Co or Ru.

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