Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the semiconductor structure comprising: a first transistor structure comprising a substrate, a first channel layer on the substrate, a first gate dielectric layer covering the first channel layer, a first gate structure covering the first gate dielectric layer, and first source / drain doped layers on both sides of the first gate structure; a bonding layer on a bonding surface of the first transistor structure; a second transistor structure on the bonding layer, comprising a second channel layer, a second gate dielectric layer covering the second channel layer, a second gate structure covering the second gate dielectric layer, and second source / drain doped layers on both sides of the second gate structure; and a conductive plug penetrating through the second gate dielectric layer at the bottom of the second gate structure and the bonding layer, electrically connecting the second gate structure and the first gate structure. The present application realizes the electrical connection of the first gate structure and the second gate structure through the conductive plug without physical contact, thereby facilitating the obtaining of an inverter based on the CFET structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink. To adapt to the shrinking feature size, the channel length of MOSFETs is also continuously shortening. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens, thus reducing the gate's control over the channel and making it increasingly difficult to pinch off the channel with the gate voltage. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.

[0003] Therefore, in order to better adapt to the reduction in feature size, semiconductor processes have gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher efficiency.

[0004] Among them, the vertically stacked complementary field-effect transistor (CFET) is a revolutionary three-dimensional transistor. In the CFET structure, PMOS transistors and NMOS transistors stacked vertically to each other form complementary devices, which can save area, increase transistor integration density, and thus bring benefits in power consumption and cost performance. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which makes it easy to form an inverter based on a CFET structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a first transistor structure, including a substrate, a first channel layer on the substrate, a first gate dielectric layer conformally covering the first channel layer, a first gate structure covering the first gate dielectric layer, and first source / drain doped layers on the substrate on both sides of the first gate structure, wherein the first source / drain doped layers are in contact with the end of the first channel layer located below the first gate structure, and the first transistor structure has a bonding surface located on one side of the first gate structure; a bonding layer located on the bonding surface of the first transistor structure, wherein the bonding layer is made of a dielectric material; a second transistor structure located on the bonding layer, the second transistor structure including a second channel layer, a second gate dielectric layer conformally covering the second channel layer, a second gate structure covering the second gate dielectric layer, and second source / drain doped layers on the bonding layers on both sides of the second gate structure, wherein the second source / drain doped layers are in contact with the end of the second channel layer located below the second gate structure; and a conductive plug penetrating the second gate dielectric layer and the bonding layer at the bottom of the second gate structure, wherein the conductive plug is electrically connected to the second gate structure and the first gate structure.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: forming a first transistor structure, the first transistor structure including a first substrate, a first channel layer on the first substrate, a first gate dielectric layer conformally covering the first channel layer, a first gate structure covering the first gate dielectric layer, and a first source / drain doped layer on a first substrate on both sides of the first gate structure, the first source / drain doped layer being in contact with the end of the first channel layer located below the first gate structure, the first transistor structure having a bonding surface located on one side of the first gate structure; bonding a second substrate to the bonding surface using a bonding layer, the bonding layer being made of a dielectric material; patterning the second substrate to form a second channel layer; forming a dummy gate structure on the bonding layer, the dummy gate structure spanning the second channel layer and covering a portion of the top and a portion of the sidewalls of the second channel layer; forming a second source / drain doped layer in the second channel layer on both sides of the dummy gate structure, the second source / drain doped layer being in contact with the end of the first channel layer located below the dummy gate structure. The lower end of the second channel layer is in contact with the first gate structure; after forming the second source / drain doped layer, a top interlayer dielectric layer is formed on the bonding layer on the side of the dummy gate structure, the top interlayer dielectric layer covers the sidewall of the dummy gate structure and exposes the top of the dummy gate structure; the dummy gate structure is removed, and a gate opening is formed in the top interlayer dielectric layer; a second gate dielectric layer is formed conformally covering the bottom and sidewall of the gate opening, the second gate dielectric layer also conformally covering the second channel layer in the gate opening; an interconnection opening is formed in the gate opening, penetrating the bottom of the second gate dielectric layer and the bonding layer, the interconnection opening exposes the first gate structure, and the interconnection opening is connected to the gate opening; a conductive plug is formed in the interconnection opening, and a second gate structure is formed in the gate opening, the second gate structure and the first gate structure are electrically connected through the conductive plug, wherein the second gate structure, the second gate dielectric layer, the second source / drain doped layer and the second channel layer are used to constitute a second transistor structure.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] In the semiconductor structure provided by this invention, the first transistor structure and the second transistor structure are bonded together through a bonding layer. Therefore, during the manufacturing process of the semiconductor structure, the fabrication process of the second transistor structure can be completed independently after the fabrication process of the first transistor structure is completed, reducing the process difficulty of fabricating the second transistor structure and the impact on the first transistor structure. In addition, the semiconductor structure also includes a conductive plug located at the bottom of the second gate structure. The conductive plug penetrates the bonding layer at the bottom of the second gate structure and electrically connects the second gate structure and the first gate structure. Therefore, even when the first gate structure and the second gate structure are not in physical contact, the electrical connection between the first gate structure and the second gate structure is achieved by the conductive plug disposed between the first transistor structure and the second transistor structure, thereby making it easy to obtain an inverter based on the CFET structure and correspondingly reducing the process complexity of forming the semiconductor structure.

[0010] In the semiconductor structure formation method provided in this embodiment of the invention, after forming a first transistor structure, a second substrate is bonded to the bonding surface of the first transistor structure using a bonding layer. The second substrate is patterned to form a second channel layer. After removing the dummy gate structure to form a gate opening, a second gate dielectric layer is formed conformally covering the bottom and sidewalls of the gate opening. Subsequently, an interconnection opening is formed in the gate opening, penetrating the bottom of the gate opening through the second gate dielectric layer and the bonding layer. The interconnection opening exposes the first gate structure and is connected to the gate opening. A conductive plug is formed in the interconnection opening, and a second gate structure is formed in the gate opening. The second gate structure and the first gate structure are electrically connected through the conductive plug. In this embodiment of the invention, the second substrate is bonded to the bonding surface of the first transistor structure using a bonding method. In other words, after completing the fabrication process of the first transistor structure, the fabrication process of the second transistor structure is completed independently, which reduces the process difficulty of fabricating the second transistor structure and the impact on the first transistor structure. In addition, by forming an interconnection opening at the bottom of the gate opening to expose the first gate structure before forming the second gate structure, the formation of the conductive plug will not be blocked by the second gate structure. Moreover, after the second gate structure is formed in the gate opening, the conductive plug is located between the first transistor structure and the second transistor structure. Electrical connection between the first gate structure and the second gate structure is achieved without physical contact between them, thereby facilitating the formation of an inverter based on the CFET structure and reducing the process complexity of forming the semiconductor structure. Attached Figure Description

[0011] Figure 1 This is a 3D diagram of a semiconductor structure;

[0012] Figure 2 This is a 3D diagram of another semiconductor structure;

[0013] Figure 3 and Figure 4 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0014] Figures 5 to 18 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0015] As the background technology shows, the CFET device structure includes PMOS transistors and NMOS transistors stacked perpendicularly to each other. However, the fabrication process for inverters based on the CFET structure is currently quite challenging.

[0016] This paper analyzes the reasons why the fabrication process of CFET-based inverters is currently quite difficult, using a semiconductor structure as an example.

[0017] refer to Figure 1 The diagram shows a three-dimensional representation of a semiconductor structure.

[0018] The semiconductor structure includes: a first transistor structure 40, including a substrate 41, a first channel layer 42 located on the substrate 41, and a first gate structure 43 covering the first channel layer 41; and a second transistor structure 50 located on the first transistor structure 40, the second transistor structure 50 including a second channel layer (not shown) suspended above the first transistor structure 40, and a second gate structure 51 covering the second channel layer, the second gate structure 51 being located on top of the first gate structure 43, and the bottom of the second gate structure 51 being in contact with the top of the first gate structure 43.

[0019] The semiconductor structure is a monolithic CFET structure. Specifically, the first transistor structure 40 and the second transistor structure 50 are both fabricated on the same silicon wafer. Furthermore, the bottom of the second gate structure 51 is in contact with the top of the first gate structure 43, and the second gate structure 51 and the first gate structure 43 are electrically connected, thereby forming an inverter. However, this easily leads to a more complex fabrication process for the monolithic CFET, and since the bottom of the second gate structure 51 is in contact with the top of the first gate structure 43, the fabrication process of the second transistor structure 50 can also affect the first transistor structure 40. For example, the formation of the second gate structure 51 can easily affect the first gate structure 43.

[0020] Figure 2 This is a 3D diagram of another semiconductor structure.

[0021] The semiconductor structure includes: a first transistor structure 10, including a substrate 11, a first channel layer 12 on the substrate 11, and a first gate structure 13 spanning the first channel layer 12, the first transistor structure 10 having a bonding surface (not shown) on one side of the first gate structure 13; a bonding layer 30 located on the bonding surface; and a second transistor structure 20 located on the bonding layer 30, the second transistor structure 20 including a second channel layer 22 and a second gate structure 23 covering the second channel layer 22.

[0022] The semiconductor structure is a sequential CFET structure. Specifically, a first transistor structure 10 and a second transistor structure 20 are fabricated using separate silicon wafers, and the first transistor structure 10 and the second transistor structure 20 are bonded together. In this semiconductor structure, a bonding layer 30 separates the second transistor structure 20 and the first transistor structure 10. The second gate structure 23 and the first gate structure 13 are not in contact. When an inverter needs to be formed, an additional interconnect structure is usually required to bring out the electrical properties of the first gate structure 13, thereby achieving electrical connection between the first gate structure 13 and the second gate structure 23 through interconnect lines. However, since the second gate structure 23 completely blocks the first gate structure 13, it is difficult to bring out the electrical properties of the first gate structure 13.

[0023] Therefore, the process of forming inverters based on CFET structures is currently quite challenging.

[0024] To address the aforementioned technical problems, the semiconductor structure provided in this embodiment of the invention involves bonding the first transistor structure and the second transistor structure together via a bonding layer. Therefore, during the manufacturing process of the semiconductor structure, the fabrication process of the second transistor structure can be completed independently after the fabrication process of the first transistor structure is finished. This reduces the process difficulty of fabricating the second transistor structure and the impact on the first transistor structure. Furthermore, the semiconductor structure includes a conductive plug located at the bottom of the second gate structure. The conductive plug penetrates the bonding layer at the bottom of the second gate structure and electrically connects the second gate structure and the first gate structure. Therefore, even when the first gate structure and the second gate structure are not physically in contact, the electrical connection between the first gate structure and the second gate structure is achieved through the conductive plug disposed between them. This facilitates the acquisition of an inverter based on a CFET structure, thereby reducing the process complexity of forming the semiconductor structure.

[0025] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0026] Figure 3 and Figure 4 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. Figure 3 It is a cross-sectional view along the first gate structure or the extension direction of the first gate structure. Figure 4 It is a cross-sectional view in a direction perpendicular to the first gate structure or the extension direction of the first gate structure.

[0027] The semiconductor structure includes: a first transistor structure 400, comprising a substrate 410, a first channel layer 470 on the substrate 410, a first gate dielectric layer 430 conformally covering the first channel layer 470, a first gate structure 460 covering the first gate dielectric layer 430, and a first source / drain doped layer 403 on the substrate 410 on both sides of the first gate structure 460 (e.g., ...). Figure 4 (As shown), the first source / drain doped layer 403 is in contact with the end of the first channel layer 470 located below the first gate structure 460. The first transistor structure 400 has a bonding surface 401 located on one side of the first gate structure 460; a bonding layer 500 is located on the bonding surface 401, and the material of the bonding layer 500 is a dielectric material; a second transistor structure 600 is located on the bonding layer 500, and the second transistor structure 600 includes a second channel layer 520, a second gate dielectric layer 610 conformally covering the second channel layer 520, a second gate structure 690 covering the second gate dielectric layer 610, and a second source / drain doped layer 601 located on the bonding layer 500 on both sides of the second gate structure 690 (as shown). Figure 4 As shown, the second source / drain doped layer 601 is in contact with the end of the second channel layer 520 located below the second gate structure 690; the conductive plug 660 penetrates the second gate dielectric layer 610 and the bonding layer 500 at the bottom of the second gate structure 690, and the conductive plug 660 is electrically connected to the second gate structure 690 and the first gate structure 460.

[0028] The first transistor structure 400 and the second transistor structure 600 are bonded together by a bonding layer 500. Therefore, during the manufacturing process of the semiconductor structure, the fabrication process of the second transistor structure 600 can be completed independently after the fabrication process of the first transistor structure 400 is completed, reducing the process difficulty of fabricating the second transistor structure 600 and the impact of the fabrication process of the second transistor structure 600 on the first transistor structure 400. In addition, the semiconductor structure also includes a conductive plug 660 located at the bottom of the second gate structure 690. The conductive plug 660 penetrates the second gate dielectric layer 610 and the bonding layer 500 at the bottom of the second gate structure 690. The conductive plug 660 electrically connects the second gate structure 690 and the first gate structure 460. Therefore, even when the first gate structure 460 and the second gate structure 690 are not in physical contact, the electrical connection between the first gate structure 460 and the second gate structure 690 is achieved by the conductive plug 660 disposed between the first transistor structure 400 and the second transistor structure 600, thereby facilitating the acquisition of an inverter based on a CFET structure and correspondingly reducing the process complexity of forming the semiconductor structure.

[0029] The semiconductor structure is a CFET structure, and the first transistor structure 400 includes a first transistor, which is the bottom transistor in the CFET structure. The first transistor includes a first channel layer 470, a first gate dielectric layer 430, a first gate structure 460, and a first source / drain doped layer 403, thereby enabling the normal function of the first transistor.

[0030] In a CFET structure, PMOS and NMOS transistors stacked vertically to each other constitute complementary devices. Therefore, depending on the channel conductivity type of the first transistor in the first transistor structure 400, the first transistor can be an NMOS transistor or a PMOS transistor. As an example, the first transistor in the first transistor structure 400 is an NMOS transistor. Depending on the structure type of the first transistor structure 400, the first transistor structure 400 includes a FinFET or a Gate-All-Around (GAA) transistor. Specifically, the GAA transistor can be a Horizontal Nanosheet transistor. This embodiment uses a GAA transistor as an example for the first transistor.

[0031] The substrate 410 serves as a process platform for forming the semiconductor structure. Depending on the structure type of the first transistor, the substrate 410 may be a substrate, or it may include a substrate and fins protruding from the substrate. As an example, if the first transistor is a GAA transistor, then when the substrate 410 includes a substrate and fins protruding from the substrate, the substrate 410 also includes an isolation layer (not shown) located on the substrate, which covers the sidewalls of the fins. The isolation layer may be a shallow trench isolation (STI) structure.

[0032] In this embodiment, the substrate material is silicon. In other embodiments, the substrate material may also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, and the substrate may also be other types of substrates such as silicon-on-insulator substrate or germanium-on-insulator substrate.

[0033] The first channel layer 470 is used to provide the channel for the first transistor.

[0034] In this embodiment, taking a GAA transistor as an example, the first channel layer 470 is located on and spaced apart from the substrate 410. The first channel layer 470 includes one or more spaced first sub-channel layers 476. It should be noted that this embodiment only illustrates one first sub-channel layer 476, but the number of first sub-channel layers 476 is not limited to one. In other embodiments, when the first transistor is a FinFET, the first channel layer is a first fin protruding from the substrate.

[0035] The material of the first channel layer 470 includes silicon, silicon germanide, germanium, or a group III-V semiconductor material. The material of the first channel layer 470 is determined according to the channel conductivity type and performance requirements of the first transistor. As an example, the material of the first channel layer 470 is silicon.

[0036] The first gate structure 460 is a device gate structure used to control the opening or closing of the channel of the first transistor. In this embodiment, the first gate structure 460 surrounds the first gate dielectric layer 430 covering the first channel layer 470. In other embodiments, when the first channel layer is a first fin protruding from the substrate, the first gate structure correspondingly spans the first fin and covers a portion of the top and sidewalls of the first fin with the first gate dielectric layer.

[0037] In this embodiment, the first gate structure 460 is a first metal gate structure. The material of the first metal gate structure includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. As an example, the first metal gate structure includes a first work function layer 440 and a first gate electrode layer 450 covering the first work function layer 440.

[0038] The first work function layer 440 is used to adjust the threshold voltage of the first transistor. When the first transistor is a PMOS transistor, the first work function layer 440 is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN; when the first transistor is an NMOS transistor, the first work function layer 440 is an N-type work function layer, and the material of the N-type work function layer includes one or two of TiAl and TiAlC.

[0039] The first gate electrode layer 450 is used to electrically expose the first metal gate structure. The material of the first gate electrode layer 450 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. As an example, the material of the first gate electrode layer 450 is W.

[0040] In this embodiment, the first gate dielectric layer 430 is located between the first gate structure 460 and the first channel layer 470. The first gate dielectric layer 430 is used to isolate the first gate structure 460 and the first channel layer 470.

[0041] The material of the first gate dielectric layer 430 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the first gate dielectric layer 430 includes a first gate oxide layer and a first high-k gate dielectric layer covering the first gate oxide layer.

[0042] As an example, the material of the first gate oxide layer is silicon oxide.

[0043] In this embodiment, the material of the first high-k gate dielectric layer is a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the first high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the first high-k gate dielectric layer is HfO2.

[0044] It should be noted that the first gate dielectric layer 430 and the first gate structure 460 are formed by a process of forming a high k last metal gate last after forming a high k last gate dielectric layer. Therefore, the first gate dielectric layer 430 is also located between the bottom of the first gate structure 460 and the substrate 110, and extends to cover the sidewall of the first gate structure 460.

[0045] It should also be noted that, in other embodiments, depending on process requirements, the first gate structure may also be other types of device gate structures such as polysilicon gate structures.

[0046] The first source / drain doped layer 403 is used as the source or drain of the first transistor. The conductivity type of the doped ions in the first source / drain doped layer 403 is the same as the channel conductivity type of the first transistor. That is, when the first transistor is an NMOS transistor, the conductivity type of the doped ions in the first source / drain doped layer 403 is N-type, and N-type ions include one or more of As, P, and Sb; when the first transistor is a PMOS transistor, the conductivity type of the doped ions in the first source / drain doped layer 403 is P-type, and P-type ions include one or more of B, Ga, and In. A detailed description of the first source / drain doped layer 403 is omitted here.

[0047] In this embodiment, the first transistor structure 400 further includes a first gate sidewall 405, which covers the sidewall of the first gate structure 460. Specifically, the first gate sidewall 405 covers the first gate dielectric layer 430 located on the sidewall of the first gate structure 460.

[0048] The first gate sidewall 405 is used to protect the sidewalls of the first gate structure 460 and the first gate dielectric layer 430, and also to define the position of the first source / drain doped layer 403.

[0049] The first gate sidewall 405 can be a single-layer structure or a multilayer structure, and the material of the first gate sidewall 405 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the first gate sidewall 405 is a single-layer structure, and the material of the first gate sidewall 405 is silicon nitride.

[0050] like Figure 4 As shown, it should be noted that, taking the first transistor as a GAA transistor as an example, the first transistor structure 400 may further include: a first inner wall (not shown), located between adjacent first sub-channel layers 476 along the normal direction of the surface of the substrate 410, or located between the first sub-channel layer 476 and the substrate 410, and along a direction perpendicular to the extension direction of the first gate structure 460, the first inner wall is located between the sidewall of the first gate dielectric layer 430 and the first source / drain doped layer 403.

[0051] The first inner wall serves to isolate the first gate structure 460 and the first source / drain doped layer 403, thereby reducing the parasitic capacitance between the first gate structure 460 and the first source / drain doped layer 403.

[0052] The material of the first inner sidewall is an insulating material, which includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the first inner sidewall is silicon nitride.

[0053] In this embodiment, the first transistor structure 400 further includes a bottom interlayer dielectric layer 420, which is located on the substrate 410 on the side of the first gate structure 460 and covers the sidewall of the first gate structure 460.

[0054] The bottom interlayer dielectric layer 420 is used to isolate adjacent transistors in the first transistor structure 400. The bottom interlayer dielectric layer 420 is made of an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the bottom interlayer dielectric layer 420 is made of silicon oxide. Correspondingly, the first gate dielectric layer 430 is located between the bottom of the first gate structure 460 and the substrate 410, and between the sidewall of the first gate structure 460 and the bottom interlayer dielectric layer 420.

[0055] In this embodiment, the first transistor structure 400 has a bonding surface 401 located on one side of the first gate structure 460. The bonding surface 401 is the front side of the first transistor structure 400. During the fabrication of the semiconductor structure, the bonding surface 401 is used as a process platform to fabricate the second transistor structure 600 above the bonding surface 401.

[0056] The bonding layer 500 is located on the bonding surface 401, and the material of the bonding layer 500 is a dielectric material. During the fabrication of the second transistor structure 600, the substrate required to form the second transistor structure 600 is bonded to the bonding surface 401 through the bonding layer 500.

[0057] The bonding layer 500 enhances the bonding strength between the first transistor structure 400 and the second transistor structure 600, thereby improving the reliability of the semiconductor structure. Furthermore, the bonding layer 500 is made of a dielectric material, which provides electrical isolation between the second transistor structure 600 and the first transistor structure 400, and makes the bonding layer 500 compatible with semiconductor processes. In addition, the bonding layer 500 also protects the first transistor structure 400 during the fabrication of the second transistor structure 600.

[0058] The bonding layer 500 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, and carbon-doped silicon oxide. In this embodiment, the bonding layer 500 is made of silicon oxide. By using silicon oxide, bonding can be achieved using fusion bonding, which is beneficial for improving bonding efficiency and bonding strength; moreover, it is also beneficial for further improving the electrical isolation effect between the second transistor structure 600 and the first transistor structure 400; in addition, by using silicon oxide, the bonding temperature is lower, thereby reducing the impact on the performance of the first transistor in the first transistor structure 400. It should be noted that the bonding layer 500 is located on the bonding surface 401, and the bonding layer 500 covers not only the top of the first gate structure 460, but also the top of the bottom interlayer dielectric layer 420.

[0059] The second transistor structure 600 is located on the bonding layer 500 and includes a second transistor, which is the top transistor in the CFET structure. The second transistor includes a second channel layer 520, a second gate dielectric layer 610, a second gate structure 690, and a second source / drain doped layer 601, thereby enabling the normal function of the second transistor.

[0060] Therefore, the second transistor in the second transistor structure 600 can be an NMOS transistor or a PMOS transistor, and the channel conductivity type of the second transistor is different from that of the first transistor.

[0061] In this embodiment, the first transistor is an NMOS transistor; therefore, the second transistor is a PMOS transistor. In other embodiments, when the first transistor is a PMOS transistor, the second transistor is correspondingly an NMOS transistor.

[0062] Depending on the structural type of the second transistor structure 600, the second transistor structure 600 includes a fin field-effect transistor or a GAA transistor. Specifically, the GAA transistor can be a horizontal nanosheet transistor.

[0063] The second channel layer 520 is used to provide a channel for the second transistor. In this embodiment, taking a GAA transistor as an example, the second channel layer 520 is located on the bonding layer 500 and spaced apart from the bonding layer 500. The second channel layer 520 includes one or more spaced second sub-channel layers 526.

[0064] It should be noted that, Figure 3 Only one second sub-channel layer 526 is illustrated, but the number of second sub-channel layers 526 is not limited to one. In other embodiments, when the second transistor is a FinFET, the second channel layer is a second fin protruding from the bonding layer.

[0065] It should be noted that, in this embodiment, during the fabrication of the second transistor structure 600, the substrate bonded to the bonding surface 401 is directly patterned as the second channel layer 520. Therefore, the second transistor structure 600 does not contain an additional substrate (e.g., a substrate). Correspondingly, when the second channel layer is a second fin protruding from the bonding layer, the second fin is in contact with the bonding layer.

[0066] The material of the second channel layer 520 includes silicon, silicon germanide, germanium, or group III-V semiconductor materials. The material of the second channel layer 520 is determined according to the channel conductivity type and performance requirements of the second transistor. As an example, the material of the second channel layer 520 is silicon.

[0067] The second gate structure 690 is a device gate structure used to control the opening or closing of the channel of the second transistor. In this embodiment, the second gate structure 690 surrounds the second gate dielectric layer 610 covering the second channel layer 520. In other embodiments, when the second channel layer is a second fin protruding from the bonding layer, the corresponding second gate structure spans the second fin and covers a portion of the top and sidewalls of the second fin with the second gate dielectric layer.

[0068] In this embodiment, the second gate structure 690 is a second metal gate structure, and the material of the second metal gate structure includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. Specifically, the second gate structure 690 includes a second work function layer 670 and a second gate electrode layer 680 covering the second work function layer 670. For a detailed description of the second work function layer 670 and the second gate electrode layer 680 and their materials, please refer to the foregoing descriptions of the first work function layer 440 and the first gate electrode layer 450, respectively, which will not be repeated here.

[0069] In this embodiment, the second gate dielectric layer 610 is located between the second gate structure 690 and the second channel layer 520, and is also located between the second gate structure 690 and the bonding layer 500.

[0070] The second gate dielectric layer 610 is used to isolate the second gate structure 690 and the second channel layer 520. The material of the second gate dielectric layer 610 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0071] As an example, the second gate dielectric layer 610 includes a second gate oxide layer and a second high-k gate dielectric layer covering the second gate oxide layer. For a detailed description of the second gate dielectric layer 610, please refer to the foregoing description of the first gate dielectric layer 430, which will not be repeated here.

[0072] In this embodiment, the second transistor structure 600 does not contain an additional substrate (e.g., a substrate), therefore, the second gate dielectric layer 610 is in contact with the top of the bonding layer 500.

[0073] It should be noted that the second gate dielectric layer 610 and the second gate structure 690 are formed by a process of forming a high-k gate dielectric layer and then forming a gate electrode layer. Therefore, the second gate dielectric layer 610 also conformally covers the bottom and sidewalls of the second gate structure 690. That is, the second gate dielectric layer 610 is located between the second gate structure 690 and the bonding layer 500, and extends to cover the sidewalls of the second gate structure 690.

[0074] It should also be noted that, in other embodiments, depending on process requirements, the second gate structure may also be other types of device gate structures such as polysilicon gate structures.

[0075] The second source / drain doped layer 601 is used as the source or drain of the second transistor. The conductivity type of the doped ions in the second source / drain doped layer 601 is the same as the channel conductivity type of the second transistor. For a detailed description of the second source / drain doped layer 601, please refer to the aforementioned description of the first source / drain doped layer 403, which will not be repeated here.

[0076] In this embodiment, the second transistor structure 600 further includes a second gate sidewall 605, which covers the sidewall of the second gate structure 690. Specifically, the second gate sidewall 605 covers the second gate dielectric layer 610 located on the sidewall of the second gate structure 690.

[0077] The second gate sidewall 605 is used to protect the sidewalls of the second gate structure 690 and the second gate dielectric layer 610, and also to define the position of the second source / drain doped layer 601.

[0078] The second gate sidewall 605 can be a single-layer structure or a multilayer structure, and the material of the second gate sidewall 605 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the second gate sidewall 605 is a single-layer structure, and the material of the second gate sidewall 605 is silicon nitride.

[0079] like Figure 4 As shown, it should be noted that, taking the second transistor as a GAA transistor as an example, the second transistor structure 600 may further include: a second inner sidewall (not shown), located between adjacent second channel layers 520 along the normal direction of the surface of the substrate 410, or located between the second channel layer 520 and the bonding layer 500, and in a direction perpendicular to the extension direction of the second gate structure 690, the second inner sidewall is located between the sidewall of the second gate dielectric layer 610 and the second source / drain doped layer 601.

[0080] The second inner wall serves to isolate the second gate structure 690 and the second source / drain doped layer 601, thereby reducing the parasitic capacitance between the second gate structure 690 and the second source / drain doped layer 601.

[0081] The material of the second inner sidewall is an insulating material, which includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the second inner sidewall is silicon nitride.

[0082] In this embodiment, the second transistor structure 600 further includes a top interlayer dielectric layer 560, located on the bonding layer 500 on the side of the second gate structure 690, and the top interlayer dielectric layer 560 covers the sidewall of the second gate structure 690. The top interlayer dielectric layer 560 is used to isolate adjacent transistors in the second transistor structure.

[0083] The top interlayer dielectric layer 560 is made of an insulating material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In this embodiment, the top interlayer dielectric layer 560 is made of silicon oxide.

[0084] The conductive plug 660 is electrically connected to the second gate structure 690 and the first gate structure 460.

[0085] In this embodiment, along the stacking direction of the first transistor structure 400 and the second transistor structure 600, the two ends of the conductive plug 660 are electrically connected to the bottom of the second gate structure 690 and the top of the first gate structure 460, respectively.

[0086] Specifically, the two ends of the conductive plug 660 are in contact with the bottom of the second gate structure 690 and the top of the first gate structure 460, respectively. The sidewalls of the first gate structure 460 are typically covered by the first gate dielectric layer 430, while the top of the first gate structure 460 is exposed by the first gate dielectric layer 430. By placing the conductive plug 660 on top of the first gate structure 460, the process difficulty of forming the conductive plug 660 is reduced, and the impact on the first gate dielectric layer 430 is reduced, thereby reducing the impact on the performance of the first transistor structure 400.

[0087] In other embodiments, depending on the projection relationship between the first gate structure and the second gate structure on the substrate 410, the conductive plug may also be located on one side of the first gate structure and extend into or through a portion of the bottom dielectric layer along the stacking direction of the first transistor structure and the second transistor structure, contacting the sidewall of the first gate structure. In this case, the first gate dielectric layer covers the exposed sidewall of the first gate structure.

[0088] In this embodiment, the conductive plug 660 and the second gate structure 690 are independent structures, connected together by an electrical connection. By selecting an independent conductive plug 660, the material of the conductive plug 660 can be flexibly selected according to performance requirements.

[0089] Specifically, the conductive plug 660 is made of one or more of the following materials: W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. These materials exhibit good conductivity and high compatibility with metal gate structures.

[0090] In other embodiments, the conductive plug can also be integral with the second gate structure, and the conductive plug and the second gate structure are made of the same material. Since the second gate structure is conductive, using the second gate structure located in the bonding layer as a conductive plug still allows it to function as an electrical connection.

[0091] In this embodiment, along the stacking direction of the first transistor structure 400 and the second transistor structure 600, the conductive plug 660 also extends into a portion of the thickness of the second gate structure 690. Therefore, the second gate structure 690 not only covers the end of the conductive plug 660 but also a portion of its sidewalls, which helps to reduce the contact resistance between the second gate structure 690 and the conductive plug 660. Furthermore, since the conductive plug 660 only extends into a portion of the thickness of the second gate structure 690, its impact on the performance of the second gate structure 690 is minimal.

[0092] Figures 5 to 18 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0093] Reference Figure 5 and Figure 6 , Figure 5 This is a cross-sectional view along the extension direction of the first gate structure. Figure 6 This is a cross-sectional view perpendicular to the extension direction of the first gate structure, forming a first transistor structure 100, including a first substrate 110, a first channel layer 170 on the first substrate 110, a first gate dielectric layer 130 conformally covering the first channel layer 170, a first gate structure 160 covering the first gate dielectric layer 130, and a first source / drain doped layer 103 on the first substrate 110 on both sides of the first gate structure 160. The first source / drain doped layer 103 is in contact with the end of the first channel layer 170 located below the first gate structure 160. The first transistor structure 100 has a bonding surface 101 on one side of the first gate structure 160.

[0094] The formation method is used to form a CFET structure, wherein the first transistor structure 100 includes a first transistor, which is the bottom transistor in the CFET structure. The first transistor includes a first channel layer 170, a first gate dielectric layer 130, a first gate structure 160, and a first source / drain doped layer 103, thereby realizing the normal function of the first transistor.

[0095] The first transistor in the first transistor structure 100 can be an NMOS transistor or a PMOS transistor. As an example, the first transistor is an NMOS transistor. Depending on the structure type of the first transistor structure 100, the first transistor structure 100 includes a FinFET or a GAA transistor. Specifically, the GAA transistor can be a horizontal nanosheet transistor. This embodiment takes a GAA transistor as an example.

[0096] The first substrate 110 provides a process platform for the formation of a semiconductor structure. Depending on the structure type of the first transistor, the first substrate 110 may be a substrate, or it may include a substrate and fins protruding from the substrate. As an example, if the first transistor is a GAA transistor, then when the first substrate 110 includes a substrate and fins protruding from the substrate, the first substrate 110 also includes an isolation layer (not shown) located on the substrate, covering the sidewalls of the fins. The isolation layer may be a shallow trench isolation structure. The description of the substrate can be referred to in conjunction with the corresponding description in the foregoing embodiments, and will not be repeated here.

[0097] The first channel layer 170 is used to provide a channel for the first transistor. In this embodiment, the first channel layer 170 is located on and spaced apart from the substrate 110, and the first channel layer 170 includes one or more spaced-apart first sub-channel layers 176. It should be noted that this embodiment only illustrates one first sub-channel layer 176, but the number of first sub-channel layers 176 is not limited to one. In other embodiments, when the first transistor is a FinFET, the first channel layer is a first fin protruding from the substrate.

[0098] The material of the first channel layer 170 includes silicon, silicon germanide, germanium, or a group III-V semiconductor material. The material of the first channel layer 170 is determined according to the channel conductivity type and performance requirements of the first transistor. As an example, the material of the first channel layer 170 is silicon.

[0099] The first gate structure 160 is a device gate structure used to control the opening or closing of the channel of the first transistor. In this embodiment, the first gate structure 160 surrounds the first gate dielectric layer 130 covering the first channel layer 170. In other embodiments, when the first channel layer is a first fin protruding from the substrate, the first gate structure correspondingly spans the first fin and covers a portion of the top and sidewalls of the first fin with the first gate dielectric layer.

[0100] In this embodiment, the first gate structure 160 is a first metal gate structure. The material of the first metal gate structure includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. As an example, the first metal gate structure includes a first work function layer 140 and a first gate electrode layer 150 covering the first work function layer 140.

[0101] In this embodiment, the first gate dielectric layer 130 is located between the first gate structure 160 and the first channel layer 170. The first gate dielectric layer 130 is used to isolate the first gate structure 160 and the first channel layer 170. Specifically, the first gate dielectric layer 130 includes a first gate oxide layer and a first high-k gate dielectric layer covering the first gate oxide layer.

[0102] For a detailed description of the first gate dielectric layer 130, the first work function layer 140, and the first gate electrode layer 150, please refer to the corresponding descriptions in the foregoing embodiments. This embodiment will not repeat them here.

[0103] It should be noted that the first gate dielectric layer 130 and the first gate structure 160 are formed by a process of forming a high-k gate dielectric layer and then forming a gate electrode layer. Therefore, the first gate dielectric layer 130 also covers the bottom and sidewalls of the first gate structure 160.

[0104] It should also be noted that, in other embodiments, depending on process requirements, the first gate structure may also be other types of device gate structures such as polysilicon gate structures.

[0105] In this embodiment, the first source / drain doped layer 103 is used as the source or drain of the first transistor. The conductivity type of the doped ions in the first source / drain doped layer is the same as the channel conductivity type of the first transistor.

[0106] In this embodiment, the first transistor structure 100 further includes a first gate sidewall 105, which covers the sidewall of the first gate structure 160. Specifically, the first gate sidewall 105 covers the first gate dielectric layer 130 located on the sidewall of the first gate structure 160.

[0107] It should be noted that, taking the first transistor as a GAA transistor as an example, the first transistor structure 100 may further include: a first inner wall (not shown), located between adjacent first sub-channel layers 176 along the normal direction of the surface of the first substrate 110, or located between the first sub-channel layer 176 and the first substrate 110, and along a direction perpendicular to the extension direction of the first gate structure 160, the first inner wall is located between the sidewall of the first gate dielectric layer 130 and the first source / drain doped layer 103.

[0108] For a detailed description of the first source / drain doped layer 103, the first gate sidewall 105, and the first inner sidewall, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0109] In this embodiment, the first transistor structure 100 further includes a bottom interlayer dielectric layer 120, which is located on the substrate 110 on the side of the first gate structure 160 and covers the sidewall of the first gate structure 160.

[0110] The bottom interlayer dielectric layer 120 is used to isolate adjacent transistors in the first transistor structure 100. The bottom interlayer dielectric layer 120 is made of an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the bottom interlayer dielectric layer 120 is made of silicon oxide.

[0111] In this embodiment, the first transistor structure 100 has a bonding surface 101. The bonding surface 101 is the front side of the first transistor structure 100. Subsequently, using the bonding surface 101 as a process platform, a second transistor structure is fabricated on top of the bonding surface 101, thereby forming a sequential CFET structure.

[0112] Continue to refer to Figure 5 and Figure 6 The second substrate 205 is bonded to the bonding surface 101 using a bonding layer 200, wherein the material of the bonding layer 200 is a dielectric material.

[0113] The second substrate 205 is used to form the second channel layer in the second transistor structure.

[0114] A second transistor structure is subsequently formed on the bonding layer 200. This second transistor structure includes a second transistor, which is the top transistor in a CFET structure. The second transistor can be an NMOS transistor or a PMOS transistor, and the channel conductivity type of the second transistor is different from that of the first transistor. In this embodiment, the first transistor is an NMOS transistor; therefore, the second transistor is a PMOS transistor. In other embodiments, when the first transistor is a PMOS transistor, the second transistor is correspondingly an NMOS transistor.

[0115] In this embodiment, the second substrate 205 is bonded to the bonding surface 101 by bonding. That is, after the fabrication process of the first transistor structure 100 is completed, the fabrication process of the second transistor structure is completed independently, which reduces the difficulty of subsequent fabrication of the second transistor structure and the impact of the fabrication process of the second transistor structure on the first transistor structure 100.

[0116] The bonding layer 200 enhances the bonding strength between the first transistor structure 400 and the second substrate 205, thereby improving the reliability of the semiconductor structure. Furthermore, the bonding layer 200 is made of a dielectric material, which provides electrical isolation between the first transistor structure 200 and the subsequently formed second transistor structure, and makes the bonding layer 200 compatible with semiconductor processes. In addition, the bonding layer 200 can also protect the first transistor structure 200 during the subsequent fabrication of the second transistor structure.

[0117] The bonding layer 200 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, and carbon-doped silicon oxide. In this embodiment, the bonding layer 200 is made of silicon oxide. By using silicon oxide, bonding can be achieved through melt bonding, which is beneficial for improving bonding efficiency and bonding strength; moreover, it is also beneficial for further improving the electrical isolation effect of the bonding layer 200; in addition, by using silicon oxide, the bonding temperature is lower, thereby reducing the impact on the performance of the first transistor in the first transistor structure 200.

[0118] In this embodiment, the bonding layer 200 is located between the second substrate 205 and the first transistor structure 100, and the bonding layer 200 covers the top of the first gate structure 160 and the top of the bottom interlayer dielectric layer 120.

[0119] As an example, taking the bonding surface 101 of the first transistor structure 100 as the first bonding surface 101, and the second substrate 205 including a second bonding surface (not shown), the step of bonding the second substrate 205 to the bonding surface 101 using the bonding layer 200 includes: forming a first sub-bonding layer (not shown) on the first bonding surface 101, forming a second sub-bonding layer (not shown) on the second bonding surface; and placing the first sub-bonding layer and the second sub-bonding layer opposite to each other and bonding them together, thereby bonding the second substrate 205 to the bonding surface 101. Accordingly, the first sub-bonding layer and the second sub-bonding layer constitute a stacked bonding layer 200. In this embodiment, the materials of both the first sub-bonding layer and the second sub-bonding layer are silicon oxide, thereby achieving silicon oxide-silicon oxide fusion bonding.

[0120] It should be noted that in other embodiments, the second substrate may be bonded to the bonding surface only on one of the first bonding surface and the second bonding surface after the bonding layer is formed on one of the two bonding surfaces.

[0121] In this embodiment, a deposition process (e.g., chemical vapor deposition) is used to form the bonding layer 200.

[0122] In this embodiment, taking the subsequently formed second transistor as a GAA transistor as an example, in the step of bonding the second substrate 205 to the bonding surface 101 using the bonding layer 200, the second substrate 205 includes one or more stacked channel material stacks 206. The channel material stack 206 includes a sacrificial material layer 215 and a channel material layer 225 located on the sacrificial material layer 215. In the same channel material stack 206, the sacrificial material layer 215 is closer to the bonding layer 200 than the channel material layer 225.

[0123] The sacrificial material layer 21 is used to prepare for the subsequent formation of the sacrificial layer, and the channel material layer 225 is used to prepare for the subsequent formation of the second channel layer. In this embodiment, only one channel material stack 206 is illustrated. However, the number of channel material stacks 206 is not limited to one.

[0124] Specifically, taking the second substrate 205 including a channel material stack 206 as an example, the steps of forming the second substrate 205 and the second sub-bonding layer include: providing an initial substrate, the material of which is the same as the material of the channel material layer 225; forming a sacrificial material layer 215 on the channel material layer 225, the sacrificial material layer 215 and the channel material layer 225 constituting a channel material stack 206; and forming the channel material stack 206, and then forming the second sub-bonding layer on the sacrificial material layer 215.

[0125] In this embodiment, after the second substrate 205 is bonded to the bonding surface 101 using the bonding layer 200, the initial substrate is thinned until the remaining initial substrate reaches the target thickness. The target thickness of the remaining initial substrate is equal to the target thickness of the channel material layer 225.

[0126] Accordingly, when the second substrate 205 includes a plurality of stacked channel material stacks 206, after the formation of the first channel material stack 206 and before the formation of the second sub-bonding layer, the method further includes: alternately forming a channel material layer 225 and a sacrificial material layer 215 on the first channel material stack 206 until the total number of channel material stacks 206 reaches the target number.

[0127] Therefore, in this embodiment, after the second transistor structure is subsequently formed, the second transistor structure does not contain an additional substrate (e.g., a base).

[0128] The channel material layer 225 may be made of silicon, silicon germanide, germanium, or a group III-V semiconductor material. The material of the channel material layer 225 is determined based on the channel conductivity type and performance requirements of the second transistor. As an example, the channel material layer 225 may be made of silicon.

[0129] Based on the material of the channel material layer 225, the sacrificial material layer 215 is selected from materials with an etch selectivity ratio that is similar to that of the channel material layer 225. In this embodiment, the channel material layer 225 is silicon, therefore, the sacrificial material layer 215 is silicon germanide. Silicon germanide has a high etch selectivity ratio with silicon, making it easier to remove the sacrificial material layer 215 subsequently and reducing damage to the channel material layer 225 during the removal process.

[0130] It should be noted that in other embodiments, when the subsequently formed second transistor is a FinFET, in the step of bonding the second substrate to the bonding surface using a bonding layer, the second substrate is a fin material layer. Correspondingly, the initial substrate contains the same material layer as the fin material layer, and after bonding, the initial substrate is thinned until the target thickness of the fin material layer is reached.

[0131] refer to Figure 7 , Figure 7 Based on Figure 5 A cross-sectional view, graphically representing the second substrate 205 (e.g.) Figure 5 As shown), a second channel layer 220 is formed.

[0132] The second channel layer 220 is used to provide a channel for the second transistor. As an example, the material of the second channel layer 220 is silicon.

[0133] Specifically, in the step of patterning the second substrate 205, the channel material stack 206 is patterned as one or more stacked channel stacks 227 protruding from the bonding layer 200. The channel stack 227 includes a sacrificial layer 210 and sub-channel layers 226 located on the sacrificial layer 210. The one or more sub-channel layers 226 constitute the second channel layer 220.

[0134] It should be noted that the first channel layer 170 includes one or more first sub-channel layers 176 spaced apart. Therefore, in the step of graphically representing the second substrate 205, the sub-channel layer 226 in the channel stack 227 is defined as the second sub-channel layer 226, and the one or more second sub-channel layers 226 constitute the second channel layer 220.

[0135] In other embodiments, when the second substrate is a fin material layer, the second channel layer is a fin (specifically a second fin) protruding from the bonding layer in the step of patterning the second substrate.

[0136] Reference Figure 8 and Figure 9 , Figure 8 Based on Figure 7 Cross-sectional view, Figure 9 Based on Figure 8 In a cross-sectional view perpendicular to the extension direction of the first gate structure or dummy gate structure, a dummy gate structure 250 is formed on the bonding layer 200, the dummy gate structure 250 spanning the second channel layer 220 and covering a portion of the top and a portion of the sidewalls of the second channel layer 220.

[0137] The dummy gate structure 250 is used to occupy space for the subsequent formation of a second gate structure. Specifically, the dummy gate structure 250 spans the channel stack 227 and covers a portion of the top and sidewalls of the channel stack 227.

[0138] In this embodiment, the dummy gate structure 250 includes a dummy gate oxide layer 230 covering the channel stack 227 and a dummy gate layer 240 covering the dummy gate oxide layer 230. As an example, the dummy gate oxide layer 230 is made of silicon oxide or silicon oxynitride, and the dummy gate layer 240 is made of polycrystalline silicon, amorphous silicon, or amorphous carbon.

[0139] In other embodiments, when the second channel layer is a second fin protruding from the bonding layer, the pseudo-gate structure correspondingly spans the second fin and covers part of the top and part of the sidewalls of the second fin.

[0140] Continue to refer to Figure 8 and Figure 9 After forming the dummy gate structure 250, the method further includes: forming a second gate sidewall 205 on the sidewall of the dummy gate structure 250; after forming the second gate sidewall 205, forming a second source / drain doped layer 201 in the second channel layer 220 on both sides of the dummy gate structure 250, wherein the second source / drain doped layer 201 is in contact with the end of the second channel layer 220 located below the dummy gate structure 250.

[0141] The conductivity type of the doped ions in the second source / drain doped layer 201 is the same as the channel conductivity type of the second transistor. Specifically, after forming grooves (not shown) in the second channel layer 220 on both sides of the dummy gate structure 250, an epitaxial process is used to form the second source / drain doped layer 201 in the grooves.

[0142] It should be noted that, after the groove is formed and before the second source / drain doped layer 201 is formed, the process further includes: laterally etching a sacrificial layer 210 of the exposed width of the groove to form a trench connected to the groove; and forming a second inner sidewall (not shown) in the trench.

[0143] For a detailed description of the second gate sidewall 205, the second source / drain doped layer 201, and the second inner sidewall, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0144] Continue to refer to Figure 8 and Figure 9 After forming the second source / drain doped layer 201, a top interlayer dielectric layer 260 is formed on the bonding layer 200 on the side of the pseudo-gate structure 250. The top interlayer dielectric layer 260 covers the sidewall of the pseudo-gate structure 250 and exposes the top of the pseudo-gate structure 250.

[0145] The top interlayer dielectric layer 260 is used to isolate adjacent transistors in the subsequent second transistor structure, and also to provide a process basis for the subsequent formation of interconnect openings and second gate structures.

[0146] The top interlayer dielectric layer 260 is made of an insulating material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride. In this embodiment, the top interlayer dielectric layer 260 is made of silicon oxide.

[0147] refer to Figure 10 , Figure 10 Based on Figure 8 The cross-sectional view, removing the pseudo-gate structure 250 (e.g.) Figure 6 As shown, a gate opening 270 is formed in the top interlayer dielectric layer 260.

[0148] The gate opening 270 is used to provide space for the subsequent formation of the second gate structure and also to provide a process basis for the subsequent formation of interconnect openings.

[0149] In this embodiment, after forming the gate opening 270, the method further includes: removing the sacrificial layer 210 exposed by the gate opening 270 to form a through groove 280 communicating with the gate opening 270.

[0150] The through slot 280 is also used to provide space for the subsequent formation of the second gate structure.

[0151] refer to Figure 11 A second gate dielectric layer 310 is formed to conformally cover the bottom and sidewalls of the gate opening 270, and the second gate dielectric layer 310 also conformally covers the second channel layer 220 in the gate opening 270.

[0152] In this embodiment, the second gate dielectric layer 310 is used to isolate the subsequently formed second gate structure and second channel layer 220.

[0153] In this embodiment, the second gate dielectric layer 310 includes a high-k gate dielectric layer. Specifically, the second gate dielectric layer 310 includes a gate oxide layer and a high-k gate dielectric layer covering the gate oxide layer. The gate oxide layer conformally covers each surface of the second channel layer 220; the high-k gate dielectric layer conformally covers the gate oxide layer and also conformally covers the bottom and sidewalls of the gate opening 270. For a detailed description of the second gate dielectric layer 310, please refer to the foregoing description of the first gate dielectric layer 130, which will not be repeated here.

[0154] It should be noted that the second gate dielectric layer 310 also covers the top of the top interlayer dielectric layer 260.

[0155] refer to Figure 12 After forming the second gate dielectric layer 310, the process further includes: forming a conformal capping layer (not shown) covering the second gate dielectric layer 310, and a sacrificial layer 320 covering the conformal capping layer; after forming the sacrificial layer 320, the second gate dielectric layer 310 is annealed 330.

[0156] Subsequently, when the second work function layer is formed in the gate opening 270, the capping layer protects the high-k gate dielectric layer in the second gate dielectric layer 310, preventing metal ions in the second work function layer from diffusing into the high-k gate dielectric layer. The capping layer also prevents oxygen ions in the high-k gate dielectric layer from diffusing into the second work function layer, thereby avoiding the problem of increased oxygen vacancy content in the high-k gate dielectric layer. In this embodiment, the capping layer is made of TiN. In other embodiments, the capping layer may also be made of TiSiN or TaN.

[0157] The sacrificial layer 320 is used to improve the electrical performance stability of the subsequently formed second transistor. In this embodiment, the material of the sacrificial layer 320 is amorphous silicon (a-Si).

[0158] The annealing process 330 is used to improve the quality of the second gate dielectric layer 310. The annealing process 330 may include one or both of peak annealing and laser annealing processes.

[0159] Reference Figures 13 to 14 In the gate opening 270, an interconnection opening 350 is formed that extends through the bottom of the gate opening 270 to the second gate dielectric layer 310 and the bonding layer 200 (e.g., Figure 11 As shown, the interconnect opening 350 exposes the first gate structure 160, and the interconnect opening 350 is connected to the gate opening 270.

[0160] Interconnection opening 350 provides space for the subsequent formation of conductive plugs. At this time, the second gate structure has not yet been formed in the gate opening 270, and the formation of the conductive plug will not be blocked by the second gate structure. Moreover, after the second gate structure is subsequently formed in the gate opening 270, the conductive plug is located between the first transistor structure 100 and the second transistor structure. Without physical contact between the first gate structure 160 and the second gate structure, the electrical connection between the first gate structure and the second gate structure is achieved through the conductive plug, thereby facilitating the formation of an inverter based on a CFET structure.

[0161] In this embodiment, after forming the second gate dielectric layer 310, an interconnect opening 350 is formed to prevent the second gate dielectric layer 310 from forming in the interconnect opening 350. Correspondingly, after forming a conductive plug in the interconnect opening 350, there will be no second gate dielectric layer 310 between the conductive plug and the first gate structure 160, and the conductive plug can be electrically connected to the first gate structure 160. Moreover, after forming the sacrificial layer 320, the interconnect opening 350 is formed, so that the sacrificial layer 320 protects the second gate dielectric layer 310 during the formation of the interconnect opening 350, reducing the probability of damage to the second gate dielectric layer 310. In addition, after annealing the second gate dielectric layer 310, the interconnect opening 350 is formed. During the annealing process 330, the bonding surface 101 of the first transistor structure 100 is completely covered by the bonding layer 200, thereby reducing the impact of the annealing process 330 on the first transistor structure 100 (especially the first gate structure 160).

[0162] Specifically, the steps for forming the interconnect opening 350 include: as follows Figure 13 As shown, a protective layer 330 is filled in the gate opening 270; a mask layer 340 is formed on top of the protective layer 330, and a mask opening 345 is formed in the mask layer 340, the mask opening 345 exposing a portion of the top of the protective layer 330 on the side of the second channel layer 220; as shown Figure 11 As shown, using the mask layer 340 as a mask, the protective layer 330, the second gate dielectric layer 310 and the bonding layer 200 are sequentially etched along the mask opening 345 to form an interconnect opening 350 that penetrates the second gate dielectric layer 310 and the bonding layer 200.

[0163] In this embodiment, the protective layer 330 is made of an organic material. The formation of the mask opening 345 typically requires a photolithography process, and organic materials are compatible with photolithography processes. Furthermore, organic materials have good filling properties. In addition, organic materials are easy to remove, and the removal process causes minimal damage to other film layers. As an example, the protective layer 330 is formed using a spin-coating process. Accordingly, the protective layer 330 also covers the top of the top interlayer dielectric layer 260.

[0164] The protective layer 330 is made of materials including BARC (bottom anti-reflective coating), ODL (organic dielectric layer), DARC (dielectric anti-reflective coating), spin-on carbon (SOC), DUO (Deep UV Light Absorbing Oxide), or APF (Advanced Patterning Film). As an example, the protective layer 330 is made of SOC material. SOC material has good filling properties.

[0165] In this embodiment, after etching the protective layer 330 and before etching the second gate dielectric layer 310, the sacrificial layer 320 is also etched.

[0166] In this embodiment, a dry etching process (e.g., anisotropic dry etching process) is used to sequentially etch the protective layer 330, sacrificial layer 320, second gate dielectric layer 310, and bonding layer 200 along the mask opening 345. The dry etching process has anisotropic etching characteristics, making it easier to obtain a better etching profile for the interconnect opening 350. Furthermore, in this embodiment, the bonding layer 200 is made of a dielectric material, which is an inorganic material; therefore, it is easier to obtain a better etching profile during the etching process.

[0167] In this embodiment, after forming the interconnect opening 350, the method further includes removing the mask layer 340 and the protective layer 330. Removing the mask layer 340 and the protective layer 330 exposes the gate opening 270 and the through-slot 280, thereby preparing for the subsequent formation of the conductive plug and the second gate structure.

[0168] In this embodiment, after removing the mask layer 340 and the protective layer 330, the sacrificial layer 320 is retained.

[0169] Reference Figures 15 to 16 Conductive plugs 360 are formed in interconnect openings 350.

[0170] The conductive plug 360 is used to electrically connect the first gate structure 160 and the second gate structure subsequently formed in the gate opening 270.

[0171] In this embodiment, after forming the conductive plug 360 in the interconnect opening 350, a second gate structure is subsequently formed in the gate opening. The conductive plug 360 and the second gate structure are independent structures, but they are connected together by electrical connection. By forming the conductive plug 360 separately, the material of the conductive plug 360 can be flexibly selected according to performance requirements. Specifically, the material of the conductive plug 360 includes one or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. The above materials have good conductivity and high compatibility with metal gate structures.

[0172] Specifically, the step of forming the conductive plug 360 in the interconnection opening 350 includes: as follows Figure 15 As shown, conductive material 365 is filled into the interconnect opening 350, and conductive material 365 is also formed in the gate opening 270 and the through-hole 280; as Figure 16 As shown, the conductive material 365 in the gate opening 270 and the through trench 280 is removed by back etching, and the remaining conductive material 365 in the interconnect opening 350 is retained as a conductive plug 360.

[0173] In this embodiment, according to the material and process requirements of the conductive plug 360, the process of filling the interconnect opening 350 with conductive material 365 includes one or more of physical vapor deposition, chemical vapor deposition and atomic layer deposition processes, thereby obtaining a better filling effect.

[0174] In this embodiment, the conductive material 365 is formed using a deposition process. The conductive material 365 also covers the top of the top interlayer dielectric layer 260. Correspondingly, during the etch-back process, the conductive material 365 located on top of the top interlayer dielectric layer 260 is also removed. In other embodiments, depending on the selected process, the conductive material may also be selectively formed in gate openings, vias, and interconnect openings.

[0175] In this embodiment, one or both of dry etching and wet etching processes are used to etch back the conductive material 365.

[0176] In this embodiment, after the conductive plug 360 is formed, the top of the conductive plug 360 is flush with the top of the sacrificial layer 320 located at the bottom of the gate opening 270. Accordingly, during the etching back of the conductive material 365, the top of the sacrificial layer 320 located at the bottom of the gate opening 270 can be used as the etching stop position, which is beneficial for precisely controlling the amount of etching back of the conductive material 365. Moreover, during the etching back of the conductive material 365, the sacrificial layer 320 can also protect the second gate dielectric layer 310, reducing the probability of damage to the second gate dielectric layer 310.

[0177] Therefore, refer to Figure 17 After forming the conductive plug 360, the process also includes: removing the sacrificial layer 320.

[0178] The sacrificial layer 320 is a film layer that is not desired to remain in the second gate structure. Removing the sacrificial layer 320 prepares for the subsequent formation of the second gate structure.

[0179] In this embodiment, after removing the sacrificial layer 320, the top of the second gate dielectric layer 310 located at the bottom of the gate opening 270 is lower than the top of the conductive plug 360. Therefore, when the second gate structure is subsequently formed, the second gate structure not only covers the end of the conductive plug 360, but also covers part of the sidewall of the conductive plug 360, which helps to reduce the contact resistance of the conductive plug 360 and the second gate structure.

[0180] refer to Figure 18 After forming the conductive plug 360, a second gate structure 390 is formed in the gate opening 270. The second gate structure 390 and the first gate structure 160 are electrically connected through the conductive plug 360. The second gate structure 390, the second gate dielectric layer 310, and the second source / drain doped layer 201 (as shown in the image) are also included. Figure 9 (As shown) and the second channel layer 220 are used to form the second transistor structure.

[0181] The second gate structure 390 is a device gate structure used to control the opening or closing of the channel of the second transistor. In this embodiment, the second gate structure 390 surrounds the second gate dielectric layer 310 covering the second channel layer 220. In other embodiments, when the second channel layer is a second fin, the corresponding second gate structure spans the second fin and covers a portion of the top and a portion of the sidewalls of the second fin's second gate dielectric layer.

[0182] In this embodiment, the second gate structure 390 is a second metal gate structure, and the material of the second metal gate structure includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. Specifically, the second gate structure 390 includes a second work function layer 370 and a second gate electrode layer 380 covering the second work function layer 370. For a detailed description of the second work function layer 370 and the second gate electrode layer 380, please refer to the foregoing descriptions of the first work function layer 140 and the first gate electrode layer 150, respectively, and will not be repeated here.

[0183] Specifically, a second gate structure 390 is formed in the gate opening 270 through a sequential deposition and planarization step. During the planarization process, the second gate dielectric layer 310 located on top of the top interlayer dielectric layer 260 is also removed.

[0184] It should be noted that in this embodiment, the conductive plug and the second gate structure are formed sequentially in different steps. In other embodiments, the conductive plug and the second gate structure can also be formed in the same step. Specifically, in the step of forming the second gate structure in the gate opening, the second gate structure is also formed in the interconnect opening. The second gate structure located in the interconnect opening serves as the conductive plug. Correspondingly, the second gate structure and the conductive plug are an integral structure, and the film structure and material of the second gate structure and the conductive plug are the same.

[0185] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The first transistor structure includes a substrate, a first channel layer on the substrate, a first gate dielectric layer conformally covering the first channel layer, a first gate structure covering the first gate dielectric layer, and first source / drain doped layers on the substrate on both sides of the first gate structure. The first source / drain doped layers are in contact with the end of the first channel layer located below the first gate structure. The first transistor structure has a bonding surface located on one side of the first gate structure. A bonding layer is located on the bonding surface of the first transistor structure, and the material of the bonding layer is a dielectric material; The second transistor structure is located on the bonding layer. The second transistor structure includes a second channel layer, a second gate dielectric layer that conformally covers the second channel layer, a second gate structure that covers the second gate dielectric layer, and a second source / drain doped layer on the bonding layer on both sides of the second gate structure. The second source / drain doped layer is in contact with the end of the second channel layer located below the second gate structure. A conductive plug extends through the second gate dielectric layer and bonding layer at the bottom of the second gate structure, and the conductive plug is electrically connected to the second gate structure and the first gate structure.

2. The semiconductor structure as described in claim 1, characterized in that, Along the stacking direction of the first transistor structure and the second transistor structure, the two ends of the conductive plug are electrically connected to the bottom of the second gate structure and the top of the first gate structure, respectively.

3. The semiconductor structure as described in claim 1, characterized in that, The conductive plug and the second gate structure are an integral structure.

4. The semiconductor structure as described in claim 1, characterized in that, The conductive plug is made of one or more of the following materials: Co, Ru, TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

5. The semiconductor structure as described in claim 1, characterized in that, The first channel layer is a first fin protruding from the substrate; the first gate structure spans the first fin and covers a portion of the top and a portion of the sidewalls of the first fin, forming a first gate dielectric layer. Alternatively, the first channel layer is located on the substrate and spaced apart from the substrate, and the first channel layer includes one or more spaced first sub-channel layers; the first gate structure surrounds and covers the first gate dielectric layer on the first channel layer.

6. The semiconductor structure as described in claim 1, characterized in that, The second channel layer is a second fin protruding from the bonding layer; the second gate structure spans the second fin and covers a portion of the top and a portion of the sidewalls of the second fin, forming a second gate dielectric layer. Alternatively, the second channel layer is located on the bonding layer and spaced apart from the bonding layer, and the second channel layer includes one or more spaced second sub-channel layers; the second gate structure surrounds and covers the second gate dielectric layer on the second channel layer.

7. The semiconductor structure as described in claim 1, characterized in that, The first gate structure includes a first metal gate structure, and the second gate structure includes a second metal gate structure.

8. The semiconductor structure as described in claim 1, characterized in that, Along the stacking direction of the first transistor structure and the second transistor structure, the conductive plug also extends into the second gate structure, which has a certain thickness.

9. The semiconductor structure as described in claim 1, characterized in that, The first transistor structure includes an NMOS transistor, and the second transistor structure includes a PMOS transistor; Alternatively, the first transistor structure may include a PMOS transistor, and the second transistor structure may include an NMOS transistor.

10. The semiconductor structure as claimed in claim 1, characterized in that, The material of the first channel layer includes silicon, silicon germanide, germanium, or a group III-V semiconductor material; the material of the second channel layer includes silicon, silicon germanide, germanium, or a group III-V semiconductor material.

11. The semiconductor structure as claimed in claim 1, characterized in that, The bonding layer is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, and carbon-doped silicon oxide.

12. The semiconductor structure as claimed in claim 1, characterized in that, The material of the first gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3; the material of the second gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

13. The semiconductor structure as described in claim 7, characterized in that, The material of the first metal gate structure includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC; the material of the second metal gate structure includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

14. A method for forming a semiconductor structure, characterized in that, include: A first transistor structure is formed, the first transistor structure including a first substrate, a first channel layer on the first substrate, a first gate dielectric layer conformally covering the first channel layer, a first gate structure covering the first gate dielectric layer, and a first source / drain doped layer on the first substrate on both sides of the first gate structure, the first source / drain doped layer being in contact with the end of the first channel layer located below the first gate structure, and the first transistor structure having a bonding surface located on one side of the first gate structure. A second substrate is bonded to the bonding surface using a bonding layer, wherein the bonding layer is made of a dielectric material. The second substrate is graphically represented to form the second channel layer; A pseudo-gate structure is formed on the bonding layer, the pseudo-gate structure spanning the second channel layer and covering part of the top and part of the sidewalls of the second channel layer; A second source / drain doped layer is formed in the second channel layer on both sides of the pseudo-gate structure, and the second source / drain doped layer is in contact with the end of the second channel layer located below the pseudo-gate structure; After forming the second source / drain doped layer, a top interlayer dielectric layer is formed on the bonding layer on the side of the pseudo-gate structure. The top interlayer dielectric layer covers the sidewall of the pseudo-gate structure and exposes the top of the pseudo-gate structure. Remove the dummy gate structure and form a gate opening in the top interlayer dielectric layer; A second gate dielectric layer is formed to conformally cover the bottom and sidewalls of the gate opening, and the second gate dielectric layer also conformally covers the second channel layer in the gate opening; An interconnection opening is formed in the gate opening, extending through the bottom of the gate opening to the second gate dielectric layer and the bonding layer. The interconnection opening exposes the first gate structure and is connected to the gate opening. A conductive plug is formed in the interconnect opening, and a second gate structure is formed in the gate opening. The second gate structure and the first gate structure are electrically connected through the conductive plug. The second gate structure, the second gate dielectric layer, the second source / drain doped layer, and the second channel layer are used to form a second transistor structure.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, After forming a conductive plug in the interconnect opening, a second gate structure is formed in the gate opening.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The step of forming a conductive plug in the interconnect opening includes: filling the interconnect opening with a conductive material, the conductive material also being formed in the gate opening; The conductive material in the gate opening is removed by etching back, while the remaining conductive material in the interconnect opening is retained as a conductive plug.

17. The method for forming a semiconductor structure as described in claim 14, characterized in that, In the step of forming a second gate structure in the gate opening, the second gate structure is also formed in the interconnect opening, and the second gate structure located in the interconnect opening serves as a conductive plug.

18. The method for forming a semiconductor structure as described in claim 14, characterized in that, The step of forming the interconnect opening includes: filling the gate opening with a protective layer; forming a mask layer on top of the protective layer, wherein a mask opening is formed in the mask layer, and the mask opening exposes a portion of the top of the protective layer on the side of the second channel layer; using the mask layer as a mask, sequentially etching the protective layer, the second gate dielectric layer and the bonding layer along the mask opening to form an interconnect opening penetrating the second gate dielectric layer and the bonding layer; Before forming the conductive plug and the second gate structure, the forming method further includes removing the mask layer and the protective layer.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, In the step of filling the gate opening with a protective layer, the material of the protective layer includes an organic material.

20. The method for forming a semiconductor structure as described in claim 14, characterized in that, In the step of forming the second gate dielectric layer, the second gate dielectric layer includes a high-k gate dielectric layer; After forming the second gate dielectric layer and before forming the interconnect opening, the method further includes: forming a conformal sacrificial layer covering the second gate dielectric layer; and after forming the sacrificial layer, annealing the second gate dielectric layer. Before forming the second gate structure, the process also includes removing the sacrificial layer.

21. The method for forming a semiconductor structure as described in claim 20, characterized in that, After forming a conductive plug in the interconnection opening, a second gate structure is formed in the gate opening; In the step of forming the conductive plug, the top of the conductive plug is flush with the top of the sacrificial layer located at the bottom of the gate opening; After the conductive plug is formed and before the second gate structure is formed, the sacrificial layer is removed.

22. The method for forming a semiconductor structure as described in claim 14, characterized in that, In the step of bonding the second substrate to the bonding surface using a bonding layer, the second substrate is a fin material layer; In the step of graphically representing the second substrate, the second channel layer is a fin protruding from the bonding layer; In the step of forming the pseudo-gate structure, the pseudo-gate structure spans the fin and covers part of the top and part of the sidewalls of the fin; or, In the step of bonding a second substrate to the bonding surface using a bonding layer, the second substrate includes one or more stacked channel material stacks, the channel material stacks including a sacrificial material layer and a channel material layer located on the sacrificial material layer, and in the same channel material stack, the sacrificial material layer is closer to the bonding layer than the channel material layer; In the step of patterning the second substrate, the channel material stack is patterned as one or more stacked channel stacks protruding from the bonding layer, the channel stack including a sacrificial layer and sub-channel layers located on the sacrificial layer, the one or more sub-channel layers constituting the second channel layer; In the step of forming the pseudo-gate structure, the pseudo-gate structure spans the channel stack and covers part of the top and part of the sidewalls of the channel stack; After forming the gate opening and before forming the second gate dielectric layer, the method further includes: removing the sacrificial layer exposed by the gate opening; In the step of forming the second gate structure, the second gate structure surrounds a second gate dielectric layer covering the second channel layer.

23. The method for forming a semiconductor structure as described in claim 16, characterized in that, The process of filling the interconnect opening with conductive material includes one or more of physical vapor deposition, chemical vapor deposition, and atomic layer deposition.

24. The method for forming a semiconductor structure as described in claim 16, characterized in that, The process for etching back the conductive material includes one or both of dry etching and wet etching processes.

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