Image sensing device

Abstract

An image sensing device is disclosed, which includes: a plurality of defect detectors, each of which is suitable for: detecting whether a corresponding target image value is defective, and generating detection information corresponding to the detection result; a defect scheduler, which is suitable for sequentially outputting one or more defective image values ​​based on the detection information, the defective image value being a target image value detected as defective among a plurality of target image values; and a defect corrector, which is suitable for correcting the output defective image value.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2021-0038902, filed on March 25, 2021, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to semiconductor design technology, and more particularly, to image sensing devices. Background Art

[0004] An image sensing device is a device that captures an image using the property of a semiconductor to react to light. Image sensing devices can be roughly divided into a charge coupled device (CCD) image sensing device and a complementary metal oxide semiconductor (CMOS) image sensing device. Recently, CMOS image sensing devices are widely used because CMOS image sensing devices can allow analog control circuits and digital control circuits to be directly implemented on a single integrated circuit (IC). Summary of the invention

[0005] Various embodiments of the present disclosure are directed to an image sensing device that can control a processing schedule of defective image values.

[0006] According to an embodiment of the present disclosure, an image sensing device may include: multiple defect detectors, suitable for detecting whether each of multiple target image values ​​has defects, and generating multiple detection information corresponding to the detection results; a defect scheduler, suitable for sequentially outputting one or more defective image values ​​among the multiple target image values ​​in which defects occur based on the multiple detection information; and a defect corrector, suitable for correcting the one or more defective image values.

[0007] The defect scheduler may sequentially output the defect image values ​​by determining priorities based on the detection information, and sequentially selecting the defect image values ​​according to the priorities.

[0008] The detection information may include a flag signal indicating whether a corresponding target image value has a defect and a distortion value of the corresponding target image value.

[0009] The distortion value may be the sum of differences between a corresponding target image value and surrounding image values ​​of the corresponding target image value.

[0010] According to an embodiment of the present disclosure, an image sensing device may include: a plurality of defect detectors, suitable for: detecting whether each of a plurality of target image values ​​is defective, and generating a plurality of detection information corresponding to the detection results; a priority controller, suitable for: determining the priority of one or more defective image values ​​based on the plurality of detection information, and generating a plurality of control signals corresponding to the priority; an output unit, suitable for sequentially outputting the one or more defective image values ​​according to the priority based on the plurality of control signals; and a defect corrector, suitable for correcting the one or more defective image values.

[0011] The detection information may include a flag signal indicating whether a corresponding target image value has a defect and a distortion value of the corresponding target image value.

[0012] The distortion value may be the sum of differences between a corresponding target image value and surrounding image values ​​of the corresponding target image value.

[0013] The output unit may include: a plurality of selection circuits adapted to select the defective image values ​​according to the priority; and at least one buffer circuit adapted to store at least one defective image value having a second priority or lower among the defective image values.

[0014] According to an embodiment of the present disclosure, an image sensing device may include: an image sensor, including a plurality of pixels arranged at intersections of a plurality of rows and a plurality of columns, and suitable for generating target image values ​​corresponding to pixel signals read out from the plurality of pixels; and an image processor, suitable for: dividing the target image values ​​into a plurality of groups, and sequentially correcting one or more defective image values ​​among the target image values ​​for each group.

[0015] The image processor may sequentially select the defective image values ​​according to the priority.

[0016] The image processor may also be adapted to determine priorities based on distortion values ​​corresponding to respective defective image values.

[0017] Each of the plurality of distortion values ​​may be a sum of differences between a corresponding defect image value and a peripheral image value of the corresponding defect image value.

[0018] The image processor may sequentially select one or more defective image values ​​according to a priority.

[0019] Priorities may be determined according to distortion values ​​corresponding to defective image values, respectively.

[0020] Each of the plurality of distortion values ​​may be a sum of differences between a corresponding target image value and surrounding image values ​​of the corresponding target image value.

[0021] According to an embodiment of the present disclosure, an operating method of an image sensing device may include: receiving a group of kernel image values ​​at each clock, each kernel image value including a target image value and a peripheral image value; for each of the kernel image values, calculating a degree of distortion based on the target image value and the peripheral image values; for each of the kernel image values, detecting the target image value as a defective image value based on the degree of distortion; queuing one or more kernel image values ​​with defective image values ​​in the group in descending order of the degree of distortion; and dequeuing the queued kernel image values ​​in a first-in-first-out (FIFO) manner to correct the defective image values ​​in the group in the above-mentioned descending order. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a block diagram showing an image sensing device according to an embodiment of the present disclosure.

[0023] Figure 2 The present invention is shown in Figure 1 Block diagram of the image sensor shown.

[0024] Figure 3 The present invention is shown in Figure 2 A diagram of an example of a pixel array is shown.

[0025] Figure 4 The present invention is shown in Figure 1 A block diagram of the image processor is shown.

[0026] Figure 5 The present invention is shown in Figure 4 Block diagram of the defect scheduler shown.

[0027] Figure 6 is a diagram illustrating a method for calculating a distortion value according to an embodiment of the present disclosure.

[0028] Figure 7 The present invention is shown in Figure 1 A diagram illustrating the operation of an image sensing device.

[0029] Figures 8 to 16 It is additionally shown according to the embodiment of the present disclosure Figure 7 The operation of the image sensing device 10 is shown in FIG. DETAILED DESCRIPTION

[0030] Various embodiments of the present disclosure are described below with reference to the accompanying drawings in order to describe the present disclosure in detail so that those skilled in the art to which the present disclosure belongs can easily realize the technical spirit of the present disclosure.

[0031] Throughout the specification, it should be understood that when an element is referred to as being "connected to" or "coupled to" another element, the element may be directly connected to or directly coupled to the other element, or may be electrically connected to or electrically coupled to the other element through one or more elements interposed therebetween. In addition, it should be understood that, unless otherwise mentioned, the terms "comprise", "comprising", "including", "comprising" when used in this specification do not exclude the presence of one or more other elements, but may also include or have one or more other elements. In the description throughout the specification, some components are described in singular form, but the present disclosure is not limited thereto, and it should be understood that these components may be formed in plurality.

[0032] Figure 1 is a block diagram showing an image sensing device 10 according to an embodiment of the present disclosure.

[0033] Reference Figure 1 , the image sensing device 10 may include an image sensor 100 and an image processor 200 .

[0034] The image sensor 100 may generate an image value DPX corresponding to a captured image.

[0035] The image processor 200 may process the image values ​​DPX. For example, the image processor 200 may divide the image values ​​DPX into a plurality of groups (see Figure 7 The image processor 200 may select one or more defective image values ​​in sequence according to the priority. The priority may be determined according to each distortion value corresponding to each defective image value (refer to Figure 7 For example, the image processor 200 may provide an output circuit 223 (see Figure 5 ), the output circuit 223 is designed in an optimal manner based on the probability of occurrence of the defective image value, thereby minimizing the circuit area. In addition, since the image processor 200 can use the buffer circuits STG1, STG2 and STG3 (refer to Figure 5 as well as Figures 7 to 16 ) performs time-sharing processing, thereby reducing the amount of processing required when correcting defective image values.

[0036] Figure 2 The present invention is shown in Figure 1 A block diagram of an image sensor 100 is shown.

[0037] Reference Figure 2 , the image sensor 100 may include a pixel array 110 and a signal converter 120 .

[0038] The pixel array 110 may include a plurality of pixels (see Figure 3 ). The pixel array 110 may generate a pixel signal VPX for each row. For example, the pixel array 110 may generate a pixel signal VPX from pixels arranged in a first row during a first row time, and may generate a pixel signal VPX from pixels arranged in an nth row during an nth row time, where “n” is an integer greater than 2. Each of the pixel signals VPX may be an analog type pixel signal.

[0039] The signal converter 120 may convert the analog type pixel signal VPX into a digital type image value DPX. For example, the signal converter 120 may include an analog-to-digital converter.

[0040] Figure 3 The present invention is shown in Figure 2 A diagram of an example of a pixel array 110 is shown.

[0041] Reference Figure 3 , the pixel array 110 may include a plurality of pixels arranged at the intersection of a plurality of rows and a plurality of columns. The plurality of pixels may be arranged in a predetermined pattern. For example, the plurality of pixels may be arranged in a Bayer pattern. The Bayer pattern may be composed of repeating units each having 2x2 pixels. In each unit, two pixels Gb and Gr, each having a green filter, may be arranged to face each other obliquely at a corner of the unit, and a pixel B having a blue filter and a pixel R having a red filter may be arranged at other corners of the unit. The four pixels B, Gb, Gr, and R are not necessarily limited to Figure 3 The arrangement shown may instead be arranged in a different manner based on the above-described Bayer pattern.

[0042] The image value DPX can be used by the image processor 200 in units of "n" x "n" pixels, where "n" is a natural number. In the following, an example is described in which the image value DPX is generated in units of 5x5 pixels and the image value corresponding to the 5x5 pixels is referred to as the kernel image value. The kernel image value may include a target image value and a peripheral image value. The target image value may be an image value corresponding to a pixel set at the center within the "5" x "5" pixels. The peripheral image value may be an image value corresponding to a pixel that is set on the periphery of a pixel set at the center within the "5" x "5" pixels and has the same color filter as the pixel set at the center.

[0043] Figure 4 The present invention is shown in Figure 1 FIG. 2 is a block diagram of an image processor 200. For ease of description, Figure 4 Only components related to a set of kernel image values ​​5X5V1, 5X5V2, 5X5V3 and 5X5V4 corresponding to one group among the image values ​​DPX are shown.

[0044] Reference Figure 4 , the image processor 200 may include first to fourth defect detectors 211 , 213 , 215 , and 217 , a defect scheduler 220 , a defect corrector 230 , and first to fourth selectors 241 , 243 , 245 , and 247 .

[0045] The first defect detector 211 may detect whether the first target image value is defective based on the first kernel image value 5X5V1 including the first target image value, and generate first detection information DINF1 corresponding to the detection result. The first detection information DINF1 may include a first flag signal F1 indicating whether the first target image value is detected as a defective image value and a first distortion value V1 corresponding to the first target image value. For example, the first defect detector 211 may calculate the first distortion value V1 based on the first target image value and one or more first peripheral image values ​​within the first kernel image value 5X5V1, and generate the first flag signal F1 corresponding to whether the first target image value is defective by comparing the first distortion value V1 with a reference value.

[0046] The second defect detector 213 may detect whether the second target image value is defective based on the second kernel image value 5X5V2 including the second target image value, and generate second detection information DINF2 corresponding to the detection result. The second detection information DINF2 may include a second flag signal F2 indicating whether the second target image value is detected as a defective image value and a second distortion value V2 corresponding to the second target image value. For example, the second defect detector 213 may calculate the second distortion value V2 based on the second target image value and one or more second peripheral image values ​​within the second kernel image value 5X5V2, and generate a second flag signal F2 corresponding to whether the second target image value is defective by comparing the second distortion value V2 with a reference value.

[0047] The third defect detector 215 may detect whether the third target image value is defective based on the third kernel image value 5X5V3 including the third target image value, and generate third detection information DINF3 corresponding to the detection result. The third detection information DINF3 may include a third flag signal F3 indicating whether the third target image value is detected as a defective image value and a third distortion value V3 corresponding to the third target image value. For example, the third defect detector 215 may calculate the third distortion value V3 based on the third target image value and one or more third peripheral image values ​​within the third kernel image value 5X5V3, and generate a third flag signal F3 corresponding to whether the third target image value is defective by comparing the third distortion value V3 with a reference value.

[0048] The fourth defect detector 217 may detect whether the fourth target image value is defective based on the fourth kernel image value 5X5V4 including the fourth target image value, and generate fourth detection information DINF4 corresponding to the detection result. The fourth detection information DINF4 may include a fourth flag signal F4 indicating whether the fourth target image value is detected as a defective image value and a fourth distortion value V4 corresponding to the fourth target image value. For example, the fourth defect detector 217 may calculate the fourth distortion value V4 based on the fourth target image value within the fourth kernel image value 5X5V4 and one or more fourth peripheral image values, and generate a fourth flag signal F4 corresponding to whether the fourth target image value is defective by comparing the fourth distortion value V4 with a reference value.

[0049] The defect scheduler 220 may sequentially output the defect kernel image value 5X5V including one or more defect image values ​​in which a defect occurs among the first to fourth target image values ​​based on the first to fourth detection information DINF1, DINF2, DINF3, and DINF4. For example, the defect scheduler 220 may determine the priority of the one or more defect image values ​​based on the first to fourth detection information DINF1, DINF2, DINF3, and DINF4, and sequentially select and output the defect kernel image value 5X5V according to the priority.

[0050] The defect corrector 230 may correct one or more defective image values ​​within the defective kernel image value 5X5V and generate at least one of the first to fourth corrected image values ​​CV1, CV2, CV3, and CV4. For example, the defect corrector 230 may generate at least one of the first to fourth corrected image values ​​CV1, CV2, CV3, and CV4 based on each defective image value within each kernel image value 5X5V and the surrounding image value of each defective image value.

[0051] The first selector 241 may select and output one of the first target image value TV1 and the first corrected image value CV1 based on the first flag signal F1 .

[0052] The second selector 243 may select and output one of the second target image value TV2 and the second corrected image value CV2 based on the second flag signal F2.

[0053] The third selector 245 may select and output one of the third target image value TV3 and the third corrected image value CV3 based on the third flag signal F3.

[0054] The fourth selector 247 may select and output one of the fourth target image value TV4 and the fourth corrected image value CV4 based on the fourth flag signal F4.

[0055] Figure 5 The present invention is shown in Figure 4 A block diagram of defect scheduler 220 is shown.

[0056] Reference Figure 5 , the defect scheduler 220 may include a priority controller 221 and an output unit 223 .

[0057] The priority controller 221 may determine priorities of one or more defective image values ​​based on the first to fourth detection information DINF1 , DINF2 , DINF3 , and DINF4 , and generate first to fourth control signals CRL1 , CTRL2 , CTRL3 , and CTRL4 corresponding to the priorities.

[0058] The output unit 223 may sequentially output one or more defective image values ​​based on the first to fourth control signals CTRL1, CRTL2, CTRL3, and CTRL4 in which the priorities are reflected. For example, the output unit 223 may include first to fourth selection circuits M1, M2, M3, and M4 and first to third buffer circuits STG1, STG2, and STG3.

[0059] The first selection circuit M1 may select and output a defect kernel image value including a defect image value corresponding to a first priority based on a first control signal CTRL1 .

[0060] The second selection circuit M2 may select and output a defect kernel image value including a defect image value corresponding to a second priority level based on the second control signal CTRL2.

[0061] The third selection circuit M3 may select and output a defect kernel image value including a defect image value corresponding to a third priority level based on a third control signal CTRL3 .

[0062] The fourth selection circuit M4 may select and output defect kernel image values ​​including a defect image value corresponding to a fourth priority level based on a fourth control signal CTRL4.

[0063] The first buffer circuit STG1 may store defective kernel image values ​​including a defective image value corresponding to a second priority level.

[0064] The second buffer circuit STG2 may store defective kernel image values ​​including a defective image value corresponding to a third priority level.

[0065] The third buffer circuit STG3 may store defective kernel image values ​​including a defective image value corresponding to a fourth priority level.

[0066] In the present embodiment, an example is described in which the first to third buffer circuits STG1, STG2, and STG3 are configured to be associated with image values ​​5X5V1, 5X5V2, 5X5V3, and 5X5V4 corresponding to one group. However, the number of buffer circuits STG is not necessarily limited thereto, but may be changed according to the design. For example, the number of buffer circuits STG may be determined according to the probability that the number of defective image values ​​is equal to or greater than the number of defect correctors 230. According to the example, the probability ND Prob. that the number of defective image values ​​is equal to or greater than the number of defect correctors 230 is defined by the following "Equation 1".

[0067] [Equation 1]

[0068]

[0069] Here, “n” may represent the number of defective image values ​​generated at the same time, “t” may represent the number of defect correctors 230, “s” may represent the number of kernels processed at the same time, “c” may represent a combination, and “p n " can represent the probability that n target image values ​​are defective, and "(1-p) s-n ” can represent the probability that sn target image values ​​have no defects.

[0070] According to another example, when a phase detection auto focus (PDAF) pixel is included in the pixel array 110, the probability PD Prob. that the number of defective image values ​​is equal to or greater than the number of defect correctors 230 may be defined by the following “Equation 2”. The image value of the phase detection auto focus pixel may be considered to be the same as the defective image value.

[0071] [Equation 2]

[0072]

[0073] Here, “n” may represent the number of defective image values ​​generated at the same time, “t” may represent the number of defect correctors 230, “a” may represent the number of image values ​​of phase detection autofocus pixels among the image values ​​of each group, “s” may represent the number of kernels processed at the same time, “c” may represent combination, “pn” may represent the probability that n target image values ​​are defective, and “(1-p) s-n-a " can represent the probability that sna target image values ​​have no defects.

[0074] Figure 6 is a diagram illustrating a method for calculating a distortion value according to an embodiment of the present disclosure.

[0075] Reference Figure 6, the distortion value of the target image value may be the sum of the differences between the target image value and the surrounding image values ​​of the target image value. For example, the distortion value may be defined by the following “Equation 3”.

[0076] [Equation 3]

[0077] V=|PV1-TV|+|PV2-TV|+|PV3-TV|+|PV4-TV|+|PV5-TV|+|PV6-TV|+|PV7-TV|+|PV8-TV|

[0078] Here, 'V' may represent a distortion value, 'TV' may represent a target image value, and 'PV1' to 'PV8' may represent first to eighth peripheral image values, respectively.

[0079] Hereinafter, the operation of the image sensing device 10 having the above-described configuration according to the embodiment is described.

[0080] Figure 7 The present invention is shown in Figure 1 The operation of the image sensing device 10 is shown in FIG. Figures 8 to 16 It is additionally shown according to the embodiment of the present disclosure Figure 7 The operation of the image sensing device 10 is shown in FIG.

[0081] Reference Figure 7 , the first to fourth target image values ​​TV1, TV2, TV3 and TV4 may be periodically input according to the clock signal. For example, the first to fourth target image values ​​TV1, TV2, TV3 and TV4 may be input according to the first cycle #1Clk to the ninth cycle #9Clk of the clock signal.

[0082] Reference Figure 7 and Figure 8, the second target image value TV2 and the fourth target image value TV4 among the first to fourth target image values ​​TV1, TV2, TV3 and TV4 input according to the first cycle #1Clk of the clock signal are defective image values, and the distortion value corresponding to the fourth target image value TV4 is greater than the distortion value corresponding to the second target image value TV2. The image processor 200 may give priority to the fourth target image value TV4 among the second target image value TV2 and the fourth target image value TV4. The image processor 200 may output the fourth target image value TV4 from the output circuit 223 to the defect corrector 230 to correct the fourth target image value TV4 having a high priority among the second target image value TV2 and the fourth target image value TV4, and generate the fourth target image value TV4 as the fourth corrected image value CV4. The image processor 200 may store the second target image value TV2 having a low priority among the second target image value TV2 and the fourth target image value TV4 in the first buffer circuit STG1.

[0083] Reference Figure 7 and Fig. 9 , the fourth target image value TV4 among the first to fourth target image values ​​TV1, TV2, TV3 and TV4 input according to the second cycle #2Clk of the clock signal is a defective image value. The image processor 200 may output the second target image value TV2 previously stored in the first buffer circuit STG1 from the output circuit 223 to the defect corrector 230 to correct the second target image value TV2, and store the fourth target image value TV4 currently input in the first buffer circuit STG1.

[0084] Reference Figure 7 and Fig.10 , the second target image value TV2 and the fourth target image value TV4 among the first to fourth target image values ​​TV1, TV2, TV3 and TV4 input according to the third cycle #3Clk of the clock signal are defective image values, and the distortion value corresponding to the fourth target image value TV4 is greater than the distortion value corresponding to the second target image value TV2. The image processor 200 may give priority to the fourth target image value TV4 among the second target image value TV2 and the fourth target image value TV4. The image processor 200 may output the fourth target image value TV4 previously stored in the first buffer circuit STG1 from the output circuit 223 to the defect corrector 230 to correct the fourth target image value TV4, and store the fourth target image value TV4 with a high priority among the second target image value TV2 and the fourth target image value TV4 currently input into the first buffer circuit STG1, and store the second target image value TV2 with a low priority into the second buffer circuit STG2.

[0085] Reference Figure 7 and Fig.11 , the first target image value TV1, the second target image value TV2, and the fourth target image value TV4 among the first to fourth target image values ​​TV1, TV2, TV3, and TV4 input according to the fourth cycle #4Clk of the clock signal are defective image values, the distortion value corresponding to the second target image value TV2 among the first target image value TV1, the second target image value TV2, and the fourth target image value TV4 is the largest, and the distortion value corresponding to the fourth target image value TV4 is the smallest. In this case, the image processor 200 may determine the second target image value TV2 among the first target image value TV1, the second target image value TV2, and the fourth target image value TV4 as the first priority, the first target image value TV1 as the second priority, and the fourth target image value TV4 as the third priority. The image processor 200 may output the fourth target image value TV4 previously stored in the first buffer circuit STG1 from the output circuit 223 to the defect corrector 230 to correct the fourth target image value TV4, and shift the second target image value TV2 previously stored in the second buffer circuit STG2 to the first buffer circuit STG1. The image processor 200 may store the second target image value TV2 having the first priority currently input into the second buffer circuit STG2, and store the first target image value TV1 having the second priority currently input into the third buffer circuit STG3. At this time, since image values ​​have been stored in all the first to third buffer circuits STG1, STG2, and STG3, the image processor 200 may process the fourth target image value TV4 having the third priority currently input as an exception. For example, the image processor 200 may ignore defects in the fourth target image value TV4 having the third priority currently input, and process the fourth target image value TV4 as a normal image value.

[0086] Reference Figure 7 and Fig.12 , the first target image value TV1 among the first to fourth target image values ​​TV1, TV2, TV3 and TV4 input according to the fifth cycle #5Clk of the clock signal is a defective image value. The image processor 200 may output the second target image value TV2 previously stored in the first buffer circuit STG1 from the output circuit 223 to the defect corrector 230 to correct the second target image value TV2, shift the second target image value TV2 previously stored in the second buffer circuit STG2 to the first buffer circuit STG1, and shift the first target image value TV1 previously stored in the third buffer circuit STG3 to the second buffer circuit STG2. The image processor 200 may store the first target image value TV1 currently input in the third buffer circuit STG3.

[0087] Reference Figure 7 and Fig.13 , the third target image value TV3 among the first to fourth target image values ​​TV1, TV2, TV3 and TV4 input according to the sixth cycle #6Clk of the clock signal is a defective image value. The image processor 200 may output the second target image value TV2 previously stored in the first buffer circuit STG1 from the output circuit 223 to the defect corrector 230 to correct the second target image value TV2, shift the first target image value TV1 previously stored in the second buffer circuit STG2 to the first buffer circuit STG1, and shift the first target image value TV1 previously stored in the third buffer circuit STG3 to the second buffer circuit STG2. The image processor 200 may store the third target image value TV3 currently input in the third buffer circuit STG3.

[0088] Reference Figure 7 as well as Figures 14 to 16 When no defective image value is detected during the seventh cycle #7Clk to the ninth cycle #9Clk of the clock signal, the image processor 200 can sequentially shift and sequentially output the image values ​​previously stored in the first to third buffer circuits STG1, STG2 and STG3 from the output circuit 223 to the defect corrector 230 during the seventh cycle #7Clk to the ninth cycle #9Clk to correct the sequentially output image values.

[0089] although Figure 7 It is shown that only the defect image value is stored in the first to third buffer circuits STG1 , STG2 , and STG3 , but actually the kernel image value including the defect image value may be stored therein.

[0090] According to the embodiments of the present disclosure, defective image values ​​may be processed without affecting the performance of processing the defective image values.

[0091] According to the embodiments of the present disclosure, the area of ​​a component for processing a defective image value can be minimized without affecting the performance of processing the defective image value.

[0092] Although the present disclosure is shown and described with respect to specific embodiments, the disclosed embodiments are provided for the purpose of description and are not intended to be limiting. In addition, it should be noted that, as will be appreciated by those skilled in the art from the present disclosure, the present disclosure may be implemented in various ways by substitutions, changes and modifications falling within the scope of the appended claims. Furthermore, the embodiments may be combined to form additional embodiments.

Claims

1. An image sensing device, comprising: a plurality of defect detectors, each defect detector being adapted to: detect whether a corresponding target image value has a defect, and generate detection information corresponding to a result of the detection, wherein the detection information comprises: a flag signal indicating whether the corresponding target image value has a defect, and a distortion value of the corresponding target image value; a defect scheduler adapted to sequentially output one or more defective image values ​​based on the detection information, the one or more defective image values ​​being target image values ​​detected as defective among a plurality of target image values; and A defect corrector, suitable for correcting output defective image values.

2. The image sensing device according to claim 1, wherein: The defect scheduler sequentially outputs the defect image values ​​by: determining a priority based on the detection information, and The defective image values ​​are sequentially selected according to the priorities.

3. The image sensing device according to claim 1, wherein: The distortion value is the sum of differences between the corresponding target image value and surrounding image values ​​of the corresponding target image value.

4. The image sensing device according to claim 1, wherein: Each of the defect detectors detects whether the corresponding target image value is defective by: calculating the distortion value based on the corresponding target image value and surrounding image values ​​of the corresponding target image value, and The distortion value is compared with a reference value.

5. The image sensing device according to claim 1, wherein: The defect corrector corrects the output defect image values ​​by generating corrected image values ​​respectively corresponding to the output defect image values ​​based on the respective output defect image values ​​and peripheral image values ​​of the respective output defect image values. 6 . The image sensing device according to claim 5 , further comprising a plurality of selectors, each of which is adapted to selectively output one of the corresponding target image value and the corrected image value based on a flag signal included in the detection information.

7. An image sensing device, comprising: a plurality of defect detectors, each defect detector being adapted to: detect whether a corresponding target image value has a defect, and generate detection information corresponding to a result of the detection; a priority controller adapted to: determine priorities of one or more defective image values ​​based on the detection information, and to generate a plurality of control signals corresponding to the priorities, the one or more defective image values ​​being target image values ​​detected as defective among a plurality of target image values; an output unit adapted to sequentially output the defective image values ​​according to the priorities based on the plurality of control signals; as well as A defect corrector, suitable for correcting the output defect image values, Each of the defect detectors detects whether the corresponding target image value has a defect by: calculating a distortion value based on the corresponding target image value and surrounding image values ​​of the corresponding target image value, and The distortion value is compared with a reference value.

8. The image sensing device according to claim 7, wherein: The detection information includes: a flag signal indicating whether the corresponding target image value has a defect, and a distortion value of the corresponding target image value.

9. The image sensing device according to claim 8, wherein: The distortion value is the sum of differences between the corresponding target image value and surrounding image values ​​of the corresponding target image value.

10. The image sensing device according to claim 7, wherein: The output unit comprises: a plurality of selection circuits adapted to select the defective image values ​​according to the priority levels; and At least one buffer circuit is adapted to store at least one defective image value having a second priority or lower priority among the defective image values.

11. The image sensing device according to claim 7, wherein: The defect corrector corrects the output defect image values ​​by generating corrected image values ​​respectively corresponding to the output defect image values ​​based on the respective output defect image values ​​and peripheral image values ​​of the respective output defect image values. 12 . The image sensing device according to claim 11 , further comprising a plurality of selectors, each selector being adapted to selectively output one of the corresponding target image value and the corrected image value based on a flag signal included in the detection information.

13. An image sensing device, comprising: an image sensor comprising a plurality of pixels arranged at intersections of a plurality of rows and a plurality of columns and adapted to generate target image values ​​corresponding to pixel signals read out from the plurality of pixels; as well as an image processor adapted to: divide the target image values ​​into a plurality of groups; One or more defective image values ​​among the target image values ​​are sequentially selected and corrected for each group according to a priority; and the priority is determined according to a distortion value corresponding to each defective image value.

14. The image sensing device according to claim 13, wherein: Each of the distortion values ​​is a sum of differences between a corresponding defect image value and surrounding image values ​​of the corresponding defect image value.

15. An operating method of an image processor, the operating method comprising: receiving a set of kernel image values ​​at each clock, each kernel image value comprising a target image value and a peripheral image value; For each of the kernel image values, calculating a degree of distortion based on the target image value and the surrounding image values; for each of the kernel image values, detecting the target image value as a defective image value based on the degree of distortion; arranging one or more kernel image values ​​having the defective image value into a queue in descending order of the degree of distortion within the group; as well as The queued kernel image values ​​are dequeued in a first-in-first-out (FIFO) manner to correct the defective image values ​​in the descending order within the group.

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